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fn8661 rev 4.00 page 1 of 18 may 12, 2016 fn8661 rev 4.00 may 12, 2016 ISL8203M dual 3a/single 6a step-down dc/dc power module datasheet the ISL8203M is an integrated step-down power module rated for dual 3a output current or 6a current sharing operation. optimized for generating low output voltages down to 0.8v, the ISL8203M is ideal for any low power low voltage applications. the supply voltage range is from 2.85v to 6v. the two channels are 180 out-of-phase for input rms current and emi reduction. each channel is capable of 3a output current. they can be combined to form a single 6a output in current sharing mode. while in current sharing mode, the interleaving of the two channels reduces input and output voltage ripple. the ISL8203M offers an independ ent power-good (pg) signal for each channel. when shut down, the ISL8203M discharges the output capacitor. other feat ures include internal digital soft-start, enable for power sequence, overcurrent protection and over-temperature protection. the ISL8203M integrates a pwm controller, synchronous switching mosfets, inductors and passive components to maximize efficiency and minimize external component count. the ISL8203M is available in a thermally-enhanced, compact qfn package. features ? dual 3a and single 6a switching power supply ? high efficiency, up to 95% ? input voltage range: 2.85v to 6v ? output voltage range: 0.8v to 5v ? internal digital soft-start: 1.5ms ? external synchronization up to 4mhz ? compact size: 9.0mmx6.5mmx1.83mm ? peak current limiting and hiccup mode short-circuit protection ? overcurrent protection applications ? c/p, fpga and dsp power ? plug-in dc/dc modules for routers and switchers ? test and measurement systems ? barcode reader related literature ? an1941 , ?ISL8203Meval2z evaluation board user guide? figure 1. typical application circuit - dual 3a figure 2. small footprint package with low profile ISL8203M vout1 fb1 sgnd vout2 fb2 sgnd vin2 vdd en1 sync en2 pgnd output1 1.5v/3a vin1 100k 113k 80.6k ss 100k 1800pf 1800pf output2 1.8v/3a 2x22f input 2.85v to 6v 3x22f 3x22f 9 m m 6 . 5 m m 1.83mm
ISL8203M fn8661 rev 4.00 page 2 of 18 may 12, 2016 figure 3. internal block diagram sw 1 + csa1 + + + slo pe comp so ft- start 0.8v eamp comp pwm logic controller protection driver fb1 pg1 sync shutdow n vin1 pgnd oscillator bandgap referen ce en1 shutdow n 1ms delay sgn d 3pf 1.6k + + 0.8v eamp comp fb2 pg2 en2 sgn d thermal shutdow n shutdow n comp 1m vin1 ocp threshold logic ss ss + csa2 pwm logic controller protection driver shutdow n + slo pe comp bandgap referen ce shutdow n 1ms delay vin2 sw 2 pgnd vin2 vout1 vout2 so ft- start 1h 1h 1.6k rc network rc network pgood comparators pgood comparators 3pf 1f 1f
ISL8203M fn8661 rev 4.00 page 3 of 18 may 12, 2016 pin configuration ISL8203M (23 ld qfn) top view vdd ss 1 2 3 4 5 6 7 8 910 11 12 13 14 15 16 17 18 19 20 21 22 23 vin1 pgnd sw1 vout1 vout2 sw2 pgnd vin2 en2 pg2 nc fb2 nc nc comp fb1 nc pg1 sync en1 sgnd pin descriptions pin number symbol description 1ss soft-start pin. ss is used to adjust the soft-start time. for dual-out put mode, tie ss pin to vin directly and the soft-start time is fixed at 1.5ms. ss pin is tied to css only in pa rallel mode operation, with external compensation. in parallel mode, connect a capacitor c ss from ss to sgnd to adjust the soft-start time. c ss should not be larger than 33nf. this capacitor, along with an internal 5a current source sets the soft-start time, (refer to equation 2 ) . 2vdd input voltage for internal control circuit. tie vdd directly to vin1. vdd should be at the same potential as the input voltage. 3, 10 vin1, vin2 power inputs. input voltage range: 2.85v to 6v. tie directly to the input rail. input ceramic capacitors are needed between these two pins and pgnd. 4, 9 pgnd power ground. power ground pins for both input and output returns. 5, 8 sw1, sw2 switching node. use for monitoring switching frequency. switchin g nodes should be floating or used for snubber connections. 6, 7 vout1, vout2 power output. apply output load between these pins and pgnd pins. output voltage range: 0.8v to 5v. 22, 11 en1, en2 power enable pins. the output is enabled when the respective enable pin is driven to high. the output is shut down and output capacitors discharged when the respective enable pi n is driven to low. typically, tie to vin pin directly. do not leave this pin floating. 20, 12 pg1, pg2 power-good pins. at power-up or en hi, this output is a 1ms delayed power-good signal for the output voltage. 13, 15, 16, 19 nc no connection pins. these pins have no connections inside. leave these pins floating. 14 fb2 voltage setting pin. the output voltage v out2 is set by an external resistor divider connected to fb2. refer to ? programming the output voltage ? on page 12 . 17 comp compensation pin. typically floating for dual output mode. for dual ou tput operation, internal compensation networks are implemented for stable operation in the full range of i/o conditions. for parallel mode operation, external compensation is required. refer to ? output current sharing ? on page 11 .
ISL8203M fn8661 rev 4.00 page 4 of 18 may 12, 2016 18 fb1 voltage setting pin. the output voltage v out1 is set by an external resistor divider connected to fb1. refer to ? programming the output voltage ? on page 12 . 21 sync synchronization pin. connect to logic high or input voltage vin for non- use. connect to an external function generator for external synchronization. negative edge trigger. do not leave this pin floating. do not tie this pin low (or to pgnd). 23 sgnd control signal ground. connect to pgnd under the module on the top layer. make sure to have only two connect locations between sgnd and pgnd to avoid noise coupling. see ? pcb layout recommendation ? on page 14 . pin descriptions (continued) pin number symbol description ordering information part number ( notes 1 2 , 3 ) part marking temp. range (c) package (rohs compliant) pkg. dwg. # ISL8203Mirz ISL8203M -40 to +85 23 ld qfn l23.6.5x9 ISL8203Meval2z evaluation board notes: 1. add ?-t? suffix for 1k unit or ?-t7a? suffix for 250 unit tape and reel options. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see product information page for ISL8203M . for more information on msl, please see technical brief tb363 .
ISL8203M fn8661 rev 4.00 page 5 of 18 may 12, 2016 absolute maximum ratings (reference to sgnd) thermal information vin1, vin2, vdd . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v (dc) or 7v (20ms) sw1, sw2 . . . . . . . . . . . -3v/(10ns)/-1.5v (100ns)/-0.3v (dc) to 6.5v (dc) or . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v (20ms)/8.5v(10ns) en1, en2, pg1, pg2, sync, ss . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.5v fb1, fb2, comp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v esd ratings human body model (tested per jesd22-a114) . . . . . . . . . . . . . . . .1.5kv charged device model (tested per jesd22-c101e). . . . . . . . . . . . . . 1kv latch-up (tested per jesd-78a; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ? ja (c/w) ? jc (c/w) 23 ld qfn ( notes 4 , 5 ) . . . . . . . . . . . . . . . . 15 2 junction temperature range . . . . . . . . . . . . . . . . . . . . . . .-40c to +125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-55c to +150c ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40 c to +85 c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see tb493 recommended operating conditions v in supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.85v to 6v output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.8v to 5v load current range per channel . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 3a ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ? ja is measured in free air with the compon ent mounted on the ISL8203Meval2z evaluation board with ?direct attach? features. see t ech brief tb379 . 5. ????? jc , ?case temperature? location is at the center of the exposed metal pad on the package underside. electrical specifications unless otherwise noted, the typical specificatio ns are measured at the following conditions: t a = +25c, v out =1.2v. boldface limits apply across internal junction temperature range, -40c to +125c. symbol parameter test conditions min ( note 6 )typ max ( note 6 )unit input supply v uvlo vin undervoltage lockout threshold ( note 7 ) rising 2.50 2.85 v hysteresis 35 130 mv i vin input supply current ( note 7 )v in = 6v, en1 = en2 = 0, no load 42 a output regulation i out(dc) output continuous current range v in = 5v, v out1 = 1.2v 03 a v in = 5v, v out2 = 1.2v 03 a v in = 5v, v out1 = 1.2v, in parallel mode 06 a v out1 /v out1 v out2 /v out2 line regulation v in = 2.85v to 6v, v out1 = 1.2v, no load 0.25 % v in = 2.85v to 6v, v out2 = 1.2v, no load 0.25 % v in = 2.85v to 6v, v out1 = 1.2v, i out1 = 3a 0.25 % v in = 2.85v to 6v, v out2 = 1.2v, i out2 = 3a 0.25 % v out1 /v out1 v out2 /v out2 load regulation v in = 5v, 2x22f ceramic output capacitor i out1 = 0a to 3a, v out1 = 1.2v 1 % i out2 = 0a to 3a, v out2 = 1.2v 1 % output voltage accuracy over line/load/temperature range -1.5 1.5 % over line/load/temperature/life range -2.0 2.0 % v out output ripple voltage v in = 5v, 3x22f ceramic output capacitor i out1 = 0a, v out1 = 1.2v 10 mv p-p i out2 = 0a, v out2 = 1.2v 10 mv p-p i out1 = 3a, v out1 = 1.2v 12 mv p-p i out2 = 3a, v out2 = 1.2v 12 mv p-p v fb fb1, fb2 regulation voltage ( note 7 )0.8v i fb fb1, fb2 bias current ( note 7 ) vfb = 0.75v 0.1 a soft-start ramp time cycle ( note 7 )ss = vdd 1.5 ms i ss soft-start charging current ( note 7 ) 4 5 6 a
ISL8203M fn8661 rev 4.00 page 6 of 18 may 12, 2016 dynamic characteristics v out-dp voltage change for positive load step current slew rate = 1a/s, v in = 5v, v out = 1.2v, 3x22f ceramic output capacitor i out1 = 0a to 1.5a 35 mv p-p i out2 = 0a to 1.5a 35 mv p-p v out-dp voltage change for negative load step current slew rate = 1a/s, v in = 5v, v out = 1.2v, 3x22f ceramic output capacitor i out1 = 1.5a to 0a 45 mv p-p i out2 = 1.5a to 0a 45 mv p-p overcurrent protection t ocon dynamic current limit on-time 17 clock pulses t ocoff dynamic current limit off-time 8 ss cycle i out1 output overcurrent limit v in = 5v, v out1 = 1.2v 4.8 a i out2 v in = 5v, v out2 = 1.2v 4.8 a sw1, sw2 ( note 7 ) sw_ maximum duty cycle 100 % f sw pwm switching frequency 0.85 1.10 1.32 mhz f sync synchronization frequency range ( note 8 ) 2.64 4 mhz channel 1 to channel 2 phase shift rising edge to rising edge timing 180 sw minimum on-time sync = high (pwm mode) 140 ns r dis soft discharge resistance en = low 80 100 124 pg1, pg2 ( note 7 ) output low voltage sinking 1ma, vfb = 0.7v 0.32 v pg pin leakage current pg = v in = 6v 0.01 0.10 a internal pgood threshold percentage of nominal regulation voltage 90 % delay time (rising edge) time from v out reached regulation 1 ms internal pgood delay time (falling edge) 7 15 s en1, en2, sync ( note 7 ) logic input low 0.4 v logic input high 1.5 v i sync sync logic input leakage current pulled up to 6v 0.1 1 a i en enable logic input leakage current pulled up to 6v 0.1 1 a thermal shutdown 150 c thermal shutdown hysteresis 25 c notes: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 7. parameters with min and/or max limits are 100% tested for internal ic prior to module assembly, unless otherwise specified. t emperature limits established by characterization and are not production tested. 8. the operational frequency per switching channel is half of the sync frequency. electrical specifications unless otherwise noted, the typical specificatio ns are measured at the following conditions: t a = +25c, v out =1.2v. boldface limits apply across internal junction temperature range, -40c to +125c. (continued) symbol parameter test conditions min ( note 6 )typ max ( note 6 )unit
ISL8203M fn8661 rev 4.00 page 7 of 18 may 12, 2016 typical performance characteristics efficiency t a = +25c. figure 4. single channel, en1 = high, en2 = low, v in =3.3v figure 5. single channel, en1 = high, en2 = low, v in = 5v figure 6. parallel single output, v in = 3.3v figure 7. single channel, v in = 5v output voltage ripple t a = +25c. figure 8. single channel, en1 = high, en2 = low, v in = 5v, v out =1.5v, i out = 3a, c out = 3x22f ceramic capacitors figure 9. parallel single output, v in = 5v, v out = 1.5v, i out =6a, c out = 6x22f ceramic capacitors 60 65 70 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 load current (a) v out = 1v v out = 1.5v efficiency (%) v out = 1.2v v out = 2.5v 60 65 70 75 80 85 90 95 100 0 0.5 1.0 1.5 2.0 2.5 3.0 v out = 1v v out = 1.5v v out = 1.2v v out = 2.5v v out = 3.3v load current (a) efficiency (%) 60 65 70 75 80 85 90 95 100 0123456 load current (a) v out = 1.2v v out = 1v efficiency (%) v out = 1.5v v out = 2.5v 60 65 70 75 80 85 90 95 100 0123456 v out = 1.2v v out = 1v v out = 1.5v v out = 2.5v v out = 3.3v load current (a) efficiency (%) 20mv/div 2s/div 20mv/div 2s/div
ISL8203M fn8661 rev 4.00 page 8 of 18 may 12, 2016 load transient response t a = +25c. load current step slew rate: 1a/s figure 10. single channel, en1 = high, en2 = low, v in = 3.3v, v out = 1v, i out = 0a to 1.5a step, c out = 3x22f ceramic capacitors figure 11. single channel, en1 = high, en2 = low, v in = 5v, v out = 1v, i out = 0a to 1.5a step, c out = 3x22f ceramic capacitors figure 12. single channel, en1 = high, en2 = low, v in = 5v, v out = 1.5v, i out = 0a to 1.5a step, c out = 3x22f ceramic capacitors figure 13. single channel, en1 = high, en2 = low, v in = 5v, v out = 3.3v, i out = 0a to 1.5a step, c out = 3x22f ceramic capacitors figure 14. parallel single output, v in = 3.3v, v out = 1v, i out = 0a to 1.5a step, c out = 6x22f ceramic capacitors figure 15. parallel single output, v in = 5v, v out = 1.2v, i out = 0a to 1.5a step, c out = 6x22f ceramic capacitors typical performance characteristics (continued) 50mv/div 50s/div 50mv/div 50s/div 50mv/div 50s/div 50mv/div 50s/div 50mv/div 50s/div 50mv/div 50s/div
ISL8203M fn8661 rev 4.00 page 9 of 18 may 12, 2016 start-up t a = +25c figure 16. single channel, en1 = high, en2 = low, soft-start with 3a load, v in = 5v, v out1 = 1.2v, i out1 = 3a, c out = 3x22f ceramic capacitors, c in = 100f + 22f ceramic capacitors figure 17. parallel single outp ut, soft-start with 6a load, v in = 5v, v out = 1.2v, i out = 6a, css = 0.022f, c out = 6x22f ceramic capacitors, c in = 100f + 22f ceramic capacitors short-circuit protection t a = +25c, parallel single output mode, v in = 5v, v out = 1.5v, i out = 6a, c in = 100f+22f ceramic capacitors, c out = 6x22f ceramic capacitors. figure 18. output short-circuit protection figure 19. output short-circ uit protection, hiccup mode figure 20. output short-circ uit recovery from hiccup typical performance characteristics (continued) 1ms/div pgood 5v/div i in 1a/div v out 0.5v/div v out 0.5v/div 1ms/div pgood 5v/div i in 2a/div v out 0.5v/div 20s/div i in 2a/div sw1 2v/div v out 0.5v/div 10ms/div i in 2a/div sw1 2v/div 5ms/div i in 2a/div sw1 2v/div v out 0.5v/div
ISL8203M fn8661 rev 4.00 page 10 of 18 may 12, 2016 typical application circuits figure 21. dual output for 1.5v/3a and 1.8v/3a figure 22. parallel single output for 1.5v/6a figure 23. 4-phase parallel single output for 1.2v/12a notes: 9. refer to ? pcb layout recommendation ? on page 14 for shorting sgnd to pgnd. 10. refer to ? output current sharing ? on page 11 for external compensation components. ISL8203M vout1 fb1 sgnd vout2 fb2 sgnd vin2 vdd en1 pg1 sync en2 pg2 pgnd output1 1.5v/3a vin1 100k 3x22f 113k 80.6k ss 100k 3x22f 1800pf 1800pf output2 1.8v/3a input 2.85v to 6v 3 10 2 22 11 1 21 20 12 4, 9 23 14 7 23 18 6 2x22f ISL8203M vout1 fb1 sgnd vout2 fb2 vin2 vdd en1 pg1 ss en2 pg2 pgnd output 1.5v/6a vin1 100k 2x47f 113k sync 1800pf 30.1k input 2.85v to 6v comp 270pf 3 10 2 22 11 21 1 20 12 4, 9 6 18 23 7 14 17 2x22f ISL8203M vout1 fb1 sgnd vout2 fb2 vin2 vdd en1 pg1 ss en2 pg2 pgnd output 1.2v/12a vin1 100k 3x100f 200k sync 1800pf 15.4k input 2.8v to 6v comp 470pf ISL8203M vout1 fb1 sgnd vout2 fb2 vin2 vdd en1 pg1 ss en2 pg2 pgnd vin1 sync comp 3 10 2 22 11 21 1 20 12 4, 9 6 18 23 7 14 17 3 10 2 22 11 21 1 20 12 4, 9 6 18 23 7 14 17 external sync signal 4x22f 0.22f
ISL8203M fn8661 rev 4.00 page 11 of 18 may 12, 2016 functional description pwm control scheme each channel of the ISL8203M employs the current-mode pulse-width modulation (pwm) control scheme for fast transient response and pulse-by-pulse current limiting, as shown in the ? internal block diagram ? on page 2 and with waveforms in figure 24 . the current loop consists of the oscillator, the pwm comparator comp, current sensing circuit, and the slope compensation for the current loop stability. the current sensing circuit consists of the resistance of the p-mosfet when it is turned on and the current sense amplifier csa1 (or csa2 of channel 2). the gain for the current sensing circuit is typically 0.2v/a. the control reference for the current loops comes from the error amplifier eamp of the voltage loop. the pwm operation is initialized by the clock from the oscillator. the p-channel mosfet is turned on at the beginning of a pwm cycle and the current in the mosfet starts to ramp up. when the sum of the current amplifier csa1 (or csa2 of channel 2) and the compensation slope (0.46v/s) re aches the control reference of the current loop, the pwm comparator comp sends a signal to the pwm logic to turn off the p-mosfet and to turn on the n-channel mosfet. the n-mosfet stays on until the end of the pwm cycle. figure 24 shows the typical operating waveforms during the pwm operation, where the dotted lines illustrate the sum of the compensation ramp and the curr ent-sense amplifier output v csa1 , v eamp represents the output of the error amplifier, and i l represents the in ductor current. the output voltage is regulated by controlling the reference voltage to the current loop. the bandgap circuit outputs a 0.8v reference voltage to the voltage control loop. the feedback signal comes from the fb pin. the soft-start circuitry only affects the operation during start-up and will be discussed separately; please refer to ? soft-start ? on page 12 . the voltage loop is internally compensated for the dual output mode. for parallel current sharing mode, external compensation is required. synchronization control the frequency of operation can be synchronized up to 4mhz by an external signal applied to th e sync pin. the 1st falling edge on the sync triggers the rising edge of the pwm on pulse of channel 1. the 2nd falling edge of the sync triggers the rising edge of the pwm on pulse of channel 2. this process alternates indefinitely allowing 180 out-of-phase operation between the two channels. the switching freque ncy per channel is half of the external signal?s frequency applied to the sync pin. the maximum external signal frequency is limited by the sw minimum on time (140ns max) requirement. the maximum external signal frequency can be calculated as shown in equation 1 . where: ?f sync-max is the maximum external signal frequency ?f sw-max is the maximum switching frequency per channel ?v out is the output voltage ?v in is the input voltage output current sharing the ISL8203M?s two channels can be paralleled for dual-phase operation in order to support a 6a output. in the parallel mode, the two channels are 180 out-of-phase, which reduces input and output voltage ripple and emi. connect v out1 to v out2 , fb1 to fb2, en1 to en2, pg1 to pg2 and connect a soft-start capacitor c ss from ss to sgnd; refer to figure 22 . in parallel mode, external compensation network of a resistor and a capacitor is required with the typical values of 30.1k and 270pf; refer to figure 22 . similar to the dual-phase operation, multiple modules can be paralleled for higher current capability. connect all the modules? fb pins, comp pins, ss pins, en pins and pg pins; refer to figure 23 . overcurrent protection current sense amplifiers csa1 and csa2 are used to monitor the two channels? internal inductor current, respectively. the overcurrent protection is realized by monitoring the csa output with the ocp threshold logic, as shown in figure 2 on page 1 . the current sensing circuit has a gain of 0.2v/a, from the p-mosfet current to the csa_ output. when the csa1 output reaches the threshold, the ocp comparator is tripped to turn off the p-mosfet immediately. the overcurrent function protects the module from a shorted output by monitoring the current flowing through the upper mosfets. upon detection of an overcurrent condition, the upper mosfet will be immediately turned off an d will not be turned on again until the next switching cycle. upon detection of the initial overcurrent condition, the overcurrent fault counter is set to 1 and the overcurrent condition flag is set from low to high. if, on the subsequent cycle, another overcurrent condition is detected, the oc fault counter will be incremented. if there are 17 sequential oc fault detections, the module will shut down under an overcurrent fault condition. an overcurrent fault condition will result in the module attempting to restart in a hiccup mode with the delay between restarts being 8 soft-start periods. at the end of the eighth soft-start wait pe riod, the fault counters are reset and soft-start is attempted agai n. if the overcurrent condition goes away prior to the oc fault counter reaching a count of four, the overcurrent condition fl ag will set back to low. figure 24. pwm operation waveforms v eamp v csa1 duty cycle i l v out 1 2 -- - f ? sync max C f sw max C v out v in --------------- - 1 140ns ---------------- - ? ? = (eq. 1)
ISL8203M fn8661 rev 4.00 page 12 of 18 may 12, 2016 if the negative current of the internal inductor reaches -2.5a, the module enters negative overcurrent protection. at this point, all switching stops and the module enters tri-state mode while the pull-down mosfet discharges the output until it reaches normal regulation voltage, then the module restarts. power-good there are two independent power-good signals for each of the two outputs via the fb pins. pg1 monitors the output channel 1 and pg2 monitors the output cha nnel 2. when powering up, the open-collector power-on reset output holds low for about 1ms after v out reaches within 8% of the preset voltage. the pg pins do not require a pull-up resistor. uvlo (undervoltage lockout) when the input voltage is below the undervoltage lockout (uvlo) threshold, the module is disabled. the maximum uvlo threshold is 2.85v. enable the enable (en) input allows the user to control the turning on or off of the module for purposes such as power-up sequencing. each channel of the ISL8203M can be turned on or off independently through the en pins . once the module is enabled, there is typically a 600s delay for waking up the bandgap reference, then the soft start-up begins. soft-start the ISL8203M employs an internal digital soft-start circuitry which minimizes input inrush current during the start-up. the soft-start circuitry outputs a ramp reference to both the voltage loop and the current loop. the two ramps limit the inductor current rising speed as well as th e output voltage rising speed so that the output voltage rises in a controlled fashion. at the beginning of the soft-start internal, when the voltage on the fb pin is less than 0.5v, the pwm oscillator frequency is forced to half of the normal frequency. during the soft-start, the module cannot sink current, behaving as in diode emulated mode for the soft-start time. if ss pin is tied to vin, the soft -start time is an internally fixed 1.5ms. for parallel current sharing mode operation, connect a capacitor c ss from ss to sgnd. c ss should not be larger than 33nf. this capacitor along with th e internal current source of 5a sets the soft-start time t ss , which can be calculated as shown in equation 2 . discharge mode when a transition to shutdown mode occurs, or the output undervoltage fault latch is set, the module?s output discharges to pgnd through an internal 100 switch. power mosfets the internal power mosfets are optimize for best efficiency. the on-resistance for the p-mosfet is typically 50m and the on-resistance for the n-mosfet is typically 50m . 100% duty cycle operation the ISL8203M offers 100% duty cy cle operation. when the input voltage drops to a level that the ISL8203M can no longer maintain the regulation at the output, the module completely turns on the p-mosfet. the maximum dropout voltage under the 100% duty-cycle operation is the product of the load current and the on-resistance of the p-mosfet. thermal shutdown the ISL8203M offers built-in over-temperature protection. when the junction temperature re aches +150c, the module is completely shut down. as the temperature drops to +125c, the ISL8203M resumes operation by st epping through a soft-start. applications information programming the output voltage the output voltage of the module is programmed by an external resistor divider between vout, fb and sgnd pins, as shown in figure 21 . the output voltage can be calculated as shown in equation 3 . where: ?r fbtop is the top feedback resistor ?r fbbot is the bottom feedback resistor the top resistor is typically a 100k value, and a 1800pf capacitor is recommended to be connected in parallel if the output capacitors are all ceramic capacitors or bulk capacitors with low esr (equivalent series resistance). the value of the bottom resistor for different output voltages is shown in table 1 . please note that the output volt age accuracy is also dependent on the resistor accuracy of r fbtop and r fbbot . the user needs to select high accuracy resistor s (i.e., 0.5%) in order to achieve the overall output accuracy. input capacitor selection low equivalent series resistance (esr) ceramic capacitance is recommended to reduce input voltage ripple and decouple between the vin and pgnd of each channel. this capacitance t ss ms ?? 0.16 c ss nf ?? ? = (eq. 2) table 1. value of bottom resistor for different output voltages (v out vs r fbbot ) r fbtop (k )v out (v) r fbbot (k ) 100 0.8 open 100 1.0 402 100 1.2 200 100 1.5 113 100 1.8 80.6 100 2.5 47.5 100 3.3 32.4 vout 0.8v 1 r fbtop r fbbot ----------------------- + ?? ?? ?? ? = (eq. 3)
ISL8203M fn8661 rev 4.00 page 13 of 18 may 12, 2016 reduces voltage ringing created by the switching current across parasitic circuit elements. the ceramic capacitors should be placed as closely as possible to the module pins. a minimum of 22f ceramic capacitance for each channel is recommended. a bulk input capacitance may also be needed if the input source does not have enough output capacitance. a typical value of bulk input capacitor is 100f. in such conditions, this bulk input capacitance can supply the current during output load transient conditions. output capacitor selection ceramic capacitors are typically used as the output capacitors for the ISL8203M. a minimum output capacitance of 2x22f per phase is recommended. bulk output capacitors that have adequately low equivalent series resistance (esr), such as low esr polymer capacitors or a low esr tantalum capacitor, may also be used in combination with the ceramic capacitors, depending on the output voltage ripple and transient requirements. thermal consideration and current derating experimental power loss data ( figures 25 and 26 ), along with ? ja from thermal modeling analysis, can be used as a guide for thermal consideration for the mo dule. the ISL8203M?s thermally enhanced package offers typical junction to ambient thermal resistance ? ja of approximately 15c/w at natural convection (13c/w with 200lfm airflow) with a typical 4-layer pcb board. the derating curves ( figures 27 through 31 ) are derived from the maximum power dissipation allowed, while maintaining the junction temperature below a maximum junction temperature of +120c; the derating curves take into consideration the increased power dissipation at elevated ambient temperatures. the maximum +120c junction temperature is recommended for the module to load the current consistently and it provides the 5c margin of safety from the rated junction temperature of +125c. all the derating curves are obtained based on tests on the ISL8203Meval2z evaluation board (refer to an1941 , ?ISL8203Meval2z evaluation board user guide?). if necessary, the customer can adjust the margin of safety according to the real application. in the actual ap plication, other heat sources and design margins shou ld be considered. power loss curves figure 25. power loss at v in = 5v, parallel single output, t a = +25c figure 26. power loss at v in = 3.3v, parallel single output, t a = +25c 0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 load current (a) power loss (s) v out = 1v v out = 3.3v 0 0.5 1.0 1.5 2.0 2.5 3.0 0123456 v out = 1v v out = 2.5v load current (a) power loss (s)
ISL8203M fn8661 rev 4.00 page 14 of 18 may 12, 2016 pcb layout recommendation to achieve stable operation, low losses and good thermal performance, some layout considerations are necessary ( figure 31 ). ? use large copper areas for power path (vin1, vin2, sgnd, pgnd, vout1 and vout2) to minimize conduction loss and thermal stress. also, it is recommended to use multiple vias to connect the power planes in different layers. use at least 5 vias on the sgnd pad 23 connected to sgnd plane(s) for the best thermal relief. ? use a separate sgnd ground copper area for components connected to signal ground pins. connect sgnd pad 23 to pgnd pin 4 at a single location and sgnd pad 23 to pgnd pin 9 at a single location. ? the switching node of the modu le, the sw pins and the traces connected to the pins are very noisy. keep these pads under the module. for noise sensitive applications, it is recommended to keep the sw pads only on the top and inner layers of the pcb. do not expose the sw pads to the outside on the bottom layer of the pcb. ? avoid routing noise-sensitive signal traces such as fb1, fb2, and comp near the noisy sw pins. ? the feedback network should be placed as close as possible to the fb pins, and far away from the sw pins. ? place high frequency ceramic capacitors between vin, vout and pgnd, as close to the module as possible in order to minimize high frequency noise. place several vias close to the ceramic capacitors. the grou nd terminal of the input capacitors and output capacitors should be placed as close as possible. package description the ISL8203M is integrated into a quad flatpack no-lead (qfn) package. this package has such advantages as good thermal and electrical conductivity, low weight and small size. the qfn package is applicable for surface mounting technology and is becoming more comm on in the industry. the ISL8203M is a copper leadframe based package with exposed copper thermal pads, which have good electrical and thermal conductivity. the copper leadframe and mult icomponent a ssembly are overmolded with polymer mold compound to protect these devices. derating curves figure 27. derating curves at v in = 5v, v out = 1v figure 28. derating curves at v in = 5v, v out = 3.3v figure 29. derating curves at v in = 3.3v, v out = 1v figure 30. derating curves at v in = 3.3v, v out = 2.5v 0 1 2 3 4 5 6 7 20 30 40 50 60 70 80 90 100 110 120 ambient temperature (c) load current (a) 0lfm 200lfm 0 1 2 3 4 5 6 7 20 30 40 50 60 70 80 90 100 110 120 ambient temperature (c) load current (a) 0lfm 200lfm 0 1 2 3 4 5 6 7 20 30 40 50 60 70 80 90 100 110 120 ambient temperature (c) load current (a) 0lfm 200lfm 0 1 2 3 4 5 6 7 20 30 40 50 60 70 80 90 100 110 120 ambient temperature (c) load current (a) 0lfm 200lfm
ISL8203M fn8661 rev 4.00 page 15 of 18 may 12, 2016 the package outline, typical pcb layout pattern, and typical stencil pattern design are shown in the l23.6.5x9 ? package outline drawing ? on page 17 . tb493 shows typical reflow profile parameters. these guidelines are general design rules. users can modify parameters according to specific applications. pcb layout pattern design the bottom of ISL8203M is a leadframe footprint, which is attached to the pcb by surface mounting. the pcb layout pattern is shown in the l23.6.5x9 ? package outline drawing ? on page 17 . the pcb layout pattern is essentially 1:1 with the qfn exposed pad and the i/o terminatio n dimensions, except that the pcb lands are slightly longer than the qfn terminations by about 0.2mm (0.4mm max). this extension allows for solder filleting around the package periphery an d ensures a more complete and inspectable solder joint. the thermal lands on the pcb layout should match 1:1 with the package exposed die pads. thermal vias a grid of 1.0mm to 1.2mm pitched thermal vias, which drops down and connects to buried copper planes, should be placed under the thermal land. the vias should be about 0.3mm to 0.33mm in diameter, with the barrel plated to about 2.0 ounce copper. although adding more vias (by decreasing pitch) improves thermal performance, it also diminishes results as more vias are added. use only as many vias as are needed for the thermal land size and as your board design rules allow. stencil pattern design reflowed solder joints on the perimeter i/o lands should have about a 50m to 75m (2 mil to 3 mil) standoff height. the solder paste stencil design is the first step in developing optimized, reliable solder joins. the stencil aperture size to land size ratio should typically be 1:1. aperture width may be reduced slightly to help prevent solder bridging between adjacent i/o lands. to reduce solder paste volume on the larger thermal lands, an array of smaller apertures inst ead of one large aperture is recommended. the stencil printing area should cover 50% to 80% of the pcb layout pattern. consider the symmetry of the whole stencil pattern when designing the pads. a laser-cut, stainless-steel stencil with electropolished trapezoidal walls is recommended. electropolishing smooths the aperture walls, resulting in reduced surface friction and better paste release, which reduces voids. using a trapezoidal section aperture (tsa) also promotes paste release and forms a brick-like paste deposit, whic h assists in firm component placement. reflow parameters due to the low mount height of the qfn, "no clean" type 3 solder paste, per ansi/j-std-005, is re commended. nitr ogen purge is also recommended during reflow. a system board reflow profile depends on the thermal mass of the entire populated board, so it is not practical to define a specific soldering profile just for the qfn. the profile given in tb493 is provided as a guideline to customize for varying manufacturing practices and applications. figure 31. recommended layout
fn8661 rev 4.00 page 16 of 18 may 12, 2016 ISL8203M intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas llc 2014-2016. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related docu mentation and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change may 12, 2016 fn8661.4 updated note 1 in the ordering information table. updated pod to the latest revision changes are as follows: -updated bottom view by adding two dimensions and moved two dimension labels over so they are easier to read. january 19, 2015 fn8661.3 updated ?package outline drawing? on page 17 with latest revision. corrected/updated recommended pcb land pattern and added recommended stencil patterns. august 28, 2014 fn8661.2 added to sentence that is under ? programming the output voltage ? on page 12 after ?...in parallel.?, which reads ?if the output capacitors are all ceramic capacitors or bulk capacitors with low esr (equivalent series resistance)." replaced schematics on page 1 and page 10 . figure 2 , added the xyz dimension on the picture (9.0mmx6.5mmx1.83mm. figure 23 , changed the "113k" resistor to "200k". july 23, 2014 fn8661.1 added evaluation board to ?ordering information? on page 4 . june 23, 2014 fn8661.0 initial release
ISL8203M fn8661 rev 4.00 page 17 of 18 may 12, 2016 package outline drawing l23.6.5x9 23 lead quad flat no-lead plastic package rev 2, 10/15 bottom view top view located within the zone indicated. the pin #1 identifier may be tiebar shown (if present) i s a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be 5. either a mold or mark feature. 4. dimensions are in millimeters. 1. notes: 6.500 pin 1 index area b a 9.00 13x 0.55 2x 0.60 0.90 1.20 36x 0.50 4x 0.550 46x 0.22 22x 0.30 2x 2.70 2x 0.50 2x 2.70 0.60 2x 1.60 2x 0.90 3.30 2x 1.40 2x 1.42 2x 1.49 2x 1.00 2x 0.50 2x 0.42 3.60 pin #1 identification chamfer 0.300x45 6 7 23 12 13 22 1 0.100 00.50 m m cab 0.100 m c a c b see detail x c seating plane 1.90 max 0.100 c 0.05 c 46x 0.05 side view detail x c 0.203 ref 0 - 0.05 4 dimensioning and tolerancing conform to asmey 14.5m-1994. 2. unless otherwise specified, tolerance: decimal 0.05. 3. 6 6 lead pitches not centered in y direction. 6. 2x 1.08 2x 1.26
fn8661 rev 4.00 page 18 of 18 may 12, 2016 ISL8203M 0.090 stencil pattern with 23 moslp top view 2.845 2.168 1.968 1.745 1.545 0.445 0.445 1.545 1.745 1.968 2.168 2.845 2.850 2.845 2.450 1.596 2.850 1.577 0.495 0.373 1.460 0.790 2.560 0.495 4.100 3.400 1.577 0.373 0.511 0.000 0.090 0.790 1.460 1.861 2.061 2.505 3.411 4.185 3.305 2.950 3.495 1.845 2.845 2.655 2.345 2.155 1.155 1.655 1.345 2.950 0.845 0.655 0.655 0.845 1.155 1.345 1.655 1.845 2.155 2.345 2.655 2.845 3.995 3.805 0.695 3.305 1.495 1.305 0.995 0.805 0.495 0.305 0.005 0.195 0.505 2.005 1.505 1.695 2.195 3.005 2.505 2.695 3.695 3.195 3.325 3.505 3.425 2.845 2.655 2.725 2.155 2.345 1.155 1.845 1.655 1.345 0.155 0.845 0.655 0.345 0.155 0.345 0.655 0.845 1.155 1.345 1.655 1.845 2.155 2.345 2.655 2.845 4.200 3.995 3.805 3.495 0.305 1.495 1.305 0.995 0.805 0.495 0.000 3.695 0.005 0.195 0.505 0.695 1.505 1.695 2.005 2.195 2.505 2.695 3.005 3.195 3.505 3.975 4.675 stencil pattern with 23 moslp top view 0.100 0.100 1.600 2.450 0.000 0.000 typical recommended land pattern 4.700 2.860 0.250 0.250 3.450 3.200 3.200 1.777 1.777 0.177 0.010 0.290 0.000 0.323 0.890 1.310 2.710 2.990 3.210 3.490 3.710 3.623 0.177 0.290 0.010 1.310 0.890 2.710 2.990 3.210 3.300 3.490 4.700 3.710 2.350 3.950 2.640 2.360 2.140 1.860 1.800 1.640 1.140 1.360 0.140 0.860 0.000 0.140 0.860 1.360 1.140 1.800 1.640 2.640 1.860 2.360 2.860 2.950 2.350 2.140 3.450

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