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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XRT91L33A sts-12/sts-3 multirate clock and data recovery unit june 2010 rev. 1.0.1 features ? performs clock and data recovery for selectable data of 622.08 mbps (sts-12/stm-4) or 155.52 mbps (sts-3/stm-1) nrz data ? meets telcordia, ansi and itu-t g.783 and g.825 sdh jitter requirements including t1.105.03 - 2002 sonet jitter tolerance specification, and gr-253 core, gr-253 ilr sonet jitter specifications. ? lock is a status output that monitors data run length and frequency drift away from the reference clock ? data is resampled at the output ? active high signal detect (sigd) lvpecl input ? low jitter, high-speed ou tputs support lvpecl and low-power lvds termination ? 19.44 mhz reference frequency lvttl input ? low power: 215 mw typical ? 3.3v power supply ? 20-pin tssop package ? requires one external capacitor ? pll bypass operation facilitates board debug process ? esd greater than 2kv on all pins ? enhanced jitter performance ? meets both jitter tolerance and generation requirements applications ? sonet/sdh-based transmission systems ? dslams and add/drop multiplexers ? cross connect equipment ? atm and multi-service switches, routers and switch/routers ? dwdm termination equipment general description the XRT91L33A is a fully integrated multirate clock and data recovery (cdr) device for sonet/sdh 622.08 mbps sts-12/stm-4 or 155.52 mbps sts-3/ stm-1 applications. the device provides clock and data recovery (cdr) function by synchronizing its on-chip voltage controlled oscillator (v co) to the incoming serial scrambled non-return to zero (nrz) data stream. figure 1 shows the block diagram of the XRT91L33A. f igure 1. b lock d iagram of XRT91L33A rxdop rxdon rxclkop rxclkon lock lvds/lvpecl output drivers cdr recvd- dataout recvd- clkout sts-12/3 or stm-4/1 clock and data recovery differential receiver rxdip rxdin rxdatain rx loop filter sigd lcktorefn 1 0 pll sts12_mode refck 19.44 mhz test internal biasing external 100r termination 1u f mute rxdo cap+ cap-
XRT91L33A 2 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 clock and data recovery overview the clock and data recovery (cdr) unit accepts high spee d nrz serial data from the differential receiver and generates a clock with a freque ncy equal to that of the incoming data. the cdr block uses a reference clock to train and monitor its clock recovery pll. upon startup, th e pll locks to the local reference clock. once this is achieved, the pll attempts to lock onto the incoming receive serial data stream. whenever the recovered clock frequency deviates from the local reference cloc k frequency by more than approximately 500 ppm, the clock recovery pll will switch and lo ck back onto the local reference cl ock and declare a loss of lock. whenever a loss of lock or a loss of signal event occurs, the cdr will cont inue to supply a recovered clock (based on the local reference) to the framer/mapper device. an los condition occurs when either sigd or lcktorefn is low. in this case, the receive serial data output is forced to a logic zero state for the entire duration of the los condition. this acts as a receive data mute upon los function to prevent random noise from being misinterpreted as valid incoming data. when sigd becomes active again, the recovered clock is determined to be within 500 ppm accuracy with respect to the local reference source and los is no longer declared, the clock recovery pll will switch and lock back onto the inco ming receive serial data stream. f igure 2. 20 pin tssop o f XRT91L33A (t op v iew ) t able 1: o rdering i nformation p art n umber p ackage o perating t emperature r ange XRT91L33Aig-f 20-pin tssop lead-free package -40 c to +95 c 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vdda rxdip rxdin vssa lock sts12_mode refck lcktorefn vss vdd vdda vssa cap+ cap- test sigd rxdop rxdon rxclkop rxclkon
XRT91L33A 3 rev. 1.0.1 sts-12/sts-3 multirate cl ock and data recovery unit features.............. ................ ................ ................. .............. .............. .............. .............. .. 1 applications ............. ................ ................ .............. .............. ............... .............. ........... 1 general description........ ................. ................ ................ ............... .............. ........... 1 f igure 1. b lock d iagram of XRT91L33A..................................................................................................................... ................ 1 c lock and d ata r ecovery o verview ....................................................................................................... 2 f igure 2. 20 pin tssop o f XRT91L33A (t op v iew )................................................................................................................... 2 t able 1: o rdering i nformation ............................................................................................................................... ..................... 2 1.0 pin descriptions ........................................................................................................ ...................... 4 t able 2: p in d escription t able ............................................................................................................................... ..................... 4 2.0 functional description .................................................................................................. ............. 6 2.1 reference clock input ................................................................................................... ........................ 6 2.2 receive clock and data recovery ......................................................................................... ........... 6 2.3 external receive loop filter capacitor .................................................................................. ..... 6 2.4 sts-12/stm-4 and sts-3/stm-1 mode of operation .......................................................................... . 6 2.5 signal detection ........................................................................................................ ............................... 6 f igure 3. c ontrol d iagram f or s ignal d etection c ircuit and pll t est o peration ............................................................. 7 2.6 lock detection .......................................................................................................... ................................. 7 2.7 test pin operation ...................................................................................................... .............................. 7 t able 3: s ignal d etect and test p in o peration c ontrol ........................................................................................................ 8 3.0 electrical characteristics .............................................................................................. ....... 9 3.1 absolute maximum ratings ................................................................................................ ................... 9 t able 4: a bsolute m aximum r atings ............................................................................................................................... ............. 9 3.2 operating conditions .................................................................................................... .......................... 9 t able 5: r ecommended o perating c onditions ........................................................................................................................... 9 3.3 lvpecl single ended input and output dc charact eristics ......... .............. ........... ............ .... 9 t able 6: lvpecl s ingle e nded i nputs and o utputs .................................................................................................................. 9 3.4 lvpecl differential input and output dc charact eristics .......... ........... ............ ........... ..... 10 t able 7: lvpecl d ifferential i nputs and o utputs ................................................................................................................. 10 f igure 4. d ifferential voltage swing definitions ( input or output ) for clock and data .................................................... 10 t able 8: lvds o utputs ............................................................................................................................... ................................ 10 t able 9: lvttl i nputs ............................................................................................................................... .................................. 11 3.5 ac characteristics .. .............. .............. .............. .............. ........... ............ ........... .......... .......................... 11 t able 10: p erformance s pecifications ............................................................................................................................... ...... 11 4.0 jitter performance ...................................................................................................... .............. 12 4.1 sonet jitter requirements ............................................................................................... .................. 12 4.1.1 rx jitter tolerance: ................................................................................................... ....................................... 12 f igure 5. gr-253/g.783 j itter t olerance m ask ...................................................................................................................... 12 f igure 6. XRT91L33A j itter t olerance at 155 m bps oc3/stm-1 l ow b andwidth ............................................................. 13 f igure 7. XRT91L33A j itter t olerance at 155 m bps oc3/stm-1 h igh b andwidth ............................................................ 13 f igure 8. XRT91L33A j itter t olerance at 622 m bps oc12/stm-4 l ow b andwidth ........................................................... 14 f igure 9. XRT91L33A j itter t olerance at 622 m bps oc12/stm-4 h igh b andwidth .......................................................... 14 4.1.2 jitter generation...................................................................................................... .......................................... 14 4.1.3 jitter transfer ........................................................................................................ ............................................ 15 f igure 10. XRT91L33A j itter t ransfer at 155 m bps oc3/stm-1 l ow b andwidth ............................................................. 15 f igure 11. XRT91L33A j itter t ransfer at 622 m bps oc12/stm-4 l ow b andwidth ........................................................... 15 5.0 high-speed outputs ...................................................................................................... ............... 16 f igure 12. h igh s peed o utputs , lvds t ermination ................................................................................................................. 16 f igure 13. h igh -s peed o utputs , lvpecl t ermination options .............................................................................................. 16 6.0 resampled data and clock outputs ................................................................................... 17 f igure 14. o utput d ata and c lock after r esampling ............................................................................................................. 17 t able 11: o utput t iming ............................................................................................................................... .............................. 17 7.0 package dimensions ...................................................................................................... .............. 18 t able 12: r evision h istory ............................................................................................................................... .......................... 18
XRT91L33A 4 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 1.0 pin descriptions t able 2: p in d escription t able n ame l evel t ype p in d escription vdda pwr pwr 1 3.3v power supply rxdip lvds/pecl i 2 positive side of receive data input. the high-speed output clock (rxclkop/n) is recovered from this high-speed differential input data. rxdin lvds/pecl i 3 negative side of receive data input. the high-speed output clock (rxclkop/n) is recovered from this high-speed differen - tial input data. vssa pwr pwr 4 ground pin lock lvpecl o 5 active high to indicate that the pll is locked to serial data input and valid clock and data are present at the serial outputs (rxdop/n and rxclkop/n). the lock will go inactive under the following conditions: ? if sigd is set low ? if lcktorefn is set low ? if the vco has drifted away from the local reference clock, refck, by more than +/- 500 ppm sts12_mode lvttl i 6 sts-12 or sts-3 mode selection. set high to select the sts- 12 operation. set low for sts-3 operation refck lvttl i 7 local 19.44 mhz reference clock input for the cdr. refck is used for the pll phase adjustment during power up. it also serves as a stable clock source in the absence of serial input data. lcktorefn lvttl i 8 lock to refck input. when set low, this pin causes the out - put clock, rxclkop/n to be he ld within +/- 500ppm of the input reference clock refcl and forces the rxdop/n to a low state. vss pwr pwr 9 ground pin vdd pwr pwr 10 3.3v power supply rxclkon lvds/ lvpecl o 11 high-speed clock output, negative. this clock is recovered from the receive data input (rxdip/n) and supports either lvds or lvpecl termination rxclkop lvds/ lvpecl o 12 high-speed clock output, positive this clock is recovered from the receive data input (rxdip/n) and supports either lvds or lvpecl. termination rxdon lvds/ lvpecl o 13 high-speed output, negative this is the retimed version of the recovered data stream from rxdip/n and can be in either lvds or lvpecl termination rxdop lvds/ lvpecl o 14 high-speed output, positive. this is the retimed version of the recovered data stream from rx dip/n and can be in either lvds or lvpecl termination
XRT91L33A 5 rev. 1.0.1 sts-12/sts-3 multirate cl ock and data recovery unit sigd lvpecl i 15 signal detect. sigd should be connected to the sigd output on the optical module. sigd is active high. when sigd is set high, it means there is sufficie nt optical power. when sigd is low, this indicates an los cond ition, the rxclkop/n output signal will be held to within +/- 500 ppm of the refck input. additionally, the rxdop/n wil l be held in the low state. test lvttl i 16 three-level input: set to vss for normal operation, vdd for improved jitter transfer characteristics and 1.4v for bypass mode (used for production testing). note: to improve jitter transfer, set the test pin to vdd. cap- analog i 17 negative side of the external loop filter. the loop filter capacitor should be connected to these pins. the capacitor value should be 1.0 ? f +/- 10% cap+ analog i 18 positive side of the external loop filter. the loop filter capacitor should be connected to these pins. the capacitor value should be 1.0 ? f +/- 10%. vssa pwr pwr 19 ground pin vdda pwr pwr 20 3.3v power supply n ame l evel t ype p in d escription
XRT91L33A 6 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 2.0 functional description the XRT91L33A cdr is designed to operate with a so net framer/asic device and provide a high-speed serial clock and data recovery inte rface to optical networks. the cdr rece ives a differential nrz serial bit stream running at sts-12/stm-4 or sts-3/stm-1 a nd generates recovered serial clock and data via differential lvds/lvpecl drivers. 2.1 reference clock input the XRT91L33A accepts a 19.44 mhz lvttl clock input at refck. the refck should be generated from a source that has a frequency accuracy better than 100ppm in order for the cdr loss of lock detector to have the necessary accu racy required for sonet systems. 2.2 receive clock and data recovery the clock and data recovery (cdr) unit accepts the high-speed nrz serial data from the differential receiver and generates a clock that is the sa me frequency as the incoming data. the clock recovery block utilizes the reference clock from refck to train and monitor its clock recovery pll. upon startup, the pll locks to the local reference clock. once this is achieved, the pll then attempts to lock onto the incoming receive serial data stream. whenever the recovered clock frequency de viates from the local reference clock frequency by more than approximately 50 0ppm, the clock recovery pl l will switch to the local reference clock, declare a loss of lock and output a low level signal on the lock output pin. whenever a loss of lock (lol) or a loss of signal (los) event occurs, the cdr will continue to su pply a receive clock (based on the local reference). 2.3 external receive loop filter capacitor for sts12/stm4 and sts3/stm1 operation, the xrt91l33 a uses a 1.0uf external loop filter capacitor to achieve the required receiver jitter performance. it must be well isolated to prohibit noise entering the cdr block and should be placed as close to the pins as possible. the non-polarized capacitor should be of 10% tolerance. use type x7r or x5r capacitors for improved stability over temperature. 2.4 sts-12/stm-4 and sts-3/stm-1 mode of operation the vco output signal is fed into a programmable freq uency divider allowing one to properly set the pll operating frequency corresponding to the desired data rate. for 622.08 mbps signal sts12_mode is set high and for 155.52 mbps, sts12_mode is set low. 2.5 signal detection XRT91L33A has two control pins that ar e used to indicate an los condition (loss of signal). the sigd pin is a lvpecl input and the lcktorefn pin is a lvttl input. they are interna lly connected as shown in figure 3. if either of these two inputs goes low and test is low or high, XRT91L33A will enter a loss of signal (los) state, and will mute the rxdo p/n. during the los state, xrt 91l33a will also maintain rxclkop/n within 500ppm of the input reference clock, refck. most optical modules have an sigd output. this sigd output indicates that there is sufficient optical power and is typically active high. if the sigd output on the optical module is lvpecl, it should be connected directly to the sigd input of xr t91l33a, and the lcktorefn input should be tied high. if the sigd output is lvttl, it should be connected directly to the lcktorefn input and the sigd input should be tied high. the sigd and lcktorefn inputs also can be used for other applications when it is required to hold rxclkop/n output within 500ppm of the input reference clock and mute the serial data output lines.
XRT91L33A 7 rev. 1.0.1 sts-12/sts-3 multirate cl ock and data recovery unit f igure 3. c ontrol d iagram f or s ignal d etection c ircuit and pll t est o peration 2.6 lock detection XRT91L33A features a pll lock detection circuit. the lock detect (lock) output goes high to indicate that the pll is locked to the serial data input and valid data and clock are present at the high-speed differential output. the lock output will go lo w if either the locktorefn or the sigd input is forced low. additionally, lock will also go low if the incoming da ta frequency is more than +/-500ppm away from the reference clock frequency (refck x 32 in oc12 mo de, refck x 8 in oc3 mode). when lock output is driven low, the vco is forced to lock to refck and then released to lock on the incoming data. if the incoming data frequency remains outside the +/-500ppm window, the training mode is repeated. debounce logic stabilizes the lock output pin to stay low for incomi ng frequencies well bey ond the +/-5 00ppm window. 2.7 test pin functionality the test pin on the XRT91L33A is a three-level control input - vdd, vss and 1.4v. this pin determines the test (bypass) mode operation and controls the bandwid th of the pll. pulling this pin low sets the high bandwidth operation and is used fo r normal operation. pulling this pin hi gh sets the low bandwidth operation that is used for improved sonet jitter transfer performanc e. applying 1.4v to the input configures the device into a bypass mode for use in production test. 2.7.1 normal operation if the test pin is held low the part functions normally with similar performance to the XRT91L33A. the pll bandwidth is configured for high bandwidth. 2.7.2 improved jitter transfer operation if the test pin is held high the part optimizes the sone t jitter transfer performance. this mode is offered for applications where the jitter transfer characteristics are more critical. the pll bandwid th is configured for low bandwidth. 2.7.3 bypass mode operation if test is set to 1.4v and sts12_m ode pin is set to logic high, xrt9 1l33a will bypass the pll and present an inverted version of the refck to the clock output rxclkop/n. refck?s rising edge is used to capture the input data and transmit data to rxdo p/n. this bypass test operation ca n be used to facilitate board level debugging process. 0 1 los (internal ) sigd locktorefn test sts12_ mode refck pll clock (internal ) rxdip/n 22 2 rxclkop/n rxdop/n bw select (internal)
XRT91L33A 8 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 . t able 3: s ignal d etect and test p in o peration c ontrol sts12_mode test lcktorefn sigd rxdo rxclko 1 1 or 0 1 1 rxdi pll clock 1 1 or 0 1 0 muted pll clock 1 1 or 0 0 1 muted pll clock 1 1 or 0 0 0 muted pll clock 1 1.4v x x rxdi refck 0 1 or 0 1 1 rxdi pll clock 0 1 or 0 1 0 muted pll clock 0 1 or 0 0 1 muted pll clock 0 1 or 0 0 0 muted pll clock 0 1.4v x x not allowed not allowed
XRT91L33A 9 rev. 1.0.1 sts-12/sts-3 multirate cl ock and data recovery unit 3.0 electrical characteristics 3.1 absolute maximum ratings 3.2 operating conditions 3.3 lvpecl single ended input and output dc characteristics t able 4: a bsolute m aximum r atings s ymbol p arameter m inimum m aximum u nit v dd power supply voltage, referenced to gnd -0.5 4.0 v dc input voltage (lvpecl, lvttl) -0.5 vdd+0.5 v output current (lvds or lvpecl) -50 +50 ma t s storage temperature -65 150 v esd electrostatic discharge voltage, human body model -2000 2000 v t able 5: r ecommended o perating c onditions s ymbol p arameter m in . t yp m ax . u nits v dd power supply voltage 3.135 3.3 3.465 v te m p operating temperature under bias 1 1. lower limit of specification is ambient temperature, and upper limit is case temperature. -40 95 c i dd power supply current (outputs unterminated) 71 80 ma p d power dissipation (outputs unterminated) 234 277 mw t able 6: lvpecl s ingle e nded i nputs and o utputs s ymbol p arameter m in . t yp . m ax . u nits c onditions v ih input high voltage v dd -1.125 v dd -0.5 v guaranteed input high voltage v il input low voltage v dd -2.0 v dd -1.5 v guaranteed input low voltage i ih input high current -0.5 10 a v in = v dd - 0.5v i il input low current -0.5 10 v in =v dd -2.0v v ol output low voltage v dd -2.0 v dd -1.8 v 50 to (v dd -2.0v) v oh output high voltage v dd -1.25 v dd -0.67 v 50 to (v dd -2.0v) ? c ? ? ? a ? ?
XRT91L33A 10 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 3.4 lvpecl differential input and output dc characteristics f igure 4. d ifferential voltage swing definitions ( input or output ) for clock and data t able 7: lvpecl d ifferential i nputs and o utputs s ymbol p arameter m in . t yp . m ax . u nits c onditions v ih input high voltage v dd -1.75 v dd -0.4 v guaranteed input high voltage v il input low voltage v dd -2.0 v dd -0.7 v guaranteed input low voltage i ih input high current -0.5 10 a v in diff =0.5v i il input low current -0.5 10 v in diff =0.5v v idiff input pecl differential voltage, peak- to-peak swing (see figure 4 ) 250 mv v ocm output common-mode voltage 0.8 1.35 1.7 v 50 to (v dd -2.0v) v odiff output lvpecl differential voltage, peak-to-peak swing (see figure 4 ) 800 1700 mv 50 to (v dd -2.0v) t able 8: lvds o utputs s ymbol p arameter m in . t yp . m ax . u nits c onditions v ocm output common-mode voltage 1.0 1.35 1.7 v 100 between rxdop/n and rxclkp/n v odiff output lvds differential voltage, peak-to-peak swing (see figure 4 ) 700 1700 mv 100 between rxdop/n and rxclkp/n ? ? a ? ? v(+) v(-) 0 v 2 x v single v single v diff = v(+)-v(-) ? ?
XRT91L33A 11 rev. 1.0.1 sts-12/sts-3 multirate cl ock and data recovery unit 3.5 ac characteristics t able 9: lvttl i nputs s ymbol p arameter m in . t yp . m ax . u nits c onditions v ih input high voltage 2.0 v dd v v il input low voltage 0 0.8 v i ih input high current -50 50 vin = 2.75 v, v dd = maximum i il input low current -50 50 vin = 0.5 v, v dd = maximum t able 10: p erformance s pecifications test condition: vdd = 3.3v + 5% unless otherwise specified s ymbol p arameter m in t yp m ax u nits c onditions f vco center frequency 622.08 mhz f tol cdr?s reference clock frequency -250 250 ppm ft ref_clk oc-12/sts-12 capture range -500 500 ppm with respect to the fixed reference frequency clkout dc clock output duty cycle 45 55 % ui 20% minimum transition density t lock oc-12/sts-12 acquisition lock time 16 valid refck and device already pow - ered up t lock_r , t lock_f lock output rise and fall time 500 ps 10% to 90%, with 100 and 5 pf capacitive equivalent load j gen_clck rxclkop/n jitter generation 0.005 0.01 u irms j tol oc-12/sts-12 jitter tolerance 0.40 0.5 ui sinusoidal input jitter of rxdip/n from 250 khz to 5mhz ? a ? a ? s ?
XRT91L33A 12 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 4.0 jitter performance 4.1 sonet jitter requirements sonet receive equipment jitter requirem ents are specified jitter tolerance a nd jitter transfer. the definitions of each of these types of jitter are given below. 4.1.1 rx jitter tolerance: oc-3/stm-1, and oc-12/stm-4 category ii sonet in terfaces should tolerate , the input jitter applied according to the mask of figure 5 , with the corresponding specified parameters. jitter measurements are done with standard sonet/sdh testers such as acte rna ant20 as well as agilent omniber testers. f igure 5. gr-253/g.783 j itter t olerance m ask oc-n stm-x level 1 3 12 f0 (hz) 10 10 10 f1 (hz) 30 30 30 f2 (hz) 300 300 300 f3 (hz) 2k 6.5k 25k f4 (hz) 20k 65k 250k a1 (uipp) 0.15 0.15 0.15 a2 (uipp) 1.5 1.5 1.5 a3 (uipp) 15 15 15 input jitter amplitude (ui pp ) a 3 a 2 a 1 f 0 f 1 f 2 f 3 f 4 slope= -20db/decade slope= -20db/decade jitter frequency (hz) 3 12 10 10 10 30 30 30 300 300 300 2k 6.5k 25k 20k 65k 250k 0.15 0.15 0.15 1.5 1.5 1.5 15 15 15 oc1/sts1 stm0 oc3/sts3 stm1 oc12/sts12 stm4
XRT91L33A 13 sts-12/sts-3 multirate clock and data recovery unit f igure 6. XRT91L33A j itter t olerance at 155 m bps oc3/stm-1 (l ow b andwidth ) f igure 7. XRT91L33A j itter t olerance at 155 m bps oc3/stm-1 (h igh b andwidth ) 1.00 10.00 100.00 amplitude, ui XRT91L33A oc-3 low bandwidth jitter tolerance jitter tol.@ 1.3mhz = >0.60ui vdd = 3.3v, ta = 25c 0.10 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz mask, ui vdd = 3.30v 1.00 10.00 100.00 amplitude, ui XRT91L33A oc-3 high bandwidth jitter tolerance jitter tol.@ 1.3mhz = >0.60ui vdd = 3.3v, ta = 25c 0.10 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz mask, ui vdd = 3.30v
XRT91L33A 14 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 f igure 8. XRT91L33A j itter t olerance at 622 m bps oc12/stm-4 (l ow b andwidth ) f igure 9. XRT91L33A j itter t olerance at 622 m bps oc12/stm-4 (h igh b andwidth ) 4.1.2 jitter generation maximum jitter generation is less than 0.01 ui rms wi thin the sonet/sdh band, when rms jitter of less than 14 ps (oc-12) or 56 ps (oc-3) is presented to the serial data inputs. 10 100 1000 amplitude, ui XRT91L33A oc-12 low bandwidth jitter tolerance vdd = 3.3v, ta = 25c 0.1 1 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz mask, ui vdd = 3.30v 10 100 1000 amplitude, ui XRT91L33A oc-12 high bandwidth jitter tolerance vdd = 3.0v, ta = 25c 0.1 1 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz mask, ui vdd = 3.30v
XRT91L33A 15 sts-12/sts-3 multirate clock and data recovery unit 4.1.3 jitter transfer when in the low bandwidth mode (test pin = vdd) th e XRT91L33A does meet the jitter transfer requirement in the itu standard. f igure 10. XRT91L33A j itter t ransfer at 155 m bps oc3/stm-1 (l ow b andwidth ) f igure 11. XRT91L33A j itter t ransfer at 622 m bps oc12/stm-4 (l ow b andwidth ) -15.00 -10.00 -5.00 0.00 5.00 gain, db XRT91L33A oc-3 low bandwidth transfer function mask, ui vdd = 3.3v, ta = 25 q c -3.00 low bw -3db pt. = 65.54khz -30.00 -25.00 -20.00 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz -15.00 -10.00 -5.00 0.00 5.00 gain, db XRT91L33A oc-12 low bandwith transfer function mask, ui vdd = 3.3v, ta = 25 q c -3.00 lo bw -3db pt. -30.00 -25.00 -20.00 1 10 100 1000 10000 100000 1000000 10000000 frequency, hz
XRT91L33A 16 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 5.0 high-speed outputs the high-speed output buffers, rx dop/n and rxclkop/n can be termi nated as either lvds or lvpecl outputs. in lvds mode, the transmis sion lines must be routed with 100 differential impedance and terminated at the receive end with a line-to-line 100 resistor (see figure 12 ). for lvpecl connections, the transmissi on line must be terminated with 50 pull-down resistors near the receiving end or an equivalent circuit. (see figure 13 ) f igure 12. h igh s peed o utputs , lvds t ermination f igure 13. h igh -s peed o utputs , lvpecl t ermination options ? ? XRT91L33A 100 ohm receiver ? XRT91L33A 50 ohm 50 ohm v dd ?2.0v v dd ?2.0v receiver XRT91L33A 82 ohm 124 ohm v ss receiver v dd v dd v ss 168 ohm 168 ohm creates 2v bias when v dd = 3.3v XRT91L33A 168 ohm 168 ohm receiver (baised with internal termination) unbiased (no internal termination)
XRT91L33A 17 sts-12/sts-3 multirate clock and data recovery unit 6.0 resampled data and clock outputs it is recommended that the retimed data output be captured with the rising edge of the clock output as shown in figure 14 . data valid time is longer for oc-3/sts-3 mode of operation than that of oc-12/sts-12. data valid time before the output clock?s rising edge is the available setup time (t su ), while the data valid time after the clock?s rising edge is the available hold time (t h ). f igure 14. o utput d ata and c lock after r esampling t able 11: o utput t iming s ymbol p arameter m inimum m aximum u nit c ondition t su available setup time 450 ps sts-12 operation (622.08 mhz) 2.0 ns sts-3 operation (155.52 mhz) t h available hold time 650 ps sts-12 operation (622.08 mhz) 3.0 ns sts-3 operation (155.52 mhz) t h t su rxdop/n rxclkop/n
XRT91L33A 18 sts-12/sts-3 multirate clock and data recovery unit rev. 1.0.1 7.0 package dimensions 20 pin surface mount tssop t able 12: r evision h istory r evision # d ate d escription 1.0.0 march 2010 initial release of final product datasheet 1.0.1 june 2010 changed the maximum temperature to 95 o c, updated the typical idd and typical power values in the electrical table.

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