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KSZ9021GQ gigabit ethernet transceiver with gmii / mii support linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944-0800 ? fax + 1 (408) 474-1000 ? http://www.micrel.com september 2010 m9999-091010-1.2 general description the KSZ9021GQ is a completely integrated triple speed (10base-t/100base-tx/1000base-t) ethernet physical layer transceiver for transmission and reception of data on standard cat-5 unshielded twisted pair (utp) cable. the KSZ9021GQ provides the industry standard gmii/mii (gigabit media independent interface / media independent interface) for direct connection to gmii/mii macs in gigabit ethernet processors and switches for data transfer at 1000 mbps or 10/100 mbps speed. the KSZ9021GQ reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a ldo controller to drive a low cost mosfet to supply the 1.2v core. the KSZ9021GQ provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz9021 i/os and board. micrel linkmd ? tdr-based cable diagnostics permit identification of faulty copper cabling. remote and local loopback functions provide verification of analog and digital data paths. the KSZ9021GQ is available in a 128-pin, lead-free pqfp package (see ordering information). features ? single-chip 10/100/1000 mbps ieee 802.3 compliant ethernet transceiver ? gmii/mii standard compliant interface ? auto-negotiation to automatically select the highest link up speed (10/100/100 mbps) and duplex (half/full) ? on-chip termination resistors for the differential pairs ? on-chip ldo controller to support single 3.3v supply operation ? requires only external fet to generate 1.2v for the core ? jumbo frame support up to 16kb ? 125mhz reference clock output ? programmable led outputs for link, activity and speed ? baseline wander correction ? linkmd ? tdr-based cable diagnostics for identification of faulty copper cabling ? parametric nand tree support for fault detection between chip i/os and board. ? loopback modes for diagnostics ? automatic mdi/mdi-x crossover for detection and correction of pair swap at all speeds of operation ____________________________________________________________________________________________________________ functional diagram magnetics rj-45 connector on-chip termination resistors
micrel, inc. KSZ9021GQ september 2010 2 m9999-091010-1.2 more features ? automatic detection and correction of pair swaps, pair skew and pair polarity ? mdc/mdio management interface for phy register configuration ? interrupt pin option ? power down and power saving modes ? operating voltages core: 1.2v (external fet or regulator) i/o: 3.3v or 2.5v transceiver: 3.3v ? available in 128-pin pqfp (14mm x 20mm) package applications ? laser/network printer ? network attached storage (nas) ? network server ? gigabit lan on motherboard (glom) ? broadband gateway ? gigabit soho/smb router ? iptv ? ip set-top box ? game console ? triple-play (data, voice, video) media center ? media converter ordering information part number temp. range package lead finish description KSZ9021GQ 0c to 70c 128-pin pqfp pb-free gmii / mii, commercial temperature KSZ9021GQi (1) -40c to 85c 128-pin pqfp pb-free gmii / mii, industrial temperature note: 1. contact factory for lead time.
micrel, inc. KSZ9021GQ september 2010 3 m9999-091010-1.2 revision history revision date summary of changes 1.0 1/16/09 data sheet created 1.1 10/13/09 updated current consumption in electrical characteristics section. corrected data sheet omission of register 1 bit 8 for 1000base-t extended status information. added the following register bits to provide further power saving during software power down: tri- state all digital i/os (reg. 258.7), ldo disable (reg. 263.15), low frequency osc illator m ode (reg. 263.8). corrected tsu minimum for 1000base-t in gmii receive timing parameters table. 1.2 9/10/10 added support for 2.5v vdd i/o. added led drive current. updated KSZ9021GQ pin outs throughout data sheet to reflect pin out changes for silicon revision a3. updated boilerplate.
micrel, inc. KSZ9021GQ september 2010 4 m9999-091010-1.2 contents pin confi guration .............................................................................................................. .................................................... 8 pin descr ipti on ................................................................................................................ ...................................................... 9 strapping opti ons .............................................................................................................. ................................................. 18 functional ov erview ............................................................................................................ ............................................... 19 functional description: 10ba se-t/100base-tx transceiver ....................................................................... .................. 20 100base-tx transmit............................................................................................................ ........................................... 20 100base-tx receive............................................................................................................. ........................................... 20 scrambler/de-scrambler (100base-tx only)....................................................................................... ............................. 20 10base-t transmit .............................................................................................................. ............................................. 20 10base-t receive ............................................................................................................... ............................................. 20 functional description: 1000base-t transceiver................................................................................ ........................... 21 analog echo cancellation circuit ............................................................................................... ...................................... 21 automatic gain control (agc) ................................................................................................... ...................................... 21 analog-to-digital converter (adc) .............................................................................................. ..................................... 21 timing recovery circuit........................................................................................................ ............................................ 22 adaptive eq ualizer ............................................................................................................. ............................................... 22 trellis encoder and decoder .................................................................................................... ........................................ 22 functional description: additi onal 10/100/1000 phy features................................................................... .................. 22 auto mdi/mdi-x................................................................................................................. ............................................... 22 pair- swap, alignment, and polarity check...................................................................................... ................................ 23 wave shaping, slew rate c ontrol and part ial response........................................................................... ..................... 23 pll clock sy nthesizer.......................................................................................................... ............................................ 23 auto-negot iation ............................................................................................................... .................................................. 23 gmii interface................................................................................................................. ...................................................... 25 gmii signal definition ......................................................................................................... .............................................. 26 gmii signal diagram ............................................................................................................ ............................................ 26 mii interface .................................................................................................................. ....................................................... 27 mii signal definition.......................................................................................................... ................................................ 28 mii signal diagram ............................................................................................................. .............................................. 28 mii management (miim) interface................................................................................................ ....................................... 29 interrupt (int_n).............................................................................................................. .................................................... 29 led mode....................................................................................................................... ...................................................... 29 4-led configuration ............................................................................................................ ............................................. 30 5-led configuration ............................................................................................................ ............................................. 30 6-led configuration ............................................................................................................ ............................................. 31 nand tree suppor t .............................................................................................................. .............................................. 32 power management ............................................................................................................... ............................................. 33 power saving mode.............................................................................................................. ............................................ 33 software power down mode ....................................................................................................... ..................................... 33 chip power down mode ........................................................................................................... ........................................ 33 register map................................................................................................................... ..................................................... 34 register description ........................................................................................................... ................................................ 35 ieee defined registers ......................................................................................................... ........................................... 35 vendor specific registers ...................................................................................................... .......................................... 41
micrel, inc. KSZ9021GQ september 2010 5 m9999-091010-1.2 extended registers ............................................................................................................. ............................................. 44 absolute maximum ratings (1) ............................................................................................................................... ............. 46 operating ratings (2) ............................................................................................................................... ............................. 46 electrical characteristics (3) ............................................................................................................................... ................. 46 timing di agrams ................................................................................................................ ................................................. 49 gmii transmit timing ........................................................................................................... ............................................ 49 gmii receive timing ............................................................................................................ ............................................ 50 mii transmit timing ............................................................................................................ .............................................. 51 mii receive timing ............................................................................................................. .............................................. 52 auto-negotiat ion timing ........................................................................................................ ........................................... 53 mdc/mdio timing ................................................................................................................ ........................................... 54 reset timing................................................................................................................... .................................................. 55 reset circuit .................................................................................................................. ...................................................... 55 reference circuits ? led strap-in pins......................................................................................... ................................... 56 reference clock ? conne ction & se lection ....................................................................................... .............................. 57 magnetics speci ficati on ........................................................................................................ ............................................. 57 package info rmation ............................................................................................................ ............................................... 58
micrel, inc. KSZ9021GQ september 2010 6 m9999-091010-1.2 list of figures figure 1. KSZ9021GQ block diagram........................................................................................... .................................... 19 figure 2. KSZ9021GQ 1000base-t block diagram ? single channel............................................................... ............... 21 figure 3. auto-negotiation flow chart....................................................................................... ........................................ 24 figure 4. KSZ9021GQ gmii interface .......................................................................................... ..................................... 26 figure 5. KSZ9021GQ mii interface ........................................................................................... ....................................... 28 figure 6. gmii transmit timing ? data input to phy .......................................................................... .............................. 49 figure 7. gmii receive timing ? data input to mac ........................................................................... ............................. 50 figure 8. mii transmit timing ? data input to phy ........................................................................... ................................ 51 figure 9. mii receive timing ? data input to mac ............................................................................ ............................... 52 figure 10. auto-negotiation fast link pulse (flp) timing ...................................................................... ........................... 53 figure 11. mdc/mdio timing.................................................................................................... .......................................... 54 figure 12. reset timing....................................................................................................... ................................................ 55 figure 13. recommended reset circuit.......................................................................................... .................................... 55 figure 14. recommended reset circuit for inte rfacing with cpu/fpga reset output. .............................................. ...... 56 figure 15. reference circuits for led strapping pins.......................................................................... ............................... 56 figure 16. 25mhz crystal / oscilla tor reference clock connection .............................................................. ..................... 57
micrel, inc. KSZ9021GQ september 2010 7 m9999-091010-1.2 list of tables table 1. mdi / mdi-x pin mapping ............................................................................................ ........................................ 22 table 2. auto-negotiation timers ............................................................................................ .......................................... 25 table 3. gmii signal definition ............................................................................................. ............................................. 26 table 4. mii signal definition .............................................................................................. ............................................... 28 table 5. mii management frame format ? for KSZ9021GQ ........................................................................ .................... 29 table 6. 4-led confi guration ? pin definition ............................................................................... .................................... 30 table 7. 5-led confi guration ? pin definition ............................................................................... .................................... 30 table 8. 6-led confi guration ? pin definition ............................................................................... .................................... 31 table 9. nand tree test pin order ? for KSZ9021GQ ........................................................................... ......................... 32 table 10. gmii transmit timing parameters..................................................................................... .................................. 49 table 11. gmii receive timing parameters...................................................................................... .................................. 50 table 12. mii transmit timing parameters...................................................................................... .................................... 51 table 13. mii receive timing parameters....................................................................................... .................................... 52 table 14. auto-negotiation fast link pulse (flp) timing parameters ............................................................ ................... 53 table 15. mdc/mdio timing parameters .......................................................................................... ................................. 54 table 16. reset timing parameters ............................................................................................. ....................................... 55 table 17. reference crysta l/clock select ion criteria.......................................................................... ................................ 57 table 18. magnetics selection criteria ........................................................................................ ........................................ 57 table 19. qualified single port 10/100/1 000 magnetics......................................................................... ............................. 57
micrel, inc. KSZ9021GQ september 2010 8 m9999-091010-1.2 pin configuration 128-pin pqfp (top view)
micrel, inc. KSZ9021GQ september 2010 9 m9999-091010-1.2 pin description pin number pin name type (1) pin function 1 nc - no connect 2 nc - no connect 3 nc - no connect 4 nc - no connect 5 nc - no connect 6 nc - no connect 7 txrxp_a i/o media dependent interface[0], positive signal of differential pair 1000base-t mode: txrxp_a corresponds to bi_da+ for mdi configuration and bi_db+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_a is the positive transmit signal (tx+) for mdi configuration and the positive receive signal (rx+) for mdi-x configuration, respectively. 8 txrxm_a i/o media dependent interface[0], negative signal of differential pair 1000base-t mode: txrxm_a corresponds to bi_da- for mdi configuration and bi_db- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_a is the negative transmit signal (tx-) for mdi configuration and the negative receive signal (rx-) for mdi-x configuration, respectively. 9 avddh p 3.3v analog v dd 10 agndh gnd analog ground 11 agndl_adc_a gnd analog ground 12 avddl p 1.2v analog v dd 13 avddl p 1.2v analog v dd 14 agndl_adc_b gnd analog ground 15 agndh gnd analog ground 16 avddh p 3.3v analog v dd 17 txrxp_b i/o media dependent interface[1], positive signal of differential pair 1000base-t mode: txrxp_b corresponds to bi_db+ for mdi configuration and bi_da+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_b is the positive receive signal (rx+) for mdi configuration and the positive transmit signal (tx+) for mdi-x configuration, respectively. 18 txrxm_b i/o media dependent interface[1], negative signal of differential pair 1000base-t mode: txrxm_b corresponds to bi_db- for mdi configuration and bi_da- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_b is the negative receive signal (rx-) for mdi configuration and the negative transmit signal (tx-) for mdi-x configuration, respectively. 19 agndh gnd analog ground
micrel, inc. KSZ9021GQ september 2010 10 m9999-091010-1.2 pin number pin name type (1) pin function 20 txrxp_c i/o media dependent interface[2], positive signal of differential pair 1000base-t mode: txrxp_c corresponds to bi_dc+ for mdi configuration and bi_dd+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_c is not used. 21 txrxm_c i/o media dependent interface[2], negative signal of differential pair 1000base-t mode: txrxm_c corresponds to bi_dc- for mdi configuration and bi_dd- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_c is not used. 22 avddh p 3.3v analog v dd 23 agndh gnd analog ground 24 agndl_adc_c gnd analog ground 25 avddl p 1.2v analog v dd 26 avddl p 1.2v analog v dd 27 agndl_adc_d gnd analog ground 28 agndh gnd analog ground 29 avddh p 3.3v analog v dd 30 txrxp_d i/o media dependent interface[3], positive signal of differential pair 1000base-t mode: txrxp_d corresponds to bi_dd+ for mdi configuration and bi_dc+ for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxp_d is not used. 31 txrxm_d i/o media dependent interface[3], negative signal of differential pair 1000base-t mode: txrxm_d corresponds to bi_dd- for mdi configuration and bi_dc- for mdi-x configuration, respectively. 10base-t / 100base-tx mode: txrxm_d is not used. 32 avddh p 3.3v analog v dd 33 nc - no connect 34 nc - no connect 35 nc - no connect 36 nc - no connect 37 nc - no connect
micrel, inc. KSZ9021GQ september 2010 11 m9999-091010-1.2 pin number pin name type (1) pin function 38 led6 i/o led output: programmable led6 output the led6 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as followed: led_sel[1:0] = (1,1) // 6-led configuration (default) led_sel[1:0] = (0,1) // 5-led configuration 10base-t link pin state led definition link off h off link on l on led_sel[1:0] = (1,0) // 4-led configuration 10base-t ? link / activity pin state led definition link off h off link on l on activity (rx, tx) toggle blinking led_sel[1:0] = (0,0) // reserved ? not used 39 dvddl p 1.2v digital v dd 40 vss gnd digital ground 41 vss gnd digital ground 42 led5 / phyad4 i/o led output: programmable led5 output / configuration mode: the pull-up/pull-down value is latched as phyadd[4] during power-up / reset. see ?strapping options? section for details. the led5 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as followed: led_sel[1:0] = (1,1) // 6-led configuration (default) led_sel[1:0] = (0,1) // 5-led configuration 100base-t link pin state led definition link off h off link on l on led_sel[1:0] = (1,0) // 4-led configuration 100base-t ? link / activity pin state led definition link off h off link on l on activity (rx, tx) toggle blinking led_sel[1:0] = (0,0) // reserved ? not used
micrel, inc. KSZ9021GQ september 2010 12 m9999-091010-1.2 pin number pin name type (1) pin function 43 led4 / phyad3 i/o led output: programmable led4 output / configuration mode: the pull-up/pull-down value is latched as phyadd[3] during power-up / reset. see ?strapping options? section for details. the led4 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as follows: led_sel[1:0] = (1,1) // 6-led configuration (default) led_sel[1:0] = (0,1) // 5-led configuration 1000base-t link pin state led definition link off h off link on l on led_sel[1:0] = (1,0) // 4-led configuration 1000base-t ? link / activity pin state led definition link off h off link on l on activity (rx, tx) toggle blinking led_sel[1:0] = (0,0) // reserved ? not used 44 led3 / phyad2 i/o led output: programmable led3 output / configuration mode: the pull-up/pull-down value is latched as phyadd[2] during power-up / reset. see ?strapping options? section for details. the led3 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as follows: led_sel[1:0] = (1,1) // 6-led configuration (default) led_sel[1:0] = (0,1) // 5-led configuration led_sel[1:0] = (1,0) // 4-led configuration duplex / collision pin state led definition half duplex h off full duplex l on collision toggle blinking led_sel[1:0] = (0,0) // reserved ? not used
micrel, inc. KSZ9021GQ september 2010 13 m9999-091010-1.2 pin number pin name type (1) pin function 45 led2 / phyad1 i/o led output: programmable led2 output / configuration mode: the pull-up/pull-down value is latched as phyadd[1] during power-up / reset. see ?strapping options? section for details. the led2 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as follows: led_sel[1:0] = (1,1) // 6-led configuration (default) receive activity pin state led definition no receive activity h off receive activity l, toggle on, blinking led_sel[1:0] = (0,1) // reserved ? not used led2 pin is internally pulled high. led_sel[1:0] = (1,0) // reserved ? not used led2 pin is internally pulled high. led_sel[1:0] = (0,0) // reserved ? not used 46 dvddh p 3.3v or 2.5v digital v dd 47 vsspst gnd digital ground 48 led1 / phyad0 i/o led output: programmable led1 output / configuration mode: the pull-up/pull-down value is latched as phyadd[0] during power-up / reset. see ?strapping options? section for details. the led1 pin is programmed via register 11h bits [7:6], led_sel[1:0], and is defined as follows: led_sel[1:0] = (1,1) // 6-led configuration (default) transmit activity pin state led definition no transmit activity h off transmit activity l, toggle on, blinking led_sel[1:0] = (0,1) // 5-led configuration receive/transmit activity pin state led definition no receive/transmit activity h off receive/transmit activity l, toggle on, blinking led_sel[1:0] = (1,0) // reserved ? not used led1 pin is internally pulled high. led_sel[1:0] = (0,0) // reserved ? not used 49 dvddl p 1.2v digital v dd 50 vss gnd digital ground
micrel, inc. KSZ9021GQ september 2010 14 m9999-091010-1.2 pin number pin name type (1) pin function 51 txd0 i gmii mode: gmii txd0 (transmit data 0) input mii mode: mii txd0 (transmit data 0) input 52 txd1 i gmii mode: gmii txd1 (transmit data 1) input mii mode: mii txd1 (transmit data 1) input 53 txd2 i gmii mode: gmii txd2 (transmit data 2) input mii mode: mii txd2 (transmit data 2) input 54 txd3 i gmii mode: gmii txd3 (transmit data 3) input mii mode: mii txd3 (transmit data 3) input 55 vss gnd digital ground 56 dvddl p 1.2v digital v dd 57 dvddh p 3.3v or 2.5v digital v dd 58 txd4 i gmii mode: gmii txd4 (transmit data 4) input mii mode: this pin is not used and can be driven high or low 59 txd5 i gmii mode: gmii txd5 (transmit data 5) input mii mode: this pin is not used and can be driven high or low 60 txd6 i gmii mode: gmii txd6 (transmit data 6) input mii mode: this pin is not used and can be driven high or low 61 txd7 i gmii mode: gmii txd7 (transmit data 7) input mii mode: this pin is not used and can be driven high or low 62 vsspst gnd digital ground 63 dvddh p 3.3v or 2.5v digital v dd 64 tx_er i gmii mode: gmii tx_er (transmit error) input mii mode: mii tx_er (transmit error) input if gmii / mii mac does not provide the tx_er output signal, this pin should be tied low. 65 gtx_clk i gmii mode: gmii gtx_clk (transmit reference clock) input 66 vsspst gnd digital ground 67 tx_en i gmii mode: gmii tx_en (transmit enable) input mii mode: mii tx_en (transmit enable) input 68 dvddh p 3.3v or 2.5v digital v dd 69 dvddh p 3.3v or 2.5v digital v dd 70 rxd7 o gmii mode: gmii rxd7 (receive data 7) output mii mode: this pin is not used and is driven low. 71 vss gnd digital ground 72 vss gnd digital ground 73 rxd6 o gmii mode: gmii rxd6 (receive data 6) output mii mode: this pin is not used and is driven low. 74 dvddl p 1.2v digital v dd 75 dvddl p 1.2v digital v dd 76 rxd5 o gmii mode: gmii rxd5 (receive data 5) output mii mode: this pin is not used and is driven low. 77 rxd4 o gmii mode: gmii rxd4 (receive data 4) output mii mode: this pin is not used and is driven low.
micrel, inc. KSZ9021GQ september 2010 15 m9999-091010-1.2 pin number pin name type (1) pin function 78 rxd3 / mode3 i/o gmii mode: gmii rxd3 (receive data 3) output mii mode: mii rxd3 (receive data 3) output / configuration mode: the pull-up/pull-down value is latched as mode3 during power-up / reset. see ?strapping options? section for details. 79 vsspst gnd digital ground 80 vsspst gnd digital ground 81 dvddh p 3.3v or 2.5v digital v dd 82 dvddh p 3.3v or 2.5v digital v dd 83 rxd2 / mode2 i/o gmii mode: gmii rxd2 (receive data 2) output mii mode: mii rxd2 (receive data 2) output) / configuration mode: the pull-up/pull-down value is latched as mode2 during power-up / reset. see ?strapping options? section for details. 84 vss gnd digital ground 85 vss gnd digital ground 86 dvddl p 1.2v digital v dd 87 dvddl p 1.2v digital v dd 88 rxd1 / mode1 i/o gmii mode: gmii rxd1 (receive data 1) output mii mode: mii rxd1 (receive data 1) output / configuration mode: the pull-up/pull-down value is latched as mode1 during power-up / reset. see ?strapping options? section for details. 89 rxd0 / mode0 i/o gmii mode: gmii rxd0 (receive data 0) output mii mode: mii rxd0 (receive data 0) output / configuration mode: the pull-up/pull-down value is latched as mode0 during power-up / reset. see ?strapping options? section for details. 90 rx_dv / clk125_en i/o gmii mode: gmii rx_dv (receive data valid) output mii mode: mii rx_dv (receive data valid) output / configuration mode: latched as clk125_ndo output enable during power- up / reset. see ?strapping options? section for details. 91 vsspst gnd digital ground 92 dvddh p 3.3v or 2.5v digital v dd 93 rx_er o gmii mode: gmii rx_er (receive error) output mii mode: mii rx_er (receive error) output 94 rx_clk o gmii mode: gmii rx_clk (receive reference clock) output mii mode: mii rx_clk (receive reference clock) output 95 vsspst gnd digital ground 96 crs o gmii mode: gmii crs (carrier sense) output mii mode: mii crs (carrier sense) output 97 mdc ipu management data clock input this pin is the input reference clock for mdio (pin 98). 98 mdio ipu/o management data input / output this pin is synchronous to mdc (pin 97) and requires an external pull-up resistor to dvddh (digital v dd ) in a range from 1.0k to 4.7k .
micrel, inc. KSZ9021GQ september 2010 16 m9999-091010-1.2 pin number pin name type (1) pin function 99 col o gmii mode: gmii col (collision detected) output mii mode: mii col (collision detected) output 100 dvddh p 3.3v or 2.5v digital v dd 101 int_n o interrupt output this pin provides a programmable interrupt output and requires an external pull-up resistor to dvddh (digital v dd ) in a range from 1.0k to 4.7k when active low. register 1bh is the interrupt control/status register for programming the interrupt conditions and reading the interrupt status. register 1fh bit 14 sets the interrupt output to active low (default) or active high. 102 vss gnd digital ground 103 dvddl p 1.2v digital v dd 104 vss gnd digital ground 105 dvddl p 1.2v digital v dd 106 dvddh p 3.3v or 2.5v digital v dd 107 clk125_ndo o 125mhz clock output this pin provides a 125mhz reference clock output option for use by the mac. 108 vsspst gnd digital ground 109 vsspst gnd digital ground 110 reset_n ipu chip reset (active low) hardware pin configurations are strapped-in at the de-assertion (rising edge) of reset_n. see ?strapping options? section for more details. 111 nc - no connect 112 nc - no connect 113 vss gnd digital ground 114 dvddl p 1.2v digital v dd 115 tx_clk o mii mode: mii tx_clk (transmit reference clock) output 116 a1 i factory test pin ? float for normal operation 117 agndh gnd analog ground 118 ldo_o o on-chip 1.2v ldo controller output this pin drives the input gate of a p-channel mosfet to generate 1.2v for the chip?s core voltages. if 1.2v is provided by the system and this pin is not used, it can be left floating. 119 agndl_pll gnd analog ground 120 avddl_pll p 1.2v analog v dd for pll 121 avddl_pll p 1.2v analog v dd for vco 122 avddh p 3.3v analog v dd 123 xo o 25mhz crystal feedback this pin is a no connect if oscillator or external clock source is used. 124 xi i crystal / oscillator / external clock input 25mhz +/-50ppm tolerance 125 avddh p 3.3v analog v dd 126 iset i/o set transmit output level connect a 4.99k 1% resistor to ground on this pin 127 agndh_bg gnd analog ground 128 avddh p 3.3v analog v dd
micrel, inc. KSZ9021GQ september 2010 17 m9999-091010-1.2 note: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi-directional. ipu = input with internal pull-up. ipu/o = input with internal pull-up / output.
micrel, inc. KSZ9021GQ september 2010 18 m9999-091010-1.2 strapping options pin number pin name type (1) pin function 42 43 44 45 48 phyad4 phyad3 phyad2 phyad1 phyad0 i/o i/o i/o i/o i/o the phy address, phyad[4:0], is latched at power-up / reset and is configurable to any value from 1 to 31. each phy address bit is configured as follows: pull-up = 1 pull-down = 0 78 83 88 89 mode3 mode2 mode1 mode0 i/o i/o i/o i/o the mode[3:0] strap-in pins are latched at power-up / reset and are defined as follows: mode[3:0] mode 0000 reserved ? not used 0001 gmii / mii mode 0010 reserved ? not used 0011 reserved ? not used 0100 nand tree mode 0101 reserved ? not used 0110 reserved ? not used 0111 chip power down mode 1000 reserved ? not used 1001 reserved ? not used 1010 reserved ? not used 1011 reserved ? not used 1100 reserved ? not used 1101 reserved ? not used 1110 reserved ? not used 1111 reserved ? not used 90 clk125_en i/o clk125_en is latched at power-up / reset and is defined as follows: pull-up = enable 125mhz clock output pull-down = disable 125mhz clock output pin 107 (clk125_ndo) provides the 125mhz reference clock output option for use by the mac. notes: 1. i/o = bi-directional. 2. pin strap-ins are latched during power-up or reset. in some systems, the mac receive input pins may be driven during power- up or reset, and consequently cause the phy strap-in pins on the gmii/mii signals to be latched to the incorrect configuration. in this cas e, it is recommended to add external pull-ups/pull-downs on the phy strap-in pins to ensure the phy is configured to the correct pin str ap-in mode.
micrel, inc. KSZ9021GQ september 2010 19 m9999-091010-1.2 functional overview the KSZ9021GQ is a completely integrated triple speed (10base-t/100base-tx/1000base-t) ethernet physical layer transceiver solution for transmission and reception of data over a standard cat-5 unshielded twisted pair (utp) cable. its on-chip proprietary 1000base-t transceiver and manchester/mlt-3 signaling-based 10base-t/100base-tx transceivers are all ieee 802.3 compliant. the KSZ9021GQ reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential pairs and by integrating a ldo controller to drive a low cost mosfet to supply the 1.2v core. on the copper media interface, the KSZ9021GQ can automatically detect and correct for differential pair misplacements and polarity reversals, and correct propagation delays and re-sync timing between the four differential pairs, as specified in the ieee 802.3 standard for 1000base-t operation. the KSZ9021GQ provides the gmii/mii interface for a direct and seamless connection to gmacs in gigabit ethernet processors and switches for data transfer at 10/100/1000 mbps speed. the following figure shows a high-level block diagram of the KSZ9021GQ. figure 1. KSZ9021GQ block diagram
micrel, inc. KSZ9021GQ september 2010 20 m9999-091010-1.2 functional description: 10base-t/100base-tx transceiver 100base-tx transmit the 100base-tx transmit function performs parallel to serial conversion, 4b/5b coding, scrambling, nrz-to-nrzi conversion, and mlt-3 encoding and transmission. the circuitry starts with a parallel-to-serial conversion, whic h converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding, followed by a scrambler. the serialized data is further converted from nrz-to-nrzi format, and then transmitted in mlt-3 current output. the output current is set by an external 4.99k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ansi tp-pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave-shaped 10base-t output is also incorporated into the 100base-tx transmitter. 100base-tx receive the 100base-tx receiver function performs adaptive equalization, dc restoration, mlt-3-to-nrzi conversion, data and clock recovery, nrzi-to-nrz conversion, de-scrambling, 4b/5b decoding, and serial-to-parallel conversion. the receiving side starts with the equalization filter to compensate for inter-symbol interference (isi) over the twisted pair cable. since the amplitude loss and phase distortion is a function of the cable length, the equalizer must adjust its characteristics to optimize performance. in this design, the variable equalizer makes an initial estimation based on comparisons of incoming signal strength against some known cable characteristics, and then tunes itself for optimization. this is an ongoing process and self-adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc restoration and data conversion block. the dc restoration circuit is used to compensate for the effect of baseline wander and to improve the dynamic range. the differential data conversion circuit converts the mlt-3 format back to nrzi. the slicing threshold is also adaptive. the clock recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this recovered clock is then used to convert the nrzi signal into the nrz format. this signal is sent through the de-scrambler followed by the 4b/5b decoder. finally, the nrz serial data is converted to the gmii/mii format and provided as the input data to the mac. scrambler/de-scrambler (100base-tx only) the purpose of the scrambler is to spread the power spectrum of the signal to reduce electromagnetic interference (emi) and baseline wander. transmitted data is scrambled through the use of an 11-bit wide linear feedback shift register (lfsr). the scrambler generates a 2047-bit non-repetitive sequence, and the receiver then de-scrambles the incoming data stream using the same sequence as at the transmitter. 10base-t transmit the output 10base-t driver is incorporated into the 100base-tx driver to allow transmission with the same magnetic. they are internally wave-shaped and pre-emphasized into typical outputs of 2.5v amplitude. the harmonic contents are at least 31 db below the fundamental when driven by an all-ones manchester-encoded signal. 10base-t receive on the receive side, input buffer and level detecting squelch circuits are employed. a differential input receiver circuit and a phase-locked loop (pll) perform the decoding function. the manchester-encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 300 mv or with short pulse widths in order to prevent noises at the receive inputs from falsely triggering the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the KSZ9021GQ decodes a data frame. the receiver clock is maintained active during idle periods in between receiving data frames.
micrel, inc. KSZ9021GQ september 2010 21 m9999-091010-1.2 functional description: 1000base-t transceiver the 1000base-t transceiver is based-on a mixed-signal / digital signal processing (dsp) architecture, which includes the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancellers, cross-talk cancellers, precision clock recovery scheme, and power efficient line drivers. the following figure shows a high-level block diagram of a single channel of the 1000base-t transceiver for one of the four differential pairs. clock generation baseline wander compensation echo canceller transmit block next canceller next canceller next canceller rx- adc agc + ffe slicer clock & phase recovery auto- negotiation pma state machines mii registers mii management control dfe analog hybrid pcs state machines pair swap & align unit descrambler + decoder side-stream scrambler & symbol encoder led driver xtal other channels tx signal rx signal figure 2. KSZ9021GQ 1000base-t block diagram ? single channel analog echo cancellation circuit in 1000base-t mode, the analog echo cancellation circuit helps to reduce the near-end echo. this analog hybrid circuit relieves the burden of the adc and the adaptive equalizer. this circuit is disabled in 10base-t/100base-tx mode. automatic gain control (agc) in 1000base-t mode, the automatic gain control (agc) circuit provides initial gain adjustment to boost up the signal level. this pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal. analog-to-digital converter (adc) in 1000base-t mode, the analog-to-digital converter (adc) digitizes the incoming signal. adc performance is essential to the overall performance of the transceiver. this circuit is disabled in 10base-t/100base-tx mode.
micrel, inc. KSZ9021GQ september 2010 22 m9999-091010-1.2 timing recovery circuit in 1000base-t mode, the mixed-signal clock recovery circuit together with the digital phase locked loop is used to recover and track the incoming timing information from the received data. the digital phase locked loop has very low long-term jitter to maximize the signal-to-noise ratio of the receive signal. the 1000base-t slave phy is required to transmit the exact receive clock frequency recovered from the received data back to the 1000base-t master phy. otherwise, the master and slave will not be synchronized after long transmission. additionally, this helps to facilitate echo cancellation and next removal. adaptive equalizer in 1000base-t mode, the adaptive equalizer provides the following functions: ? detection for partial response signaling ? removal of next and echo noise ? channel equalization signal quality is degraded by residual echo that is not removed by the analog hybrid and echo due to impedance mismatch. the KSZ9021GQ employs a digital echo canceller to further reduce echo components on the receive signal. in 1000base-t mode, data transmission and reception occurs simultaneously on all four pairs of wires (four channels). this results in high frequency cross-talk coming from adjacent wires. the KSZ9021GQ employs three next cancellers on each receive channel to minimize the cross-talk induced by the other three channels. in 10base-t/100base-tx mode, the adaptive equalizer needs only to remove the inter-symbol interference and recover the channel loss from the incoming data. trellis encoder and decoder in 1000base-t mode, the transmitted 8-bit data is scrambled into 9-bit symbols and further encoded into 4d-pam5 symbols. the initial scrambler seed is determined by the specific phy address to reduce emi when more than one KSZ9021GQ are used on the same board. on the receiving side, the idle stream is examined first. the scrambler seed, pair skew, pair order and polarity have to be resolved through the logic. the incoming 4d-pam5 data is then converted into 9-bit symbols and then de-scrambled into 8-bit data. functional description: additional 10/100/1000 phy features auto mdi/mdi-x the automatic mdi/mdi-x feature eliminates the need to determine whether to use a straight cable or a crossover cable between the KSZ9021GQ and its link partner. this auto-sense function detects the mdi/mdi-x pair mapping from the link partner, and then assigns the mdi/mdi-x pair mapping of the KSZ9021GQ accordingly. the following table shows the KSZ9021GQ 10/100/1000 pin-out assignments for mdi/mdi-x pin mapping. mdi mdi-x pin (rj-45 pair) 1000base-t 100base-tx 10base-t 1000base-t 100base-tx 10base-t txrxp/m_a (1,2) a+/- tx+/- tx+/- b+/- rx+/- rx+/- txrxp/m_b (3,6) b+/- rx+/- rx+/- a+/- tx+/- tx+/- txrxp/m_c (4,5) c+/- not used not used d+/- not used not used txrxp/m_d (7,8) d+/- not used not used c+/- not used not used table 1. mdi / mdi-x pin mapping auto mdi/mdi-x is enabled by default. it is disabled by writing a one to register 28 (1ch) bit 6. mdi and mdi-x mode is set by register 28 (1ch) bit 7 if auto mdi/mdi-x is disabled. an isolation transformer with symmetrical transmit and receive data paths is recommended to support auto mdi/mdi-x.
micrel, inc. KSZ9021GQ september 2010 23 m9999-091010-1.2 pair- swap, alignment, and polarity check in 1000base-t mode, the KSZ9021GQ ? detects incorrect channel order and automatically restore the pair order for the a, b, c, d pairs (four channels) ? supports 50+/-10ns difference in propagation delay between pairs of channels in accordance with the ieee 802.3 standard, and automatically corrects the data skew so the corrected 4-pairs of data symbols are synchronized incorrect pair polarities of the differential signals are automatically corrected for all speeds. wave shaping, slew rate control and partial response in communication systems, signal transmission encoding methods are used to provide the noise-shaping feature and to minimize distortion and error in the transmission channel. ? for 1000base-t, a special partial response signaling method is used to provide the band-limiting feature for the transmission path. ? for 100base-tx, a simple slew rate control method is used to minimize emi. ? for 10base-t, pre-emphasis is used to extend the signal quality through the cable. pll clock synthesizer the KSZ9021GQ generates 125 m z, 25 m z and 10 m z clocks for system timing. internal clocks are generated from the external 25 mhz crystal or reference clock. auto-negotiation the KSZ9021GQ conforms to the auto-negotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto-negotiation allows utp (unshielded twisted pair) link partners to select the highest common mode of operation. during auto-negotiation, link partners advertise capabilities across the utp link to each other, and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest. ? priority 1: 1000base-t, full-duplex ? priority 2: 1000base-t, half-duplex ? priority 3: 100base-tx, full-duplex ? priority 4: 100base-tx, half-duplex ? priority 5: 10base-t, full-duplex ? priority 6: 10base-t, half-duplex if auto-negotiation is not supported or the KSZ9021GQ link partner is forced to bypass auto-negotiation for 10base-t and 100base-tx modes, then the KSZ9021GQ sets its operating mode by observing the input signal at its receiver. this is known as parallel detection, and allows the KSZ9021GQ to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. the auto-negotiation link up process is shown in the following flow chart.
micrel, inc. KSZ9021GQ september 2010 24 m9999-091010-1.2 figure 3. auto-negotiation flow chart for 1000base-t mode, auto-negotiation is required and always used to establish a link. during 1000base-t auto- negotiation, the master and slave configuration is first resolved between link partners, and then the link is established with the highest common capabilities between link partners. auto-negotiation is enabled by default at power-up or after hardware reset. afterwards, auto-negotiation can be enabled or disabled through register 0 bit 12. if auto-negotiation is disabled, the speed is set by register 0 bits 6 and 13, and the duplex is set by register 0 bit 8. if the speed is changed on the fly, the link goes down and either auto-negotiation or parallel detection will initiate until a common speed between KSZ9021GQ and its link partner is re-established for a link. if link is already established and there is no change of speed on the fly, then the changes will not take effect unless either auto-negotiation is restarted through register 0 bit 9, or a link down to link up transition occurs (i.e., disconnecting and reconnecting the cable). after auto-negotiation is completed, the link status is updated in register 1 and the link partner capabilities are updated in registers 5, 6, and 10. the auto-negotiation finite state machines employ interval timers to manage the auto-negotiation process. the duration of these timers under normal operating conditions are summarized in the following table.
micrel, inc. KSZ9021GQ september 2010 25 m9999-091010-1.2 auto-negotiation interval timers time duration transmit burst interval 16 ms transmit pulse interval 68 us flp detect minimum time 17.2 us flp detect maximum time 185 us receive minimum burst interval 6.8 ms receive maximum burst interval 112 ms data detect minimum interval 35.4 us data detect maximum interval 95 us nlp test minimum interval 4.5 ms nlp test maximum interval 30 ms link loss time 52 ms break link time 1480 ms parallel detection wait time 830 ms link enable wait time 1000 ms table 2. auto-negotiation timers gmii interface the gigabit media independent interface (gmii) is compliant to the ieee 802.3 specification. it provides a common interface between gmii phys and macs, and has the following key characteristics: ? pin count is 24 pins (11 pins for data transmission, 11 pins for data reception, and 2 pins for carrier and collision indication). ? 1000mbps is supported at both half and full duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 8-bit wide, a byte. in gmii operation, the gmii pins function as follow: ? the mac sources the transmit reference clock, gtx_clk, at 125mhz for 1000mbps. ? the phy recovers and sources the receive reference clock, rx_clk, at 125mhz for 1000mbps. ? tx_en, txd[7:0] and tx_er are sampled by the KSZ9021GQ on the rising edge of gtx_clk. ? rx_dv, rxd[7:0], and rx_er are sampled by the mac on the rising edge of rx_clk. ? crs and col are driven by the KSZ9021GQ and are not required to transition synchronously with respect to either gtx_clk or rx_clk. the KSZ9021GQ combines gmii mode with mii mode to form gmii/mii mode to support data transfer at 10/100/1000 mbps speed. after power-up or reset, the KSZ9021GQ is configured to gmii/mii mode if the mode[3:0] strap-in pins are set to 0001. see strapping options section. the KSZ9021GQ has the option to output a low jitter 125mhz reference clock on clk125_ndo (pin 107). this clock provides a lower cost reference clock alternative for gmii/mii macs that require a 125mhz crystal or oscillator. the 125mhz clock output is enabled after power-up or reset if the clk125_en strap-in pin is pulled high. the KSZ9021GQ provides a dedicated transmit clock input pin for gmii mode, defined as follow: ? gtx_clk (input, pin 65): sourced by mac in gmii mode for 1000mbps speed
micrel, inc. KSZ9021GQ september 2010 26 m9999-091010-1.2 gmii signal definition the following table describes the gmii signals. refer to clause 35 of the ieee 802.3 specification for more detailed information. gmii signal name (per spec) gmii signal name (per KSZ9021GQ) pin type (with respect to phy) pin type (with respect to mac) description gtx_clk gtx_clk input output transmit reference clock (125mhz for 1000mbps) tx_en tx_en input output transmit enable txd[7:0] txd[7:0] input output transmit data [7:0] tx_er tx_er input output transmit error rx_clk rx_clk output input receive reference clock (125mhz for 1000mbps) rx_dv rx_dv output input receive data valid rxd[7:0] rxd[7:0] output input receive data [7:0] rx_er rx_er output input receive error crs crs output input carrier sense col col output input collision detected table 3. gmii signal definition gmii signal diagram the KSZ9021GQ gmii pin connections to the mac are shown in the following figure. figure 4. KSZ9021GQ gmii interface
micrel, inc. KSZ9021GQ september 2010 27 m9999-091010-1.2 mii interface the media independent interface (mii) is compliant with the ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 16 pins (7 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). ? 10mbps and 100mbps are supported at both half and full duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4-bit wide, a nibble. in mii operation, the mii pins function as follow: ? the phy sources the transmit reference clock, tx_clk, at 25mhz for 100mbps and 2.5mhz for 10mbps. ? the phy recovers and sources the receive reference clock, rx_clk, at 25mhz for 100mbps and 2.5mhz for 10mbps. ? tx_en, txd[3:0] and tx_er are driven by the mac and shall transition synchronously with respect to tx_clk. ? rx_dv, rxd[3:0], and rx_er are driven by the KSZ9021GQ and shall transition synchronously with respect to rx_clk. ? crs and col are driven by the KSZ9021GQ and are not required to transition synchronously with respect to either tx_clk or rx_clk. the KSZ9021GQ combines gmii mode with mii mode to form gmii/mii mode to support data transfer at 10/100/1000 mbps speed. after the power-up or reset, the KSZ9021GQ is then configured to gmii/mii mode if the mode[3:0] strap-in pins are set to 0001. see strapping options section. the KSZ9021GQ has the option to output a low jitter 125mhz reference clock on clk125_ndo (pin 107). this clock provides a lower cost reference clock alternative for gmii/mii macs that require a 125mhz crystal or oscillator. the 125mhz clock output is enabled after power-up or reset if the clk125_en strap-in pin is pulled high. the KSZ9021GQ provides a dedicated transmit clock output pin for mii mode, defined as follow: ? tx_clk (output, pin 115) : sourced by KSZ9021GQ in mii mode for 10/100mbps speed
micrel, inc. KSZ9021GQ september 2010 28 m9999-091010-1.2 mii signal definition the following table describes the mii signals. refer to clause 22 of the ieee 802.3 specification for detailed information. mii signal name (per spec) mii signal name (per KSZ9021GQ) pin type (with respect to phy) pin type (with respect to mac) description tx_clk tx_clk output input transmit reference clock (25mhz for 100mbps, 2.5mhz for 10mbps) tx_en tx_en input output transmit enable txd[3:0] txd[3:0] input output transmit data [3:0] tx_er tx_er input output transmit error rx_clk rx_clk output input receive reference clock (25mhz for 100mbps, 2.5mhz for 10mbps) rx_dv rx_dv output input receive data valid rxd[3:0] rxd[3:0] output input receive data [3:0] rx_er rx_er output input receive error crs crs output input carrier sense col col output input collision detected table 4. mii signal definition mii signal diagram the KSZ9021GQ mii pin connections to the mac are shown in the following figure. figure 5. KSZ9021GQ mii interface
micrel, inc. KSZ9021GQ september 2010 29 m9999-091010-1.2 mii management (miim) interface the KSZ9021GQ supports the ieee 802.3 mii management interface, also known as the management data input / output (mdio) interface. this interface allows upper-layer devices to monitor and control the state of the KSZ9021GQ. an external device with miim capability is used to read the phy status and/or configure the phy settings. further detail on the miim interface can be found in clause 22.2.4.5 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the aforementioned physical connection that allows an external controller to communicate with one or more KSZ9021GQ device. each KSZ9021GQ device is assigned a phy address between 1 and 31 by the phyad[4:0] strapping pins. ? a 32 register address space to access the KSZ9021GQ ieee defined registers, vendor specific registers and extended registers. see register map section. the following table shows the mii management frame format for the KSZ9021GQ. preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta data bits [15:0] idle read 32 1?s 01 10 aaaaa rrrrr z0 dddddddd_dddddddd z write 32 1?s 01 01 aaaaa rrrrr 10 dddddddd_dddddddd z table 5. mii management frame format ? for KSZ9021GQ interrupt (int_n) int_n (pin 101) is an optional interrupt signal that is used to inform the external controller that there has been a status update in the KSZ9021GQ phy register. bits [15:8] of register 27 (1bh) are the interrupt control bits to enable and disable the conditions for asserting the int_n signal. bits [7:0] of register 27 (1bh) are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading register 27 (1bh). bit 14 of register 31 (1fh) sets the interrupt level to active high or active low. the default is active low. the mii management bus option gives the mac processor complete access to the KSZ9021GQ control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll the phy for status change. led mode the KSZ9021GQ provides six programmable led output pins (led1 thru led6) that are configurable to support three led modes. bits [7:6] of register 17 (11h) are the led mode select [1:0] bits, and are defined as follow: ? 00 = reserved ? not used ? 10 = 4-led configuration ? 01 = 5-led configuration ? 11 = 6-led configuration (default setting after power-up / reset)
micrel, inc. KSZ9021GQ september 2010 30 m9999-091010-1.2 4-led configuration in this led mode, the link and activity are combined into one led for each speed. the unused pins led2 and led1 are internally pulled high. led pin pin state led definition description h off 10base-t, link off l on 10base-t, link on led6 toggle blinking 10base-t, activity h off 100base-tx, link off l on 100base-tx, link on led5 toggle blinking 100base-tx, activity h off 1000base-t, link off l on 1000base-t, link on led4 toggle blinking 1000base-t, activity h off half-duplex l on full-duplex led3 toggle blinking collision table 6. 4-led configuration ? pin definition 5-led configuration in this led mode, the transmit and receive activities are combined into pin led1. the unused pin led2 is internally pulled high. led pin pin state led definition description h off 10base-t, link off led6 l on 10base-t, link on h off 100base-tx, link off led5 l on 100base-tx, link on h off 1000base-t, link off led4 l on 1000base-t, link on h off half-duplex l on full-duplex led3 toggle blinking collision h off no activity l on led1 toggle blinking transmit or receive activity table 7. 5-led configuration ? pin definition
micrel, inc. KSZ9021GQ september 2010 31 m9999-091010-1.2 6-led configuration in this led mode, all six led pins are used. pins led2 and led1 are dedicated for receive activity and transmit activity, respectively, for all speeds. led pin pin state led definition description h off 10base-t, link off led6 l on 10base-t, link on h off 100base-tx, link off led5 l on 100base-tx, link on h off 1000base-t, link off led4 l on 1000base-t, link on h off half-duplex l on full-duplex led3 toggle blinking collision h off no receive activity l on led2 toggle blinking receive activity h off no transmit activity l on led1 toggle blinking transmit activity table 8. 6-led configuration ? pin definition each led output pin can directly drive a led with a series resistor (typically 220 ? to 470 ? ). for activity indication, the led output toggles at approximately 12.5hz (80ms) to ensure visibility to the human eye.
micrel, inc. KSZ9021GQ september 2010 32 m9999-091010-1.2 nand tree support the KSZ9021GQ provides parametric nand tree support for fault detection between chip i/os and board. the nand tree mode is enabled at power-up / reset with the mode[3:0] strap-in pins set to 0100. the following table lists the nand tree pin order. pin description led6 input led5 input led4 input led3 input led2 input led1 input txd0 input txd1 input txd2 input txd3 input txd4 input txd5 input txd6 input txd7 input tx_er input gtx_clk input tx_en input rxd7 input rxd6 input rxd5 input rxd4 input rx_dv input rx_er input rx_clk input crs input col input int_n input mdc input a1 input mdio input clk125_ndo output table 9. nand tree test pin order ? for KSZ9021GQ
micrel, inc. KSZ9021GQ september 2010 33 m9999-091010-1.2 power management the KSZ9021GQ offers the following power management modes: power saving mode this mode is a KSZ9021GQ green feature to reduce power consumption when the cable is unplugged. it is in effect when auto-negotiation mode is enabled and the cable is disconnected (no link). software power down mode this mode is used to power down the KSZ9021GQ device when it is not in use after power-up. power down mode is enabled by writing a one to register 0h bit 11. in the power down state, the KSZ9021GQ disables all internal functions, except for the mii management interface. the KSZ9021GQ exits power down mode after writing a zero to register 0h bit 11. chip power down mode this mode provides the lowest power state for the KSZ9021GQ when it is not in use and is mounted on the board. chip power down mode is enabled at power-up / reset with the mode[3:0] strap-in pins set to 0111. the KSZ9021GQ exits chip power down mode when a hardware reset is applied to reset_n (pin 110) with the mode[3:0] strap-in pins set to an operating mode other than chip power down mode.
micrel, inc. KSZ9021GQ september 2010 34 m9999-091010-1.2 register map the ieee 802.3 specification provides a 32 register address space for the phy. registers 0 thru 15 are standard phy registers, defined per the specification. registers 16 thru 31 are vendor specific registers. the KSZ9021GQ uses the ieee provided register space for ieee defined registers and vendor specific registers, and uses the following registers to access extended registers: ? register 11 (bh) for extended register ? control ? register 12 (ch) for extended register ? data write ? register 13 (dh) for extended register ? data read examples: ? extended register read // read from operation mode strap status register 1. write register 11 (bh) with 0103h // set register 259 (103h) for read 2. read register 13 (dh) // read register value ? extended register write // write to operation mode strap override register 1. write register 11 (bh) with 8102h // set register 258 (102h) for write 2. write register 12 (ch) with 0010h // write 0010h value to register to set nand tree mode register number (hex) description ieee defined registers 0 (0h) basic control 1 (1h) basic status 2 (2h) phy identifier 1 3 (3h) phy identifier 2 4 (4h) auto-negotiation advertisement 5 (5h) auto-negotiation link partner ability 6 (6h) auto-negotiation expansion 7 (7h) auto-negotiation next page 8 (8h) auto-negotiation link partner next page ability 9 (9h) 1000base-t control 10 (ah) 1000base-t status 11 (bh) extended register ? control 12 (ch) extended register ? data write 13 (dh) extended register ? data read 14 (eh) reserved 15 (fh) extended ? mii status vendor specific registers 16 (10h) reserved 17 (11h) remote loopback, led mode 18 (12h) linkmd ? ? cable diagnostic 19 (13h) digital pma/pcs status 20 (14h) reserved 21 (15h) rxer counter 22 (16h) ? 26 (1ah) reserved
micrel, inc. KSZ9021GQ september 2010 35 m9999-091010-1.2 register number (hex) description 27 (1bh) interrupt control/status 28 (1ch) digital debug control 1 29 (1dh) ? 30 (1eh) reserved 31 (1fh) phy control extended registers 257 (101h) strap status 258 (102h) operation mode strap override 259 (103h) operation mode strap status 263 (107h) analog test register register description ieee defined registers address name description mode (1) default register 0 (0h) ? basic control 0.15 reset 1 = software phy reset 0 = normal operation this bit is self-cleared after a ?1? is written to it rw/sc 0 0.14 loop-back 1 = loop-back mode 0 = normal operation rw 0 0.13 speed select (lsb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000mbps [0,1] = 100mbps [0,0] = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1) rw hardware setting 0.12 auto- negotiation enable 1 = enable auto-negotiation process 0 = disable auto-negotiation process if enabled, auto-negotiation result overrides settings in register 0.13, 0.8 and 0.6 rw 1 0.11 power down 1 = power down mode 0 = normal operation rw 0 0.10 isolate 1 = electrical isolation of phy from gmii/mii 0 = normal operation rw 0 0.9 restart auto- negotiation 1 = restart auto-negotiation process 0 = normal operation this bit is self-cleared after a ?1? is written to it rw/sc 0 0.8 duplex mode 1 = full-duplex 0 = half-duplex rw hardware setting 0.7 collision test 1 = enable col test 0 = disable col test rw 0
micrel, inc. KSZ9021GQ september 2010 36 m9999-091010-1.2 address name description mode (1) default 0.6 speed select (msb) [0.6, 0.13] [1,1] = reserved [1,0] = 1000mbps [0,1] = 100mbps [0,0] = 10mbps this bit is ignored if auto-negotiation is enabled (register 0.12 = 1) rw 0 0.5:0 reserved ro 00_0000 register 1 (1h) ? basic status 1.15 100base-t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base-tx full duplex 1 = capable of 100mbps full-duplex 0 = not capable of 100mbps full-duplex ro 1 1.13 100base-tx half duplex 1 = capable of 100mbps half-duplex 0 = not capable of 100mbps half-duplex ro 1 1.12 10base-t full duplex 1 = capable of 10mbps full-duplex 0 = not capable of 10mbps full-duplex ro 1 1.11 10base-t half duplex 1 = capable of 10mbps half-duplex 0 = not capable of 10mbps half-duplex ro 1 1.10:9 reserved ro 00 1.8 extended status 1 = extended status information in reg. 15 0 = no extended status information in reg. 15 ro 1 1.7 reserved ro 0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto-negotiation process completed 0 = auto-negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = capable to perform auto-negotiation 0 = not capable to perform auto-negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capabilities registers ro 1 register 2 (2h) ? phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizationally unique identifier (oui) kendin communication?s oui is 0010a1 (hex) ro 0022h
micrel, inc. KSZ9021GQ september 2010 37 m9999-091010-1.2 address name description mode (1) default register 3 (3h) ? phy identifier 2 3.15:10 phy id number assigned to the 19th through 24 th bits of the organizationally unique identifier (oui) kendin communication?s oui is 0010a1 (hex) ro 0001_01 3.9:4 model number six bit manufacturer?s model number ro 10_0001 3.3:0 revision number four bit manufacturer?s revision number ro indicates silicon revision register 4 (4h) ? auto-negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capability rw 0 4.14 reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved ro 0 4.11:10 pause [4.11, 4.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric & asymmetric pause (local device) rw 00 4.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 4.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability rw 1 4.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability rw 1 4.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability rw 1 4.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5 (5h) ? auto-negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved ro 0
micrel, inc. KSZ9021GQ september 2010 38 m9999-091010-1.2 address name description mode (1) default 5.11:10 pause [5.11, 5.10] [0,0] = no pause [1,0] = asymmetric pause (link partner) [0,1] = symmetric pause [1,1] = symmetric & asymmetric pause (local device) rw 00 5.9 100base-t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base-tx full-duplex 1 = 100mbps full-duplex capable 0 = no 100mbps full-duplex capability ro 0 5.7 100base-tx half-duplex 1 = 100mbps half-duplex capable 0 = no 100mbps half-duplex capability ro 0 5.6 10base-t full-duplex 1 = 10mbps full-duplex capable 0 = no 10mbps full-duplex capability ro 0 5.5 10base-t half-duplex 1 = 10mbps half-duplex capable 0 = no 10mbps half-duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0000 register 6 (6h) ? auto-negotiation expansion 6.15:5 reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link partner has auto-negotiation capability 0 = link partner does not have auto-negotiation capability ro 0 register 7 (7h) ? auto-negotiation next page 7.15 next page 1 = additional next page(s) will follow 0 = last page rw 0 7.14 reserved ro 0 7.13 message page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic one 0 = logic zero ro 0 7.10:0 message field 11-bit wide field to encode 2048 messages rw 000_0000_0001
micrel, inc. KSZ9021GQ september 2010 39 m9999-091010-1.2 address name description mode (1) default register 8 (8h) ? auto-negotiation link partner next page ability 8.15 next page 1 = additional next page(s) will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt of link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = able to act on the information 0 = not able to act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic zero 0 = previous value of transmitted link code word equal to logic one ro 0 8.10:0 message field ro 000_0000_0000 register 9 (9h) ? 1000base-t control 9:15:13 test mode bits transmitter test mode operations [9.15:13] mode [000] normal operation [001] test mode 1 ?transmit waveform test [010] test mode 2 ?transmit jitter test in master mode [011] test mode 3 ?transmit jitter test in slave mode [100] test mode 4 ?transmitter distortion test [101] reserved, operations not identified [110] reserved, operations not identified [111] reserved, operations not identified rw 000 9.12 master- slave manual configuration enable 1 = enable master-slave manual configuration value 0 = disable master-slave manual configuration value rw 0 9.11 master- slave manual configuration value 1 = configure phy as master during master-slave negotiation 0 = configure phy as slave during master- slave negotiation this bit is ignored if master-slave manual configuration is disabled (register 9.12 = 0) rw 0
micrel, inc. KSZ9021GQ september 2010 40 m9999-091010-1.2 address name description mode (1) default 9.10 port type 1 = indicate the preference to operate as multiport device (master) 0 = indicate the preference to operate as single- port device ( slave ) this bit is valid only if the master-slave manual config enable bit is disabled (register 9.12 = 0) rw 0 9.9 1000base-t full-duplex 1 = advertise phy is 1000base-t full-duplex capable 0 = advertise phy is not 1000base-t full- duplex capable rw 1 9.8 1000base-t half-duplex 1 = advertise phy is 1000base-t half-duplex capable 0 = advertise phy is not 1000base-t half- duplex capable rw hardware setting 9.7:0 reserved write as 0, ignore on read ro register 10 (ah) ? 1000base-t status 10.15 master- slave configuration fault 1 = master-slave configuration fault detected 0 = no master-slave configuration fault detected ro/lh/sc 0 10.14 master- slave configuration resolution 1 = local phy configuration resolved to master 0 = local phy configuration resolved to slave ro 0 10.13 local receiver status 1 = local receiver ok (loc_rcvr_status = 1) 0 = local receiver not ok (loc_rcvr_status = 0) ro 0 10.12 remote receiver status 1 = remote receiver ok (rem_rcvr_status = 1) 0 = remote receiver not ok (rem_rcvr_status = 0) ro 0 10.11 lp 1000t fd 1 = link partner is capable of 1000base-t full- duplex 0 = link partner is not capable of 1000base-t full-duplex ro 0 10.10 lp 1000t hd 1 = link partner is capable of 1000base-t half- duplex 0 = link partner is not capable of 1000base-t half-duplex ro 0 10.9:8 reserved ro 00 10.7:0 idle error count cumulative count of errors detected when receiver is receiving idles and pma_txmode.indicate = send_n the counter is incremented every symbol period that rxerror_status = error ro/sc 0000_0000 register 11 (bh) ? extended register ? control 11.15 extended register ? read/write select 1 = write extended register 0 = read extended register rw 0
micrel, inc. KSZ9021GQ september 2010 41 m9999-091010-1.2 address name description mode (1) default 11.14:9 reserved rw 000_000 11.8 extended register ? page select page for extended register rw 0 11.7:0 extended register ? address select extended register address rw 0000_0000 register 12 (ch) ? extended register ? data write 12.15:0 extended register ? write 16-bit value to write to extend register address in register 11 (bh) bits [7:0] rw 0000_0000_0000_0000 register 13 (dh) ? extended register ? data read 13.15:0 extended register ? read 16-bit value read from extend register address in register 11 (bh) bits [7:0] ro 0000_0000_0000_0000 register 15 (fh) ? extended ? mii status 15.15 1000base-x full-duplex 1 = phy able to perform 1000base-x full-duplex 0 = phy not able to perform 1000base-x full-duplex ro 0 15.14 1000base-x half-duplex 1 = phy able to perform 1000base-x half-duplex 0 = phy not able to perform 1000base-x half-duplex ro 0 15.13 1000base-t full-duplex 1 = phy able to perform 1000base-t full-duplex 1000base-x 0 = phy not able to perform 1000base-t full-duplex ro 1 15.12 1000base-t half-duplex 1 = phy able to perform 1000base-t half-duplex 0 = phy not able to perform 1000base-t half-duplex ro 1 15.11:0 reserved ignore when read ro - note: 1. rw = read/write. ro = read only. sc = self-cleared. lh = latch high. ll = latch low. vendor specific registers address name description mode (1) default register 17 (11h) ? remote loopback, led mode 17.15:9 reserved rw 0000_001
micrel, inc. KSZ9021GQ september 2010 42 m9999-091010-1.2 address name description mode (1) default 17.8 remote loopback 1 = enable remote loopback 0 = disable remote loopback rw 0 17.7:6 led mode select [17.7, 17.6] [0,0] = reserved ? not used [1,0] = 4-led configuration [0,1] = 5-led configuration [1,1] = 6-led configuration rw 11 17.5:4 reserved rw 11 17.3 led test enable 1 = enable led test mode 0 = disable led test mode rw 0 17.2:1 reserved rw 00 17.0 reserved ro 0 register 18 (12h) ? linkmd ? ? cable diagnostic 18.15 reserved rw/sc 0 18.14:8 reserved rw 000_0000 18.7:0 reserved ro 0000_0000 register 19 (13h) ? digital pma/pcs status 19.15:3 reserved ro/lh 0000_0000_0000_0 19.2 1000base-t link status 1000 base-t link status 1 = link status is ok 0 = link status is not ok ro 0 19.1 100base-tx link status 100 base-tx link status 1 = link status is ok 0 = link status is not ok ro 0 19.0 reserved ro 0 register 21 (15h) ? rxer counter 21.15:0 rxer counter receive error counter for symbol error frames ro/rc 0000_0000_0000_0000 register 27 (1bh) ? interrupt control/status 27.15 jabber interrupt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 27.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 27.13 page received interrupt enable 1 = enable page received interrupt 0 = disable page received interrupt rw 0 27.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 27.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0
micrel, inc. KSZ9021GQ september 2010 43 m9999-091010-1.2 address name description mode (1) default 27.10 link down interrupt enable 1 = enable link down interrupt 0 = disable link down interrupt rw 0 27.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 27.8 link up interrupt enable 1 = enable link up interrupt 0 = disable link up interrupt rw 0 27.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occurred ro/rc 0 27.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occurred ro/rc 0 27.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occurred ro/rc 0 27.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occurred ro/rc 0 27.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occurred ro/rc 0 27.2 link down interrupt 1 = link down occurred 0 = link down did not occurred ro/rc 0 27.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occurred ro/rc 0 27.0 link up interrupt 1 = link up occurred 0 = link up did not occurred ro/rc 0 register 28 (1ch) ? digital debug control 1 28.15:8 reserved rw 0000_0000 28.7 mdi_set mdi_set has no function when swapoff (reg28.6) is de-asserted 1 = when swapoff is asserted, if mdi_set is asserted, chip will operate at mdi mode 0 = when swapoff is asserted, if mdi_set is de- asserted, chip will operate at mdi-x mode rw 0 28.6 swapoff 1 = disable auto crossover function 0 = enable auto crossover function rw 0 28.5:1 reserved rw 00_000 28.0 pcs loopback 1 = enable 10base-t and 100base-tx loopback for register 0h bit 14 0 = normal function rw 0 register 31 (1fh) ? phy control 31.15 reserved rw 0 31.14 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 31.13:12 reserved rw 00 31.11:10 reserved ro/lh/rc 00
micrel, inc. KSZ9021GQ september 2010 44 m9999-091010-1.2 address name description mode (1) default 31.9 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 31.8:7 reserved rw 00 31.6 speed status 1000base-t 1 = indicate chip final speed status at 1000base-t ro 0 31.5 speed status 100base-tx 1 = indicate chip final speed status at 100base-tx ro 0 31.4 speed status 10base-t 1 = indicate chip final speed status at 10base-t ro 0 31.3 duplex status indicate chip duplex status 1 = full-duplex 0 = half-duplex ro 0 31.2 1000base-t mater/slave status 1 = indicate 1000base-t master mode 0 = indicate 1000base-t slave mode ro 0 31.1 software reset 1 = reset chip, except all registers 0 = disable reset rw 0 31.0 link status check fail 1 = fail 0 = not failing ro 0 note: 1. rw = read/write. rc = read-cleared ro = read only. sc = self-cleared. lh = latch high. extended registers address name description mode (1) default register 257 (101h) ? strap status 257.15:6 reserved ro 257.5 clk125_en status 1 = clk125_en strap-in is enabled 0 = clk125_en strap-in is disabled ro 257.4:0 phyad[4:0] status strapped-in value for phy address ro register 258 (102h) ? operation mode strap override 258.15:8 reserved rw 258.7 tri-state all digital i/os 1 = tri-state all digital i/os for further power saving during software power down rw 0 258.6:5 reserved rw 258.4 nand tree override 1 = override strap-in for nand tree mode rw 258.3:2 reserved rw 258.1 gmii / mii override 1 = override strap-in for gmii / mii mode rw 258.0 reserved rw
micrel, inc. KSZ9021GQ september 2010 45 m9999-091010-1.2 address name description mode (1) default register 259 (103h) ? operation mode strap status 259.15:5 reserved ro 259.4 nand tree strap-in status 1 = strap to nand tree mode ro 259.3:2 reserved ro 259.1 gmii / mii strap-in status 1 = strap to gmii / mii mode ro 259.0 reserved ro register 263 (107h) ? analog test register 263.15 ldo disable 1 = ldo controller disable 0 = ldo controller enable rw 0 263.14:9 reserved rw 000_000 263.8 low frequency oscillator mode 1 = low frequency oscillator mode enable 0 = low frequency oscillator mode disable use for further power saving during software power down rw 0 263.7:0 reserved rw 0000_0000 note: 1. rw = read/write. ro = read only.
micrel, inc. KSZ9021GQ september 2010 46 m9999-091010-1.2 absolute maximum ratings (1) supply voltage (dvddl, avddl, avddl_pll).......-0.5v to vdd+10% (avddh) ...........................................-0.5v to vdd+10% (dvddh)...........................................-0.5v to vdd+10% input voltage (all input s) .........................-0.5v to vdd+10% output voltage (all outputs) ....................-0.5v to vdd+10% lead temperature (soldering, 10sec.) ....................... 260c storage temperature (t s ) ..........................-55c to +150c operating ratings (2) supply voltage (dvddl, avddl, avddl_pll).... +1.140v to +1.260v (avddh)........................................ +3.135v to +3.465v (dvddh @ 3.3v) .......................... +3.135v to +3.465v (dvddh @ 2.5v) .......................... +2.375v to +2.625v ambient temperature (t a commercial: KSZ9021GQ)................ 0c to +70c (t a industrial: KSZ9021GQi) ................-40c to +85c maximum junction temperature (t j max) ................. 125c thermal resistance ( ja ) ....................................41.54c/w thermal resistance ( jc ) ....................................19.78c/w electrical characteristics (3) symbol parameter condition min typ max units supply current ? core / digital i/os 1000base-t link-up (no traffic) 522 ma 1000base-t full-duplex @ 100% utilization 555 ma 100base-tx link-up (no traffic) 159 ma 100base-tx full-duplex @ 100% utilization 160 ma 10base-t link-up (no traffic) 7 ma 10base-t full-duplex @ 100% utilization 7 ma power-saving mode (cable un-plugged) 15 ma software power down mode (register 0.11 =1) 1.3 ma i core 1.2v total of: dvddl (1.2v digital core) + avddl (1.2v analog core) + avddl_pll (1.2v for pll) chip power down mode (strap-in pins mode[3:0] = 0111) 1.2 ma 1000base-t link-up (no traffic) 22 ma 1000base-t full-duplex @ 100% utilization 39 ma 100base-tx link-up (no traffic) 15 ma 100base-tx full-duplex @ 100% utilization 19 ma 10base-t link-up (no traffic) 10 ma 10base-t full-duplex @ 100% utilization 11 ma power-saving mode (cable un-plugged) 14 ma software power down mode (register 0.11 =1) 8 ma i dvddh_2.5 2.5v for digital i/os (gmii / mii operating @ 2.5v) chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma 1000base-t link-up (no traffic) 32 ma 1000base-t full-duplex @ 100% utilization 57 ma 100base-tx link-up (no traffic) 19 ma 100base-tx full-duplex @ 100% utilization 25 ma 10base-t link-up (no traffic) 13 ma 10base-t full-duplex @ 100% utilization 17 ma power-saving mode (cable un-plugged) 23 ma software power down mode (register 0.11 =1) 16 ma i dvddh_3.3 3.3v for digital i/os (gmii / mii operating @ 3.3v) chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma
micrel, inc. KSZ9021GQ september 2010 47 m9999-091010-1.2 symbol parameter condition min typ max units supply current ? transceiver (equivalent to current draw through external transformer center taps for phy transceivers with current-mode transmit drivers) 1000base-t link-up (no traffic) 74 ma 1000base-t full-duplex @ 100% utilization 73 ma 100base-tx link-up (no traffic) 28 ma 100base-tx full-duplex @ 100% utilization 28 ma 10base-t link-up (no traffic) 35 ma 10base-t full-duplex @ 100% utilization 43 ma power-saving mode (cable un-plugged) 35 ma software power down mode (register 0.11 =1) 2 ma i avddh 3.3v for transceiver chip power down mode (strap-in pins mode[3:0] = 0111) 1 ma cmos inputs dvddh = 3.3v 2.0 v v ih input high voltage dvddh = 2.5v 1.8 v dvddh = 3.3v 0.8 v v il input low voltage dvddh = 2.5v 0.7 v i in input current v in = gnd ~ v ddio -10 10 a cmos outputs dvddh = 3.3v 2.4 v v oh output high voltage dvddh = 2.5v 2.0 v dvddh = 3.3v 0.4 v v ol output low voltage dvddh = 2.5v 0.4 v |i oz | output tri-state leakage 10 a led outputs i led output drive current each led pin (led1, led2, led3, led4, led5, led6) 8 ma 100base-tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbalance 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % v set reference voltage of i set r(i set ) = 4.99k 0.535 v output jitter peak-to-peak 0.7 1.4 ns 10base-t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak-to-peak 3.5 ns harmonic rejection transmit all-one signal sequence -31 db
micrel, inc. KSZ9021GQ september 2010 48 m9999-091010-1.2 symbol parameter condition min typ max units 10base-t receive v sq squelch threshold 5mhz square wave 300 400 mv notes: 1. exceeding the absolute maximum rating may damage the device. stresses greater than the absolute maximum rating may cause p ermanent damage to the device. operation of the device at these or any other conditions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25 c. specification is for packaged product only.
micrel, inc. KSZ9021GQ september 2010 49 m9999-091010-1.2 timing diagrams gmii transmit timing figure 6. gmii transmit timing ? data input to phy timing parameter description min typ max unit 1000base-t t cyc gtx_clk period 7.5 8.0 8.5 ns t su tx_en, txd[7:0], tx_er setup time to rising edge of gtx_clk 2.0 ns t hd tx_en, txd[7:0], tx_er hold time from rising edge of gtx_clk 0 ns t hi gtx_clk high pulse width 2.5 ns t lo gtx_clk low pulse width 2.5 ns t r gtx_clk rise time 1.0 ns t f gtx_clk fall time 1.0 ns table 10. gmii transmit timing parameters
micrel, inc. KSZ9021GQ september 2010 50 m9999-091010-1.2 gmii receive timing figure 7. gmii receive timing ? data input to mac timing parameter description min typ max unit 1000base-t t cyc rx_clk period 7.5 8.0 8.5 ns t su rx_dv, rxd[7:0], rx_er setup time to rising edge of rx_clk 2.5 ns t hd rx_dv, rxd[7:0], rx_er hold time from rising edge of rx_clk 0.5 ns t hi rx_clk high pulse width 2.5 ns t lo rx_clk low pulse width 2.5 ns t r rx_clk rise time 1.0 ns t f rx_clk fall time 1.0 ns table 11. gmii receive timing parameters
micrel, inc. KSZ9021GQ september 2010 51 m9999-091010-1.2 mii transmit timing figure 8. mii transmit timing ? data input to phy timing parameter description min typ max unit 10base-t t cyc tx_clk period 400 ns t su tx_en, txd[3:0], tx_er setup time to rising edge of tx_clk 15 ns t hd tx_en, txd[3:0], tx_er hold time from rising edge of tx_clk 0 ns t hi tx_clk high pulse width 140 260 ns t lo tx_clk low pulse width 140 260 ns 100base-tx t cyc tx_clk period 40 ns t su tx_en, txd[3:0], tx_er setup time to rising edge of tx_clk 15 ns t hd tx_en, txd[3:0], tx_er hold time from rising edge of tx_clk 0 ns t hi tx_clk high pulse width 14 26 ns t lo tx_clk low pulse width 14 26 ns table 12. mii transmit timing parameters
micrel, inc. KSZ9021GQ september 2010 52 m9999-091010-1.2 mii receive timing figure 9. mii receive timing ? data input to mac timing parameter description min typ max unit 10base-t t cyc rx_clk period 400 ns t su rx_dv, rxd[3:0], rx_er setup time to rising edge of rx_clk 10 ns t hd rx_dv, rxd[3:0], rx_er hold time from rising edge of rx_clk 10 ns t hi rx_clk high pulse width 140 260 ns t lo rx_clk low pulse width 140 260 ns 100base-tx t cyc rx_clk period 40 ns t su rx_dv, rxd[3:0], rx_er setup time to rising edge of rx_clk 10 ns t hd rx_dv, rxd[3:0], rx_er hold time from rising edge of rx_clk 10 ns t hi rx_clk high pulse width 14 26 ns t lo rx_clk low pulse width 14 26 ns table 13. mii receive timing parameters
micrel, inc. KSZ9021GQ september 2010 53 m9999-091010-1.2 auto-negotiation timing auto-negotiation fast link pulse (flp) timing t pw tx+/tx- clock pulse data pulse clock pulse t pw t ctd t ctc t flpw t btb tx+/tx- data pulse flp burst flp burst figure 10. auto-negotiation fast link pulse (flp) timing timing parameter description min typ max units t btb flp burst to flp burst 8 16 24 ms t flpw flp burst width 2 ms t pw clock/data pulse width 100 ns t ctd clock pulse to data pulse 55.5 64 69.5 s t ctc clock pulse to clock pulse 111 128 139 s number of clock/data pulse per flp burst 17 33 table 14. auto-negotiation fast link pulse (flp) timing parameters
micrel, inc. KSZ9021GQ september 2010 54 m9999-091010-1.2 mdc/mdio timing figure 11. mdc/mdio timing timing parameter description min typ max unit t p mdc period 400 ns t 1md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 10 ns t md3 mdio (phy output) delay from rising edge of mdc 0 ns table 15. mdc/mdio timing parameters
micrel, inc. KSZ9021GQ september 2010 55 m9999-091010-1.2 reset timing the recommended KSZ9021GQ power-up reset timing is summarized in the following figure and table. figure 12. reset timing parameter description min max units t sr stable supply voltage to reset high 10 ms table 16. reset timing parameters after the de-assertion of reset, it is recommended to wait a minimum of 100s before starting programming on the miim (mdc/mdio) interface. reset circuit the following reset circuit is recommended for powering up the KSZ9021GQ if reset is triggered by the power supply. figure 13. recommended reset circuit
micrel, inc. KSZ9021GQ september 2010 56 m9999-091010-1.2 the following reset circuit is recommended for applications where reset is driven by another device (e.g., cpu or fpga). at power-on-reset, r, c and d1 provide the necessary ramp rise time to reset the KSZ9021GQ device. the rst_out_n from cpu/fpga provides the warm reset after power up. figure 14. recommended reset circuit for interfacing with cpu/fpga reset output reference circuits ? led strap-in pins the pull-up and pull-down reference circuits for the led5/phyad4, led4/phyad3, led3/phyad2, led2/phyad1 and led1/phyad0 strapping pins are shown in the following figure. figure 15. reference circuits for led strapping pins
micrel, inc. KSZ9021GQ september 2010 57 m9999-091010-1.2 reference clock ? connection & selection a crystal or external clock source, such as an oscillator, is used to provide the reference clock for the KSZ9021GQ. the reference clock is 25 mhz for all operating modes of the KSZ9021GQ. the following figure and table shows the reference clock connection to xi (pin 124) and xo (pin 123) of the KSZ9021GQ, and the reference clock selection criteria. 25mhz osc +/-50ppm nc nc xi xo xi xo 22pf 22pf 22pf 22pf 25mhz xtal +/-50ppm figure 16. 25mhz crystal / oscillator reference clock connection characteristics value units frequency 25 mhz frequency tolerance (max) 50 ppm table 17. reference crystal/clock selection criteria magnetics specification a 1:1 isolation transformer is required at the line interface. an isolation transformer with integrated common-mode chokes is recommended for exceeding fcc requirements. the following tables provide recommended magnetic characteristics and a list of qualified magnetics for the KSZ9021GQ. parameter value test condition turns ratio 1 ct : 1 ct open-circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss (max.) 1.0db 0mhz ? 100mhz hipot (min.) 1500vrms table 18. magnetics selection criteria magnetic manufacturer part number auto mdi-x number of port pulse h5007nl yes 1 tdk tla-7t101lf yes 1 table 19. qualified single port 10/100/1000 magnetics
micrel, inc. KSZ9021GQ september 2010 58 m9999-091010-1.2 package information 128-pin (14mm x 20mm) pqfp (q)
micrel, inc. KSZ9021GQ september 2010 59 m9999-091010-1.2 micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944-0800 fax +1 (408) 474-1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or other wise, to any intellectual property rights is granted by this document. except as provided in micrel?s terms and conditions of sale for such products, mi crel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/or use of micrel products including l iability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual p roperty right. micrel products are not designed or authorized for use as components in life support appliances, devices or systems where malfu nction of a product can reasonably be expected to result in personal injury. life support devices or systems are devices or systems that (a) are in tended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a si gnificant injury to the user. a purchaser?s use or sale of micrel products for use in life support appliances, devices or systems is a purchaser?s own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2009 micrel, incorporated.

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