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m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 i cdr/reclocker with 4:1 input multiplexer rev v3 features ? cdr/reclocker with 4:1 input mutliplexer ? integrated loop filter and terminations ? serial control or hardwired control, jtag boundary scan ? low power consumption of 405 mw (all channels active) ? built-in pattern genera tor and receiver for mo dule and system testing (prbs, 8b/10b, fibre channel, user programmable patterns) ? user selectable input equalization and pre-emphasis for backplane isi reduction the m21262 is a cdr/reclocker with 4:1 input multiplexer fo r telecom, datacom, and hd/sd video applications. each output channel has an independent multi-rate cdr capable of op erating at data rates between 42 mbps and 3.2 gbps. the m21262 can be controlled either through hardwired pins or through a serial programming interface. the hardwired mode eliminates the need for an external microcontroller to configur e the device. the serial programming interface allows complete control of the device and is available as a two-wire or a four-wire interface. the m21262 device supports jtag external boundary scan, which in cludes all of the high-speed i/ o as well as the traditional digital i/o. functional block diagram adaptive input equalization input buffer bist transmitter mux bist 4:1 selector bist receiver mux selectable cml, lvds lvpecl output buffer + pre-emphasis din0 [p/n] din3 [p/n] din1 [p/n] din2 [p/n] bist reclocker array vddt0/1 vddt2/3 multifunction pin array serial interface/hardwired mode xjtag_en voltage regulator xregu_en jtag dout [p/n] ctrl_mode [1:0] out_mode [1:0] xrst mf [11:0] select [1:0] xen_port [3:0] transmitter receiver refclkp/n applications ? hd/sd-sdi routing swit chers, distribution ampl ifiers, and transport systems ? sonet systems and modules ? 10 gbase-cx4 systems ? gigabit ethernet systems ? pci-express ? sas/s-ata/s-ata2 systems standards compliance ? smpte 292m ? smpte 259m ? smpte 344m ? smpte 424m
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support ii cdr/reclocker with 4:1 input multiplexer rev v3 ordering information part number package operating temperature m21262-12 72-terminal, 10mm, mlf -40 c to 85 c M21262G-12* 72-terminal, 10mm, mlf -40 c to 85 c * the letter ?g? designator after the part number indicates that the device is rohs compliant. the rohs compliant devices are b ackwards compatible with 225 c reflow profiles. revision history revision level date description v3 release may 2015 updated logos and page layout. no content changes. c (v2) release april 2008 added smpte 424m in standards compliance list. revised section 2.8 . added 2 x hd-sdi data in table 1-6 , table 1-15 , and table 2-14 . b (v1) release april 2007 removed m21261 from data sheet. added support for datacom/telecom rates up to 3.2 gbps. updated specification tables. updated register tables. a (v1p) preliminary april 2004 initial release. original document number 21261-dsh-001-a.
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 iii cdr/reclocker with 4:1 input multiplexer rev v3 table of contents ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii 1.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 detailed feature descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1.1 conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.3 internal voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1.4 high-speed input/output pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.1.5 selector settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.1.6 reclocker reference frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.7 multifunction pins overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 1.1.8 multifunction pins defined for hardwired mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1.9 multifunction pins: four-wir e serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.10 two-wire serial interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.1.11 jtag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.12 input deterministic jitter attenuators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1.13 output pre-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.1.14 cdr/rclk overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.1.15 general cdr/rclk features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.16 multirate cdr data rate selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 1.1.17 frequency acquisition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.1.18 cdr/reclocker data rate programming (hd/sd-sdi data rates only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 1.1.19 ambient temperature range limitations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 1.1.20 loss of activity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.21 built-in self test (bist) overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.22 bist test patterns. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 1.1.23 bist receiver (bist rx) operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1.24 bist transmitter (bist tx) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 1.1.25 junction temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.1.26 ic identification / revision code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1.2 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 2.0 product specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support iv cdr/reclocker with 4:1 input multiplexer rev v3 2.2 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.3 power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.4 input/output specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 2.5 high-speed performance specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.6 package drawings and surface m ount assembly details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.7 pcb high-speed design and layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 2.8 auto rate detect (ard). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 3.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 3.1 global control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 3.1.1 global control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1.2 input multiplexer settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 3.1.3 external reference frequency divider control (rfd) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1.4 master ic reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1.5 ic electronic identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1.6 ic revision code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 3.1.7 built in self-test (bist) receiver main control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.8 built in self-test (bist) receiver bit error counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 3.1.9 built in self-test (bist) transmitter channel select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 3.1.10 built in self-test (bist) transmitte r main control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3.1.11 built in self-test (bist) transmitter pll loss of lock r egister . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 3.1.12 built in self-test (bist) transmitte r pll control register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 3.1.13 built in self-test (bist) transmitte r pll control register b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1.14 built in self-test (bist) transmitte r pll control register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 3.1.15 built in self-test (bist) transmitte r 20 bit user programmable pattern. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.1.16 built in self-test (bist) transmitte r 16/20 bit user programmable pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.1.17 built in self-test (bist) transmitte r 16/20 bit user programmable pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.1.18 built in self-test (bist) transmitte r alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.19 internal junction temperature monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.1.20 internal junction temperature value . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.21 cdr/rclk loss of lock register alarm status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.22 cdr/rclk loss of activity register alarm status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 3.1.23 cdr/rclk control register a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 3.1.24 cdr/rclk control register b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1.25 cdr/rclk control register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3.1.26 output buffer control for cdr/rclk. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 3.1.27 output buffer pre-emphasis control for output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.1.28 input equalization control for output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.1.29 cdr/rclk loop bandwidth and data sampling point adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 3.1.30 cdr/rclk lol window control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 3.1.31 jitter reduction control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 a.1 glossary of terms/acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support v cdr/reclocker with 4:1 input multiplexer rev v3 a.2 reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 a.2.1 external . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 a.2.2 macom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 1 cdr/reclocker with 4:1 input multiplexer rev v3 1.0 functional description 1.1 detailed feature descriptions 1.1.1 conventions throughout this data sheet, ph ysical pins will be denoted in bold italic print. an array of pins can be called by each individual pin name (e.g. mf0 , mf1 , mf2 , mf3 , and mf6 ) or as an array (e.g. mf [6, 3:0]). the m21262 control is accessed through registers that employ an 8-bit address and an 8-bit data scheme. registers are denoted in italic print, (e.g. testregister) and individual bits within the register will be called out as testregister [4:3] to denote the 4 th and 3 rd bit where bit 0 is the lsb and bit 7 is the msb. many features of the device are bit mapped within a register; if the status of the other bits are uncertain, it is recommended that the user reads the value from the register before writing, to assure only the desired bits chan ge. writing in the same value to the bits within a register does not cause glitches to the uncha nged features. the addresses for the regi sters as well as their functions can be found in detail in chapter 3 . the purpose of the text description is to highlight the features of the registers. for redundant items, such as t he channel number, the regist ers will have a nom enclature of testreg_ 0 for channel 0, testreg_ 1 for channel 1, testreg_ 2 for channel 2, testreg_ 3 for channel 3. 1.1.2 reset upon application of power, the m21262 automatically generates a master reset. at any time, forcing xrst =l causes the m21262 to enter the master reset state. a master reset can also be initiated through the registers in the serial interface control mode by writing aah to mastreset . once a master reset is initia ted, all registers are returned to the default values, the internal state machines cleared, and all cdr/rclk/bist reset to the out-of-lock condition. after a reset, the register mastreset will automatically return to the default va lue of 00h. the cdr/rclk can be soft reset by setting cdr rclk_ctrla [7] = 1. the bit should be returned to 0b for normal operation. after a soft reset, the registers that determine the cdr/rclk operation option s such as data rate, window sizes, etc., remain unchanged an d only the cdr/rclk state machine is reset, resulting in an out-of-lock condition. 1.1.3 internal voltage regulator the digital and analog core are designed to run at 1.2v, how ever, for operation from 1.8v to 3.3v, an internal linear regulator is provided. xregu_en = l enables the voltage regulator which uses avdd_i/o and dvdd_i/o to generate the required 1.2v for avdd_core and dvdd_core . in this mode, the avdd_core and dvdd_core pins should be connected to a floating dc low inductance pcb plane and ac bypassed to vss using standard decoupling techniques. if desired, avdd_core and dvdd_core can be separated into individual planes. if 1.2v is available, it can be connected directly to avdd_core and dvdd_core, to save power, by bypassing the internal linear regulator with xregu_en = h. in this case, it is recommended that the avdd_core and dvdd_core pins be tied together to a common pcb plane, and bypassed to vss with standard decoupling techniques.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 2 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.4 high-speed input/output pins the high-speed input data interface is a differential input buffer, similar to a pcml des ign that is referenced to avdd_core (1.2v). the high-speed serial differential data (42 mbps to 3200 mbps) enters the device via din [3:0, p/n]. inputs 0 and 1 are internally terminated with 50 to vddt0/1 and inputs 2 and 3 are terminated with 50 to vddt2/3 . the vddt pins should be connected to avdd_core for a proper termination of the inputs. see figure 1-1 for recommended data and reference clock input coupling circuits. figure 1-1. recommended data and reference clock input coupling circuitry m21262 vddt (connect to avdd_core) dinp dinn 50 50 0.1 f 0.1 f refclkp refclkn reference clock input buffer 2 k 50 vdd_i/o 10 k data input buffer 4.7 f 4.7 f 50 50 50 10 k 2 k
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 3 cdr/reclocker with 4:1 input multiplexer rev v3 the m21262 supports multiple high-speed output modes. the output modes are selectable with hardwired pins only. the i/o interface is set with out_mode [1:0] and the output level with mf [9:8] as shown in ta b l e 1 -1 . in the serial interface mode, the out_ctrl_ n [7:6] register is used to set the data level, and out_mode [1:0] is used to set the interface type. in the serial interface mode, the data output can be enabled with out_ctrl_ n [2] = 1b (default) and the output data polarity can be flipped by setting out_ctrl_ n [3] = 1b (default: no inversion). output data polarity flip is an internal function that would have th e same effect as switching the p and n terminals. the recommended avdd_i/o for the different output interfaces is shown in ta b l e 1 - 2 . the nonstandard lower swing modes for pecl and infiniband are provided for lower power dissipation, when desired. 1.1.5 selector settings ta b l e 1 - 3 details the selector configuration fo r each setting for the hardwired pins select_mode [1:0]. the m21262 allows the user to route any of the four inpu ts to the output channel. the selector can be configured through the control register or through the hardwired pins select_mode [1:0]. table 1-1. output interface and level mapping (for both hardwired and software modes) multifunction pins & register mf [9:8] out_ctrl_n [7:6] pcml mode out_mode [1:0] = 00b lvds mode out_mode [1:0] = 01b pcml+ mode out_mode [1:0] = 11b 00b off off off 01b 550 mv rrl at 450 mv 900 mv 10b 900 mv gpl at 650 mv 1200 mv 11b 1200 mv 1000 mv 1500 mv table 1-2. output interface and recommended avdd_i/o range output logic avdd_i/o range (v) off 1.8?3.3 pcml at 550 mv 1.8?3.3 pcml at 900 mv 1.8?3.3 pcml at 1200 mv 1.8?3.3 pcml+ at 1500 mv 1.8?3.3 lvds gpl 1.8?3.3 lvds rrl 1.8?3.3
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 4 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.6 reclocker reference frequency an external reference clock is applied to refclk [p/n] to enable frequency acquisition in the reclocker. pcml, lvttl, cmos are examples of the wide variety of interfac es supported for the reference clock. the inputs contain a dc-coupled 100 differential termination between refclkp and refclkn along with a 100 k pull-down on each terminal to vss . after this termination/pull-down block, the inputs are ac coupled internally. the common-mode and allowable voltage swings are specified in ta b l e 2 - 1 0 . the refclk common-mode must be above 250 mv, which may require external pull-ups, in the case of external ac coupling. 1.1.7 multifunction pins overview the m21262 is designed to be an extremely versatile devi ce, with many user selectable options in the cdr/rclk and i/o to optimize performance. all of these options can be ac cessed and controlled through the serial interface. the serial interface i/o pins and address pins are mapped to the multifunction pins mf [11:0]. a subset of the key features for most applications, such as standard da ta rates, i/o levels, etc., can be selected through mf [11:0] in the hardwired mode. the hardwired mode does not require the use of the serial interface. in this mode, upon power up (auto reset on power up), the m21262 function is determined by the stat us of the hardwired pins. during operation, the hardwired pins can change states, whic h would cause the device to follow with the appropriate action. another feature of the multif unction pins is to support jtag testing of this device during pcb manufacturing. the various control and test modes of this device are selected with three pins: ctrl_mode [1:0] , and xjtag_en . xjtag_en = l overrides ctrl_mode [1:0] , and puts the device in jtag test mode, while xjtag_en = h allows ctrl_mode [1:0] to determine the m21262 control mode, as summarized in ta b l e 1 - 4 . table 1-3. selector configuration settings mode 0 mode 1 output 0 0 input 0 0 1 input 1 1 0 input 2 1 1 input 3 table 1-4. mode select pins pin jtag test mode hardwired mode 4-wire serial i 2 c-compatible 2-wire serial xjtag_en lh h h ctrl_mode [1:0] no impact 11b 00b 01b
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 5 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.8 multifunction pins defined for hardwired mode in the hardwired mode, a subset of options in the m21262 can be accessed with hardwired physical pins, as defined in ta b l e 1 - 5 . the hardwired bit rates along with the defa ult reference clock frequency are shown in ta b l e 1 - 5 . ta b l e 1 - 6 provides the default reference clock frequency associated with each hardwired data rate. table 1-5. multifunction pins for hardwired mode pin name function description mf0 rate_sel_0 data rate selection cdr/reclocker data rate select (see table 1-6 for description) mf1 rate_sel_1 data rate selection cdr/reclocker data rate select (see table 1-6 for description) mf2 rate_sel_2 data rate selection cdr/reclocker data rate select (see table 1-6 for description) mf3 rate_sel_3 data rate selection cdr/reclocker data rate select (see table 1-6 for description) mf4 xpre_emp_en pre-emphasis control l = pre-emphasis enable h = pre-emphasis disable mf5 rsvd_int_0 macom internal internal use only mf6 rsvd_int_1 macom internal internal use only mf7 xpol_flip_en data polarity flip l = data polarity flip h = standard data polarity mf8 out_level_[1:0] output level sele ction 00b: all outputs disabled 01b: 500 mv (cml) 10b: 900 mv (cml) 11b: 1200 mv (cml) see table 1-1 for the other output interface modes. mf9 output level selection mf10 xeq_en equalization control l = input equalization enabled h = input equalization disabled mf11 xrclk_byp_en cdr/rclk bypass control l = cdr /reclocker bypassed and powered down h = cdr/reclocker enabled table 1-6. hardwired bit rates and associated reference frequencies pins mf[3:0] application bit rate (mbps) reference frequency (mhz) 0000 2 x hd-sdi 2967/2970 12.0 0001 hd-sdi 1485 /1483.5 12.0 0010 2 x sd-sdi 540 12.0 0011 progressive scan video 360 12.0 0100 sd-sdi 270 12.0 0101 legacy comp video 177 12.0 0110 legacy comp video 143 12.0
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 6 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.9 multifunction pins: four-wire serial interface the second serial interface mode is a four-wire programmi ng interface that has been traditionally used on macom earlier generation crosspoints and cdrs and is capable of higher speed operation then the two-wire interface. the interface consists of a unidirectional clock and a data input and data output line. for use with multiple ics, a serial interface chip select pin is provided. table 1-7 illustrates how the fo ur-wire serial interf ace maps into the multifunction pins. this serial interface can operate with a maximum clock rate of 20 mhz. the serial i/o shifts data in from the ex ternal controller on the rising edge of sclk . the serial i/o operation is gated by xcs . data is shifted in on sdi on the falling edge of sclk , and shifted out on sdo on the rising edge of sclk . to address a register, a 10-bit input consists of the fi rst bit (start bit, sb = 1), the second bit (operation bit, op = 1 for read, = 0 for write), followed by the 8-bit addr (msb first) as shown in figure 1-2 . figure 1-3 illustrates the serial write mode . to initiate a write sequence, xcs goes low before the falling edge of sclk . on each falling edge of the clock, the 18-bits co nsisting of the sb = 1, op = 0, addr, and data, are latched into the input shift register. the rising edge of xcs must occur before the falling edge of sclk for the last bit. upon receipt of the last bit, one additional cycle of sclk is necessary before data transfers from the input shift register to the addressed register. if consecutive re ad/write cycles are being perfor med, it is not necessary to insert an extra clock cycle between read/write cycles, ho wever one extra clock cycle is needed after the last data bit of the last read/write cycle. table 1-7. multifunction pins for four-wire interface pin function description mf4 sdi serial data in mf5 xcs chip select, active low mf10 sclk clock mf11 sdo serial data out figure 1-2. serial word format 1 rw a[7:0] d[7:0] 17 16 15 8 7 0 start bit read/write address data lsb msb msb lsb
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 7 cdr/reclocker with 4:1 input multiplexer rev v3 figure 1-4 illustrates the serial read mode in where xcs goes low before the falling edge of sclk . on each falling edge of sclk , the 10-bits consisting of sb = 1, op = 1, and th e 8-bit addr are written to the serial input shift register and copied to the serial output shift regi ster. on the next rising edge after the address lsb, the sb and 8-bits of the data are shifted out. the sb for a read is always 0. on a write cycle, any bits that follow the expected number of bits are ignored, and only the first 16-bits following sb and op are used. on a read cycle, any ex tra clock cycles will result in the repe at of the data lsb. an invalid sb or op renders the operation und efined. the falling edge of xcs always resets the serial operation for a new read or write cycle. the timing diagrams for the serial write and read operations are shown in figure 1-3 and figure 1-4 , respectively. ta b l e 1 - 8 contains the specifications for the various timi ng parameters for the serial programming interface. figure 1-3. serial write mode figure 1-4. serial read mode 1 1 t dw tens t clk t wclk sclk sdi t cs t ch xc s t ds t dh w r a 4 a 5 a 6 a 7 a 3 d 7 a 0 a 1 d 4 d 5 d 6 d 3 d 2 d 1 d 0 x x x x x x x x 1 1 0 x scl k xcs t rdd t rds t dw tens t ds t dh t wclk t clk t cs t ch sd o sd i r d a 2 a 1 a 0 d 6 d 7 d 5 d 4 d 3 d 0 d 1 d 2 a 4 a 5 a 6 a 7
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 8 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.10 two-wire serial interface the two-wire serial interfac e is compatible with the i 2 c standard. the m21262 supports the read/write slave-only mode, 7-bit device address field width, and supports the standard rate of 100 kbps, fast mode of 400 kbps, and high-speed mode of 3.4 mbps. the 7-bit ad dress for the device is determined with mf [6:0], which allows for a maximum of 124 unique addresses for this device. the four addresses 000001xx should not be used. sda ( mf11 ) and scl ( mf10 ) can drive a maximum of 500 pf each at the maximum rate. during the write mode from the master to the m21262, data is latched into the internal m21262 registers on the rising edge of scl, during the acknowledge phase (ack) of communication. table 1-9 summarizes the multifunction pins for the two-wire serial interface mode. for further information on timing, please see the i 2 c bus specification standard. table 1-8. serial interface timing?specifie d at recommended operating conditions symbol item notes minimum typical maximum units t dw data width ? 14 ? ? ns t dh data hold time ? 5 ? ? ns t ds data setup time ? 5 ? ? ns t ens enable setup time ? 5 ? ? ns t cs chip select setup time ? 2 ? tclk - 2 ns t ch chip select hold time ? 2 ? ? ns t rdd read data output delay ? 1 ? ? ns t rds read data valid ? 9 ? ? ns t clk sclk period width ? 14 ? ? ns t wclk sclk minimum low duration ? 5 ? tclk - 5 ns t r output rise time 1 1 ? 4 ns t f output fall time 1 1 ? 4 ns notes: 1. edge rate in the high-edge rate mode. 2. designed for max serial speed of 20 mhz read/write.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 9 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.11 jtag the m21262 supports jtag external boundary scan, whic h includes all of the high-speed i/o, as well as the traditional digital i/o. table 1-10 shows the multifunction pins signal mapping for jtag testing. 1.1.12 input determini stic jitter attenuators each of the four input channels contains an input eq ualizer to compensate for high-frequency loss. in the hardwired mode, there is the option to set input equalization on or off. in the two-wire serial interface control mode, the default state allows for configurable input equalization settings using ineq_ctrl_ n [2:0], for which the default setting of 100b is optimized for trace lengths between 10?46 inches. the input equalization settings have been optimized for a variety of backplane pcb applications, such as board traces and cables. for board traces on fr4, the input equa lizer can drive trace lengths of up to 72? at 1.6 gbps and up to 60? at 3.1875 gbps. the equalizer has simila r high performance on nelco-13, arlon 25, rogers 3003, 4003c, 4340, getek pcb materials, and twinaxial cables . the input equalizer was designed to compensate for the deterministic jitter accumulation effe cts of typical backplane interconnect s, which have bandwidths of hundreds of mhz to a few ghz. the equalizers are not expected to make a significant difference in performance with signal data rates less than 1 gbps. another component of input deterministic jitter is inter-symbol inte rference (isi) due to dc offsets. by default, a dc servo-like circuit is enabled to correct for this type of deterministic jitter, and can be disabled by setting table 1-9. multifunction pins for two-wire interface pin function description mf0 address bit 0 7-bit device address; address bit 0 is lsb, address bit 6 is msb mf1 address bit 1 mf2 address bit 2 mf3 address bit 3 mf4 address bit 4 mf5 address bit 5 mf6 address bit 6 mf10 scl clock input mf11 sda data input/output table 1-10. multifunction pins for jtag pin function description mf8 tms test select mf9 tdi test data input mf10 tck test clock mf11 tdo test data output
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 10 cdr/reclocker with 4:1 input multiplexer rev v3 ineq_ctrl [4] = 0b. the dc servo can also be used to track changes in the common mode, for single-ended operation. when the cdr, dc servo, and aie are all ena bled, the jitter tolerance should be greater than 1 ui. figure 1-5. sts-48 waveform after transmission th rough 76? of pcb traces (input to m21262)
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 11 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.13 output pre-emphasis the output channel contains an output pre-emphasis circui t that can be used to select the optimal pre-emphasis level. the pre-emphasis settings have been optimize d for a variety of backplane pcb applications. for board traces on fr4, the pre-emphasis circuit can drive trace lengths up to 60? at 1.6 gbps. like the input equalizer settings, the output pre-emphasis circuit has similar high performance on nelco-13, ar lon 25, rogers 3003, 4003c, 4340, getek pcb materials, and twinaxial cables. the digital pre-emphasis level is selected, for each output channel, with preemp_ctrl [2:0], and the default value of 000b corres ponds to pre-emphasis disabled. the pre- emphasis circuit tracks the signal data rate throughout th e multirate range, however, like the input equalizer, it is designed to compensate for the bandwidth limitations of th e interconnect, and may not have the desired effects at the low end of the multirate range. when the cdr/rclk has been disabled or bypassed, analog pre-emphasis must be used in place of digital pre-emphasis. writing the data value 1b to the register preemp_ctrl [3] enables analog pre-emphasis, whereas writing the data value 0b to the register preemp_ctrl [3] enables digital pre- emphasis. once analog pre-emphasis has been enabled, the boost level may be chosen with preemp_ctrl [5:4], and the bandwidth may be chosen with preemp_ctrl [6]. the output pre-emphasis function is available for all data interfaces and levels. figure 1-6. sts-48 waveform at m21260 output with input shown in figure 1-4
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 12 cdr/reclocker with 4:1 input multiplexer rev v3 1.1.14 cdr/rclk overview when the cdr/rclk achieves phase lock onto the incomi ng data stream, it removes the incoming random jitter above its loop bandwidth. the m21262 output data has extremely low jitter, due to retiming with a very low jitter generation cdr/rclk. clock outputs are also provided, but are disabled by default. each cdr/rclk is capable of multirate operation which is achieved by a combinatio n of built in vco frequency dividers (vcd), data rate dividers (drd), and a wide vco tuning range (f min = 2.0 ghz, f max = 3.2 ghz). as a result, the allowed input data range is f min / drd max to f max / drd min . although the ranges are not continuous, the ranges are deliberately chosen to cover all typical applications. by default, the loop bandwidth is set to pass 2 x hd-sdi video and sonet sts-48 specifications, with less than 0.1 db of bandwidth peaking. within a given vco frequency rang e, the bandwidth will scale proportionately. for example, if the loop bandwidth (lbw) is 1.19 mhz at 1. 485 ghz, then at 2.97 ghz the lbw will be 2.38 mhz, and peaking will be less than 0.1 db. when drd is not equal to 1, the bandwidth at drd = 1 scales by the drd divide ratio. for example, if the lbw is 2.38 mhz at 2 x hd-s di with drd = 1, then if drd = 2 for hd operation, the lbw will be 1.19 mhz. in general, the default bandwidth will me et smpte specifications fo r all bit rates down to 143 mhz. internal filter components assu re that the peaking will not exceed 0.1 db for a ll drds up to 16. in the hardwired mode, the lbw will be properly set for the hardwired bit rates. in the serial re gister mode, the default bandwidth scales automatically with the input bit rate , and the bandwidth can be tuned through registers. the cdr/rclk requires an external reference clock to be connected to the refclkp/n pins. the cdr/rclk contains an internal frequency prescaler that allows a sing le reference to be used for mu ltiple bit rates and thereby ease the burden of having to route and switch multiple frequency references. figure 1-7. definition of pre-emphasis levels v b v s pre-empasis level = x 100 v b v s
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 13 cdr/reclocker with 4:1 input multiplexer rev v3 frequency acquisition is accomplished with two key sect ions. the first section is a secondary phase/frequency lock loop (p/fll) that drives the vco towards the desired frequency. the second section is the loss-of-lock circuitry (lolcir), that turns on or off the secondary p/fll. in general lol has register bits ( alarm_lol ) which are active high, and pins ( xlol [3:0]) which are active low, for wired or use to be wired or externally. in the general context, they will be referred to as lo l which is active h. with both methods, frequency acquisition takes place when the lolcir determines an out of lock conditi on (lol = h) for each cdr/rclk, when the vco frequency exceeds a given range (window). lolcir enables the secondary p/fll to drive the vco close to the desired frequency (the input data bit rate). when the vco falls within a given frequency range where the cdr/rclk loop can acquire phase lock, lolcir turns off the second ary p/fll and sets lol = l, allowing the cdr/rclk to achieve phase lock. during this time , lolcir continues to monitor the fr equency difference and will signal a lol = h to start the acquisition routin e again; if the frequency falls out of range. the lolcir range is fixed in hardwired mode, and programmable in 2-wire or 4-wire serial interface mode. in general, the frequency threshold (window) for lol = h-to-l and lol = l-to-h are different to prevent lol from toggling when the frequency is near one of the windows. these registers al so control the frequency acquisition time. suggested values are given in this document for general r obust operation, an d are used as register defaults, however, th e programmability of the registers allow for optimization based on a gi ven application (e.g. faster lock times). 1.1.15 general cdr/rclk features the cdr/rclk is reset upon xrst = l , mastreset = aah, or upon power up. a soft reset through rclk_ctrla [3] = 1b resets the cdr/rclk state machine, and presets the cdr/rclk to an out-of-lock condition, however, the register contents that are related to cd r/rclk setup are unchanged. it is required to force a soft reset if the bit rate is dynamically changed. the soft rese t register bit needs to be cleared for proper operation. in general, a reset during operation will cause bit er rors, until the cdr/rclk achieves phase lock. by default, the cdr/rclk is active and po wered up for normal operation. by setting rclk_ctrlb [7:6] = 11b, the cdr/rclk can be bypassed and powered down, to allow for nonstandard bit rates, or to save power when the cdr/rclk is not required at lower bit rates. when rclk_ctrlb [7:6] = 01b, the cdr/rclk is bypassed so the output data is not retimed but active (vco lo cked to the input data). in the last mode with rclk_ctrlb [7:6] = 10b, the cdr/rclk is powered down, and all signals along the input and output paths are also powered down, to save power. in this case, the input data does not reach the output. to prevent the propagation of noise in the case where there is a lol c ondition, the cdr/rclk contains an auto- inhibit feature, which is enabled by def ault. when lol is active, the output of the cdr/rclk is fixed at a logic high state ( doutp =h, doutn = l). this feature can be disabled by setting rclk_ctrla [3] = 0b, which allows rclk_ctrla [5] to either force an inhibit (1 b) or to never inhibit (0b). in some applications, the optimal data sampling point is no t in the middle of the data eye. by default, the cdr/ rclk achieves phase lock very near the center of the ey e. for optimal performance (jitter tolerance), the actual sampling point can be adjusted with phadj_ctrl [3:0]. the adjustment range is fr om -122.5 mui to +122.5 mui with 17.5 mui steps. 1.1.16 multirate cdr data rate selection for multirate operation, the first step is to determine the desired data rate range. the input data range must be bracketed by df min =f vco, min /drd max to df max =f vco, max /drd min . df max/min are the maximum/minimum input data rate frequencies, drd max/min are the maximum/minimum data rate divider settings using cdr_ctrlb [3:0] , and f vco, min /f vco, max are the minimum/maximum vco frequencies, whic h are 2.0 ghz and 3.2 ghz respectively. the valid data rates are shown in table 1-11 .
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 14 cdr/reclocker with 4:1 input multiplexer rev v3 it is important to note the difference between the vco frequency (f vco ), and the data rate frequency (df). f vco is always between 2 ghz to 3.2 ghz, while df is the divided down f vco that matches the input data rate. 1.1.17 frequency acquisition frequency acquisition is enabled by the lolcir when lol = h ( alarm_lol =h or xlol = l). a secondary fll attempts to lock the vco to a frequency derived from the external reference. when the frequency is close to the desired frequency, lolcir sets lol = l and disables the secondary fll, thus, the main cdr/rclk pll is free to phase lock to the incoming data. although the ma in cdr/rclk pll can achiev e frequency lock, the vco frequency tuning range typically exceeds the cdr/rclk pll inherent acquisition range. this implies that the fll needs to get the vco within the cdr/rcl k pll range. the loss of lock circ uitry (lolcir) is used to determine when the secondary fll is active. the lolcir consists of window detectors that constantly compare a scaled vco frequency, to a frequency related to the external refe rence. when lol = h the loop is out of lock, the fll is activated until the frequency difference is within the narrow reference window (nrw). when lol = l, the fll is not engaged until the frequency exceeds the wide reference window (wrw). if a signal is not present, the fll circuit will drive the vco frequency to t he nrw and turn off. without data pres ent, the vco would then drift until the frequency difference exceeds the wrw, and repeat this c ycle. to prevent this, by de fault, the fll is activated with lol = h and de-activated with lol = l. table 1-11. valid input data ranges parameter df min df max units data rate divider (drd = 1): cdr_ctrlb [3:0] = 0000b 2.0 3.2 ghz data rate divider (drd = 2): cdr_ctrlb [3:0] = 0001b 1.0 1.6 ghz data rate divider (drd = 4): cdr_ctrlb [3:0] = 0010b 500 800 mhz data rate divider (drd = 8): cdr_ctrlb [3:0] = 0011b 250 400 mhz data rate divider (drd = 12): cdr_ctrlb [3:0] = 0100b 166.7 266.66 mhz data rate divider (drd = 16): cdr_ctrlb [3:0] = 0101b 125 200 mhz data rate divider (drd = 24): cdr_ctrlb [3:0] = 0110b 83.33 133.33 mhz data rate divider (drd = 32): cdr_ctrlb [3:0] = 0111b 62.5 100 mhz data rate divider (drd = 48): cdr_ctrlb [3:0] = 1000b 42 66.66 mhz
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 15 cdr/reclocker with 4:1 input multiplexer rev v3 figure 1-8 shows a block diagram of the frequency acquisition circuits. the secondary fll compares a scaled version of the internal vco frequency (ifv) with a scaled version of the reference clock frequency (ifr); ifr and ifv are limited to between 10 mhz and 25 mhz. the external reference clock frequency (f ref ) is applied to the refclk [p/n] terminals. this reference frequency is scaled to the ifr by the reference frequency divider (rfd) [ refclk_ctrl [3:1]], which allows for an external reference clock in the range of 10 mhz to 800 mhz. the rfd level is a globally set value that applies to all cdr/rclks. ta b l e 1 -1 2 gives the divider ratio, along with the minimum and maximum f ref values. the vco frequency is scaled to the ifv by the vco comparison divider (vcd) [ rclk_ctrlc_ n [7:0]]. ta b l e 1 -1 3 provides drd, rfd, and vcd va lues for common applications. for applications that on ly deal with sonet/sdh data rates, a 19.44 mhz reference clock frequency mu st be used. for applicati ons where a combination of figure 1-8. block diagram of frequency acquisition circuits table 1-12. reference clock frequency ranges rfd value minimum f ref (mhz) maximum f ref (mhz) rfd ( refclk_ctrl [3:1] = 000b): divide by 1 10 25 rfd ( refclk_ctrl [3:1] = 001b): divide by 2 20 50 rfd ( refclk_ctrl [3:1] = 010b): divide by 4 40 100 rfd ( refclk_ctrl [3:1] = 011b): divide by 8 80 200 rfd ( refclk_ctrl [3:1] = 100b): divide by 12 120 300 rfd ( refclk_ctrl [3:1] = 101b): divide by 16 160 400 rfd ( refclk_ctrl [3:1] = 110b): divide by 32 320 800 d in d out refclk lol loa dr f clk ifv ifr f vco f ref vco f vco,max > f vco > f vco,min cdr d in d out c in error fll error d 1 d 2 lolcir drd cdr_ctrlb [3:0] vcd rfd cdr_ctrlc [7:0] refclk_ctrl [3:1] c out c out
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 16 cdr/reclocker with 4:1 input multiplexer rev v3 sonet/sdh and other data rates are used, a 25 mhz refe rence clock frequency must be used. if either of these reference clock frequencies is not available, please contact macom technologies applications engineering for other options. table 1-13. drd/rfd/vcd settings for different data rates and reference frequencies (1 of 2) application dr (mbps) fref (mhz) drd rfd vcd notes 10ge - xaui 3125 156.25 1 8 160 ? 10ge - xaui 3125 25 1 2 250 ? 10gfc - xaui 3187.5 159.375 1 8 160 ? 10gfc - xaui 3187.5 25 1 2 255 1 sts-48+fec 2666.06 19.44 1 1 137 1 sts-48 + fec 2666.06 25 1 2 213 1 sts-48 2488.32 155.52 1 8 128 ? sts-48 2488.32 19.44 1 1 128 ? sts-48 2488.32 25 1 2 199 1 2gfc 2125 106.25 1 8 160 ? 2gfc 2125 25 1 2 170 ? ge 1250 125 2 8 160 ? ge 1250 25 2 2 200 ? fc 1062.5 106.25 2 8 160 ? fc 1062.5 25 2 2 170 1 sts-12 622.08 19.44 4 1 128 ? sts-12 622.08 25 4 2 199 1 fc 531 25 4 2 170 1 fc 266 25 12 2 255 1 escon 200 10 12 1 240 ? escon 200 25 12 2 192 ? sts-3 155.52 19.44 16 1 128 ? sts-3 155.52 25 16 2 199 1 fc 133 25 24 2 255 1 fe 125 12.5 16 1 160 ? fe 125 25 24 2 240 ? sts-1 51.84 25 48 2 199 1
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 17 cdr/reclocker with 4:1 input multiplexer rev v3 the fll drives the ifv to ifr, and it is the primary function of the lolcir to determine when to turn off the fll, so the cdr/rclk can achieve phase lock. the lolcir uses th e frequency difference betw een ifv and ifr to switch lol, which turns on and off the secondary fll. the thresholds where lol makes a transition are defined as windows. these windows are fixed in the hardwired mode, and programmable in the two-wire interface mode. to prevent lol from toggling at the thresholds, two windows are used for hysteresis. when lol = l and the frequency difference exceeds the larger window (wrw), lol l-to-h occurs to signal an out of lock case. when lol = h (and loa = l), the frequency difference is brou ght within the narrow reference window (nrw), after which lol makes a h-to-l tr ansition signaling in-lock. if loa = h when lol = l, the fll remains on to keep the vco locked to the reference, until a signal is present. n acq is defined with lol_ctrl [7:5], n narrow is defined with lol_ctrl [4:1], and n wide is defined with lol_ctrl [0]. the lolcir averages a larg e number of transitions before making an lol decision. this averaging time is referred to as the lol decision time or dt lol . ta b l e 1 -1 4 shows various window sizes for different applications , including the default value in both the hardwired and two-wire serial interface modes. 1.1.18 cdr/reclocker data rate pr ogramming (hd/sd-sdi data rates only) if the automatic rate detection (ard) algorithm developed by macom is used, it is not necessary for the user to manually program the registers of the reclockers to configur e the reclockers for operation at a specific data rate. in applications where the ard is not implemented and the device is used with software control, there are a few parameters that must be configured for the reclocker to correctly lock to the input data. the parameters that need to be programmed are the data rate divider (drd) and the vco frequency divider (vcd). the drd is programmed sts-1 51.84 19.44 48 1 128 1 ds3 44.736 25 48 2 172 1 notes: 1. set lol_ctrl _n[0] = 1b, all other bits at default values. table 1-14. lol window size and decision time examples condition n acq n narrow n wide narrow window (ppm) wide window (ppm) decision time ( s) hardwired mode default 101b 0100b 0b 1955 2930 420 two-wire serial interface mode default 101b 0100b 0b 1955 2930 420 ifv = ifr 111b 0010b 1b 245 975 1685 fast lock 010b 0001b 0b 5860 7800 56 notes: 1. decision time is calculated with ifr = 19.44 mhz; will scale proportionally with ifr range from 10 to 25 mhz. 2. above are examples showing ability to tailor windows for data rates, reference frequencies, and acquisition times. table 1-13. drd/rfd/vcd settings for different data rates and reference frequencies (2 of 2) application dr (mbps) fref (mhz) drd rfd vcd notes
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 18 cdr/reclocker with 4:1 input multiplexer rev v3 using bits [3:0] of register address 41h. the vcd is pr ogrammed using bits [7:0] of register address 42h. the following table shows the recommended values of drd and vcd for standard video data rates. 1.1.19 ambient temperature range limitations ta b l e 1 -1 6 summarizes the supported ambient temperature range as a function of data rate, and indicates when it is required to center the vco. f vco is the vco frequency, which always lies in the range 2.0? 3.2 ghz. dr is the data rate of the input signal, and drd is the data rate divider (1, 2, 4, 8, 12, 16, 24, 32, 48) set with rclk_ctrlb _n[3:0]. t a is the ambient temperature supported, which decreases for f vco > 2.666 ghz. as an example, if the da ta rate is 800 mbps drd should be set to 4; to lock to this signal the vco needs to operate at 3.2 ghz. under these condit ions the ambient temperature range supported is 0c?70c, and it is necessary to center the vco in each of the four lanes. the vco tuning range is roughly the same bandwidth as the variation in vco center frequency between the extremes of the operating temperature range. this issu e can be resolved by centering the vco frequency during the in-circuit testing (ict) phase prior to shipment of the customer systems. note: the cdr/rclk must be powered up and configured at 25c?40c ambient te mperature during ict. 1. power up the device and configure the registers via the serial interface with the appropriate settings for the application of interest. 2. read and store the vco trim code from register mbh[4:0]. 3. every time the device is powered up, this trim code mu st be forced by setting m0 h[0] = 0b then writing the code to mah[4:0]. this can be done during the same writ e cycle as when the other registers are configured. table 1-15. recommended values of drd and vcd for standard video data rates data rate (mbps) drd value vcd value fref (mhz) 143 05h bfh 12 177 04h b1h 12 270 03h b4h 12 360 03h f0h 12 540 02h b4h 12 1483.5/1485 01h f7h 12 2967/2970 00h f7h 12 table 1-16. supported ambient temperature range by data rate f vco (ghz) dr (gbps) t a (c) vco centering requirement 2.0?2.666 2.0/drd? 2.666/drd -40?85 n 2.7?2.97 2.7/drd?2.97/drd 0?70 n 2.7?2.97 2.7/drd?2.97/drd -40?85 y 3.0?3.2 3.0/drd?3.2/drd 0?70 y
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 19 cdr/reclocker with 4:1 input multiplexer rev v3 it should be noted that it is not possib le to center the vco in the hardwired mode, it is necessary to program the cdr/rclk using the serial interface. 1.1.20 loss of activity by default, the loa detector is enabl ed and can be disabled by setting cdr_ctrla _n [1] = 0b, where n is the channel number. loss of activity measures the transition density of data to determine if the data is valid. with prbs data, the transition density is typically 50%, aver aged over long periods. during small time intervals, data transition density variations are due to data content, pa cket headers, stress patterns, etc. in some applications, when data is not present, noise produces rail-to-rail tran sitions that cause problems with level based detectors. these applications include cascaded reclockers, high-gain crosspoints, and other devices. the data transition density based loa detector can separate data from random noise, determine false lock at the wrong integer and non-integer data rate, signal stuck high/low conditions , and determine false lock to retimed noise. unlike level based detectors, it cannot determine false lock with low amplitude data. 1.1.21 built-in self test (bist) overview the m21262 contains a bist test pattern generator as we ll as a test pattern receiver . both the bist transmitter (bist tx), and bist receiver (bist rx) are designed to operate with fixed patterns. for prbs evaluation, the prbs 2 7 -1, 2 15 -1, 2 23 -1, and 2 31 -1 test patterns are provided. for 8b/10b testing, the fibre channel crpat and cjtpat standard patterns are supported. in addition, an 8b/ 10b countdown pattern is also provided; this is the 8b/ 10b representation of a binary count from 255 to 0, wh ile maintaining 8b/10b running disparity requirements. user programmable 16 bit (prbs) and 20 bit (8b/10b) patterns are also provided; they are typically used to generate short patterns for debug, such as 1100b, as well as 8b/10b idle or control characters. the bist is designed to reduce system development time, as well as product test costs, and can be used by both the equipment provider as well as the equipment end user. when enabled, the bist rx allows one input from the m2 1262 to enter the bist receiver. the desired channel to monitor is selected through a control register. the bist rx uses the recovered clock and data from the selected cdr/rclk to drive the pattern checker. every time a bit er ror is received, the error register is incremented. the maximum number of errors is ffh, and a ll subsequent errors will not be counted. at any time, the error register can be cleared. by keeping track of the time between a clear and a read, a rough ber number can be obtained. when enabled, the bist tx can output a test pattern to the m21262 output (the bist tx and rx can be used at the same time). the bist tx contains an internal clock multiplier (pll), that can take its input from either the external reference frequency, or from the sa me cdr/rclk that is driving the bist rx (only in full-rate mode, drd = 1). 1.1.22 bist test patterns the test pattern is selected with bisttx_ctrl [5:2] for the transmitter, and bistrx_ctrl [5:2] for the receiver. the prbs patterns generated by the unit are itu-t 0.151 compliant, and summarized in the table below.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 20 cdr/reclocker with 4:1 input multiplexer rev v3 for 8b/10b data, three patterns are available. the cj tpat and crpat comply with the fibre channel t11.2/ project 1230/rev10 specifications. two user programmable patterns that are 16 bits long ( bisttx_ctrl [5:2] = bistrx_ctrl [5:2] = 0111b) and 20 bits long ( bisttx_ctrl [5:2] = bistrx_ctrl [5:2] = 1000b) are determined with bist_pattern0 , bist_pattern1, bist_pattern2 . note that the contents of these registers is used by both the bist tx and the bist rx, if they are setup in this mode. 1.1.23 bist receiver (bist rx) operation the bist rx is enabled and powered up by setting bistrx_ctrl [1] = 1b (off by default), resetting the bist rx block with bistrx_ctrl [0] = 1b (default), and selecting a pattern with bistrx_ctrl [5:2]. the signal to the bist rx is routed from the input of the device, and the bist rx can only ch eck one channel at a time. the desired channel to monitor is selected with bistrx_chsel [2:0]. the bist rx uses the recovered clock from the cdr/rclk to drive the bist state machine, thus the cdr/ rclk must be enabled a nd locked to data fo r proper operation. when the data is valid, bistrx_ctrl [6] = 1b is used to clear the error register, and a ll subsequent errors can be read back through bistrx_error . the bist rx automatically synchronizes the input data with the pattern. 1.1.24 bist transmitter (bist tx) operation the bist tx is enabled and powered up by setting bisttx_ctrl [1] = 1b (off by default), resetting the bist tx block with bisttx_ctrl [0] = 1b (default), and selecting a pattern with bisttx_ctrl [5:2]. the high-speed clock of the bist tx is generated from its own frequency multiplier pll, th at uses a selectable frequency reference determined by bisttx_ctrl [6]. with bisttx_ctrl [6] = 0b (default), the external referenc e clock is used and typically gives the lowest jitter output. with bisttx_ctrl [6] = 1b the reference clock is derived from the same cdr/rclk used to drive the bist rx (this fe ature only works with drd = 1 fo r that cdr/rclk). in this mo de, the bist tx output is synchronous with the cdr/rclk used in the bist rx, howeve r, it contains the low-frequency jitter from the input data. in either case, the bist tx pll needs to be conf igured for the proper data rate. when the pll is properly table 1-17. bist prbs patterns bisttx_ctrl [5:2] / bistrx_ctrl [5:2] pattern polynomial 0000b prbs 2 7 -1 2 7 +2 6 +1 0001b prbs 2 15 -1 2 15 +2 14 +1 0010b prbs 2 23 -1 2 23 +2 18 +1 0011b prbs 2 31 -1 2 31 +2 28 +1 table 1-18. bist 8b/10b patterns bisttx_ctrl [5:2] / bistrx_ctrl [5:2] pattern 0100b cjtpat 0101b crpat 0110b countdown
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 21 cdr/reclocker with 4:1 input multiplexer rev v3 configured and locked to the reference, the lol flag should be low ( bisttx_alarm [7]). a bit error can be intentionally inserted into th e bist tx output, by providing a 0b, 1b, 0b sequence to bisttx_ctrl [7] . the bist tx pll setup is similar to the cdr/rclk setup, thus, the description of si milar registers for the cdr/ rclk also applies and will not be re peated here. the desired output data rate is set with the drd register ( bisttx_pll_ctrlb [3:0]) and with the vcd register ( bisttx_pll_ctrlc [7:0]). the input reference frequency ifr is the same as for the main cdr/rclks, since the same exte rnal reference and reference dividers are used. in the internal cdr/rclk case, ifr is f vco, rxrclk /128, where f vco, rxrclk is the vco frequency of the cdr/rclk selected by bistrx_chsel [2:0]. unlike the cdr/rclk, the tx pl l always makes ifr equal to ifv, and bisttx_alarm [7] is used to determine if the tx pll is in lock. li ke the cdr/rclks, if the output data rate of the bist tx needs to be changed, the bist tx requires a soft reset. 1.1.25 junction temperature monitor an internal junction temperature monitor with a range of -4 0c to 130c is integrated into the m21260. on the low end, the temperature monitor (tmon) is set to measure - 40c to 10c in six 10c steps, and on the high end, 80c to 130c in six 10c steps. the typical temperature reso lution is 3c. the temperature monitor is enabled with temp_mon [1] = 1b. when enabled, the temperature measurement cycle is achieved by providing a rising edge for temp_mon [0]. afterwards, the correct temperature can be read from temp_value [3:0] . ta b l e 1 -1 9 shows the mapping of the temperature to temp_value [3:0] . enabling and strobing the temperature in the same write cycle will not yield reliable results. 1.1.26 ic identification / revision code the ic identification can be read back from chipcode, and the revision of the device can be read back from revcode . table 1-19. junction temperature monitor junction temperature temp_value [3:0] condition tc 130c 1100b high-alarm 130c > tc 120c 1011b high-alarm 120c > tc 110c 1010b high-warning 110c > tc 100c 1001b normal 100c > tc 90c 1000b normal 90c > tc 80c 0111b normal 80c > tc 10c 0110b normal 10c > tc 0c 0101b normal 0c > tc -10c 0100b normal -10c > tc -20c 0011b normal -20c > tc -30c 0010b warning -30c > tc -40c 0001b low-alarm -40c > tc 0000b low-alarm
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 22 cdr/reclocker with 4:1 input multiplexer rev v3 1.2 pin definitions table 1-20. power pins pin number pin name function type exposed pad vss ic ground power 1, 31, 54, 63, 64 avdd_i/o analog i/o positive supply power 21, 27, 28, 34, 57, 60, 67, 70 avdd_core analog core positive supply power 10 dvdd_i/o digital i/o posit ive supply power 11, 22, 33 dvdd_core digital core posit ive supply power notes: 1. if internal regulator is enabled, connect all of the avdd_core and/or dvdd_core pins together to a common floating plane and bypass to vss . 2. if internal regulator is not enabled, it is recommended that all avdd_core pins be tied to a plane at 1.2v, that is bypassed to ground. dvdd_core can be tied to this plane or separately decoupled. 3. ic ground ( vss ) is established by contact with exposed pad on underside of package; there are no vss pins. table 1-21. high-speed signal pins pin number pin name function termination type 19 din0p serial positive data input for channel 0 50 pull up to vddt0/1 pcml referenced to avdd_core 20 din0n serial negative data input for channel 0 50 pull up to vddt0/1 pcml referenced to avdd_core 25 din1p serial positive data input for channel 1 50 pull up to vddt0/1 pcml referenced to avdd_core 26 din1n serial negative data input for channel 1 50 pull up to vddt0/1 pcml referenced to avdd_core 29 din2p serial positive data input for channel 2 50 pull up to vddt2/3 pcml referenced to avdd_core 30 din2n serial negative data input for channel 2 50 pull up to vddt2/3 pcml referenced to avdd_core 35 din3p serial positive data input for channel 3 50 pull up to vddt2/3 pcml referenced to avdd_core 36 din3n serial negative data input for channel 3 50 pull up to vddt2/3 pcml referenced to avdd_core 23 vddt0/1 termination pin for din [1:0] terminate to avdd_core termination 32 vddt2/3 termination pin for din [3:2] terminate to avdd_core termination 72 doutp serial positive data output 50 pull up to avdd_i/o o?cml/lvds 71 doutn serial negative data output 50 pull up to avdd_i/o o?cml/lvds table 1-22. control, interface, and alarm pins (1 of 2) pin number pin name function default type 2 mf0 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 3 mf1 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 4 mf2 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 23 cdr/reclocker with 4:1 input multiplexer rev v3 5 mf3 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 9 mf4 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 12 mf5 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 13 mf6 multifunction pin for hardwired mode, and serial interface internal pull up i?cmos 43 mf7 multifunction pin for hardwired mode internal pull up i?cmos 52 mf8 multifunction pin for hardwired mode, and jtag internal pull up i?cmos 53 mf9 multifunction pin for hardwired mode, and jtag internal pull up i?cmos 8 mf10 multifunction pin for hardwired mode, serial interface, and jtag internal pull up i?cmos 14 mf11 multifunction pin for hardwired mode, serial interface, and jtag internal pull up i?cmos 6 ctrl_mode0 hardwired or serial interface mode control pin internal pull up i?cmos 7 ctrl_mode1 hardwired or serial interface mode control pin internal pull up i?cmos 44 out_mode0 output data interface control pin internal pull down i?cmos 45 out_mode1 output data interface control pin internal pull down i?cmos 42 xrst reset pin (l = reset) internal pull up i?cmos 15 xjtag_en jtag testing control pin (l = enable) internal pull up i?cmos 24 xregu_en internal voltage regulator control pin (l = enable) internal pull down i?cmos 47 refclkp reference clock positive input internal pull down i?ac coupled 46 refclkn reference clock negative input internal pull down i?ac coupled 37 select_mode_0 selector configuration pin internal pull down i?cmos 38 select_mode_1 selector configuration pin internal pull down i?cmos 69 xen_port0 control pin to enable/disable output for (l = enable) internal pull up i?cmos 16 xlol cdr/rclk loss of lock alarm no internal pull up or pull down o?open drain 48 xloa cdr/rclk loss of activity alarm no internal pull up or pull down o?open drain table 1-22. control, interface, and alarm pins (2 of 2) pin number pin name function default type
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 24 cdr/reclocker with 4:1 input multiplexer rev v3 figure 1-9. m21262 pinout diagram (top view) doutp doutn avdd_core mf5 mf6 mf11 xlol xjtag_en ctrl_mode0 ctrl_mode1 mf3 din2n xregu_en din1n avdd_core avdd_core din2p avdd_i/o din1p din0n vddt0/1 1 2 3 4 5 6 7 8 9 10 11 12 19 20 21 22 23 24 25 26 27 28 29 30 43 44 45 46 47 48 49 50 51 52 53 54 72 71 70 69 68 67 66 65 64 63 62 61 xen_out nc avdd_core nc nc avdd_i/o avdd_i/o nc nc avdd_core nc nc avdd_core nc nc 60 59 58 57 56 55 39 40 41 42 37 38 din0p din3p dvdd_core vddt2/3 avdd_core din3n nc 31 32 33 34 35 36 mf1 mf2 mf0 avdd_i/o 13 14 15 16 17 18 avdd_i/o select_mode_1 select_mode_0 mf9 mf8 refclkp refclkn nc nc nc xloa out_mode1 out_mode0 mf7 xrst nc nc dvdd_core dvdd_i/o nc nc mf10 mf4 avdd_core dvdd_core
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 25 cdr/reclocker with 4:1 input multiplexer rev v3 2.0 product specifications 2.1 absolute maximum ratings these are the absolute maximum ratings at or beyond wh ich the device can be expected to fail or be damaged. reliable operation at these extremes for any length of time is not implied. table 2-1. absolute maximum ratings symbol parameter notes minimum typical maximum units dvdd_i/o digital i/o power ? 0 1.8/2.5/3.3 3.6 v avdd_i/o analog i/o power ? 0 1.8/2.5/3.3 3.6 v avdd_core analog core power 2 0 1.2 1.5 v dvdd_core digital core power 2 0 1.2 1.5 v ? high-speed signal pins 1, 4 v ss - 0.5 ? av dd - i/o + 0.5 ? ? control, interface, and alarm pins 1, 5 v ss - 0.5 ? av dd - i/o + 0.5 ? t st storage temperature ? -65 ? +150 c esd human body model (low-speed) ? 2000 ? ? v esd human body model (high-speed) ? 350 ? ? v esd charged device model ? 100 ? ? v ? maximum dc input current 1, 3 ? ? 25 ma notes: 1. no damage under these conditions. 2. apply voltage to core pin if internal regulator is disabled. if enabled, pins should be floating with bypass to vss. 3. computed as the current through 50 from the voltage difference between the input voltage common mode and v ddt 4. high-speed signal pins are shown in table 1-17 . 5. control, interface, and alarm pins are shown in table 1-18 .
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 26 cdr/reclocker with 4:1 input multiplexer rev v3 2.2 recommended operating conditions 2.3 power dissipation table 2-2. recommended operating conditions symbol parameter notes minimum typical maximum units dvdd_i/o digital i/o power 2 ? 1.8/2.5/3.3 ? v avdd_i/o analog i/o power 2 ? 1.8/2.5/3.3 ? v avdd_core analog core power 1, 2 ? 1.2 ? v dvdd_core digital core power 1, 2 ? 1.2 ? v t a ambient temperature ? -40 ? 85 c ja junction to ambient thermal resistance 3 ? 24 ? c/w notes: 1. needed only if avdd_core or dvdd_core are provided from external source (internal regulator disabled xregu_en =h). 2. typical value 5% is acceptable. 3. with forced convection of 1 m/s and 2.5 m/s, ja is decreased to 18 c/w and 16 c/w respectively. table 2-3. dc power electrical specifications (1 of 2) symbol parameter notes minimum typical maximum units idd case 1: current consumption for output swing = 550 mv cml, internal regulator = on 1 ? 310 365 ma pdiss power dissipation at 1.8v ? ? 560 660 mw pdiss power dissipation at 3.3v 2 ? 1.02 1.2 w idd case 2: current consumption for output swing = 900 mv cml, internal regulator = on 1 ? 340 400 ma pdiss power dissipation at 1.8v ? ? 610 720 mw pdiss power dissipation at 3.3v 2 ? 1.12 1.32 w ? case 3: output swing = 550 mv cml, internal regulator = off 1 ? ? ? ? idd_core core current consumption ? ? 260 300 ma idd_io input/output buffers current consumption ? 50 70 ma pdiss power dissipation at 1.2v core, 1.8v i/o ? ? 400 490 mw pdiss power dissipation at 1.2v core, 3.3v i/o ? ? 480 590 mw idd case 4: current consumption for output swing = 450 mv lvds, internal regulator = on 1 ? 320 380 ma pdiss power dissipation at 1.8v ? ? 580 680 mw pdiss power dissipation at 3.3v 2 ? 1.06 1.25 w
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 27 cdr/reclocker with 4:1 input multiplexer rev v3 2.4 input/output specifications idd case 5: current consumption for output swing = 1.5v pcml+, internal regulator = on 1 ? 410 470 ma pdiss power dissipation at 1.8v ? ? 740 850 mw pdiss power dissipation at 3.3v 2 ? 1.35 1.55 w notes: 1. specified at recommended operating conditions?see table 2-2 . 2. thermal design such as thermal pad vias on pcb must be considered for this case. table 2-4. serial interface (2-wire and 4-wire) cmos i/o electrical specifications symbol parameter notes minimum typical maximum units v oh output logic high i oh = -3 ma 2 0.8 x dvdd_i/o dvdd_i/o ?v v ol output logic low i ol = 24 ma 2 ? 0.0 0.2 x dvdd_i/o v i oh output current (logic high) ? -10 ? 0 ma i ol output current (logic low) ? 0 ? 10 ma v ih input logic high ? 0.75 x dvdd_i/o ? dvdd_i/o + 0.3 v v il input logic low ? 0 ? 0.25 x dvdd_i/o v i ih input current (logic high) ? -100 ? 100 a i il input current (logic low) ? -100 ? 100 a t r output rise time (20?80%) ? ? ? 250 ns t f output fall time (20?80%) ? ? ? 250 ns c2wire input capacitance of mf10 and mf11 in 2-wire serial interface mode. 3? ? 10pf notes: 1. entire table specified at recommended operating conditions?see table 2-2 . 2. dvdd_i/o can be chosen independently from avdd_i/o . 3. 2-wire serial output mode can drive 500 pf. table 2-3. dc power electrical specifications (2 of 2) symbol parameter notes minimum typical maximum units
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 28 cdr/reclocker with 4:1 input multiplexer rev v3 table 2-5. input electrical specifications symbol parameter notes minimum typical maximum units dr in input signal data rate ? 42 ? 3200 mbps v id input differential voltage (p?p) 2, 3 100 ? 2000 mv v icm input common-mode voltage ? 700 ? 1200 mv v ih maximum input high voltage ? ? ? avdd_core + 400 mv v il minimum input low voltage ? 400 ? ? mv r in input termination to vddt 445 50 65 s 11 input return loss (40 mhz to 2.5 ghz) ? ? -15.0 ? db notes: 1. entire table specified at recommended operating conditions?see table 2-2 . 2. example 1200 mv pp differential = 600 mv pp for each single-ended terminal. 3. minimum input level defined as error free operation at 10 -12 ber. 4. see figure 2-1 for input term ination circuit. figure 2-1. data input internal circuitry dinp dinn data input buffer avdd_core r >> 50 r >> 50 50 50 vddt
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 29 cdr/reclocker with 4:1 input multiplexer rev v3 table 2-6. pcml (positive current mode lo gic) output electrical specifications symbol parameter notes minimum typical maximum units dr out output signal data rate (reclockers enabled) ? 42 ? 3200 mbps t r /t f rise/fall time (20?80%) for all levels ? ? 75 130 ps v oh low swing: output logic high (single-ended) ? avdd_i/o - 25 ? avdd_i/o mv v ol low swing: output logic low (single-ended) ? avdd_i/o - 370 ? avdd_i/o - 250 mv v od low swing: differential swing 2 400 550 750 mv v oh medium swing: output logic high (single-ended) ? avdd_i/o - 80 ? avdd_i/o mv v ol medium swing: output logic low (single-ended) ? avdd_i/o - 600 ? avdd_i/o - 420 mv v od medium swing: differential swing 2 700 900 1150 mv v oh high swing: output logic high (single-ended) ? avdd_i/o - 95 ? avdd_i/o mv v ol high swing: output logic low (single-ended) ? avdd_i/o - 770 ? avdd_i/o - 535 mv v od high swing: differential swing 2 900 1200 1500 mv v oh pcml+ swing: output logic high (single-ended) ? avdd_i/o - 115 ? avdd_i/o mv v ol pcml+ swing: output logic low (single-ended) ? avdd_i/o - 1000 ? avdd_i/o - 680 mv v od pcml+ swing: differential swing 2 1150 1500 1900 mv r out output termination to avdd_core ?455065 s 22 output return loss (40 mhz to 2.5 ghz) ? ? -15.0 ? db notes: 1. specified at recommended operating conditions?see table 2-2 . 2. example 1200 mv p?p differential = 600 mv p?p for each single-ended terminal. 3. all output swings defined with pre-emphasis off. table 2-7. lvds (low voltage differential signal ) output electrical specifications (1 of 2) symbol parameter notes minimum typical maximum units dr out output signal data rate (reclockers enabled) ? 42 ? 3200 mbps v ocm output average common mode range 2 ? 1200 ? mv t r /t f gpl: rise/fall time (20?80%) ? ? 75 130 ps v od gpl: differential output (p?p) 3 500 650 800 mv v od rrl: differential output (p?p) ? 300 450 550 mv
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 30 cdr/reclocker with 4:1 input multiplexer rev v3 r out output termination (differential) ? 90 100 130 s 22 output return loss (40 mhz to 2.5 ghz) ? ? -15.0 ? db notes: 1. specified at recommended operating conditions?see table 2-2 . 2. computed as average (average positive output and average negative output). 3. conforms to ieee std 1596.3?1996 for gpl. all values specified for 50 single-ended backmatch, 100 differential load. 4. all output swings defined with pre-emphasis off. 5. see figure 2-2 for definitions of eye parameters. figure 2-2. definitions of eye parameters table 2-7. lvds (low voltage differential signal ) output electrical specifications (2 of 2) symbol parameter notes minimum typical maximum units j pp t f t r v od v oh v ol v oh : average voltage high level v ol : average voltage low level v od :(v oh ) ? (v ol ) j pp : peak -peak output jitter t r : 20-80% rise time t f : 80-20% fall time
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 31 cdr/reclocker with 4:1 input multiplexer rev v3 table 2-8. input equalization performance specifications symbol parameter notes minimum typical maximum units dr in input signal data rate ? 42 ? 3200 mbps ? maximum error-free distance at 3.2 gbps 2, 3, 6, 7 ? ? 60 in ? maximum error-free distance at 1.6 gbps 2, 3, 6, 7 ? ? 72 in notes: 1. specified at recommended operating conditions?see table 2-2 . 2. performance measured on standard fr4 backplane such as standards provided by tyco for 10ge xaui. 3. measured with pcml driver without output pre-emphasis at a minimum launch voltage of 900 mvpp output swing at beginning of li ne. 4. combined input equalization + ou tput pre-emphasis perfor mance will be better than individual performance, but less than the s um of the two lengths. 5. input equalization has greatest effect for data rates higher than 1 gbps. 6. default setting optimized for driving 10?46 in of pcb trace length. equalizer can be configured for longer reach using serial interface. 7. test setup: pattern generator ? test backplane ? dut ? error detector table 2-9. output pre-emphasis performance specifications symbol parameter notes minimum typical maximum units dr out output signal data rate ? 42 ? 1600 mbps ? maximum error-free distance at 3.2 gbps 2, 3, 6 ? ? 40 in ? maximum error-free distance at 1.6 gbps 2, 3, 6 ? ? 60 in notes: 1. specified at recommended operating conditions?see table 2-2 . 2. performance measured on standard fr4 backplane such as standards provided by tyco for 10ge xaui. 3. measured with pcml receiver without input equalization, using pcml output driver at 1200 mvpp output swing at beginning of li ne. 4. combined adaptive equalization + output pre-emphasis performance will be better than individual performance, but less than th e sum of the two lengths. 5. output pre-emphasis has greatest effect for data-rates higher than 1 gbps. 6. test setup: pattern generator ? dut ? test backplane ? error detector
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 32 cdr/reclocker with 4:1 input multiplexer rev v3 table 2-10. reference clock input symbol parameter notes minimum typical maximum units f ref input frequency ( refclk_ctrl [3:1] = 000b) 2, 3 10 19.44 25 mhz f ref input frequency ( refclk_ctrl [3:1] = 001b) 2, 3 20 38.88 50 mhz f ref input frequency ( refclk_ctrl [3:1] = 010b) 2, 3 40 77.76 100 mhz f ref input frequency ( refclk_ctrl [3:1] = 011b) 2, 3 80 155.52 200 mhz f ref input frequency ( refclk_ctrl [3:1] = 100b) 2 120 250 300 mhz f ref input frequency ( refclk_ctrl [3:1] = 101b) 2, 3 160 311.04 400 mhz f ref input frequency ( refclk_ctrl [3:1] = 110b) 2, 3 320 622.08 800 mhz v id input differential voltage (p?p) 4, 5 100 ? 1600 mv v icm input common-mode voltage 2, 5 250 ? avdd_i/o mv ? input duty cycle ? 40 50 60 % ? frequency stability 2 ? ? 100 ppm r in differential termination 5 ? 100 ? ? internal pull-down to vss ?? 100 ? k ? maximum dc input current ? ? ? 15 ma notes: 1. specified at recommended operation conditions?see table 2-2 . 2. used for frequency acquisition. 3. typical values are exact integer ratios for sonet applications. 4. example 1200 mv pp differential = 600 mv pp for each single-ended terminal. 5. input can accept a cmos single-ended clock on differential p term inal when differential n terminal is decoupled to ground wit h a large enough capacitor. cmos input will then see an effective 100 load. 6. see figure 2-3 for input termination circuit.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 33 cdr/reclocker with 4:1 input multiplexer rev v3 figure 2-3. reference clock input internal circuitry 0.5 pf 0.5 pf refclkp refclkn clock input buffer vdd_core 150 k 150 k 100 100 k vss 100 k vss
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 34 cdr/reclocker with 4:1 input multiplexer rev v3 2.5 high-speed performance specifications table 2-11. cdr/rclk high-speed performance (1 of 2) symbol parameter notes minimum typical maximum units dr in input signal data rate (nrz data) divider ratio = 1 ? 2 ? 3.2 gbps dr in input signal data rate (nrz data) divider ratio = 2 ? 1 ? 1.6 gbps dr in input signal data rate (nrz data) divider ratio = 4 ? 500 ? 800 mbps dr in input signal data rate (nrz data) divider ratio = 8 ? 250 ? 400 mbps dr in input signal data rate (nrz data) divider ratio = 12 ? 167 ? 267 mbps dr in input signal data rate (nrz data) divider ratio = 16 ? 125 ? 200 mbps dr in input signal data rate (nrz data) divider ratio = 24 ? 83 ? 133 mbps dr in input signal data rate (nrz data) divider ratio = 32 ? 62.5 ? 100 mbps dr in input signal data rate (nrz data) divider ratio = 48 ? 42 ? 67 mbps j tol jitter tolerance ( figure 2-5 )2?0.625?ui j trf jitter transfer ( figure 2-6 )2, 16???? j gen jitter generation (rms) at sts-n (n = 1, 3, 12, 48) 2, 12 ? 4.5 6.5 mui j gen jitter generation (pp) at sts-n (n = 1, 3, 12, 48) 2, 12 ? 30 55 mui f lbw default loop bandwidth: divider ratio = 1 3, 4, 5 ? ? 2 mhz f lbw default loop bandwidth: divider ratio = 2 3, 4, 5 ? ? 1 mhz f lbw default loop bandwidth: divider ratio = 4 3, 4, 5 ? ? 500 khz f lbw default loop bandwidth: divider ratio = 8 3, 4, 5 ? ? 250 khz f lbw default loop bandwidth: divider ratio = 12 3, 4, 5 ? ? 167 khz f lbw default loop bandwidth: divider ratio = 16 3, 4, 5 ? ? 125 khz f lbw default loop bandwidth: divider ratio = 24 3, 4, 5 ? ? 83 khz f lbw default loop bandwidth: divider ratio = 32 3, 4, 5 ? ? 62.5 khz f lbw default loop bandwidth: divider ratio = 48 3, 4, 5 ? ? 41.6 khz r j output data random jitter (pp) 13 ? ? 100 mui d j output data deterministic jitter (pp) 13 ? ? 110 mui t j output data total jitter (pp) 13 ? ? 210 mui j rms output data broadband jitter (rms) 14, 15 ? 13 40 mui j pp output data broadband jitter (pp) 14, 15 ? 75 230 mui t lat latency from input to output (utilizing cdr) ? ? 1.75 2 ns ch sk channel to channel output data skew (utilizing cdr) ? ? 10 65 ps ? initialization time 6, 7, 10 ? 2 ? ms t fra frequency acquisition time 6, 8 ? 0.4 ? ms
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 35 cdr/reclocker with 4:1 input multiplexer rev v3 t pll phase lock time with 100 ppm delta f 9, 11 ? ? 100 ns t pll phase lock time with 0 ppm delta f 9, 11 ? ? 50 ns notes: 1. specified at recommended operating conditions?see table 2-2 . 2. jitter tolerance, jitter transfer, and jitter generation specified with input equalization and output pre-emphasis disabled, utilizing prbs 2 23 -1, per gr-253 test methodologies. 3. nominal loop bandwidth for 2.48832 ghz/ drd. 4. bandwidth is proportional to frequency. 5. for sonet data rates, default meets sonet specifications. 6. assume that reference is within 100 ppm of desired data rate. 7. time after power up, reset, or data rate change. 8. time from application of valid data to lock within 20% of lock phase. 9. defined as when phase settles to within 20% of lock phase. 10. after reset (master or soft), initialization takes place, then frequency acquisition. 11. based on nominal sonet bandwidth (bandwidth can be increased for lower phase lock time). 12. jitter generation specified per gr-253, utilizing bandpass filter with passband 12 khz to 20 mhz for sts-48. 13. r j , d j , t j represent jitter measured to ber of 10 -12 per fc-pi-2 specifications. 14. broadband jitter de fined as jitter measured on sampling oscilloscope wi thout the use of filters. 15. maximum value specified incorporates asynchronous aggressors. 16. jitter transfer of cdr meets the sonet sts-48 mask if loop bandwidth is set to 80% of nominal by writing phadj_ctrl _n[5:4] = 00b. jitter transfer at sts-12 (sts-3) exceeds mask by 0.1 db in frequency range 10 - 25.1 khz (1.5 - 10 khz). table 2-12. cdr/rclk alarm performance symbol parameter notes minimum typical maximum units dt loa xloa decision time 5 ? 26 ? s ? xloa assertion transition density threshold ( xloa = h to l) 5, 6 ? 12.5 ? % ? xloa de-assertion transition density threshold ( xloa = l to h) 5, 6 ? 12.5 ? % dt lol xlol decision time (measurement time) 2 10 420 3275 s wrw xlol assertion frequency threshold ( xlol = h to l) 2, 3 185 2930 250000 ppm nrw xlol de-assertion frequency threshold ( xlol = l to h) 2, 3 120 1955 250000 ppm notes: 1. specified at recommended operating conditions?see table 2-2 . 2. actual time is set with lol window. typical is the default value. minimum and maximum indicate dynamic range. 3. assume that reference is 50 ppm of operating frequency. 4. computed for 1.4835 gbps data rate. will scale with data rate. 5. fixed values. 6. specification shown represents deviation from 50% transition density. table 2-11. cdr/rclk high-speed performance (2 of 2) symbol parameter notes minimum typical maximum units
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 36 cdr/reclocker with 4:1 input multiplexer rev v3 figure 2-4. jitter tolerance specification mask table 2-13. smpte jitter tolerance mask jitter parameter smpte 259m smpte 292m f1 10 hz 10 hz f3 1 khz 100 khz f4 >27 mhz >148.5 mhz a1 1.0 ui 1.0 ui a2 0.2 ui 0.2 ui figure 2-5. sonet jitter tolerance specification mask a1 a2 f1 f2 f3 f4 sinusoidal input jitter amplitude jitter frequency -20 db/decade slope input jitter amplitude (uipp) slope = -20 db/decade 6k 15 10 / n 600 / n 100k 214k 1.5 j jitter frequency (hz) 0.15 macom specification 1m / n gr-253 sonet specification / n / n / n tol
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 37 cdr/reclocker with 4:1 input multiplexer rev v3 figure 2-6. jitter transfer specification mask table 2-14. loop bandwidths for typical video data rates application bit rate (mbps) value of n approximate loop bw (f) 2xhd-sdi 2967/2970 0.84 2.38 mhz hd-sdi 1485/1483.5 1.68 1.19 mhz 2xsd-sdi 540 4.6 435 mhz progressive scan 360 6.9 290 khz sd-sdi 270 9.2 217 khz legacy comp video 177 14.1 142 khz legacy comp video 143 17.4 115 khz slope = -20 db/decade f 0.1 jitter gain (db) jitter fre q uenc y ( hz )
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 38 cdr/reclocker with 4:1 input multiplexer rev v3 2.6 package drawings and surface mount assembly details the m21262 is assembled in 72-pin 10 mm x 10 mm microleadframe (mlf) packages. this is a plastic encapsulated package with a copper leadframe. the mlf is a leadless package with lands on the bottom surface of the package. the exposed die paddle serves as the ic ground ( vss ), and the primary means of thermal dissipation. this die paddle should be soldered to the pcb. a cross-section of the mlf package can be found in figure 2-7 . figure 2-7. cross-section of mlf package mold compound gold wire die attach material exposed die paddle ground bond down bond cu leadframe solder plating ag plating die
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 39 cdr/reclocker with 4:1 input multiplexer rev v3 figure 2-8 and figure 2-9 shows the package outline drawing for the 10 mm x 10 mm mlf package. figure 2-8. package drawing (1of 2) 0.80 dia. 0 . 8 0 d i a . d1/2 d 1 / 2 d1 d 1 d/2 d / 2 d d e1/2 e 1 / 2 e/2 e / 2 e1 e 1 e e 2x 2 x a a 2x 2 x 0.10 0 . 1 0 b b c c a a n n seating s e a t i n g plane p l a n e 5 5 6 6 2 2 3 3 1 1 0.08 0 . 0 8 c c c c 0.10 0 . 1 0 2x 2 x a a 0.10 0 . 1 0 0.10 0 . 1 0 2x 2 x b b 0 0 a1 a 1 10 1 0 c c c c c c a3 a 3 a2 a 2 a a b b top view side view
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 40 cdr/reclocker with 4:1 input multiplexer rev v3 figure 2-9. package drawing (2 of 2) 0. 1 0 0 . 1 0 b b a a m m c c s eating s e a t i n g plane p l a n e n n b b e e 1 1 l l ref. r e f . ( n d -1)xe ( n d - 1 ) x e ( ne-1 ) xe ( n e - 1 ) x e r ef . r e f . 4 4 2 2 2 3 3 4x p 4 x p 4 x p 4 x p d 2 d 2 d 2 / 2 d 2 / 2 e 2 e 2 e 2 / 2 e 2 / 2 p in1 i d p i n 1 i d 0. 2 0 r. 0 . 2 0 r . 0.4 5 0 . 4 5 0. 2 5 min 0 . 2 5 m i n 0. 2 5 min. 0 . 2 5 m i n . s ee detail " a " s e e d e t a i l " a " fo r pin #1 id and f o r p i n # 1 i d a n d t ie bar mark o pti o n t i e b a r m a r k o p t i o n bo tt o m vie w terminal tip t e r m i n a l t i p c l c c l l e e for odd terminal/sid e terminal tip e e l c l l c c c c c c for even terminal/sid e b 4 sc ale : n o n e a1 11 1 1 s e c ti o n " c - c "
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 41 cdr/reclocker with 4:1 input multiplexer rev v3 the relevant dimensions for the 72-pin version of the package can be found in figure 2-10 . figure 2-10. 72-pin package dimensions m m nd n d e e n n b b l l d2 d 2 q q e2 e 2 ne n e y y s s pitch variation d p i t c h v a r i a t i o n d nom. n o m . 18 1 8 72 7 2 0.23 0 . 2 3 0.40 0 . 4 0 0.20 0 . 2 0 18 1 8 0.50 bsc 0 . 5 0 b s c see exposed pad variation:c s e e e x p o s e d p a d v a r i a t i o n : c see exposed pad variation:c s e e e x p o s e d p a d v a r i a t i o n : c 0.18 0 . 1 8 0.30 0 . 3 0 0.00 0 . 0 0 min. m i n . o o l l b b 3 3 0.30 0 . 3 0 0.50 0 . 5 0 0.45 0 . 4 5 4 4 max. m a x . o o n n t t 3 3 3 3 e e 12 1 2 12 1 2 dimensions d i m e n s i o n s d d p p 0.24 0 . 2 4 r r 0.13 0 . 1 3 d1 d 1 e1 e 1 0 0 e e o o l l b b a a a1 a 1 a2 a 2 a3 a 3 - - min. m i n . - 0.00 0 . 0 0 y y m m s s 10.00 bsc 1 0 . 0 0 b s c 0.60 0 . 6 0 0.23 0 . 2 3 0.42 0 . 4 2 0.17 0 . 1 7 9.75 bsc 9 . 7 5 b s c 9.75 bsc 9 . 7 5 b s c 10.00 bsc 1 0 . 0 0 b s c 12 1 2 ? ? max. m a x . 0.20 ref. 0 . 2 0 r e f . nom. n o m . 0.85 0 . 8 5 0.01 0 . 0 1 0.65 0 . 6 5 0.90 0 . 9 0 0.05 0 . 0 5 0.70 0 . 7 0 common c o m m o n e e o o t t 11 1 1 n n variations v a r i a t i o n s exposed pad e x p o s e d p a d symbols s y m b o l s min m i n min m i n max m a x nom n o m d2 d 2 nom n o m max m a x e2 e 2 note n o t e 5.85 5 . 8 5 5.85 5 . 8 5 c c 6.15 6 . 1 5 6.00 6 . 0 0 6.00 6 . 0 0 6.15 6 . 1 5 dimension b applies to plated terminal and is measured d i m e n s i o n b a p p l i e s t o p l a t e d t e r m i n a l a n d i s m e a s u r e d 1. die thickness allowable is 0.305mm maximum(.012 inches maximum) 1 . d i e t h i c k n e s s a l l o w a b l e i s 0 . 3 0 5 m m m a x i m u m ( . 0 1 2 i n c h e s m a x i m u m ) notes: n o t e s : 2. dimensioning & tolerances conform to asme y14.5m. - 1994. 2 . d i m e n s i o n i n g & t o l e r a n c e s c o n f o r m t o a s m e y 1 4 . 5 m . - 1 9 9 4 . 4. 4 . 7. 7 . all dimensions are in millimeters. a l l d i m e n s i o n s a r e i n m i l l i m e t e r s . package by using indentation mark or other feature of package body. p a c k a g e b y u s i n g i n d e n t a t i o n m a r k o r o t h e r f e a t u r e o f p a c k a g e b o d y . the pin #1 identifier must be existed on the top surface of the t h e p i n # 1 i d e n t i f i e r m u s t b e e x i s t e d o n t h e t o p s u r f a c e o f t h e 5. 5 . exact shape and size of this feature is optional. e x a c t s h a p e a n d s i z e o f t h i s f e a t u r e i s o p t i o n a l . 6. 6 . n is the number of terminals. n i s t h e n u m b e r o f t e r m i n a l s . nd is the number of terminals in x-direction & n d i s t h e n u m b e r o f t e r m i n a l s i n x - d i r e c t i o n & ne is the number of terminals in y-direction. n e i s t h e n u m b e r o f t e r m i n a l s i n y - d i r e c t i o n . 3. 3 . between 0.20 and 0.25mm from terminal tip. b e t w e e n 0 . 2 0 a n d 0 . 2 5 m m f r o m t e r m i n a l t i p . package warpage max 0.08mm. p a c k a g e w a r p a g e m a x 0 . 0 8 m m . 9. 9 . applied only for terminals. a p p l i e d o n l y f o r t e r m i n a l s . 10. 1 0 . applied for exposed pad and terminals. a p p l i e d f o r e x p o s e d p a d a n d t e r m i n a l s . 11. 1 1 . exclude embedding part of exposed e x c l u d e e m b e d d i n g p a r t o f e x p o s e d pad from measuring. p a d f r o m m e a s u r i n g . q and r applies only for straght tiebar shapes. q a n d r a p p l i e s o n l y f o r s t r a g h t t i e b a r s h a p e s . 12. 1 2 . 8. 8 . the shape shown on four corners are not actual i/o. t h e s h a p e s h o w n o n f o u r c o r n e r s a r e n o t a c t u a l i / o . detail "a" - pin #1 id and tie bar mark option standard s t a n d a r d
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 42 cdr/reclocker with 4:1 input multiplexer rev v3 the m21262 evaluation module (evm) uses the pcb footprint shown in figure 2-11 . figure 2-11. pcb footprint for 72-pin 10 mm mlf package note : pads placed on a .374 mils square (9.5 mm). add as many vias to ground in .290 square pad as possible. add .025 round clearances on soldermask in an even pattern to help solder ground pad. inner pad: .290 sq (7.650 mm) pad size: .011 x .020 (mils) pitch: .0197 mils (0.5 mm)
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 43 cdr/reclocker with 4:1 input multiplexer rev v3 the pad length dimensions should account for componen t tolerances, pcb tolerances, and placement tolerances. at a minimum, the pad should extend at least 0.1 mm on the outside an d 0.05 mm on the inside, as shown in figure 2-12 . to efficiently dissipate heat from the m21262, a therma l pad with thermal vias sh ould be used on the pcb. an example of a thermal pad with a 4x4 via array is shown in figure 2-13 . the thermal vias provide a heat conduction path to inner and/or bottom layers of the pcb. the larger the via array, the lower the thermal resistance ( ja ) . it is recommended to use thermal vias with 1.0 to 1. 2 mm pitch with 0.3 to 0.33 mm via diameter. for further details please refer to the relevant applicati on note from package vendor amkor (see list of references at the end of this document). much of the material in this section has been adopted from the amkor smt application note. figure 2-12. pcb pad extensions figure 2-13. recommended via array for thermal pad .1 mm .05m m pcb pad
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 44 cdr/reclocker with 4:1 input multiplexer rev v3 2.7 pcb high-speed design and layout guidelines a single power plane for the avdd_io and avdd_core power supplies with bulk ca pacitors (typically 10 f) distributed throughou t the board will mitigate most po wer-rail related voltage transie nts. a bulk capacitor should also be placed where the power enters the board. it is recommended that decoupling capacitors only be routed directly to the power pin if they can be placed within 1/8 of an inch of the pin. decoupling capacitors should be dispersed around the outside of the device on the top side and underneath the ic on the bottom side of the board. it is recommended that 0.1 f and 0.01 f decoupling capacitors be used. all three capacitor values are not required on each pin, but should be dispersed un iformly to filter different frequencies of noise. a continuous ground plane is the best way to minimize ground impedance. return currents and power supply transients produce most ground noise during switching. reducing ground plane impedance minimizes this effect. there is a high frequency decoupling effect from the capaci tive effect of power/ground planes and this can be used to help minimize the amount of hi gh frequency decoupling capacitors. high-speed pcml signals should be routed with 50 equal length traces for p and n signals within each differential pair. buried strip line is recommended for intern al layers while microstrip line is used for signals routed on surface layers. there should be no discontinuity in the ground planes during the pa th of the signal traces. impedance discontinuities occur when a signal passes th rough vias and travels between layers. it is recommended to minimize the number of vias and laye rs that the transmit/receive signals travel through in the design. the system pcb should be designed so that high-speed signals pass th rough a minimal number of vias and remain on a single internal high-speed routing layer. when vias need to be used, the via design should ma tch the transmission line impedance by observing the following: ? avoid through-hole vias; they cause stubs by extending the full cross-section of the pcb despite the fact that the layer change requires only a small length via (as in the case of adjacent layers). use short blind vias. ? avoid layer changes in general as the characteristic impedance of the transmission line changes as a result. in general, some general rules for pcb design for high data rates are: ? pcb trace width for high-speed signals should closel y match the smt component width, so as to prevent stub effects from a sudden change in stripline width. a gradu al increase in trace width is recommended as it meets the smt pad. ? the pcb ground/power planes should be removed from under the i/o pins so as to reduce parasitic capacitance. ? high-speed traces should avoid sh arp changes in direction. using large radii will minimize impedance changes. avoid bending traces by more than 45 degrees; otherwise, provide a circular bend so as to prevent the trace width from widening at the bend. ? avoid trace stubs by minimizing components (resistors , capacitors) on the board. for instance, a termination resistor at the input of a receiver will inflict a stub effect at high frequency. termination resistors in tegrated on chip will eliminate the stub. componen ts designed to dc couple to one another avoid the need for coupling capacitors and the inherent stubs created from them. for high-speed differential signals, the trace lengths of each side of the differential pair should be matched to each other as much as possible. the skew between the p and n si gnals in a differential pair should be tightly controlled in order for the differential receiver to detect a valid data transition. when matching trace lengths within a
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 45 cdr/reclocker with 4:1 input multiplexer rev v3 differential pair, care should be taken to avoid introdu cing large impedance discontin uities. the figures below show two methods of matching the trace lengths for a differential pair. typically, the preferred solution for trace length matching in di fferential pairs is to use a serpentine pattern for the shorter signal as shown in figure 2-14 . using a serpentine pattern for length matching will minimize the differential impedance discontinuity while making both trace lengths equal. the loop length matching method shown in figure 2-15 will match the trace lengths of a differential pair, but will create a large impedance discontinuity in the transmission lin e, which could result in higher jitter on the signal and/ or a greater sensitivity to noise for the differential pair. when using capacitors to ac-couple the input, care shou ld be taken to minimize the pattern-dependant jitter (pd j ) associated with the low-frequency cutoff of the coupling ne twork. when nrz data containing long strings of 1s or 0s is applied to a high-pass filter, a voltage droop occurs. this voltage droop causes pd j in much the same fashion as inter-symbol interference (isi) is generated from disper sion effects of long trace lengths in backplane material. if needed, use 0.1 f capacitors to ac-couple the high-speed output signals, and the reference clock inputs. the high-speed data input signals can be dc-coupled. on the evaluation module (evm), we have tied dvdd_i/o and avdd_i/o together to minimize the number of power supply jacks. they are kept se parate on-chip to give th e flexibility to the system designers to supply a different voltage level for each. for instance, an fpga can be used to supply power to dvdd_i/o , while a lower voltage can be used to power avdd_i/o to minimize power dissipation. on the evm, we have also tied dvdd_core and avdd_core together to minimize the number of powe r supply jacks. they are kept separate on- chip to provide more isolation, however, if the system board plane is properly decoupled, they can be tied together. no inductive filtering on the system board is necessary be tween different power supplies of the ic. it is up to the system designer to determine if this needs to be consider ed for supplies that are coming from other parts of the system board (such as switching regulators or asics). an inductor should not be used at the vddt pins. these pins were made available to create a low ac impedance, such that the 50 on-chip termination impedances see a common ac ground. this assures both common-mode and differential termination. if common-mode termination is not important (such as in lvds applications), simply figure 2-14. trace length matching using serpentine pattern figure 2-15. loop length matching for differential traces
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 46 cdr/reclocker with 4:1 input multiplexer rev v3 leave the vddt pins floating. note that a low ac imp edance can also be created by tying the vddt pins to the avdd_i/o plane, thus saving on the number of external capacitors. this, however, implies a cml-like data interface (unless the data is ac-coupled). vddt is not really a supply plane on-chi p, it is simply the point to which the 50 input impedances are tied. power planes should be decoupled to ground planes us ing thin dielectric layers, to increase capacitance (preferably 2?4 mils). reference ground layers should be used on both sides of inner layer routing planes, with controlled impedance. the tota l board thickness should meet the standa rd drill holes to board thickness ratio of 1:12 or 1:14. use 1/2 ounce copper clad on all layers, which is approxima tely 0.7 mils. avoid placing solder mask and silkscreen on top of transmission lines ; solder mask will add 1?2 to the overall impedance of the transmission line. dielectric core material should be used wherever possible, as it will maintain its thic kness and geometry during processing, better than pliable prepreg. the microwave ground should follow the transmission line from end to end, or from signal input to output. it is best to designate layers as dedicated microwave/circuit grou nd planes, and properly isolate them from other ground planes by providing adequate distance. all micr owave ground planes should be tied together. uncoupled microstrip transmission lines should be placed at a distance from each other of at least three times the transmission line width. coupled microstrip transmission lines , such as differential signal pairs, must be placed close to each other and maintain the same separation distance throughout the board (separation distance of at most twice the trace width). for buried stripline transmission lines, it is good design practice to maintain equal distance between the conductor and the ground plane on both sides. during pcb manufacturing, over- and under-etching of tr aces used for transmission lines results in impedance discontinuities. use of wide traces for transmission lines will reduce the impact of etching issues. wide traces also help compensate for skin-effect losses in transmission lines. it should be noted, however, that the wider the traces in a differential pair, the thicker the underlying dielectric layer needs to be. surface mount connectors are preferred over through-moun t connectors. connectors should be selected that have controlled characteristic impedances that match the characte ristic impedances of t he transmission lines. 2.8 auto rate detect (ard) for many video applications, cdr/reclockers are required to auto rate detect (ard) the incoming data rate. macom has developed a reference design for an ard implem entation. the reference design includes binary files for the ard software and a hardware reference design based on the atmel at89c51rx2 series of micro controllers. the ard automatically config ures the device for nine possible fi xed data rates of 143, 177, 270, 360, 540, 1483.5, 1485, 2967, or 2970 mbps for the m21262. if desired, customers can expand the ard code to include operation at other data rates. please refer to the m2125x and m2126x ard software description documents for details on macom?s implementation of ard for this device.
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 47 cdr/reclocker with 4:1 input multiplexer rev v3 3.0 registers table 3-1. register table summary addr register name d7: msb d6 d5 d4 d3 d2 d1 d0: lsb common registers 00h globctrl powerup rsvd int rsvd int rsvd int rsvd int rsvd int reserved clear_alm 01h mux_ctrl port3[1] port3[0] port2[1] port2[0] port1[1] port1[0] port0[1] port0[0] 04h refclk_ctrl reserved reserved reserved reserved ref_divr[2] ref_divr[1] ref_divr[0] rsvd int 05h mastreset rst rst rst rst rst rst rst rst 06h chipcode chipcode[7] chipcode[6] chipcode[5] chipcode[4] chipcode[3] chipcode[2] chipcode[1] chipcode[0] 07h revcode revcode[7] revcode[6] revcode[5] revcode[4] revcode[3] revcode[2] revcode[1] revcode[0] 11h bistrx_ctrl rsvd int rx_ctrclr rsvd int rsvd int rsvd int rx_patt[0] en_rx rx_rst 12h bistrx_error err[7] err[6] err[5] err[4] err[3] err[2] err[1] err[0] 14h bisttx_chsel reserved reserved reserved reserved rsvd int rsvd int rsvd int tx_chan_0 15h bisttx_ctrl err_insert rx2txclk tx_patt[3] tx_patt[2] tx_patt[1] tx_patt[0] en_tx tx_rst 17h bisttx_lolctrl rsvd int rsvd int tacq_lol[0] rsvd int rsvd int rsvd int narwin_lol[0] widwin_lol[0] 18h bisttx_pll_ctrla softreset rsvd int reserved rsvd int reserved rsvd int reserved rsvd int 19h bisttx_pll_ctrlb pllmode[1] pllmode[0] rsvd int rsvd int data_rate[3] data_rate[2] data_rate[1] data_rate[0] 1ah bisttx_pll_ctrlc vco_divr[7] vco_divr[6] vco_divr[5] vco_divr[4] vco_divr[3] vco_divr[2] vco_divr[1] vco_divr[0] 1bh bist_pattern0 ? ? ? ? pattern[19] pattern[18] pattern[17] pattern[16] 1ch bist_pattern1 pattern[15] pattern[14] pattern[13] pattern[12] pattern[11] pattern[10] pattern[9] pattern[8] 1dh bist_pattern2 pattern[7] pattern[6] pattern[5] pattern[4] pattern[3] pattern[2] pattern[1] pattern[0] 1fh bisttx_alarm tx_lol reserved reserved rsvd int rsvd int rsvd int rsvd int rsvd int 20h temp_mon ? ? ? ? reserved reserved en_temp_mon strobe_temp 21h temp_value ? ? ? ? temp[3] temp[2] temp[1] temp[0] 30h alarm_lol rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int lol 31h alarm_loa rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int loa 40h rclk_ctrla softreset rsvd int inh_force rsvd int autoinh_en rsvd int loa_en rsvd int 41h rclk_ctrlb rclkmode[1] rclkmode[0] rsvd int reserved data_rate[3] data_rate[2] data_rate[1] data_rate[0] 42h rclk_ctrlc vco_divr[7] vco_divr[6] vco_divr[5] vco_divr[4] vco_divr[3] vco_divr[2] vco_divr[1] vco_divr[0] 43h out_ctrl outlvl[1] outlvl[0] reserved reserved data_pol_flip dataout_en rsvd int rsvd int 44h preemp_ctrl reserved rsvd int rsvd int rsvd int rsvd int preemph[2] preemph[1] preemph[0] 45h ineq_ctrl reserved rsvd int rsvd int en_dcservo rsvd int in_eq[2] in_eq[1] in_eq[0] 46h phadj_ctrl i_trim[1] i_trim[0] r_sel[1] r_sel[0] phase_adj[3] phase_adj[2] phase_adj[1] phase_adj[0] 49h lol_ctrl rsvd int rsvd int tacq_lol[0] rsvd int rsvd int rsvd int narwin_lol[0] widwin_lol[0] 4ah jitter_red rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int rsvd int
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 48 cdr/reclocker with 4:1 input multiplexer rev v3 3.1 global control registers nomenclature: 1. reserved bits: bits that exist and reserved for future use by macom. 2. bits not defined and not reserved do not exist. 3. do not write to reserved or undefined bits?operation not guaranteed. 4. macom internal: defines an internal function. must always write the default value to macom internal bits. when in doubt, read back default value after reset. 3.1.1 global control 3.1.2 input multiplexer settings table 3-2. global control ( globctrl : address 00h) bits type default label description 7 r/w 1b powerup powers up the ic by enabling the current references. 0b: power down the ic 1b: power up the ic (chip powerup) 6:2 r/w 00000b rsvd internal n/a 1 r/w 0b reserved n/a 0 r/w 0b clear_alm clears alarm_lol and alarm_lol alarm registers (write only) . 0b: normal operation?latch alarm bits 1b: clear alarms note : upon writing a 1b to this bit, it clears the registers, and user needs to write a 0b to enable the normal state. table 3-3. input multiplexer setting ( mux_ctrl : address 01h) bits type default label description 7:2 r/w 111001 reserved n/a 1:0 r/w 00b output determines input channel for output. 00b: selects input 0 01b: selects input 1 10b: selects input 2 11b: selects input 3
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 49 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.3 external reference freq uency divider control (rfd) 3.1.4 master ic reset 3.1.5 ic electronic identification 3.1.6 ic revision code table 3-4. external reference frequency divider control (rfd) ( refclk_ctrl : address 04h) bits type default label description 7:4 r/w 0b reserved n/a 3:1 r/w ref_divr sets the divider ratio to scale down refclk to the internal rate. 000b: divide by 1 001b: divide by 2 010b: divide by 4 011b: divide by 8 100b: divide by 12 101b: divide by 16 110b: divide by 32 0 r/w 0b rsvd internal n/a table 3-5. master ic reset ( mastreset : address 05h) bits type default label description 7:0 r/w 0b rst same feature as hardware xrst . resets the entire ic. 00h: normal operation [default] aah: reset upon write to this register with aah note : all other values are ignored. table 3-6. ic electronic id ( chipcode : address 06h) bits type default label description 7:0 r tbd chipcode this register contains the identification of this ic. table 3-7. ic revision code ( revcode : address 07h) bits type default label description 7:0 r tbd revcode this register contains the revision of the ic.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 50 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.7 built in self-test (bist) receiver main control register 3.1.8 built in self-test (bist) receiver bit error counter table 3-8. built in self-test (bist) receiver main control register ( bistrx_ctrl : address 11h) bits type default label description 7 r/w 0b rsvd internal n/a 6 r/w 0b rx_ctrclr clear the bist rx error count register, bistrx_error (active when bistrx_ctrl [1] = 1). 0b: normal operation 1b: clear register 5:2 r/w 0000b rx_patt selects the bist rx test pattern (active when bistrx_ctrl [1] = 1). 0000b: prbs 2 7 -1 0001b: prbs 2 15 -1 0010b: prbs 2 23 -1 0011b: prbs 2 31 -1 0100b: fibre channel cjtpat 0101b: fibre channel crpat 0110b: 8b/10b countdown pattern 0111b: 16 bit user programmable pattern 1000b: 20 bit user programmable pattern 1 r/w 0b en_rx powers up the bist rx. 0b: power down 1b: power up and enable 0 r/w 1b rx_rst resets the bist rx (recommended after powerup/enable, active when bistrx_ctrl [1] = 1). 0b: normal bist rx operation 1b: reset of bist rx table 3-9. built in self-test (bis t) receiver bit error counter ( bistrx_error : address 12h) bits type default label description 7:0 r/w 00h err bit error count (active when bistrx_ctrl [1] = 1). this register is set to 00h upon reset, and is incremented for every bit error the bist rx receives, up to ffh. at ffh , the register will st ay at this level until cleared.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 51 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.9 built in self-test (bis t) transmitter channel select table 3-10. built in self-test (bis t) transmitter ch annel select ( bisttx_chsel : address 14h) bits type default label description 7:4 r/w 0000b reserved n/a 3:0 r/w 0000b tx_chan selects which input channel the bist tx outputs the test pattern on (active when bisttx_ctrl [1] = 1). bit map: 1b = bist tx on, 0b = bist tx off [3]: n/a, set to ?0? [2]: n/a, set to ?0? [1]: input channel 1 [0]: input channel 0 note : registers are set up to allow for multicasting bist tx output.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 52 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.10 built in self-test (bist) transmitter main control register table 3-11. built in self-test (bist) transmitter main control register ( bisttx_ctrl : address 15h) bits type default label description 7 r/w 0b err_insert inserts a single bit error into the prbs tx. 0b: normal operation 1b: insert error note : setting the register high allows one error to be inserted into the data stream. to insert another error, the user needs to clear, then set this register bit. 6 r/w 0b rx2txclk selects the source of the clock for the bist tx pll (active when bisttx_ctrl [1] = 1). 0b: external reference frequency 1b: recovered clo ck from bist rx note : for the recovered clock option, the bist rx must be enabled with bistrx_ctrl [1] = 1, and use the recovered clock from the same cdr/rclk selected by bist rx. this option only works for the full-rate case. 5:2 r/w 0000b tx_patt selects the bist tx test pattern (active when bisttx_ctrl [1] = 1). 0000b: prbs 2 7 -1 0001b: prbs 2 15 -1 0010b: prbs 2 23 -1 0011b: prbs 2 31 -1 0100b: fibre channel cjtpat 0101b: fibre channel crpat 0110b: 8b/10b countdown pattern 0111b: 16 bit user programmable pattern 1000b: 20 bit user programmable pattern 1 r/w 0b en_tx powers up the bist tx and pll. 0b: power down 1b: power up and enable 0 r/w 1b tx_rst resets the bist tx (recommended after powerup/enable; active when bisttx_ctrl [1] = 1). 0b: normal bist tx operation 1b: reset of bist tx
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 53 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.11 built in self-test (bist) tr ansmitter pll loss of lock register table 3-12. built in self-test (bist) transmitter pll loss of lock register ( bisttx_lolctrl : address 17h) (1 of 2) bits type default label description 7:5 r/w 101b tacq_lol sets the value for the lol reference window. code 000b 001b 010b 011b 100b 101b 110b 111b value 128 256 512 1024 2048 4096 8192 16384 4:1 r/w 0011b narwin_lol sets the narrow lol window for the lol = h to lol = l transition (transition to in lock threshold). code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b value 2 3 4 6 8 12 16 24 9 10 11 12 13 14 15 32
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 54 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.12 built in self-test (bist) transmitter pll control register a 0 r/w 0b widwin_lol sets the wide lol window for the lol = l to lol = h transition (transition to out of lock threshold). narrow code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b wide code 0b 3 4 6 8 12 16 24 32 12 12 12 16 16 16 16 32 wide code 1b 8 12 16 24 32 32 32 32 32 32 32 32 32 32 32 32 note: default value applies to reference based frequency acquisition. table 3-13. built in self-test (bist) transmitter pll control register a ( bisttx_pll_ctrla : address 18h) bits type default label description 7 r/w 0b softreset resets the bi st transmitter pll (assuming bisttx_ctrl [1] = 1b). 0b: normal operation 1b: reset pll only 6 r/w 0b rsvd internal n/a 5 r/w 0b reserved n/a 4 r/w 0b rsvd internal n/a 3 r/w 0b reserved n/a 2 r/w 1b rsvd internal n/a 1 r/w 0b reserved n/a 0 r/w 1b rsvd internal n/a table 3-12. built in self-test (bist) transmitter pll loss of lock register ( bisttx_lolctrl : address 17h) (2 of 2) bits type default label description
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 55 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.13 built in self-test (bist) transmitter pll control register b 3.1.14 built in self-test (bist) transmitter pll control register c table 3-14. built in self-test (bist) transmitter pll control register b ( bisttx_pll_ctrlb : address 19h) bits type default label description 7:6 r/w 11b pllmode determines state of the pll. must be enabled in addition to the bist tx ( bisttx_ctrl [1] = 1b). 00b: channel active, pll powered up 11b: channel active, pll powered down 5:4 r/w 01b rsvd internal n/a 3:0 r/w 0000b data_rate data rate divider (drd): this divides down the vco frequency to the desired data rate. 0000b = vco/1 0001b = vco/2 0010b = vco/4 0011b = vco/8 0100b = vco/12 0101b = vco/16 0110b = vco/24 0111b = vco/32 1000b = vco/48 note : please consult f vco, max and f vco, min to determine the frequency range of each drd ratio. table 3-15. built in self-test (bist) transmitter pll control register c (bisttx_pll_ctrlc : address 1ah) bits type default label description 7:0 r/w 10000000b vco_div vco comparison divider (vcd): this divider divides down the vco to compare it with the divided down reference. binary value reflects the divider ratio 01h: minimum value (vco /1) . . . ffh: maximum value (vco / 255)
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 56 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.15 built in self-test (bist) tran smitter 20 bit user programmable pattern 3.1.16 built in self-test (bist) transmitter 16/20 bit user programmable pattern 3.1.17 built in self-test (bist) transmitter 16/20 bit user programmable pattern table 3-16. built in self-test (bist) transmitter 20 bit user programmable pattern ( bist_pattern0 : address 1bh) bits type default label description 3:0 r/w 1100b pattern sets the 20 bit user programmable pattern used in the bist. [3] msb : pattern bit#19 [2] : pattern bit#18 [1] : pattern bit#17 [0] lsb : pattern bit#16 table 3-17. built in self-test (bist) transmitter 16/20 bit user programmable pattern ( bist_pattern1 : address 1ch) bits type default label description 7:0 r/w 11001100b pattern sets the 16/20 bit user programmable pattern used in the bist. [7] msb : pattern bit#15 [6] : pattern bit#14 [5] : pattern bit#13 [4] : pattern bit#12 [3] : pattern bit#11 [2] : pattern bit#10 [1] : pattern bit#9 [0] lsb : pattern bit#8 table 3-18. built in self-test (bist) transmitter 16/20 bit user programmable pattern ( bist_pattern2 : address 1dh) bits type default label description 7:0 r/w 11001100b pattern sets the 16/20 bit user programmable pattern used in the bist. [7] msb : pattern bit#7 [6] : pattern bit#6 [5] : pattern bit#5 [4] : pattern bit#4 [3] : pattern bit#3 [2] : pattern bit#2 [1] : pattern bit#1 [0] lsb : pattern bit#0
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 57 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.18 built in self-test (bist) transmitter alarm 3.1.19 internal junction temperature monitor table 3-19. built in self-test (bist) transmitter alarm ( bisttx_alarm : address 1fh) bits type default label description 7 r 0b tx_lol loss of lock for the bist tx pll (active when bisttx_ctrl [1] = 1). 0b: normal operation 1b: loss of lock 6:5 r/w 00b reserved n/a 4:0 r/w 00000b rsvd internal n/a table 3-20. internal junction temperature monitor ( temp_mon : address 20h) bits type default label description 3:2 r/w 00b reserved n/a 1 r/w 0b en_temp_mon power up and enable the temperature monitor. 0b: disable temperature monitor 1b: enable and power up temperature monitor 0 r/w 0b strobe_temp strobes adc for temperature measurement. 0b: ok to read temperature 1b: read temperature note : to strobe adc, a rising edge should be provided by writing 1b, then writing 0b to return to default state.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 58 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.20 internal junction temperature value 3.1.21 cdr/rclk loss of lock register alarm status 3.1.22 cdr/rclk loss of acti vity register alarm status table 3-21. internal junction temperature value ( temp_value : address 21h) bits type default label description 3:0 r n/a temp a read of these bits returns the temperatur e from the last write cycle (to strobe_temp). case temperature tc 130 c 130 c > tc 120 c 120 c > tc 110 c 110 c > tc 100 c 100 c > tc 90 c 90 c > tc 80 c 80 c > tc 10 c 10 c > tc 0 c 0 c > tc -10 c -10 c > tc -20 c -20 c > tc -30 c -30 c > tc -40 c -40 c > tc temp 1100b 1011b 1010b 1001b 1000b 0111b 0110b 0101b 0100b 0011b 0010b 0001b 0000b condition high-alarm high-alarm high-warning normal normal normal normal normal normal normal low-warning low-alarm low-alarm table 3-22. cdr/rclk loss of lock register alarm status ( alarm_lol : address 30h) bits type default label description 7:1 n/a 0000000b rsvd internal n/a 0 r n/a lol latched loss of lock alarm status. 0b = normal operation 1b = loss of cdr/rclk lock note: after a clear ( globctrl [0] = 1), this register is cleared and will latch any new alarms that make a l to h transition, and set any pre-existing alarm conditions to h. table 3-23. cdr/rclk loss of activity register alarm status ( alarm_loa : address 31h) bits type default label description 7:1 n/a 0000000b rsvd internal n/a 0 r n/a lol 0b = loa alarm de-asserted 1b = loa alarm asserted note: after a clear ( globctrl [0] = 1), this register is cleared and will latch any new alarms that make a l to h transition, and set any pre-existing alarm conditions to h.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 59 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.23 cdr/rclk control register a table 3-24. cdr/rclk control register a ( rclk_ctrla : address 40h) bits type default label description 7 r/w 0b softreset resets individual cdr/rclk (s etup registers remain unchanged; need to softreset after rate change). 0b: normal operation 1b: reset single cdr/rclk only 6 r/w 0b rsvd internal n/a 5 r/w 0b inh_force manual control of the output inhibit if rclk_ctrla [3] = 0. 0b: normal operation 1b: forced inhibit 4 r/w 0b rsvd internal n/a 3 r/w 1b autoinh_en auto inhibit of the output ( doutp =h, doutn = l) if cdr/rclk has a lol condition. 0b: auto inhibit disabled, rclk_ctrla [5] determines inhibit force state 1b: auto inhibit enabled 2 r/w 1b rsvd internal n/a 1 r/w 1b rsvd internal n/a 0 r/w 1b rsvd internal n/a
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 60 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.24 cdr/rclk control register b 3.1.25 cdr/rclk control register c table 3-25. cdr/rclk control register b ( rclk_ctrlb : address 41h) bits type default label description 7:6 r/w 00b rclkmode determines state of the pll. 00b: cdr/rclk powered up and active 01b: cdr/rclk powered up and bypassed 10b: cdr/rclk powered down (no signal through) 11b: cdr/rclk powered down and bypassed 5 r/w 0b rsvd internal n/a 4 r/w 0b reserved n/a 3:0 r/w 0000b data_rate data rate divider (drd): this divides down the vco frequency to the desired data rate to match input data rate. 0000b = vco/1 0001b = vco/2 0010b = vco/4 0011b = vco/8 0100b = vco/12 0101b = vco/16 0110b = vco/24 0111b = vco/32 1000b = vco/48 note: please consult f vco, max and f vco, min to determine frequency range of each drd ratio. table 3-26. cdr/rclk n control register c ( rclk_ctrlc : address 42h) bits type default label description 7:0 r/w 10000000b vco_divr vco comparison divider (vcd): this divides down the vco, to compare it with the scaled reference clock. binary value reflects the divider ratio. 1h: minimum value (vco /1) . . . ffh: maximum value (vco / 255)
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 61 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.26 output buffer control for cdr/rclk table 3-27. output buffer control for cdr/rclk ( out_ctrl : address 43h) bits type default label description 7:6 r/w 10b outlvl determines the output swing of a data buffer for cdr/rclk. in pcml mode: 00b: power down 01b: 500 mv 10b: 900 mv 11b: 1200 mv for lvds, the output swing is reduced to: 00b: power down 01b: rrl 390 mv 10b: gpl 700 mv 11b: 940 mv for lvpecl, the output swing is increased to: 00b: power down 01b: 900 mv 10b: standard (low specification side) 1200 mv 11b: standard (nominal) 1600 mv for infiniband, the output swing is increased to: 00b: power down 01b: 900 mv 10b: 1200 mv 11b: standard (nominal) 1400 mv 5:4 r/w 00b reserved n/a 3 r/w 0b data_pol_flip flips the polarity of the output data. 0b: normal 1b: polarity flip 2 r/w 1b dataout_en enables the data output driver. 0b: data output disabled and powered down 1b: data output enabled to level specified in out_ctrl [7:6] 1:0 r/w 00b rsvd internal n/a
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 62 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.27 output buffer pre-em phasis control for output 3.1.28 input equalization control for output table 3-28. output buffer pre-emphasis control for output ( preemp_ctrl : address 44h) bits type default label description 7 r/w 0b reserved default = 0b 6:3 r/w 1000b rsvd internal n/a 2:0 r/w 000b preemph selects the pre-emphasis level. 000b: pre-emphasis off 001b: 25% 010b: 37.5% 011b: 50% 100b: 75% 101b: 100% 110b: 150% 111b: 200% table 3-29. input equalization control for output ( ineq_ctrl : address 45h) bits type default label description 7 r/w 0b reserved n/a 6:5 r/w 00b rsvd internal n/a 4 r/w 0b en_dcservo enables dc servo in the input channel to remove offset based deterministic jitter. 0b: dc servo d j attenuator off 1b: dc servo d j attenuator on 3 r/w 0b rsvd internal n/a 2:0 r/w 100b in_eq selects the input equalization level. 000b: input equalization disabled 001b: minimum input equalization level . . . 100b: nominal input equalization level . . . 111b: maximum input equalization level note: the 100b setting is optimized for pcb trace lengths between 10?46 inches, although other settings may be optimal for some applications.
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 63 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.29 cdr/rclk loop bandwidth and data sampling point adjust table 3-30. cdr/rclk loop bandwidth and data sampling point adjust ( phadj_ctrl : address 46h) bits type default label description 7:6 r/w 10b i_trim adjusts the charge-pump current; the loop bandwidth (f lbw ) scales proportionately. 00b: 0.65x 01b: 0.8x 10b: nominal 11b: 1.15x 5:4 r/w 01b r_sel adjusts the resistor of the cdr/rclk loop filter; the loop bandwidth (f lbw ) scales proportionately. 00b: 80% of the nominal value 01b: nominal 10b: 4x nominal value 11b: 6x nominal value 3:0 r/w 0000b phase_adj adjusts the static phase offset (sampling point) of the data. 1111b: -122.5 mui 1110b: -105 mui 1101b: 87.5 mui 1100b: -70 mui 1011b: -52.5 mui 1010b: -35.0 mui 1001b: -17.5 mui 1000b: 0 mui 0000b: 0 mui 0001b: 17.5 mui 0010b: 35.0 mui 0011b: 52.5 mui 0100b: 70.0 mui 0101b: 87.5 mui 0110b: 105 mui 0111b: 122.5 mui
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 64 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.30 cdr/rclk lol window control table 3-31. cdr/rclk lol window control ( lol_ctrl : address 49h) (1 of 2) bits type default label description 7:5 r/w 101b tacq_lol sets the value for the lol reference window. code 000b 001b 010b 011b 100b 101b 110b 111b value 128 256 512 1024 2048 4096 8192 16384 4:1 r/w 0011b narwin_lol sets the narrow lol window for the lol = h to lol = l transition (transition to in lock threshold). code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b value 2 3 4 6 8 12 16 24 9 10 11 12 13 14 15 32
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 65 cdr/reclocker with 4:1 input multiplexer rev v3 3.1.31 jitter reduction control 0 r/w 0b widwin_lol sets the wide lol window for the lol = l to lol = h transition (transition to out of lock threshold). narrow code 0000b 0001b 0010b 0011b 0100b 0101b 0110b 0111b 1000b 1001b 1010b 1011b 1100b 1101b 1110b 1111b wide code 0b 3 4 6 8 12 16 24 32 12 12 12 16 16 16 16 32 wide code 1b 8 12 16 24 32 32 32 32 32 32 32 32 32 32 32 32 table 3-32. jitter reduction control ( jitter_reduc : address 4ah) bits type default label description 7:6 r/w 01b rsvd internal n/a 5 r/w 0b lowjitter when data rate is in the range (2.45 gbps?2.55 gbps)/drd, setting this bit to 1b will reduce output jitter (drd is data rate divider). 0b: normal operation 1b: reduce output jitter note: this bit should be set to 1b for sonet sts-n, and gigabit ethernet applications. 4:0 r/w rsvd internal any value may be written to this register with no effect on performance. table 3-31. cdr/rclk lol window control ( lol_ctrl : address 49h) (2 of 2) bits type default label description
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m21262-12 66 cdr/reclocker with 4:1 input multiplexer rev v3 appendix a.1 glossary of terms/acronyms ber bit error rate bist built-in self test rclk reclocker drd data rate divider evm evaluation module fll frequency lock loop fra frequency reference acquisition isi inter symbol interference loa loss of activity lol loss of lock lolcir loss of lock circuitry mlf micro lead frame nrw narrow reference window pcb printed circuit board pll phase lock loop rfd reference frequency divider sonet synchronous optical network vcd vco comparison divider wrw wide reference window xpts crosspoint switch
m21262-12 m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support 67 cdr/reclocker with 4:1 input multiplexer rev v3 a.2 reference documents a.2.1 external the following external documents were referenced in this data sheet. ? synchronous optical network (sonet) transport systems: common generic criteria gr-253-core ?the i 2 c bus specification version 2.1 ? infiniband architecture specif ication volume 2 release 1.1 ? serial ata: high speed serialized at attachment revision 1.0a ? fibre channel?methodologies for jitter and signal quality specification?mjsq ? application notes for surface mount assembly of amkor?s micro lead frame (mlf) packages ? amkor technology thermal test report tt-00-06 ? smpte 292m, smpt e 259m, smpte 344m ? dvb-asi a.2.2 macom the following macom documents were referenced in this data sheet. ? application note: equipment protection sw itching using low-cost crosspoint elements ? m2125x and m2126x ard software description (212xx-swg-001) ? jitter tolerance and generation of macom crosspoint switches and cdr arrays (2110x-app-003)
m/a-com technology solutions inc. (macom) and its affiliates reserve the right to make changes to the product(s) or information contained herein without notice. visit www.macom.com for additional data sheets and product information. for further information and support please visit: http://www.macom.com/support m/a-com technology solutions inc. all rights reserved. information in this document is provided in connect ion with m/a-com technology solutions inc ("macom") products. these materials are provided by macom as a service to its customers and may be used for informational purposes only. except as provided in macom ' s terms and conditions of sale for such products or in any separate agreement related to this document, macom assumes no liability whatsoever. macom assumes no responsibility for errors or omissi ons in these materials. macom may make changes to specifications and product descriptions at any time, without notice. ma com makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities ar ising from future changes to its specifications and product descriptions. no license, ex press or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. these materials are provided "as is" withou t warranty of any kind, either express or implied, relating to sale and/or use of macom products i ncluding liability or warranties relating to fitness for a parti cular purpose, consequential or incidental damages, merchantability, or infringeme nt of any patent, copyright or other intellectual property right. macom further does not warrant the accuracy or completeness of the information, text, graph ics or other items contained within these materials. macom shall not be liable for any special, indirect, incidental, or consequential damages, including without li mitation, lost revenues or lost profits, which may result from the use of these materials. macom products are not intended for use in medical, lifes aving or life sustaining applications. macom customers using or selling macom products for use in such applications do so at their own risk and agree to fully indemnify macom for any damages resulting from such improper use or sale. m21262-12 68 cdr/reclocker with 4:1 input multiplexer rev v3

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