fn6972 rev 2.00 page 1 of 7 march 3, 2010 fn6972 rev 2.00 march 3, 2010 qlx4270-dp displayport lane extender datasheet the qlx4270-dp is a settable quad receive-side equalizer with extended functionality for displayport applications. the qlx4270-dp compensates for the frequency dependent attenuation of copper cables, allowing operation on ultra-thin 40awg cable. the small form factor, highly-integrated quad design is ideal for high-density data transmission applications including active copper cable assemblies. operating on a single 1.2v power supply, the qlx4270-dp enables per chan nel throughputs of up to 2.7gb/s. the qlx4270-dp uses current mode logic (cml) inputs/outputs and is packaged in a 4mmx7mm 46 lead qfn. features ? supports data rates up to 2.7gb/s per lane ? low power (78mw per channel) ? low latency (<500ps) ? four equalizers in a 4mmx7mm qfn package for straight route-through architecture and simplified routing ? each equalizer boost is independently pin selectable and programmable ?1.2v supply voltage applications ? displayport (vesa displayport standard v1.1a) ? displayport adaptors and repeaters benefits ? thinner gauge cable ? extends cable reach greater than 5x ?improved ber typical application circuit v dd ep bgref in1[p,n] in2[p,n] in3[p,n] in4[p,n] out1[p,n] out2[p,n] out3[p,n] out4[p,n] gnd rx1[p,n] rx2[p,n] rx3[p,n] rx4[p,n] display port sink < 5m, 40awg connector module qlx4270-dp tx4[p,n] tx3[p,n] tx2[p,n] tx1[p,n] display port source 0.1f 0.1f 0.1f 0.1f 100pf 10nf 1.2v 0.1f 0.1f 0.1f 0.1f twin ax cp 6.04k 4-pair differential 100 twin-axial cable
qlx4270-dp fn6972 rev 2.00 page 2 of 7 march 3, 2010 pin configuration qlx4270-dp (46 ld qfn) top view ordering information part number (note) part marking temp. range (c) package (pb-free) pkg. dwg. # QLX4270RIQT7 qlx4270riq 0 to +70 46 ld qfn 7? prod. tape & reel; qty 1,000 l46.4x7 qlx4270riqsr qlx4270riq 0 to +70 46 ld qfn 7? sample reel; qty 100 l46.4x7 note: these intersil pb-free plastic packag ed products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 terminatio n finish, which is rohs compliant and compatible with both snpb and pb-free solderin g operations. intersil pb-free products are msl classified at pb- free peak reflow temper atures that meet or exceed the pb-free requirements of ipc/jedec j std-020. dt in1[p] in1[n] v dd in2[p] in2[n] v dd nc nc cp1[a] cp1[b] cp1[c] cp2[b] cp2[a] 1 2 3 4 5 6 7 46 45 44 43 42 41 40 8 9 10 11 12 13 14 15 39 16 17 18 19 20 21 22 23 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 in3[p] in3[n] v dd in4[p] in4[n] is1 is2 gnd bgref out1[p] out1[n] v dd out2[p] out2[n] v dd out3[p] out3[n] v dd out4[p] out4[n] is3 is4 gnd cp2[c] exposed pad cp3[c] cp4[b] nc cp3[a] nc cp3[b] cp4[a] cp4[c] (gnd)
qlx4270-dp fn6972 rev 2.00 page 3 of 7 march 3, 2010 pin descriptions pin name pin number description dt 1 detection threshold. referenc e dc current threshold for input signal power de tection. data output out[k] is muted when the power of the equalized version of in[k] falls below the threshold. tie to ground to disabl e electrical idle preservation and always enable the limiting amplifier. in1[p,n] 2, 3 equalizer 1 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. v dd 4, 7, 10, 29, 32, 35 power supply. 1.2v supply voltage. the use of parallel 100pf and 10nf decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. in2[p,n] 5, 6 equalizer 2 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. in3[p,n] 8, 9 equalizer 3 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. in4[p,n] 11, 12 equalizer 4 differential input, cml. the use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. is1 13 impedance select 1. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1p and in1n each go above 200k ? and powers down the channel. this can be used to disable some of the channels in case the displayport application has less than four links, in order to save power consumption. otherwise, connec t to vdd to hold the input impedance at 50 ? . is2 14 impedance select 2. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1p and in1n each go above 200k ? and powers down the channel. this can be used to disable some of the channels in case the displayport application has less than four links, in order to save power consumption. otherwise, connec t to vdd to hold the input impedance at 50 ? . gnd 15, 24 ground nc 16, 17, 45, 46 no-connect cp3[a,b,c] 18, 19, 20 control pins for setting equalizer 3. cmos logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp4[a,b,c] 21, 22, 23 control pins for setting equalizer 4. cmos logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. is4 25 impedance select 4. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1p and in1n each go above 200k ? and powers down the channel. this can be used to disable some of the channels in case the displayport application has less than four links, in order to save power consumption. otherwise, connec t to vdd to hold the input impedance at 50 ? . is3 26 impedance select 3. cmos logic input. when the voltage on this pin is low, the single-ended input impedance of in1p and in1n each go above 200k ? and powers down the channel. this can be used to disable some of the channels in case the displayport application has less than four links, in order to save power consumption. otherwise, connec t to vdd to hold the input impedance at 50 ? . out4[n,p] 27, 28 equalizer 4 differential output, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. out3[n,p] 30, 31 equalizer 3 differential output, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. out2[n,p] 33, 34 equalizer 2 differential output, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. out1[n,p] 36, 37 equalizer 1 differential output, cml. th e use of 100nf low esl/esr mlcc capacitor with at least 4ghz frequency respon se is recommended. bgref 38 external bandgap reference re sistor. recommended value of 6.04k 1%. cp2[c,b,a] 39, 40, 41 control pins for setting equalizer 2. cmos logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. cp1[c,b,a] 42, 43, 44 control pins for setting equalizer 1. cmos logic inputs. pins are read as a 3-digit number to set the boost level. a is the msb, and c is the lsb. pins are internally pulled down through a 25k ? resistor. exposed pad - exposed ground pad. for proper electrical and thermal performance, this pad should be connected to the pcb ground plane.
qlx4270-dp fn6972 rev 2.00 page 4 of 7 march 3, 2010 absolute maximum ratings thermal information supply voltage (v dd to gnd) . . . . . . . . . . . . -0.3v to 1.3v voltage at all input pins . . . . . . . . . . . -0.3v to v dd + 0.3v esd rating at all pins . . . . . . . . . . . . . . . . . . . . 2kv (hbm) thermal resistance (typical) ? ja (c/w) ? jc (c/w) 46 ld qfn (notes 1, 2) . . . . . . . . . 32 2.3 operating ambient temperature range . . . . . . 0c to +70c storage ambient temperature range . . . . -55c to +150c maximum junction temperature . . . . . . . . . . . . . . . +125c pb-free reflow profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 1. ? ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 2. for ? jc , the ?case temp? location is the center of the exposed metal pad on the package underside. operating conditions parameter symbol condition min typ max units supply voltage v dd 1.1 1.2 1.3 v operating ambient temperature t a 02570c bit rate nrz data applied to any channel 1.5 2.7 gb/s control pin characteristics v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. parameter symbol condition min typ max units notes ?low? resistance state cp[k] 0 1 k ? 3 ?mid? resistance state cp[k] 22.5 25 27.5 k ? 3 ?high? resistance state cp[k] 500 ? k ? 3 input current current draw on di gital pin, i.e., cp[k] 30 100 a note: 3. if four cp pins are tied together, the resistance values in this table should be divided by four. electrical characteristics v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. parameter symbol condition min typ max units notes supply current i dd 260 ma ic input amplitude range v in measured differentially at data source before encountering channel loss 340 1380 mv p-p 4 dc differential input resistance measured on input channel in[k] 80 100 120 ? dc single-ended input resistance measured on input channel in[k]p or in[k]n 40 50 60 ? input return loss (differential) s dd 11 50mhz to 1.35ghz 9 db 5 output amplitude range v out measured differentially at out[k]p and out[k]n with 50 ? load on both output pins 150 550 650 mv p-p differential output impedance measured on out[k] 80 105 120 ? output return loss (differential) s dd 22 50mhz to 1.35ghz 10 db 5 output return loss (common mode) s cc 22 50mhz to 1.35ghz 5 db 5
qlx4270-dp fn6972 rev 2.00 page 5 of 7 march 3, 2010 control pin boost setting the voltages at the cp pins are used to determine the boost level of each channel of qlx4270-dp. for each of the four channels, k, the [a], [b], and [c] control pins (cp[k]) are associated with a 3-bit non binary word. while [a] can take one of two values, ?low? or ?high?, [b] and [c] can take one of three different values: ?low?, ?middle?, or ?high?. this is achieved by changing the value of a resistor connected between vdd and the cp pin, which is internally pulled low with a 25k ? resistor. thus, a ?high? state is achieved by using a 0 ? resistor, ?middle? is achieved with a 25k ? resistor, and ?low? is achieved with an open resi stance. table 1 defines the mapping from the 3-bit cp word to the 18 out of 32 possible levels available via the serial interface on the evaluation board kit. if all four channels are to use the same boost level, then a minimum number of board resistors can be realized by tying together like cp[k][a,b,c] pins across all channels k. for instance, all four cp[k][a] pins can be tied to the same resistor running to vdd. consequently, only three resistors are needed to control the boost of all four channels. if the cp pins are tied together and the 25k ? is used, the value changes to a 3.125k ? resistor because the 25k ? is divided by 4. channel power-down the is[k] pin powers down the equalizer channel when pulled low. this feature allows individually to power down unused channels and to minimize power consumption. example: for displayport applications with 1 or 2 links, the unused channels may be powered down to save power. the current draw for a channel is reduced from 50ma to 3.8ma when powered down. output return loss (com. to diff. conversion) s dc 22 50mhz to 1.35ghz 20 db 5 output residual jitter 2.7gb/s; up to 2m 38awg standard twin-axial cable (11.5db loss) 0.15 0.2 ui 4, 6, 7 output transition time t r , t f 20% to 80% 30 60 100 ps 8 lane-to-lane skew 50 ps propagation delay from in[k] to out[k] 500 ps notes: 4. after channel loss, differential amplitud es at qlx4270-dp inputs must meet the in put voltage range specified in ?absolute maximum ratings? on page 4. 5. temperature = +25c, v dd = 1.2v. 6. output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the tra nsmitted signal (as measured at the input to the channel). total jitter (tj) is dj pp + 14.1 x rj rms . 7. measured using a prbs 2 7 -1 pattern. deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 8. rise and fall times measured using a 1ghz clock with a 20ps edge rate. electrical characteristics v dd = 1.2v, t a = +25c, and v in = 800mv p-p , unless otherwise noted. (continued) parameter symbol condition min typ max units notes table 1. mapping between cp-setting resistor and qlx4270-dp boost levels resistance between cp pin and v dd serial boost level cp[a] cp[b] cp[c] open open open 0 open open 25k ? 2 open open 0 ? 4 open 25k ? open 6 open 25k ? 25k ? 8 open 25k ? 0 ? 10 open 0 ? open 12 open 0 ? 25k ? 14 open 0 ? 0 ? 15 0 ? open open 16 0 ? open 25k ? 17 0 ? open 0 ? 19 0 ? 25k ? open 21 0 ? 25k ? 25k ? 23 0 ? 25k ? 0 ? 24 0 ? 0 ? open 26 0 ? 0 ? 25k ? 28 0 ? 0 ? 0 ? 31 table 1. mapping between cp-setting resistor and qlx4270-dp boost levels (continued) resistance between cp pin and v dd serial boost level cp[a] cp[b] cp[c]
fn6972 rev 2.00 page 6 of 7 march 3, 2010 qlx4270-dp intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description on ly. intersil may modify the circuit design an d/or specifications of products at any time without notice, provided that such modification does not, in intersil's sole judgment, affect the form, fit or function of the product. accordingly, the reader is cautioned to verify that datasheets are current before placing orders. information fu rnished by intersil is believed to be accu rate and reliable. however, no responsib ility is assumed by intersil or its subsidiaries for its use; nor for any infrin gements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html ? copyright intersil americas ll c 2009-2010. all rights reserved. all trademarks and registered trademarks are the property of their respective owners. about q:active ? historically, cable manufacturers have relied on thick wire gauge cables to deliver deep color images to the monitors and projectors. however, these cables are bulky, unwieldy and esthetically unappealing. to address this, intersil has developed its ground breaking q:active ? product line. by integrating its analog ics inside displayport cables, intersil is able to achieve unsurpassed improvements in cable gauges, reach and transmitted image quality.
qlx4270-dp fn6972 rev 2.00 page 7 of 7 march 3, 2010 package outline drawing l46.4x7 46 lead thin quad flat no-lead plastic package (tqfn) rev 0, 9/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but mus t be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metal lized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" side view typical recommended land pattern top view c 0.152 ref 0 . 05 max. 0 . 00 min. 5 4.00 a b 7.00 (4x) 0.05 6 pin 1 index area 39 46 2.80 42x 0.40 exp. dap 15 1 38 23 46x 0.40 16 6 5.60 ( 6.80 ) ( 5.50 ) ( 46 x 0.60) (46x 0.20) ( 42x 0.40) ( 3.80 ) ( 2.50) 2.50 0.1 0.10 46x 0.20 a mc b 4 5.50 0.1 exp. dap 0.70 0.05 see detail "x" seating plane 0.05 0.10 c c c 24 side view pin 1 index area
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