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THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 1/58 security e THCV231-Q and thcv236-q serdes transmitter and receiver with bi-directional transceiver general description the THCV231-Q and thcv236-q are designed to support video data transmission between the host and display. THCV231-Q one high-speed lane can carry up to 14bits data at a pixel clock frequency from 12mhz to 160mhz. thcv236-q one high-speed lane can carry up to 32bit data and 3bits of synchronizing signals at a pixel clock frequency from 6mhz to 160mhz by converting rgb444 to ycbcr422. the chipset, which has one high-speed data lane, can transmit video data up to 1080p/60hz. the maximum serial data rate is 4.00gbps/lane. features ? data width selectable ? wide frequency range ? ac coupling for high-speed lanes ? cdr requires no extern al frequency reference ? wide range supply voltage from 1.7v to 3.6v ? additional spread spectrum on data stream ? 2-wire serial interface bridge function(400kbps) ? remote side gpio control and monitoring ? THCV231-Q qfn32 (5mm x 5mm) with exposed pad ground thcv236-q qfn64 (9mm x 9mm) with exposed pad ground ? aec-q100 grade 2 (-40 to 105degc) ? iso/ts16949 compliant ? eu rohs compliant block diagram thcv236-q cdr controls formatter ycbcr to rgb d31-d0 hsync vsync de clkout settings 2-wire i/f sda/scl rxp rxn deserializer rcmp rcmn lvcmos output THCV231-Q lvcmos input pll controls formatter d11-d0 hsync vsync clkin settings 2-wire i/f sda/scl txp txn serializer osc tcmp tcmn ldo osc ldo capout capina capinp capout capina
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 2/58 security e contents page general description .............................................................................................................................. ................ 1 features .............................................................................................................................. .................................... 1 block diagram .............................................................................................................................. ......................... 1 pin configuration .............................................................................................................................. .................... 4 pin description .............................................................................................................................. ........................ 5 pin description for THCV231-Q ................................................................................................. ....................... 5 pin description for thcv236-q ................................................................................................. ....................... 6 functional overview .............................................................................................................................. ............. 10 functional description .............................................................................................................................. .......... 10 internal reference output/input function (capout, capina, capinp) ............................................ 10 power down (pdn1, pdn0, pdn) ................................................................................................................. 11 pre-emphasis and drive select function (THCV231-Q only) ..................................................................... 11 permanent clock output (thcv236-q only) .............................................................................................. 11 spread spectrum clock generator (sscg) .................................................................................................. 12 data enable .............................................................................................................................. ........................ 14 hot-plug function .............................................................................................................................. ............. 15 lock detect function .............................................................................................................................. ........ 15 field bet operation .............................................................................................................................. ......... 16 data width and frequenc y range select function ..................................................................................... 18 data mapping .............................................................................................................................. .................... 18 2-wire serial i/f mode .............................................................................................................................. ....... 19 2-wire serial i/f de vice id setting ........................................................................................... ..................... 19 2-wire serial i/f clock stretching ............................................................................................ ..................... 19 read/write access to sub- link master register ................................................................................. .......... 21 read/write access to su b-link slave register .................................................................................. ........... 22 read/write access to remote side 2-wire serial sl ave devices connected to su b-link slave device ............ 24 gpio .......................................................................................................................... .................................... 28 interrupt ion .................................................................................................................. .................................. 30 register map .............................................................................................................................. .......................... 31 absolute maximum ratings .............................................................................................................................. . 40 recommended opera ting conditions ................................................................................................................ 40 electrical specification .............................................................................................................................. .......... 40 lvcmos dc specification ....................................................................................................... ....................... 40 cml dc specification .......................................................................................................... ............................ 41 cml bi-directional dc specifi cation ........................................................................................... ................... 41
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 3/58 security e supply current ................................................................................................................ .................................. 42 switching char acteristics ..................................................................................................... ............................. 42 ac timing diagrams and test circuits ............................................................................................................ 46 lvcmos input, output sw itching characteristics ................................................................................ .......... 46 cml output switching characteristics .......................................................................................... ................... 47 cml bi-directional outp ut test circuit ........................................................................................ .................... 48 latency characteristics ....................................................................................................... .............................. 49 lock and unlock sequence ...................................................................................................... ......................... 50 2-wire serial i/f switc hing characteristics ................................................................................... .................... 51 gpio switching characteristics ................................................................................................ ........................ 53 pcb layout guideline regarding vdd and avdd for thcv236-q ............................................................. 55 package .............................................................................................................................. ................................... 56 notices and requests .............................................................................................................................. ............. 58
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 4/58 security e pin configuration pdn d0 1 test1 2 test2 3 rf/betout 4 sda 5 scl 6 gpio3 7 gpio4 8 9 10 d1 d2 11 12 d3 clkin 13 14 d4 d5 15 16 vdd 18 17 d7 20 19 d8 22 21 d10 23 vsync d11 28 27 26 25 tcmn tcmp capout hsync 32 31 30 29 capina txp THCV231-Q (qfn 32pin) 24 (top view) 33 expgnd txn capinp a vdd d9 d6 thcv236-q (qfn 64pin) pdn0 d27 1 pdn1 2 lfsel 3 test1 4 test2 5 rf/betout 6 col0/int/gpio2 7 col1/sd0 8 outsel/sd1 9 ttldrv/sd2/ain0/gpio1 10 laten/sd3/ain1/gpio0 11 d31 12 d30 13 d29 14 d28 15 vdd 17 18 d26 d25/gpio4 19 20 d24/gpio3 d23 21 22 d22 d21 23 24 d20 vdd 25 26 clkout d19 27 28 d18 d17 29 30 d16 d15 31 32 vdd 34 33 d14 36 35 d11 d12 38 37 d9 d10 40 39 a vdd d8 42 41 d7 vdd 44 43 d5 d6 46 45 d3 d4 47 vsync d2 52 51 50 49 d1 de hsync vdd 56 55 54 53 capout lockn/mssel htpdn/submode d0 60 59 58 57 mainmode/rcmn capina rxp rxn 64 63 62 61 bet oe hfsel/rcmp 16 48 (top view) 65 expgnd d13 rxdefsel
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 5/58 security e pin description pin description for THCV231-Q pin name pin no. type description txp 29 co high-speed cml signal output (main-link) txn 30 co high-speed cml signal output (main-link) tcmp 27 cb cml signal bidirectional input/output (sub-link) tcmn 28 cb cml signal bidirectional input/output (sub-link) gpio4 8 b gpio4 : general purpose input/output. when gpio4 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio4 is used as push pull output, no external component is required. laten : latch select input under field bet (sub- link) 0 : forbidden 1 : latched result gpio3 7 b gpio3 : general purpose input/output. when gpio3 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio3 is used as push pull output, no external component is required. scl 6 b scl input/output for 2-wire serial i/f. sda 5 b sda input/output for 2-wire serial i/f. clkin 13 i clock input d11-d0 23,22,20-17,15,14,12- 9 i pixel data input hsync 25 i hsync input vsync 24 i vsync input rf/betout 4 b rf : input clock triggering edge select. see figure 17. 0 : falling edge 1 : rising edge betout : field bet result output when field bet mode. pdn 1 il power down 0 : power down 1 : normal operation test2 3 i test pin. must be tied to ground for normal operation. test1 2 il test pin. must be tied to ground for normal operation. capout 26 pwr decoupling capacitor pin, 1.2v output. capina 31 pwr reference input for an alog circuit. must be tied to capout. capinp 32 pwr reference input for an alog circuit. must be tied to capout. vdd 16 pwr 1.7-3.6v digital power supply pin for lvcmos i/o avdd 21 pwr 1.7-3.6v analog power supply pin for ldo expgnd 33 gnd exposed pad ground. must be tied to the pcb ground plane through an array of vias. co : cml output buffer , cb : cml bi-directional buffer i : lvcmos input buffer , il : lo w speed lvcmos input buffer , b : lvcmos bi-directional buffer pwr : power supply , gnd : ground
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 6/58 security e pin description for thcv236-q pin name pin no. type description rxp 58 ci high-speed cml signal input(main-link) rxn 57 ci high-speed cml signal input(main-link) hfsel/rcm p 61 cb/i hfsel : high frequency mode select when pdn1=0. 0 : high frequency mode disable 1 : high frequency mode enable rcmp : cml signal bi-directional input/output(sub-link) when pdn1=1. mainmode/ rcmn 60 cb/i mainmode : setting v-by-one ? hs mode or sync free mode when pdn1=0 0 : v-by-one ? hs mode 1 : sync free mode rcmn : cml signal bi-directional input/output(sub-link) when pdn1=1. htpdn/ submode 54 bo htpdn : hot plug detect output when pdn1=0. must be connected to tx htpdn with 10k ? pull-up resistor. submode : sub-link mode select when pdn1=1. 0 : 2-wire serial i/f mode (def ault no clock stretching mode) 1 : low speed data bridge mode forbid setting 1 when connecting with THCV231-Q. lockn/ mssel 55 bo lockn : lock detect output when pdn1=0. must be connected to tx lockn with 10k ? pull-up resistor. mssel : sub-link master/slave select when pdn1=1. 0 : sub-link master side(inside 2-wire serial i/f is slave) 1 : sub-link slave side(inside 2-wire serial i/f is master) sub-link master is connected to host mpu. forbid setting 1 when connecting with THCV231-Q. laten/sd3/ ain1/gpio0 11 b laten : latch select input under field bet(main-link or sub- link). 0 : not latched result 1 : latched result sd3 : sub-link data input/output when pdn1=1 and submode=1. when sub-link is master (mssel=0), sd3 is output. when sub-link is slave (mssel=1), sd3 is input. ain1 : device id setting fo r 2-wire serial i/f when submode=0 and mssel=0. see table 19. gpio0 : general purpose input/output when submode=0 and mssel=1. when gpio0 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio0 is used as push pull output or input, no external component is required.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 7/58 security e ttldrv/sd2 / ain0/gpio1 10 b ttldrv : lvcmos output drive strength select when pdn1=0. 0 : weak drive strength 1 : normal drive strength sd2 : sub-link data input/output when pdn1=1 and submode=1. when sub-link is master (mssel=0), sd2 is input. when sub-link is slave (mssel=1), sd2 is output. ain0 : device id setting fo r 2-wire serial i/f when submode=0 and mssel=0. see table 19. gpio1 : general purpose input/output when submode=0 and mssel=1. when gpio1 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio1 is used as push pull output or input, no external component is required. outsel/sd1 9 b outsel : permanent clock output enable when pdn1=0. 0 : permanent clock output disable 1 : permanent clock output enable sd1 : sub-link data input/output when pdn1=1. when submode=0, sd1 is used as scl input/output for 2-wire serial i/f, requires pu ll-up resistor to vdd. when submode=1 and mssel=0, sd1 is input. when submode=1 and mssel=1, sd1 is output. col1/sd0 8 b col1 : color space co nverter enable when pdn1=0 and mainmode=0. 0 : color space converter disable 1 : color space converter enable data width setting when pdn1=0 and mainmode=1. see table 16. sd0 : sub-link data input/output when pdn1=1. when submode=0, sd0 is used as sda input/output for 2-wire serial i/f, requires pu ll-up resistor to vdd. when submode=1 and mssel=0, sd0 is input. when submode=1 and mssel=1, sd0 is output. col0/int/ gpio2 7 b col0 : data width setting when pdn1=0. see table 16. int : interrupt signal output for sub-link when submode=0 and mssel=0. it must be connected with a pull-up resistor to vdd. l : interrupt occurred h : steady state gpio2 : general purpose input/output when submode=0 and mssel=1. when gpio2 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio2 is used as push pull output or input, no external component is required. clkout 26 o clock output d31-d26 12-15,17,18 o pixel data output
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 8/58 security e d25/gpio4 19 b d25 : pixel data output gpio4 : general purpose input/output when submode=0, mssel=1 and rxdefsel=0. when gpio4 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio4 is used as push pull output or input, no external component is required. d24/gpio3 20 b d24 : pixel data output gpio3 : general purpose input/output when submode=0, mssel=1 and rxdefsel=0. when gpio3 is used as open-drain output, it must be connected with a pull-up resistor to vdd. when gpio3 is used as push pull output or input, no external component is required. d23-d0 21-24,27-31,33- 39,42-47,52,53 o pixel data output de 51 o de output hsync 50 o hsync output vsync 48 o vsync output oe 63 il output enable 0 : lvcmos output disable (hi-z) except for htpdn, lockn when pdn1=0 and except for betout when bet=1 1 : lvcmos output enable bet 64 il field bet entry 0 : normal operation 1 : field bet operation rf/betout 6 b rf : output clock triggering edge select. see figure 18. 0 : falling edge 1 : rising edge betout : field bet result output rxdefsel 62 i internal register default setting select. see table 36, table 37 0 : for THCV231-Q 1 : for thcv235-q lfsel 3 i low frequency mode select 0 : low frequency mode disable 1 : low frequency mode enable forbid setting 1 when connecting with THCV231-Q. pdn1 2 il sub-link power down 0 : power down. main-link setting by external pin 1 : normal operation. main-link setting by 2-wire serial i/f pdn0 1 il main-link power down 0 : power down 1 : normal operation test2 5 i test pin. must be tied to ground for normal operation. test1 4 il test pin. must be tied to ground for normal operation. capout 56 pwr decoupling capacitor pin, 1.2v output. capina 59 pwr reference input for analog circuit. must be tied to capout. vdd 49,41,32,25,16 pwr 1.7-3.6v digital power supply pin for lvcmos i/o avdd 40 pwr 1.7-3.6v analog power supply pin for ldo expgnd 65 gnd exposed pad ground. must be tied to the pcb ground plane through an array of vias. ci : cml input buffer , cb : cml bi-directional buffer i : lvcmos input buffer , il : low speed lvcm os input buffer , o: lvcmos output buffer b : lvcmos bi-directional buffer , bo : open-drain lvcmos bi-directional buffer pwr : power supply , gnd : ground
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 9/58 security e table 1. pin sharing description (thcv236-q) sub-link state 2-wire serial i/f mode sub-link master/slave master pdn1 1 htpdn/submode 0 lockn/mssel 0 bet 0 rxdefsel 0 rf/betout rf betout (*1) col0/int/gpio2 int col1/sd0 sd0(sda) outsel/sd1 sd1(scl) ttldrv/sd2/ain0/gpio1 ain0 laten/sd3/ain1/gpio0 ain1 laten (*2) d24/gpio3 gpio3 (*3) d25/gpio4 gpio4 (*3) htpdn/submode submode lockn/mssel mssel mainmode/rcmn rcmn hfsel/rcmp rcmp *1 when field bet mode (main-link or sub-link), it functions as betout output. *2 when field bet mode (main-link or sub- link), it functions as laten input. *3 through gpio input is default on register setting
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 10/58 security e functional overview with high speed cml serdes, proprietary encoding scheme and cdr (clock and data recovery) architecture, the THCV231-Q and thcv236-q enable transmission of 14bit data through main-link by single differential pair cable with minimal external components. in addition, the THCV231-Q and thcv236-q have sub-link which enables bi-directional transmission of 2-wire serial interface signals, gpio signals and also htpdn/lockn signals for main-link through the other 1-pair of cml-line. it does not need any external frequency reference such as a crystal oscillator. the THCV231-Q - thcv236-q system is able to watch peripheral devices and to control them via 2-wire serial interface or gpios. they al so can report interrupt events caused by change of gpio inputs and internal statuses. functional description internal reference output/input function (capout, capina, capinp) an internal regulator produces the 1.2v (capout). this 1.2v linear regulator can?t supply any other external loads. bypass capout to gnd with 10uf. capinp (THCV231-Q only) supplies reference voltage for internal pll, and capina supplies reference voltage for any internal analog circuit. bypass capinp/capina to gnd with 0.1uf to remove high frequency noise. capout, capina and capi np must be tied together. power supply avdd is supposed to be stabilized with de-coupling capacitor and series noise filter (for example, ferrite bead). figure 1. connection of capout, capina, capinp and decoupling capacitor
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 11/58 security e power down (pdn1, pdn0, pdn) pdn1, pdn0 and pdn turn off internal circuitry of main-link and sub-link separately. table 2. power down setting(THCV231-Q) pdn operation 0 both main-link and sub-link power down 1 both main-link and sub-link active table 3. power down setting(thcv236-q) pdn1 pdn0 operation 0 0 both main-link and sub-link power down 0 1 only main-link is active 1 0 only sub-link is active 1 1 both main-link and sub-link active pre-emphasis and drive select function (THCV231-Q only) pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. pre register selects the strength of pre-emphasis. cmldrv register controls cml main-link output swing level. see table 4. table 4. pre-emphasis and drive se lect function table cmldrv[1:0] (register) pre (register) condition swing level pre-emphasis level 00 0 400mv diff p-p 0db 1 6db 01 0 600mv diff p-p 0db 1 3.5db 10 * 800mv diff p-p 0db 11 * forbidden permanent clock output (thcv236-q only) when there is no input from main -link, the thcv236-q w ill output internal oscillator clock from clkout pin. this function is controlled by outsel pin or outsel_enable register and outsel_setting register. see table 5. table 5. permanent clock output function table (pdn1=1) outsel _ enable (register) outsel _ setting (register) output clock frequency (*1) 0 * - 1 00 80mhz 01 40mhz(default) 10 20mhz 11 10mhz *1 typical value
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 12/58 security e spread spectrum clock generator (sscg) the THCV231-Q serial data output and the thcv236-q parallel data and clock outputs are modulated by programmable sscg. the THCV231-Q and thcv236-q sscg are enabled by only ssen register. the modulation rate and modulation frequency variation of output spread is controlled through the sscg control registers on each device. do not enable spread spectrum for both the THCV231-Q and thcv236-q at the same time. table 6. sscg enable signal mode entry signal description ssen(register) 0:sscg disable 1:sscg enable when customer use the mode and frequency range shown in table 7, register setting is required according to table 8. table 7. main-link mode and frequency ra nge requiring register setting mode setting freq.range[mhz] (sscg enable) register setting (*2) mainmode hfsel col1 col0 min max 1 0 0 0 26.6 40 case1 1 0 0 1 26.6 50 case1 1 0 1 0 33.3 66.6 case2 1 1 (*1) (*1) 50 100 case3 *1 don?t care *2 see table 8 table 8. sscg register setting step register address(hex) register value(hex) description sub-link master side sub-link slave side case1 case2 case3 THCV231-Q thcv236-q 1 0x70 0xf0 0x01 set 1 to pll_set_en 2 0x76 0xf6 0x02 0x02 0x01 set pll_set0 3 0x78 0xf8 0x3c 0x30 0x20 set pll_set1 4 0x7c 0xfc 0x35 0x34 0x24 set pll_set2 modulation frequency f mod can be determined by hfsel and lfsel settings, input clock frequency and fmod register setting (default value 0x d). refer to following formula. fmod f f clksscg ? ? 128 mod f clksscg is the frequency listed in table 9 and table 10.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 13/58 security e table 9. f clksscg (THCV231-Q) hfsel (register) f clksscg 0 (1/ttcip)/2 1 (1/ttcip)/4 table 10. f clksscg (thcv236-q) hfsel lfsel f clksscg 0 0 (1/trcp)/2 1 0 (1/trcp)/4 * 1 forbidden setting up to 0.5 % spread at the 30khz modulation frequency is stable for most cases. in case of using out of this range, please verify at the actual system.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 14/58 security e data enable v-by-one ? hs mode operation (mainmode=0) are shown below. THCV231-Q hsync pin input is de signal. table 11 and related note shows requirements for de. video hsync signal may meet de input requirement. hsync output of thcv236-q under THCV231-Q v- by-one? hs mode operation is invalid. d11-d0 vsync 1 de (hsync pin input) thcv236-q THCV231-Q vid eo da ta cont vs ync de=1, d31-d0 de=0, low fixed de=1, vsync=fixed de=0, vsync 0 figure 2. conceptual diagram of the basic op eration of the chipset in v-by-one ? hs mode high low high valid data valid data invalid invalid de (hsync pin inut) vsync d11-d0 THCV231-Q input invalid valid data clkin low valid data invalid invalid valid data low high invalid valid data (rf=1) high low high valid data valid data kee p the last data of de=l perio d de (de pin output) vsync valid data clkout low valid data valid data low high valid data (rf=1) kee p the last data of de=l perio d kee p the last data of de=l perio d tdeh tdel tdeh tdel thcv236-q output tdeint (mainmode=0) d11-d0 (mainmode=0) low fixed low fixed low fixed figure 3. data and synchronizing signals transmission timing diagram in v-by-one ? hs mode table 11. de requirement symbol paramete r condition min typ max unit tdeh de=1 duration mainmode=0 and hfsel=0 2ttcip - - ns mainmode=0 and hfsel=1 4ttcip *note - ns mainmode=1 don?t care tdel de=0 duration mainmode=0 and hfsel=0 2ttcip - - ns mainmode=0 and hfsel=1 4ttcip *note - ns mainmode=1 don?t care *note: in v-by-one ? hs mode (mainmode=0) and high frequency mode (h fsel=1), the period between rising edges of de (tdeint), high time of de (tdeh) s hould always satisfy following equations. tdeh = ttcip*(2m) and tdeint = ttcip*(2n), m,n=2,3,4,5,6??
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 15/58 security e hot-plug function htpdn signal indicates connecting condition between the transmitter and the receiver. htpdn of the transmitter side is high when the receiver is not active or not connected. then the transmitter can enter into the power down mode. htpdn is set to low by the receiver when the receiver is active and connects to the transmitter, and then the transmitter must start up and transmit cdr training pattern for link training. htpdn is transferred to the transmitter via sub-link line. host mpu can confirm htpdn state by reading sub-link master register (0x00 bit0 htpdn). lock detect function lockn indicates whether the receiver cdr pll is in the lock state or not. lockn at the transmitter input is set to high when the receiver is not active or at the cdr pll training state. lockn is set to low by the receiver when cdr lock is done. then the cdr training mode finishes and the transmitter shifts to the normal operation. lockn is transferred via sub-link line. host mpu can confirm lockn state by reading sub-link master register (0x00 bit1 lockn). figure 4. htpdn, lockn transmission route
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 16/58 security e field bet operation in order to help users to check validity of cml serial line (main-link and sub-link), the THCV231-Q and thcv236-q have an operation mode in which they act as a bit error tester (bet). in main-link field bet mode, the THCV231-Q internally generates a test pattern which is then serialized onto the main-link cml line. the thcv236-q also has bet function mode. the thcv236-q r eceives the data stream and checks bit errors. the generated data pattern is then 8b/10b encoded, scrambled, and serialized onto the cml channel. as for the thcv236-q, the internal test pattern check circuit gets enabled and reports result on a certain pin named betout. in sub-link field bet mode, sub-link master device internally generates test pattern which is then serialized onto the sub-link cml line. sub-link slave device also has bet function mode. sub-link slave device receives the data stream and checks bit errors. note that sub-link slave device must be set this mode prior to sub-link master device. pattern check result is output from betout pin of the sub-link slave device. the betout pin goes low whenever bit errors occur, or it stays high when there is no bit error. in main-link field bet mode, user can select two kinds of check result, latched result or not latched result by setting laten pin input. the latched result is reset by setting laten=0. in sub-link field bet mode, only latched result is available. in order to reset the latched result, please once turn off the power and entry sub-link field bet from power on sequence. gpio4 pin (THCV231-Q) and laten/sd3/ain1/gpio0 pin (thcv236-q) function as laten in field bet mode (main-link or sub-link). it is not possible to realize main-link field bet and sub-link field bet at the same time. table 12. main-link field bet operation settings THCV231-Q/236-q common setting thcv236-q setting condition pdn0/pdn1/pdn submode bet bet_sel laten main-link sub-link output latch select 1 0 1 (*1) 0 (*2) 0 field bet operation normal operation not latched result 1 latched result *1 THCV231-Q: register setting (0x53 bit1), thcv236-q: pin setting *2 register setting (0x53 bit0, default 0) table 13. thcv236-q main-link field bet result betout output l bit error occurred h no error
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 17/58 security e table 14. sub-link field bet operation setting THCV231-Q/thcv236-q common setting THCV231-Q setting thcv236-q setting condition bet bet_sel pdn gpio3 gpio4 pdn1 mssel laten sub-link output latch select 1 (*1) 1 (*2) 1 0 - 1 1 1 (*3) field bet operation (THCV231-Q thcv236-q) latched result 1 1 (*3) 0 - field bet operation (thcv236-q THCV231-Q) *1 THCV231-Q: register setting (0x53 bit1), thcv236-q: pin se tting. note that bet pin should be 0 at power on sequence. *2 register setting (0x53 bit0, default 0) *3 forbidden 0 setting table 15. sub-link slave device sub- link field bet result betout output l bit error occurred h no error figure 5. main-link field bet configuration THCV231-Q thcv236-q test pattern checker test pattern generator rf/betout test point for field bet osc bet=1 (register) bet_sel=1 (register) laten /sd3/ain1/gpio0 =1 bet=1 (pin) bet_sel=1 (register) sub-link figure 6. sub-link field bet configuration
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 18/58 security e data width and frequency range select function the THCV231-Q and thcv236-q support a variety of data width and frequency range. frequency range is different depending on the mode setting sscg enable and disable setting. refer to table 16 for details. table 16. main-link operation mode select mode setting freq.range [mhz] main-link cml bit rate data width comment sscg disable sscg enable (*1) mainmode hfsel col1 col0 min max min max data sync 0 * 1 * - - - - - - forbidden 0 0 0 0 15 100 26.6 100 x40 12 2 0 0 0 1 20 133.3 33.3 133.3 x30 12 2 0 1 0 0 - - - - - - - forbidden 0 1 0 1 50 70 50 70 x20 12 2 (*2) 70 160 70 160 - 1 0 0 0 12 30 26.6 60 x50 14 - 1 0 0 1 15 40 26.6 75 x40 14 - 1 0 1 0 20 75 33.3 100 x30 14 - 1 0 1 1 - - - - - - forbidden 1 1 0 0 - - - - - - forbidden 1 1 0 1 50 70 50 70 x20 14 (*2) 70 160 70 160 - 1 1 1 0 50 70 50 70 x15 10 (*2) 70 160 70 160 - 1(*3) 1 1 1 50 70 50 70 x15 8 2 (*2) (*3) 70 160 70 160 (*3) *1 note that register setting is required depending on the mode setting and used frequency range. see table 7. *2 register setting is required. see table 17. *3 while register mainmode setting = 1, however, behavior of th is exceptional setting is v-by-one? hs mode whose meaning is mai nmode = 0. table 17. register setting (hfsel=1 and freque ncy range is from 50mhz to 70mhz) step register address(hex) register value(hex) description sub-link master side sub-link slave side THCV231-Q thcv236-q 1 0x70 0xf0 0x01 set 1 to pll_set_en 2 0x76 0xf6 0x02 0x01 set pll_set0 3 0x78 0xf8 0x20 set pll_set1 4 0x7c 0xfc 0x24 set pll_set2 data mapping table 18. data mapping mainmode 0 0 0 1 1 1 1 1 1 hfsel 0 0 1 0 0 0 1 1 1 col1 0 0 0 0 0 1 0 1 1 col0 0 1 1 0 1 0 1 0 1 d0 d0/raw4 d0/raw4 d0/raw4/yc0 d0 d0 d0 d0/raw4 d0/yc0 d0/raw0/yc0 d1 d1/raw5 d1/raw5 d1/raw5/yc1 d1 d1 d1 d1/raw5 d1/yc1 d1/raw1/yc1 d2 d2/raw6 d2/raw6 d2/raw6/yc2 d2 d2 d2 d2/raw6 d2/yc2 d2/raw2/yc2 d3 d3/raw7 d3/raw7 d3/raw7/yc3 d3 d3 d3 d3/raw7 d3/yc3 d3/raw3/yc3 d4 d4/raw8 d4/raw8 d4/raw8/yc4 d4 d4 d4 d4/raw8 d4/yc4 d4/raw4/yc4 d5 d5/raw9 d5/raw9 d5/raw9/yc5 d5 d5 d5 d5/raw9 d5/yc5 d5/raw5/yc5 d6 d6/raw10 d6/raw10 d6/raw10/yc6 d6 d6 d6 d6/raw10 d6/yc6 d6/raw6/yc6 d7 d7/raw11 d7/raw11 d7/raw11/yc7 d7 d7 d7 d7/raw11 d7/yc7 d7/raw7/yc7 d8 d8/raw0 d8/raw0 d8/raw0 d8 d8 d8 d8/raw0 - - d9 d9/raw1 d9/raw1 d9/raw1 d9 d9 d9 d9/raw1 - - d10 d10/raw2 d10/raw2 d10/raw2 d10 d10 d10 d10/raw2 - - d11 d11/raw3 d11/raw3 d11/raw3 d11 d11 d11 d11/raw3 - - hsync de*2 (hsync*3) de*2 (hsync*3) de*2 (hsync*3) hsync*1 hsync*1 hsync*1 hsync*1 hsync*1 de*2 (hsync*3) v sync vsync vsync vsync vsync*1 vsync*1 vsync*1 vsync*1 vsync*1 vsync*1 *1 any signal as well as sync signal can be transmitted when mainmode=1. *2 v-by-one?hs mode operation requires data enable (de) signal rule. please refer to the related section. *3 hsync signal can be assigned to data enable input when v-by-one? hs mode requirements are met.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 19/58 security e sub-link mode setting 2-wire serial i/f mode 2-wire serial i/f mode enables register access, using gpio (general purpose input/output) pin and interrupt function. sub-link master device has 2-wire serial slave block and can be connected to host mpu, sub-link slave device has 2-wire serial master block and can be connected to remote side 2-wire serial slave devices. host mpu can access register of sub-link master device, sub-link slave device and remote side 2-wire serial slave devices. 2-wire serial i/f device id setting ain1 and ain0 pins determine device id setting of the thcv236-q. only sub-link master device has ain1 and ain0 pin. ain1 and ain0 choose one of 4 addresses which give an identification address to the thcv236- q under 2-wire serial interface bus topology. table 19. 2-wire serial i/f device id se lect (sub-link master device only) ain1 a in0 device id 0 0 0x0b 0 1 0x34 1 0 0x77 1 1 0x65 2-wire serial i/f clock stretching in principle, when sub-link brid ges 2-wire serial interface communication from sub-link master to sub-link slave or remote side 2-wire serial slave devices, time lag occurs between host mpu side 2-wire serial access and sub-link slave internal bus access or remote side 2-wire serial access. 2wire_mode (sub-link master side register, 0x0f bit1 -0) selects whether 2-wire serial slave of sub-link master perform clock stretching or not. when 2wire_mode = 00, sub-link master device wa it host mpu until sub-link slave register access or remote side 2-wire serial slave register access is completed by clock stretching. when 2wire_mode = 01, sub-link master device info rms host mpu that sub-link slave register access or remote side 2-wire serial register access has been co mpleted by interruption (int pi n) without clock stretching.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 20/58 security e figure 7. 2wire_mode operation
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 21/58 security e read/write access to sub-link master register host mpu can directly access sub-link master?s register by 2-wire serial i/f. register address of sub-link ma ster is from 0x00 to 0x7f. see register map for more information. figure 8. host to sub-link master regi ster access configuration figure 9. 2-wire serial i/f write to sub-link master register protocol figure 10. 2-wire serial i/f read to sub-link master register protocol
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 22/58 security e read/write access to sub-link slave register host mpu can access to sub-link slave?s register via sub- link master by sub-link master register settings. register address of sub-link slave is from 0x80 to 0xff. see register map for more information. figure 11. host mpu to sub-link slave re gister access configuration table 20. sub-link slave register write procedure step description r/w address 1 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 2 set the data for sub-link slave to write (max 16byte). w 0x10-0x1f 3 set device id of sub-link master device. (value corresponding to ain1 and ain0 setting. e.g.[ain1,ain0]=[0,0] 7?h0b) w 0x20 4 set the byte number written to sub-link slave (max 16byte). (byte number = register value + 1) w 0x21 5 set the start address of sub-link slave register to write. w 0x23 6 write 1 to wr_start_8b. (start write ac cess to sub-link slave register) w 0x25 (*1) 7 (*2) 2-wire serial slave of sub-link master per form clock stretching until sub-link slave register access is completed. - - 7 (*3) when write access is completed, 2wire_ acs_end_int register value become 1 and interrupt occurs (int=h l). - - 8 if write access was normally ended, read value should be ?0x1?. r 0x02 bit7 *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave before the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 23/58 security e table 21. sub-link slave register read procedure step description r/w address 1 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 2 set device id of sub-link master device. (value corresponding to ain1 and ain0 setting. e.g. [ain1,ain0]=[0,0] 7?h0b) w 0x20 3 set the byte number read from sub-link slave(max 16byte). (byte number = register value + 1) w 0x22 4 set the start address of sub-link slave register to read. w 0x24 5 write 1 to rd_start_8b. (start read access to sub-link slave register) w 0x26 (*1) 6 (*2) 2-wire serial slave of sub-link master perform clock stretching until sub-link slave register access is comple ted. when read access is comp leted, scl is released and read data is stored in sub-link master register (address 0x10-0x1f). - - 6 (*3) when read access is completed, read data is stored in sub-link master register (address 0x10-0x1f) and 2wire_acs_end_int register value become 1 and interrupt occurs (int=h l). - - 7 if read access was normally ended, read value should be ?0x1?. r 0x02 8 host mpu read data stored in sub-li nk master register. r 0x10-0x1f *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave bef ore the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 24/58 security e read/write access to remote side 2-wire serial slave devices connected to sub-link slave device host mpu can access to remote side 2-wire serial slav e register via sub-link master and sub-link slave by sub-link master register settings. sub- link slave has 2-wire serial master block. up to 8 devices are connectable to 2-wire serial master of sub-link slave device. figure 12. host to 2-wire serial slave devices connected to sub-link sl ave device access configuration table 22. remote side 2-wire serial slave register write procedure for 8bit register address step description r/w address 1 set slave address of remote side 2-wire serial slave device (low-order 7bits), and enable this address (high-order 1bit). w 0x04-0x0b 2 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 3 set the data for remote side 2-wire serial slave to write (max 16byte). w 0x10-0x1f 4 set slave address of access target 2-wire serial slave (choose the value set in 0x04- 0x0b[6:0]), and set 0 to 0x20 bit7. w 0x20 5 set the byte number written to remote side 2-wire serial slave (max 16byte). (byte number = register value + 1) w 0x21 6 set the start address of remote side 2-wire serial slave register to write. w 0x23 7 write 1 to wr_start_8b. (start write access to remote side 2-wire serial slave register) w 0x25 (*1) 8 (*2) 2-wire serial slave of sub-link master perform clock stretching until remote side 2- wire serial slave register access is completed. - - 8 (*3) when write access is completed, 2wire_ acs_end_int register value become 1 and interrupt occurs (int=h l). - - 9 if wire access was normally ended, read value should be ?0x1?. r 0x02 10 repeat from step2 to step9 if needed. - - *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave before the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 25/58 security e table 23. remote side 2-wire serial slave register write procedure for 16bit register address step description r/w address 1 set slave address of remote side 2-wire serial slave device (low-order 7bits), and enable this address (high-order 1bit). w 0x04-0x0b 2 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 3 set the data for remote side 2-wire serial slave to write (max 16byte). w 0x10-0x1f 4 set slave address of access target 2-wire serial slave (choose the value set in 0x04- 0x0b[6:0]), and set 1 to 0x20 bit7. w 0x20 5 set the byte number written to remote side 2-wire serial slave (max 16byte). (byte number = register value + 1) w 0x21 6 set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register to write. w 0x27 7 set the high-order bits([15:8]) of start addr ess of remote side 2-wire serial slave register to write. w 0x28 8 write 1 to wr_start_16b. (start write access to remote side 2-wire serial slave register) w 0x2b (*1) 9 (*2) 2-wire serial slave of sub-link master perform clock stretching until remote side 2- wire serial slave register access is completed. - - 9 (*3) when write access is completed, 2wire_ acs_end_int register value become 1 and interrupt occurs (int=h l). - - 10 if write access was normally ended, read value should be ?0x1?. r 0x02 11 repeat from step2 to step10 if needed. - - *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave before the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 26/58 security e table 24. remote side 2-wire serial slave register read procedure for 8bit register address step description r/w address 1 set slave address of remote side 2-wire serial slave device (low-order 7bits), and enable this address (high-order 1bit). w 0x04-0x0b 2 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 3 set slave address of access target 2-wire serial slave (choose the value set in 0x04- 0x0b)(low-order 7bits), and set 0 to 0x20 bit7. w 0x20 4 set the byte number read from remote side 2-wire serial slave(max 16byte). (byte number = register value + 1) w 0x22 5 set the start address of remote side 2-wire serial slave register to read. w 0x24 6 write 1 to rd_start_8b. (start read access to remote side 2-wire serial slave register) w 0x26 (*1) 7 (*2) 2-wire serial slave of sub-link master perform clock stretching until sub-link slave register access is completed. when read access is completed, scl is released and read data is stored in sub-link master register (address 0x10-0x1f). - - 7 (*3) when read access is completed, read data is stored in sub-link master register (address 0x10-0x1f) and 2wire_acs_end_int register value become 1 and interrupt occurs (int=h l). - - 8 if read access was normally ended, read value should be ?0x1?. r 0x02 9 host mpu read data stored in sub-li nk master register. r 0x10-0x1f 10 repeat from step2 to step10 if needed. - - *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave before the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 27/58 security e table 25. remote side 2-wire serial slave register read procedure for 16bit register address step description r/w address 1 set slave address of remote side 2-wire serial slave device (low-order 7bits), and enable this address (high-order 1bit). w 0x04-0x0b 2 write 1 or 0 and clear(auto clear) access stat us register (2wire_acs_end_int). w 0x02 bit7 3 set slave address of access target 2-wire serial slave (choose the value set in 0x04- 0x0b)(low-order 7bits), and set 1 to 0x20 bit7. w 0x20 4 set the byte number read from remote side 2-wire serial slave(max 16byte). w 0x22 5 set the low-order bits([7:0]) of start address of remote side 2-wire serial slave register to read. w 0x29 6 set the high-order bits([15:8]) of start address of remote side 2-wire serial slave register to read. w 0x2a 7 write 1 to rd_start_16b. (start read acce ss to remote side 2-wire serial slave register) w 0x2c (*1) 8 (*2) 2-wire serial slave of sub-link master perform clock stretching until sub-link slave register access is completed. when read ac cess is completed, scl is released and read data is stored in sub-link master register (address 0x10-0x1f). - - 8 (*3) when read access is completed, read data is stored in sub-link master register (address 0x10-0x1f) and 2wire_acs_end_int register value become 1 and interrupt occurs (int=h l). - - 9 if read access was normally ended, read value should be ?0x1?. r 0x02 10 host mpu read data stored in sub- link master register. r 0x10-0x1f 11 repeat from step2 to step10 if needed. - - *1 it?s prohibit that host mpu start access to sub-link slave or remote 2-wire serial slave before the previous access to sub-link slave or remote side 2-wi re serial slave is completed. *2 when 2wire_mode = 00 (clock stretching mode) *3 when 2wire_mode = 01 (no clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 28/58 security e gpio the gpio pin provides up to 2-i/o ports and 2 types of gpio are available (?thro ugh gpio? and ?programmable gpio?). all gpio pins of thcv236-q have another function if being set. see table 27. gpio type is selected by gpio_type register (0x40(sub-link master), 0xc0 (sub-link slave)). programmable gpio is available by all gpio pins. through gpio is available by only gpio4 and gpio3 pin. see through gpio section and programmable gpio section about detail of respective gpio type. table 26. gpio type gpio# gpio type through gpio programmable gpio gpio4 available available gpio3 table 27. gpio setting of thcv236-q pin name function sub-link maste r rxdefsel=0 d25/gpio4 gpio4 d24/gpio3 gpio3 col0/int/gpio2 int ttldrv/sd2/ain0/gpio1 ain0 laten/sd3/ain1/gpio0 ain1 through gpio input to gpio4 and gpio3 of sub-link master device is output from gpio4 and gpio3 of sub-link slave device respectively. note that these gpio signals can? t be transferred from sub-link slave device to sub-link master device. it?s possible to confirm gpio4 and gpio3 input value to sub-link master by register read (0x41 gpion_input_monitor (n=4,3) ). each gpio output signal goes to low when sub-link communication fails. sub-link communication status can be observed by register read (0x82 bit2 comerr_int). *1 see table 28 figure 13. through gpio
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 29/58 security e table 28. THCV231-Q, thcv236-q(rxdefsel=0) through gpio register setting device sub-link master/slave gpio input/output number gpio4 , gpio3 input/output configuration (i:input, o:output) register settings gpio type gpio io direction input output gpio4 gpio3 address (hex) value (bin) address (hex) value (bin) THCV231-Q slave 0 2 o o 0xc0 xxx11xxx 0xc3 xxx00xxx thcv236-q master 2 0 i i 0x40 xxx11xxx 0x43 xxx11xxx programmable gpio settings input/output and reading/writing are controlled by register settings in the sub-link master. host mpu commands register setting in the sub-link master. *1 see table 29,table 30 figure 14. programmable gpio register settings are required according to the number of gpio used by customer. see table 29 and table 30. when the number of gpio used by customer is less than the value listed in table 29 and table 30, choose any setting which includes that. table 29. THCV231-Q programmable gpio register setting sub-link master/slave gpio input/output number gpio4 C gpio3 input/output configuration (i:input, o:output) register settings gpio type gpio io direction input output gpio4 gpio3 address (hex) value (bin) address (hex) value (bin) slave 2 0 i i 0xc0 xxx00000 0xc3 xxx11xxx 1 1 i o xxx10xxx 0 2 o o xxx00xxx table 30. thcv236-q programmable gpio register setting (rxdefsel=0) sub-link master/slave gpio input/output number gpio4 ? gpio0 input/output configuration (i:input, o:output, -:unavailable) register settings gpio type gpio io direction input output gpio4 gpio3 gpio2 gpio1 gpio0 address (hex) value (bin) address (hex) value (bin) master 2 0 i i - - - 0x40 xxx00xxx 0x43 xxx11xxx 1 1 i o - - - xxx10xxx 0 2 o o - - - xxx00xxx
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 30/58 security e interruption int pin outputs interrupt event indicator on sub-link mast er side of the system. the int signal is active low. being set by 2-wire serial interface, the THCV231-Q and thcv236-q can monitor any changes of gpio input pins, sub-link communication statuses and internal statuses as an interrupt. about the way to make interruption occur and the way to clear the interruption, see table 32(address 0x02, 0x03) and table 33(address 0x82, 0x83). figure 15. 2-wire serial i/f interrupt to host access configuration table 31. interrupt output int state l interrupt occurred h steady state
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 31/58 security e register map host mpu can set various operating conditions of the THCV231-Q and thcv236-q through internal registers. sub-link master (2-wire serial sl ave) is connected to external host mpu (2-wire serial master). sub-link slave (2-wire serial master) is connect ed to external 2-wire serial slave devices. sub-link master device has address 0x00-0x7f, sub-link slave device has address 0x80-0xff. see figure 16. figure 16. sub-link master/slave device regi ster address configuration
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 32/58 security e table 32. sub-link master control register address (hex) bit# r/w default (hex) register name description note 0x00 7:3 r 0x00 reserved - 2 r 0 int interrupt condition 0: steady state 1: interrupt occurred(int output =l) - 1 r 1 lockn v-by-one ? hs lock status 0: locked (lockn=l) 1: unlocked - 0 r 1 htpdn v-by-one ? hs plug status 0: connected (htpdn=l) 1: not connected or rx inactive - 0x01 7:1 r 0x00 reserved - 0 rw 0 sftrst sub-link soft reset write 1: sub-link reset automatically cleared into 0 after reset action. 0 is always read. - 0x02 7 rw 0 2wire_acs_end_int cause of interrupt access completion to register of sub-link slave or remote side 2-wire serial slave device 0: access incomplete 1: access complete any write action: clear this bit into 0 (*1) 6 rw 0 lockn_int cause of interrupt lockn 0: no change on lock status ever 1: lock status has once changed any write action: clear this bit into 0 5 rw 0 htpdn_int cause of interrupt htpdn 0: no change on plug status ever 1: plug status has once changed any write action: clear this bit into 0 4 r 0 slaveside_int cause of interrupt sub-link slave side 0: no interrupt at sub-link slave ever 1: interrupted at sub-link slave once this bit is cleared when cause of interrupt register at sub-link slave (0x82) is cleared. 3 r 0 gpio_int cause of interrupt sub-link master gpio 0: no change in master gpio inputs ever 1: master gpio inputs have once changed. this bit is cleared when gpion_input_monitor (n=4~0) register (0x41) is read. 2 rw 0 comerr_int cause of interrupt sub-link communication error 0: no communication error on sub-link ever 1: communication error on sub-link once happened any write action: clear this bit into 0 1 rw 0 2wire_timeout_int cause of interrupt 2-wire serial time out 0: 2-wire serial access in time ever 1: 2-wire serial access has once had time out any write action: clear this bit into 0 0 rw 0 slink_timeout_int cause of interrupt sub-link time out 0: sub-link access in time ever 1: sub-link has once had time out any write action: clear this bit into 0 0x03 7 r (*2) 2wire_acs_end_int_enable 0: "2wire_acs_end_int" is blocked to take interrupt action 1: "2wire_acs_end_int" is allowed to take action on int output - 6 rw 0 lockn_int_enable 0: "lockn_int" is blocked to take interrupt action 1: "lockn_int" is allowed to take action on int output - 5 rw 0 htpdn_int_enable 0: "htpdn_int" is blocked to take interrupt action 1: "htpdn_int" is allowed to take action on int output - 4 rw 0 slaveside_int_enable 0: "slaveside_int" is blocked to take interrupt action 1: "slaveside_int" is allowed to take action on int output - 3 rw 0 gpio_int_enable 0: "gpio_int" is blocked to take interrupt action 1: "gpio_int" is allowed to take action on int output - 2 rw 0 comerr_int_enable 0: "comerr_int" is blocked to take interrupt action 1: "comerr_int" is allowed to take action on int output - 1 rw 0 2wire_timeout_int_enable 0: "2wire_timeout_int" is blocked to take interrupt action 1: "2wire_timeout_int" is allowed to take action on int output - 0 rw 0 slink_timeout_int_enable 0: "slink_timeout_int" is blocked to take interrupt action 1: "slink_timeout_int" is allowed to take action on int output - *1 these registers are always active independent of interrupt permission register. *2 when no clock stretching mode, the value is 1 fixed, otherwise 0 fixed
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 33/58 security e address (hex) bit# r/w default (hex) register name description note 0x04 7 rw 0 2wire_dev_addr_0_enable 0: value in "2wire_dev_addr_0" is inactive 1: value in "2wire_dev_addr_0" is active (*3) 6:0 rw 0x00 2wire_dev_addr_0 remote side 2-wire serial slave device address #0 0x05 7 rw 0 2wire_dev_addr_1_enable 0: value in "2wire_dev_addr_1" is inactive 1: value in "2wire_dev_addr_1" is active 6:0 rw 0x00 2wire_dev_addr_1 remote side 2-wire serial slave device address #1 0x06 7 rw 0 2wire_dev_addr_2_enable 0: value in "2wire_dev_addr_2" is inactive 1: value in "2wire_dev_addr_2" is active 6:0 rw 0x00 2wire_dev_addr_2 remote side 2-wire serial slave device address #2 0x07 7 rw 0 2wire_dev_addr_3_enable 0: value in "2wire_dev_addr_3" is inactive 1: value in "2wire_dev_addr_3" is active 6:0 rw 0x00 2wire_dev_addr_3 remote side 2-wire serial slave device address #3 0x08 7 rw 0 2wire_dev_addr_4_enable 0: value in "2wire_dev_addr_4" is inactive 1: value in "2wire_dev_addr_4" is active 6:0 rw 0x00 2wire_dev_addr_4 remote side 2-wire serial slave device address #4 0x09 7 rw 0 2wire_dev_addr_5_enable 0: value in "2wire_dev_addr_5" is inactive 1: value in "2wire_dev_addr_5" is active 6:0 rw 0x00 2wire_dev_addr_5 remote side 2-wire serial slave device address #5 0x0a 7 rw 0 2wire_dev_addr_6_enable 0: value in "2wire_dev_addr_6" is inactive 1: value in "2wire_dev_addr_6" is active 6:0 rw 0x00 2wire_dev_addr_6 remote side 2-wire serial slave device address #6 0x0b 7 rw 0 2wire_dev_addr_7_enable 0: value in "2wire_dev_addr_7" is inactive 1: value in "2wire_dev_addr_7" is active 6:0 rw 0x00 2wire_dev_addr_7 remote side 2-wire serial slave device address #7 0x0c 7:0 rw 0x00 reserved - 0x0d 7:0 r 0x00 reserved - 0x0e 7:2 r 0x00 reserved - 1:0 rw 0x0 reserved. must be 0 - 0x0f 7:2 r 0x00 reserved - 1:0 rw 0x1 2wire_mode 00: clock stretching mode 01: no clock stretching mode 10: reserved (forbidden) 11: reserved (forbidden) - 0x10 7:0 rw 0x00 2wire_data0 2-wire serial i/f write/read data #0 - 0x11 7:0 rw 0x00 2wire_data1 2-wire serial i/f write/read data #1 - 0x12 7:0 rw 0x00 2wire_data2 2-wire serial i/f write/read data #2 - 0x13 7:0 rw 0x00 2wire_data3 2-wire serial i/f write/read data #3 - 0x14 7:0 rw 0x00 2wire_data4 2-wire serial i/f write/read data #4 - 0x15 7:0 rw 0x00 2wire_data5 2-wire serial i/f write/read data #5 - 0x16 7:0 rw 0x00 2wire_data6 2-wire serial i/f write/read data #6 - 0x17 7:0 rw 0x00 2wire_data7 2-wire serial i/f write/read data #7 - 0x18 7:0 rw 0x00 2wire_data8 2-wire serial i/f write/read data #8 - 0x19 7:0 rw 0x00 2wire_data9 2-wire serial i/f write/read data #9 - 0x1a 7:0 rw 0x00 2wire_data10 2-wire serial i/f write/read data #10 - 0x1b 7:0 rw 0x00 2wire_data11 2-wire serial i/f write/read data #11 - 0x1c 7:0 rw 0x00 2wire_data12 2-wire serial i/f write/read data #12 - 0x1d 7:0 rw 0x00 2wire_data13 2-wire serial i/f write/read data #13 - 0x1e 7:0 rw 0x00 2wire_data14 2-wire serial i/f write/read data #14 - 0x1f 7:0 rw 0x00 2wire_data15 2-wire serial i/f write/read data #15 - 0x20 7 rw 0 2wire_adr_sel remote side 2-wire slave device's register address bit width select 0: 8bit register address 1: 16bit register address - 6:0 rw 0x00 2wire_target_dev_adr 2-wire serial i/f access target device address setting - 0x21 7:4 r 0x0 reserved - 3:0 rw 0x0 wr_req_byte 2-wire serial i/f write request byte number for both 8bit and 16bit register address device. byte number = register value + 1 (e.g. 0x2 for 3byte burst) - 0x22 7:4 r 0x0 reserved - 3:0 rw 0x0 rd_req_byte 2-wire serial i/f read request byte number for both 8bit and 16bit register address device. byte number = register value + 1 (e.g. 0x2 for 3byte burst) - 0x23 7:0 rw 0x00 wr_start_adr_8b 2-wire serial i/f write start register address for 8bit register address device - 0x24 7:0 rw 0x00 rd_start_adr_8b 2-wire serial i/f read start register address for 8bit register address device - 0x25 7:1 r 0x00 reserved - 0 rw 0 wr_start_8b 2-wire serial i/f write access start trigger for 8bit register address device - 0x26 7:1 r 0x00 reserved - 0 rw 0 rd_start_8b 2-wire serial i/f read access start trigger for 8bit register address device - 0x27 7:0 rw 0x00 wr_start_adr_16b_0 2-wire serial i/f write start register address(low-order bits = [7:0]) for 16bit register address device - 0x28 7:0 rw 0x00 wr_start_adr_16b_1 2-wire serial i/f write start register address(high-order bits = [15:8]) for 16bit register address device - 0x29 7:0 rw 0x00 rd_start_adr_16b_0 2-wire serial i/f read start register address(low-order bits = [7:0]) for 16bit register address device - 0x2a 7:0 rw 0x00 rd_start_adr_16b_1 2-wire serial i/f read start register address(high-order bits = [15:8]) for 16bit register address device - 0x2b 7:1 r 0x00 reserved - 0 rw 0 wt_start_16b 2-wire serial i/f write access start trigger for 16bit register address device - 0x2c 7:1 r 0x00 reserved - 0 rw 0 rd_start_16b 2-wire serial i/f read access start trigger for 16bit register address device - 0x2d-0x3f 7:0 r 0x00 reserved - *3 assignment of 2-wire serial slave device address connected to sub-link slave outside
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 34/58 security e table 33. sub-link slave control register address (hex) bit# r/w defaul t (hex) name description not e 0x80 7:0 r 0x00 reserved - 0x81 7:1 r 0x00 reserved - 0 rw 0 2wire_rst 2-wire serial i/f reset write 1: 16 pulse scl signal is sent to 2-wire serial slave device connected to sub-link slave. this bit is a remedy against sda=l, 2-wire serial stuck condition. automatically cleared into 0 after reset action.0 is always read. - 0x82 7:6 r 0x0 reserved 5 rw 0 2wire_rst_end_int cause of interrupt 2-wire serial reset done 0: normal operation 1: 2-wire serial reset signal has all finished any write action: clear this bit into 0 - 4 rw 0 2wire_nack_int cause of interrupt 2-wire serial slave nack 0: no nack from remote side 2-wire serial slave ever 1: nack from remote side 2-wire serial slave once come any write action: clear this bit into 0 - 3 r 0 gpio_int cause of interrupt sub-link slave gpio 0: no change in slave gpio inputs ever 1: slave gpio inputs have once changed. this bit is cleared when gpion_input_monitor (n=4,3) register (0xc1) is read. - 2 rw 0 comerr_int cause of interrupt sub-link communication error 0: no communication error on sub-link ever 1: communication error on sub-link once happened any write action: clear this bit into 0 - 1 rw 0 2wire_timeout_int cause of interrupt 2-wire serial time out 0: 2-wire serial access in time ever 1: 2-wire serial access has once had time out any write action: clear this bit into 0 - 0 rw 0 slink_timeout_int cause of interrupt sub-link time out0: sub-link access in time ever 1: sub-link has once had time out any write action: clear this bit into 0 - 0x83 7:6 r 0x0 reserved - 5 rw 0 2wire_rst_enabled_int_enabl e 0: "2wire_rst_end_int" is blocked to be reported to master side. 1: "2wire_rst_end_int" is allowed to be reported to master side. (*1) 4 rw 0 2wire_nack_int_enable 0: "2wire_nack_int" is blocked to be reported to master side. 1: "2wire_nack_int" is allowed to be reported to master side. 3 rw 0 gpio_int_enable 0: "gpio_int" is blocked to be reported to master side. 1: "gpio_int" is allowed to be reported to master side. 2 rw 0 comerr_int_enable 0: "comerr_int" is blocked to be reported to master side. 1: "comerr_int" is allowed to be reported to master side. 1 rw 0 2wire_timeout_int_enable 0: "2wire_timeout_int" is blocked to be reported to master side. 1: "2wire_timeout_int" is allowed to be reported to master side. 0 rw 0 slink_timeout_int_enable 0: "slink_timeout_int" is blocked to be reported to master side. 1: "slink_timeout_int" is allowed to be reported to master side. 0x84 -0x8b 7:0 r 0x00 reserved - 0x8c 7 r 0 reserved - 6:0 rw 0x2d scl_w_h scl high width [t high ] setting. output scl high width is defined as below. ((scl_w_h + 1) * 8 + 8) * t osc - 0x8d 7 r 0 reserved - 6:0 rw 0x37 scl_w_l scl low width [t low ] setting. output scl low width is defined as below. ((scl_w_l + 1) * 8 + 8) * t osc - 0x8e 7:2 r 0x00 reserved - 1:0 rw 0x0 reserved. must be 0 - 0x8f 7:2 r 0x00 reserved - 1:0 rw 0x1 reserved - 0x90 -0xbf 7:0 r 0x00 reserved - *1 interrupt signal from sub-link slave is reported to sub-link master as cause of interrupt sub-link slave side (0x02 bit4 sla veside_int).
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 35/58 security e table 34. THCV231-Q gpio control register map address (hex) bit# r/w defaul t (hex) name description note sub-link slave 0xc0 7:5 r 0x0 reserved - 4 rw 1 gpio4_type gpio4 type select 0: programmable gpio 1: through gpio - 3 rw 1 gpio3_type gpio3 type select 0: programmable gpio 1: through gpio - 2:0 r 0x0 reserved - 0xc1 7:5 r 0x0 reserved - 4 r 0 gpio4_input_monitor gpio4 input value (*1) 3 r 0 gpio3_input_monitor gpio3 input value 2:0 r 0x0 reserved - 0xc2 7:5 r 0x0 reserved - 4 rw 0 gpio4_out gpio4 output value setting (*2) 3 rw 0 gpio3_out gpio3 output value setting 2:0 rw 0x0 reserved - 0xc3 7:5 r 0x0 reserved - 4:3 rw 0x0 gpio_io_sel gpio input/output direction setting see table 28, table 29 and table 30 - 2:0 rw 0x7 reserved - 0xc4 7:5 r 0x0 reserved - 4 rw 1 gpio4_filt_enable gpio4 input filter enable 0: disable 1: enable (*3) 3 rw 1 gpio3_filt_enable gpio3 input filter enable 0: disable 1: enable 2:0 rw 0x7 reserved - 0xc5 7:5 r 0x0 reserved - 4 rw 1 gpio4_int_enable gpio4 interrupt enable 0: disable 1: enable (*4) 3 rw 1 gpio3_int_enable gpio3 interrupt enable 0: disable 1: enable 2:0 rw 0x7 reserved - 0xc6 7:5 r 0x0 reserved - 4 rw 0 gpio4_outbuf_sel gpio4 output buffer select 0: gpio4 is open-drain output 1: gpio4 is push pull output - 3 rw 0 gpio3_outbuf_sel gpio3 output buffer select 0: gpio3 is open-drain output 1: gpio3 is push pull output - 2:0 rw 0x0 reserved - 0xc7-0xcf 7:0 r 0x00 reserved - *1 active only when gpio is set as input port. *2 active only when gpio type is set as "programmable gpio" and set as output port. *3 filter eliminates input glitch shorter than t osc /2. *4 gpio input transition is counted as gpio_int(0x82 bit3).
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 36/58 security e table 35. THCV231-Q main-link control register map address (hex) bit# r/w default (hex) name description note sub-link slave 0xd0 7 rw 1 mainmode mainmode setting 0: forbidden 1: sync free mode - 6 rw 1 hfsel hfsel setting 0: high frequency mode disable 1: high frequency mode enable - 5 rw 0 col1 col1 setting data width setting. see table 16. - 4 rw 1 col0 col0 setting data width setting. see table 16. - 3 rw 0 pre pre setting 0: pre-emphasis disable 1: pre-emphasis enable (*1) 2:1 rw 0x2 cmldrv cmldrv setting 00: 400mv diff p-p 01: 600mv diff p-p 10: 800mv diff p-p 11: reserved (forbidden) 0 rw 0 reserved - 0xd1 7:6 r 0x0 reserved - 5 rw 0 ssen ssen setting 0: sscg disable 1: sscg enable (*2) 4:0 rw 0x05 spread sscg modulation depth setting spread depth = spread x 0.1% (center spread) 0xd2 7:4 r 0x0 reserved - 3:0 rw 0xd fmod sscg modulation frequency setting - 0xd3 7:2 r 0x00 reserved - 1 rw 0 bet field bet mode enable setting 0: normal mode 1: field bet operation - 0 rw 0 bet_sel main-link / sub-link field bet mode select 0: main-link field bet mode 1: sub-link field bet mode - 0xd4 7 r 0 reserved - 6:0 rw 0x3e reserved. must be default setting. - 0xd5-0xec 7:0 rw 0x00 reserved - 0xed 7:3 r 0x00 reserved - 2:0 rw 0x1 reserved - 0xee 7:1 r 0x00 reserved - 0 rw 1 reserved. must be 1 - 0xef 7:0 r 0x00 reserved - 0xf0 7:2 r 0x00 reserved - 1 rw 0 reserved. must be 0 - 0 rw 0 pll_set_en sscg pll setting register enable 1: enable 0: disable - 0xf1 -0xf5 7:0 r 0x00 reserved - 0xf6 7:6 r 0x0 reserved - 5:0 rw 0xxx pll_set0 sscg pll setting (*3) 0xf7 7:4 r 0x0 reserved - 3:0 rw 0x0 reserved. must be default setting. - 0xf8 7:0 rw 0xxx pll_set1 sscg pll setting (*3) 0xf9-0xfb 7:0 rw 0x00 reserved. must be default setting. - 0xfc 7:6 r 0x0 reserved - 5:0 rw 0xxx pll_set2 sscg pll setting (*3) 0xfd-0xff 7:0 rw 0xxx reserved. must be default setting. - *1 see table 4 *2 ssen=1 and spread=0 setting is forbidden *3 see table 8, table 17
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 37/58 security e table 36. thcv236-q gpio control register map address (hex) bit# r/w default (hex) name description note sub-link master 0x40 7:5 r 0x0 reserved - 4 rw 1 gpio4_type gpio4 type select 0: programmable gpio 1: through gpio - 3 rw 1 gpio3_type gpio3 type select 0: programmable gpio 1: through gpio - 2 r 0 gpio2_type gpio2 type select 0: programmable gpio 0 fix - 1 r 0 gpio1_type gpio1 type select 0: programmable gpio 0 fix - 0 r 0 gpio0_type gpio0 type select 0: programmable gpio 0 fix - 0x41 7:5 r 0x0 reserved - 4 r 0 gpio4_input_monitor gpio4 input value (*1) 3 r 0 gpio3_input_monitor gpio3 input value 2 r 0 gpio2_input_monitor gpio2 input value 1 r 0 gpio1_input_monitor gpio1 input value 0 r 0 gpio0_input_monitor gpio0 input value 0x42 7:5 r 0x0 reserved - 4 rw 0 gpio4_out gpio4 output value setting (*2) 3 rw 0 gpio3_out gpio3 output value setting 2 rw 0 gpio2_out gpio2 output value setting 1 rw 0 gpio1_out gpio1 output value setting 0 rw 0 gpio0_out gpio0 output value setting 0x43 7:5 r 0x0 reserved - 4 rw (*3) gpio_io_sel gpio input/output direction setting see table 28, table 29 and table 30 - 3 rw (*3) 2:0 rw 0x7 0x44 7:5 r 0x0 reserved - 4 rw 1 gpio4_filt_enable gpio4 input filter enable 0: disable 1: enable (*4) 3 rw 1 gpio3_filt_enable gpio3 input filter enable 0: disable 1: enable 2 rw 1 gpio2_filt_enable gpio2 input filter enable 0: disable 1: enable 1 rw 1 gpio1_filt_enable gpio1 input filter enable 0: disable 1: enable 0 rw 1 gpio0_filt_enable gpio0 input filter enable 0: disable 1: enable 0x45 7:5 r 0x0 reserved - 4 rw 1 gpio4_int_enable gpio4 interrupt enable 0: disable 1: enable (*5) 3 rw 1 gpio3_int_enable gpio3 interrupt enable 0: disable 1: enable 2 rw 1 gpio2_int_enable gpio2 interrupt enable 0: disable 1: enable 1 rw 1 gpio1_int_enable gpio1 interrupt enable 0: disable 1: enable 0 rw 1 gpio0_int_enable gpio0 interrupt enable 0: disable 1: enable *1 active only when gpio is set as input port. *2 active only when gpio type is set as "programmable gpio" and set as output port. *3 default value depends on rxdefsel setting when power on sequence. rxdefsel=1 default value is 0 , rxdefsel=0 default value is 1. *4 filter eliminates input glitch shorter than t osc /2. *5 gpio input transition is counted as gpio_int(0x02 bit3).
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 38/58 security e address (hex) bit# r/w default (hex) name description note sub-link master 0x46 7:5 r 0x0 reserved - 4 rw 0 gpio4_outbuf_sel gpio4 output buffer select 0: gpio4 is open-drain output 1: gpio4 is push pull output - 3 rw 0 gpio3_outbuf_sel gpio3 output buffer select 0: gpio3 is open-drain output 1: gpio3 is push pull output - 2 rw 0 gpio2_outbuf_sel gpio2 output buffer select 0: gpio2 is open-drain output 1: gpio2 is push pull output - 1 rw 0 gpio1_outbuf_sel gpio1 output buffer select 0: gpio1 is open-drain output 1: gpio1 is push pull output - 0 rw 0 gpio0_outbuf_sel gpio0 output buffer select 0: gpio0 is open-drain output 1: gpio0 is push pull output - 0x47 -0x4f 7:0 r 0x00 reserved -
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 39/58 security e table 37. thcv236-q main-link control register map address (hex) bit# r/w default (hex) name description note sub-link master 0x50 7 rw (*1) mainmode mainmode setting 0: v-by-one ? hs mode 1: sync free mode - 6 rw (*1) hfsel hfsel setting 0: high frequency mode disable 1: high frequency mode enable - 5 rw 0 col1 col1 setting when mainmode =0 0: color space converter disable 1: color space converter enable when mainmode =1 data width setting. see table 16. - 4 rw (*1) col0 col0 setting data width setting. see table 16. - 3 rw 0 reserved - 2:1 rw 0x0 reserved - 0 rw 0 ttldrv ttldrv setting 0: weak drive strength 1: normal drive strength - 0x51 7:6 r 0x0 reserved - 5 rw 0 ssen ssen setting 0: sscg disable 1: sscg enable (*2) 4:0 rw 0x05 spread sscg modulation depth setting spread depth = spread x 0.1% (center spread) 0x52 7:4 r 0x0 reserved - 3:0 rw 0xd fmod sscg modulation frequency setting - 0x53 7:2 r 0x00 reserved - 1 rw 0 reserved - 0 rw 0 bet_sel main-link / sub-link field bet mode select 0: main-link field bet mode 1: sub-link field bet mode - 0x54 7 r 0 reserved - 6:0 rw 0x3e reserved. must be default setting. - 0x55 -0x6c 7:0 rw 0x0 reserved - 0x6d 7:3 r 0x00 reserved - 2 rw 0 outsel_enable permanent clock output enable setting 0: permanent clock output disable 1: permanent clock output enable - 1:0 rw 0x1 outsel_setting permanent clock frequency setting 00: 80mhz (clock period : t osc ) 01: 40mhz (clock period : t osc /2) 10: 20mhz (clock period : t osc /4) 11: 10mhz (clock period : t osc /8) (*3) 0x6e 7:1 r 0x00 reserved - 0 rw 1 reserved. must be 1 - 0x6f 7:0 r 0x00 reserved - 0x70 7:2 r 0x00 reserved - 1 rw 0 reserved. must be 0 - 0 rw 0 pll_set_en sscg pll setting register enable 1: enable 0: disable - 0x71 -0x75 7:0 r 0x00 reserved - 0x76 7:6 r 0x0 reserved - 5:0 rw 0x00 pll_set0 sscg pll setting (*4) 0x77 7:4 r 0x0 reserved - 3:0 rw 0x0 reserved. must be default setting. - 0x78 7:0 rw 0xxx pll_set1 sscg pll setting (*4) 0x79 -0x7b 7:0 r 0x00 reserved. must be default setting. - 0x7c 7:6 r 0x0 reserved - 5:0 rw 0xxx pll_set2 sscg pll setting (*4) 0x7d -0x7f 7:0 r 0xxx reserved. must be default setting. - *1 default value depends on rxdefsel setting when power on sequence. rxdefsel=1 default value is 0 , rxdefsel=0 default value is 1. *2 ssen=1 and spread=0 setting is forbidden *3 described value is typical value. it has variation in the range from min spec value to max spec value of t osc . *4 see table 8, table 17
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 40/58 security e absolute maximum ratings table 38. absolute maximum ratings paramete r min typ max unit supply voltage(vdd,avdd) -0.3 - 4.0 v lvcmos input voltage -0.3 - vdd+0.3 v lvcmos output voltage -0.3 - vdd+0.3 v lvcmos bi-directional buffer input voltage -0.3 - vdd+0.3 v lvcmos bi-directional buffer output voltage -0.3 - vdd+0.3 v open-drain output voltage -0.3 - 4.0 v cml receiver input voltage -0.3 - capina+0.3 v cml transmitter output voltage -0.3 - capina+0.3 v cml bi-directional buffer input voltage -0.3 - vdd+0.3 v cml bi-directional buffer output voltage -0.3 - vdd+0.3 v output current -50 - 50 ma storage temperature -55 - 125 c junction temperature - - 125 c reflow peak temperature/time - - 260/10 c/sec maximum power dissipation THCV231-Q@+25c - - 3.2 w maximum power dissipation thcv236-q@+25c - - 4.0 w recommended operating conditions table 39. recommended opera ting condition paramete r min typ max unit supply voltage(vdd,avdd) 1.7 - 3.6 v operating temperature -40 - 105 c electrical specification lvcmos dc specification table 40. lvcmos dc specification symbol paramete r pin type condition min typ max unit vih high level input voltage i vdd=1.7-2.0v 0.65vdd - vdd v vdd=2.0-3.0v 0.70vdd - vdd v vdd=3.0-3.6v 2.0 - vdd v il,b vdd=1.7-3.6v 0.70vdd - vdd v vil low level input voltage i vdd=1.7-2.0v 0 - 0.35vdd v vdd=2.0-3.0v 0 - 0.30vdd v vdd=3.0-3.6v 0 - 0.8 v il,b vdd=1.7-3.6v 0 - 0.30vdd v voh high level output voltage o,b vdd=1.7-3.6v ioh=-4ma vdd-0.45 - vdd v vol low level output voltage o,b vdd=1.7-3.6v iol=4ma 0 - 0.45 v bo vdd=1.7-3.6v iol=2ma 0 - 0.2 v iih input leak current high i,il vin=vdd - - 10 ua iil input leak current low i,il vin=0v -10 - - ua iozh output leak current high in hi-z state o,b,bo vin=vdd - - 10 ua iozl output leak current low in hi-z state o,b,bo vin=0v -10 - 10 ua
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 41/58 security e cml dc specification table 41. cml dc specification(THCV231-Q) symbol paramete r condition (*1) min typ max unit vtod cml differential output voltage cmldrv[1:0]=00 133 200 267 mv cmldrv[1:0]=01 200 300 400 mv cmldrv[1:0]=10 300 400 500 mv pre cml pre-emphasis level pre=0 - 0 - % pre=1,cmldrv[1:0]=00 - 100 - % pre=1,cmldrv[1:0]=01 - 50 - % vtoc cml common mode output voltage pre=0 capina-vtod mv pre=1,cmldrv[1:0]=00 capina-2vtod mv pre=1,cmldrv[1:0]=01 capina-1.5vtod mv itoh cml output leak current high pdn=0,txp/n=capina -30 - 30 ua itos cml output short current pdn=0,txp/n=0v -80 - - ma *1 pre and cmldrv[1:0] are registers. table 42. cml dc specification(thcv236-q) symbol paramete r condition min typ max unit vrth cml differential input high threshold - - - 50 mv vrtl cml differential input high threshold - -50 - - mv irih cml input leak current high pdn0=0,rxp/n=capina -10 - 10 ua iril cml input leak current low pdn0=0,rxp/n=0v -10 - 10 ua irrih cml input current high rxp/n=capina - - 2 ma irril cml input current low rxp/n=0v -6 - - ma rrin cml differential input resistance - 80 100 120 ? cml bi-directional dc specification table 43. cml bi-directional dc specification symbol paramete r condition min typ max unit vbth bi-directional buffer differential input high threshold - - - 150 mv vbtl bi-directional buffer differential input low threshold - -150 - - mv ibih bi-directional buffer output leak current high xcmp/n=vdd(x=t,r) -10 - 10 ua ibil bi-directional buffer output leak current low xcmp/n=0v(x=t,r) -10 - 10 ua rterm bi-directional buffer termination resistance transmitter state 37.5 50 62.5 ? receiver state 150 200 250 ? vbod bi-directional buffer differential output voltage rdiff=400 ? 300 - 660 mv vboc bi-directional buffer common output voltage - - vdd- 0.3 - v iboz bi-directional buffer tri-state current pdn=0(THCV231-Q) pdn1=0(thcv236-q) -10 - 10 ua
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 42/58 security e supply current table 44. supply current(THCV231-Q) symbol paramete r condition (*1) min typ max unit itccw transmitter supply current pdn=1, hfsel=1 - - 115 ma itccs transmitter power down supply current pdn = 0 all inputs = fixed 0 or 1 typical value is under 25 c - 2.5 20 ma *1 hfsel is a register. table 45. supply current(thcv236-q) symbol paramete r condition min typ max unit irccw receiver supply current cload=8pf, pdn0=1,pdn1=1,hfsel=1 - - 220 ma irccs receiver power down supply current pdn0 = 0 and pdn1 =0 all inputs = fixed 0 or 1 typical value is under 25 c - 2.5 20 ma switching characteristics table 46. switching characteristics (THCV231-Q) symbol paramete r condition (*1) min typ max unit ttrf cml output rise and fall time (20%-80%) - 50 - 150 ps ttcip clkin period see tabl e 16 1000/freq.range[mhz] ns ttch clkin high time - 0.35ttci p 0.5ttcip 0.65ttci p ns ttcl clkin low time - 0.35ttci p 0.5ttcip 0.65ttci p ns tts data input setup to clkin - 2.0 - - ns tth data input hold to clkin - 1.0 - - ns ttpd power on to pdn high delay - 0 - - ns ttcd input clock to output data delay mainmode=1, hfsel=0 56ttcip - 65ttcip ns mainmode=1, hfsel=1 109ttcip - 132ttcip ns ttpll0 pdn high to cml output delay - - - 10 ms ttpll1 pdn low to cml output high fix delay - - - 20 ns ttnp0 lockn high to training pattern output delay - - - 10 ms ttnp1 lockn low to data pattern output delay - - - 10 ms *1 mainmode and hfsel are registers.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 43/58 security e table 47. switching characteristics (thcv236-q) symbol paramete r condition min typ max unit trbit unit interval - 250 - 1666 ps trcp clkout period see t able 16 1000/freq.range[mhz] ns trch clkout high time - - trcp/2 - ns trcl clkout low time - - trcp/2 - ns tdout data output period - - trcp - ns trpd power on to pdn0 high delay - 0 - - ns trdc input data to output clock delay mainmode=1,hfsel=0 61trcp - 70trcp ns mainmode=1,hfsel=1 116trcp - 140trcp ns trhpd0 pdn0 high to htpdn low delay - - - 10 ms trhpd1 pdn0 low to htpdn high delay - - - 50 us trpll0 training pattern input to lockn low delay - - - 10 ms trpll1 pdn0 low to lockn high delay - - - 10 us trlck0 lockn low to data output delay - - - 5 ms trlck1 lockn high to data output stop delay - - - 10 us trosc0 pdn0 high to permanent clock output delay outsel=1 - - 5 ms trosc1 lockn low to permanent clock output low delay outsel=1 - - 1 ms trosc2 lockn high to permanent clock output delay outsel=1 - - 10 us trs data output setup to clkout - 0.45trcp-0.65 - - ns trh data output hold to clkout - 0.45trcp-0.65 - - ns ttlh clock, data output low to high transition time clock , ttldrv=0 - - 2.0 ns data , ttldrv=0 - - 3.5 ns clock , ttldrv=1 - - 0.8 ns data , ttldrv=1 - - 1.9 ns tthl clock, data output high to low transition time clock , ttldrv=0 - - 2.4 ns data , ttldrv=0 - - 4.4 ns clock , ttldrv=1 - - 1.0 ns data , ttldrv=1 - - 2.2 ns table 48. cml bi-directional switching characteristics symbol paramete r condition min typ max unit tbui bi-directional buffer unit interval - 80 100 120 ns tbrf bi-directional buffer rise and fall time(20%-80%) - 150 - 1000 ps tbpjtx bi-directional buffer transmitter period jitter accuracy (peak to peak) - - - 1 ns tbpjrx bi-directional buffer receiver period jitter tolerance (peak to peak) - 8 - - ns
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 44/58 security e table 49. 2-wire serial slave ac timi ng (sub-link master device) symbol paramete r min typ max unit f scl scl clock frequency - - 400 khz t hd;sta hold time (repeated) start condition 0.6 - - us t low low period of the scl clock 1.3 - - us t high high period of the scl clock 0.6 - - us t hd;dat data hold time: output - 9t osc - us data hold time: input 20 - - ns t su;dat data setup time: output 500 - - ns data setup time: input 100 - - ns t r rise time of both sda and scl signals - - 300 (*1) ns t f fall time of both sda and scl signals (pull-up resistor:2.5k ? ,bus capacitance:400pf) - - 300 ns t su;sto setup time for stop condition 0.6 - - ns t buf bus free time between a stop and start condition 1.3 - - us t sp pulse width of spikes which mu st be suppressed by the input filter - - 50 ns t pds required wait time from pdn1 high to start condition 2 - - ms *1 please adjust pull-up resistor and bus capacitance to meet the spec value. table 50. 2-wire serial master ac ti ming (sub-link slave device) symbol paramete r min typ max unit t osc cycle of internal oscillator clock 10.417 12.5 15.625 ns t hd;sta hold time (repeated) start condition - (scl_w_h 8 ? 3) t osc - us t low low period of the scl clock - ((scl_w_l + 1) 8 + 8) t osc - us t high high period of the scl clock - ((scl_w_h + 1) 8 + 8) t osc - us t hd;dat data hold time: output - 9t osc - us data hold time: input 20 - - ns t su;dat data setup time: output 31t osc - - ns data setup time: input 100 - - ns t r rise time of both sda and scl signals - - 300 (*1) ns t f fall time of both sda and scl signals (pull-up resistor:2.5k ? , bus capacitance:400pf) - - 300 ns t su;sto setup time for stop condition - 386t osc - ns t buf bus free time between a stop and start condition 4.7 - - us *1 please adjust pull-up resistor and bus capacitance to meet the spec value.
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 45/58 security e table 51. 2-wire serial interface transaction wait time symbol paramete r min typ max unit t wssr write access completion time to sub-link slave register - - 110 us t rssr read access completion time to sub-link slave register - - 90 us t wrs write start to remote side start condition generating time - - 65 us t rpw remote side stop condition generating to write access completion time - - 300 us t rrs read start to remote side start condition generating time - - 65 us t rpr remote side stop condition generating to read access completion time - - 300 us t ssep sub-link slave external processing time depending on characteristics of 2-wire serial slave devices connected to sub- link slave us table 52. sub-link control switching characteri stics (2-wire serial i/f mode) symbol paramete r min typ max unit t pvm programmable gpio output at sub-link master data valid - - 0 us t pvs programmable gpio output at sub-link slave data valid - - 110 us t tgpio through gpio delay - - 280 us t ivm sub-link master interrupt valid - - 90 us t irm sub-link master interrupt reset delay - - 0 us t ivs sub-link slave interrupt valid - - 300 us t irs sub-link slave interrupt reset delay 2wire_mode=00 - - 300 us 2wire_mode=01 - - 0 us t ps programmable gpio input data setup 10000(1/f scl ) - - us t ph programmable gpio input data hold 0 - - us
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 46/58 security e ac timing diagrams and test circuits lvcmos input, output switching characteristics figure 17. lvcmos input switching timing diagrams figure 18. lvcmos output switching timing diagrams
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 47/58 security e cml output switching characteristics figure 19. cml output switching characteristics figure 20. cml buffer equivalent circuit
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 48/58 security e cml bi-directional output test circuit figure 21. bi-directional cml vbod/vboc test circuit figure 22. bi-directional cml switching timing diagram and test circuit
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 49/58 security e latency characteristics figure 23. THCV231-Q latency figure 24. thcv236-q latency
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 50/58 security e lock and unlock sequence figure 25. THCV231-Q lock/unlock sequence figure 26. thcv236-q lock/unlock sequence
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 51/58 security e 2-wire serial i/f switching characteristics figure 27. 2-wire serial interface timing diagram figure 28. write access completion time to sub-link slave register figure 29. read access completion time to sub-link slave register
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 52/58 security e figure 30. write access completion time to remote side 2-wire serial slave register figure 31. read access completion time to remote side 2-wire serial slave register
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 53/58 security e gpio switching characteristics figure 32. through gpio delay figure 33. programmable gpio input timi ng at sub-link master side figure 34. programmable gpio output timing at sub-link master side figure 35. programmable gpio output timi ng at sub-link slave side
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 54/58 security e figure 36. gpio input and other interrupt even t timing at sub-link master side figure 37. gpio input and other interrupt ev ent timing at sub-link slave side (clock stretching mode) write 1 to 0x26 a ... ... gpio4~0 input port (sub-link slave side) data_a 2-wire serial i/f (sub-link master side) internal interrupt event (sub-link slave side) int of sub-link master t ivs t irs t ivs t irs read data of 0xc1 (data_a) (sub-link slave s register) write to 0x82 (sub-link slave s register) write to 0x02 a write 1 to 0x25 write to 0x02 a a figure 38. gpio input and other interrupt ev ent timing at sub-link slave side (no-clock stretching mode)
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 55/58 security e pcb layout guideline regarding vdd and avdd for thcv236-q when power is supplied from reverse side layer to av dd, please place ferrite bead between through-hole and avdd/vdd pins (good example1, 2). if it is needed to set ferrite beads on reverse side, please set gnd-through- hole between avdd and vdd, and separate the distance as possible (example). don?t set through-holes next to each other between ferrite beads an d avdd/vdd pins (bad example). good example 1 good example 2 example bad example
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 56/58 security e package unit : mm figure 39. 32-pin qfn package physical dimension
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 57/58 security e unit : mm figure 40. 64-pin qfn package physical dimension
THCV231-Q_thcv236-q_rev.2.60_e copyright ? 2017 thine electronics, inc. thine electronics, inc. 58/58 security e notices and requests 1. the product specifications described in this material are subject to change without prior notice. 2. the circuit diagrams described in this material are examples of the application which may not always apply to the customer?s design. we are not responsible for possible errors and omissions in this material. please note if errors or omissions should be found in this material, we may not be able to correct them immediately. 3. this material contains our copyright, know-how or ot her proprietary. copying or disclosing to third parties the contents of this material without our prior permission is prohibited. 4. note that if infringement of any third party's industrial ownership should occur by using this product, we will be exempted from the responsibility unless it directly relates to the production process or functions of the product. 5. product application 5.1 application of this product is intended for and limited to the following applications: audio-video device, office automation device, communication device, consumer electronics, smartphone, feature phone, and amusement machine device. this product must not be used for applications that require extremely high- reliability/safety such as aerospace device, traffic device, transportation device, nuclear power control device, combustion chamber device, medical device related to critical care, or any kind of safety device. 5.2 this product is not intended to be used as an au tomotive part, unless the product is specified as a product conforming to the demands and specifications of iso/ts 16949 ("the specified product") in this data sheet. thine electronics, inc. (?thine?) ac cepts no liability whatsoever for an y product other than the specified product for it not conforming to the aforementioned demands and specifications. 5.3 thine accepts liability for demands and specifications of the specified product only to the extent that the user and thine have been previously and explicitly agreed to each other. 6. despite our utmost efforts to improve the quality and reliability of the product, faults will occur with a certain small probability, which is inevitable to a semi-conducto r product. therefore, you are encouraged to have sufficiently redundant or error preventive design applied to the use of the product so as not to have our product cause any social or public damage. 7. please note that this product is not designed to be radiation/proof. 8. testing and other quality control techni ques are used to this product to the extent thine deems necessary to support warranty for performance of this product. except where mandated by applicable law or deemed necessary by thine based on the user?s request, testing of all functions and perform ance of the product is not necessarily performed. 9. customers are asked, if required, to judge by themselves if this product falls under the category of strategic goods under the foreign exchange and foreign trade control law. 10. the product or peripheral parts may be damaged by a surge in voltage over the absolute maximum ratings or malfunction, if pins of the prod uct are shorted by such as foreign substance. the damages may cause a smoking and ignition. therefore, you are encouraged to implement safety measures by adding protection devices, such as fuses. thine electronics, inc. sales@thine.co.jp http://www.thine.co.jp

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