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mb96680 series f 2 mc - 16fx 16 - bit microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 04705 rev.*a revised august 22, 2016 mb96680 s eries is based on cypress advanced f 2 mc - 16fx architecture (16 - bit with instruction pipeline for risc - like performance). the cpu uses the same instruction set as the established f 2 mc - 16lx family thus allowing for easy migration of f 2 mc - 16lx softwar e to the new f 2 mc - 16fx products. f 2 mc - 16fx product i mprovements compared to the previous generation include significantly improved performance - even at the same operation frequency, reduced power consumption and faster start - up time. for high processing s peed at optimized power consumption an internal pll can be selected to supply the cpu with up to 32 mhz operation frequency from an external 4mhz to 8mhz resonator. the result is a minimum instruction cycle time of 31.2 ns going together with excellent emi b ehavior. the emitted power is m inimized by the on - chip voltage regulator that reduces the internal cpu voltage. a flexible clock tree allows select ing suitable operation frequencies for peripheral resources independent of the cpu speed . f eatures ? technolog y 0.18 ? m cmos ? cpu ? f 2 mc - 16fx cpu ? optimized instruction set for controller applications (bit, byte, word and long - word data types, 23 different addressing modes, barrel shift, variety of pointers) ? 8 - byte instruction queue ? signed multiply (16 - bit 16 - bit) an d divide (32 - bit/16 - bit) instructions available ? system clock ? on - chip pll clock multiplier ( ? 1 to ? 8, ? 1 when pll stop) ? 4 mhz to 8 mhz crystal oscillator (maximum frequency when using ceramic resonator depends on q - factor) ? up to 8 mhz external clock for devic es with fast clock input feature ? 32 .76 8 khz subsystem quartz clock ? 100khz/2mhz internal rc clock for quick and safe startup, clock stop detection function , watchdog ? clock source selectable from mainclock oscillator , subclock oscillator and on - chip rc oscill ator, independently for cpu and 2 clock domains of peripherals ? the subclock oscillator is enabled by the boot rom program controlled by a configuration marker after a power or external reset ? low power consumption - 13 operating modes (different run, sleep, timer, stop mode s ) ? on - chip voltage regulator internal voltage regulator supports a wide mcu supply voltage range (min=2.7v), offering low power consumption ? low voltage detection function reset is generated when supply voltage falls below programmable refe rence voltage ? code security protects flash memory content from unintended read - out ? dma automatic transfer function independent of cpu, can be assigned freely to resources ? interrupts ? fast interrupt processing ? 8 programmable priority levels ? non - maskable int errupt (nmi) ? can ? supports can protocol version 2.0 part a and b ? iso16845 certified ? bit rates up to 1m bps ? 32 message objects ? each message object has its own identifier mask ? programmable fifo mode (concatenation of message objects) ? maskable interrupt ? disable d automatic retransmission mode for time triggered can applications ? programmable loop - back mode for self - test operation ? usart ? full duplex usarts (sci/lin) ? wide range of baud rate settings using a dedicated reload timer ? special synchronous options for adapt ing to different synchronous serial protocols ? lin functionality working either as master or slave lin device ? extended support for lin - protocol to reduce interrupt load ? i 2 c ? up to 400 k b p s ? master and slave functionality, 7 - bit and 10 - bit addressing
document number: 002 - 04705 rev.*a page 2 of 68 mb96680 series ? a/d conv erter ? sar - type ? 8/ 10 - bit resolution ? signals interrupt on conversion end, single conversion mode, continuous conversion mode, stop conversion mode, activation by software, external trigger , reload timers and ppgs ? range comparator function ? scan disable functi on ? adc pulse detection function ? source clock timers three independent clock timers (23 - bit rc clock timer, 23 - bit main clock timer, 17 - bit sub clock timer) ? hardware watchdog timer ? hardware watchdog timer is active after reset ? window function of watchdog ti mer is used to select the lower window limit of the watchdog interval ? reload timers ? 16 - bit wide ? prescaler with 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 of peripheral clock frequency ? event count function ? free - running timers ? signals an interrupt on overflow ? presc aler with 1, 1/2 1 , 1/2 2 , 1/2 3 , 1/2 4 , 1/2 5 , 1/2 6 , 1/2 7 , 1/2 8 of peripheral clock frequency ? input capture units ? 16 - bit wide ? signals an interrupt upon external event ? rising edge, falling edge or both (rising & falling) edges sensitive ? programmable pulse gener ator ? 16 - bit down counter, cycle and duty setting registers ? can be used as 2 8 - bit ppg ? interrupt at trigger, counter borrow and/or duty match ? pwm operation and one - shot operation ? internal prescaler allows 1, 1/4, 1/16, 1/64 of peripheral clock as counter clock or of selected reload timer underflow as clock input ? can be triggered by software or reload timer ? can trigger adc conversion ? timing point capture ? stepping motor controller ? stepping motor controller with integrated high current output drivers ? four hig h current outputs for each channel ? two synchronized 8/10 - bit pwms per channel ? internal prescaling for pwm clock: 1, 1/4, 1/5, 1/6, 1/8, 1/10, 1/12, 1/16 of peripheral clock ? dedicated power supply for high current output drivers ? lcd controller ? lcd con troller with up to 4com ? 32seg ? internal or external voltage generation ? duty cycle: selectable from options: 1/2, 1/3 and 1/4 ? fixed 1/3 bias ? programmable frame period ? clock source selectable from four options (ma in clock, peripheral clock, sub clock or rc oscillator clock) ? internal divider resistors or external divider resistors ? on - chip data memory for display ? lcd display can be operated in timer mode ? blank display: selectable ? all seg, com and v pins can be switched between general and specialized purposes ? sound generator ? 8 - bit pwm signal is mixed with tone frequency from 16 - bit reload counter ? pwm clock by internal prescaler: 1, 1/2, 1/4, 1/8 of peripheral clock ? real time clock ? operational on main oscillation (4mhz), sub oscillation (32khz) or rc oscillation (100khz/2mhz) ? capable to correct oscillation deviation of sub clock or rc oscillator clock (clock calibration) ? read/write accessible second/minute/hour registers ? can signal interrupt every half second/second/minute/hour/day ? internal clock divider and pres caler provide exact 1s clock ? external interrupts ? edge or level sensitive ? interrupt mask bit per channel ? each available can channel rx has an external interrupt for wake - up ? selected usart channels sin have an external interrupt for wake - up ? non maskable inte rrupt ? disabled after reset, can be enabled by boot - rom depending on rom configuration block ? once enabled, cannot be disabled other than by reset ? high or low level sensitive ? pin shared with external interrupt 0 ? i/o ports ? most of the external pins can be use d as general purpose i/o ? all push - pull outputs (except when used as i 2 c sda/scl line) ? bit - wise programmable as input/output or peripheral signal ? bit - wise programmable input enable ? one input level per gpio - pin (either automotive or cmos hysteresis) ? bit - wise programmable pull - up resistor
document number: 002 - 04705 rev.*a page 3 of 68 mb96680 series ? built - in on chip debugger (ocd) ? one - wire debug tool interface ? break function: ? hardware break: 6 points (shared with code event) ? software break: 4096 points ? event function ? code event: 6 points (shared with hardware break) ? d ata event: 6 points ? event sequencer: 2 levels + reset ? execution time measurement function ? trace function: 42 branches ? security function ? flash memory ? dual operation flash allowing reading of one flash bank while programming or erasing the other bank ? comman d sequencer for automatic execution of programming algorithm and for supporting dma for programming of the flash memory ? supports automatic programming, embedded algorithm ? write/erase/erase - suspend/resume commands ? a flag indicating completion of the automat ic algorithm ? erase can be performed on each sector individually ? sector protection ? flash security feature to protect the content of the flash ? low voltage detection during flash erases or writes
document number: 002 - 04705 rev.*a page 4 of 68 mb96680 series contents 1. product lineup ................................ ................................ ................................ ................................ ................................ .. 6 2. block diagram ................................ ................................ ................................ ................................ ................................ ... 7 3. pin assignment ................................ ................................ ................................ ................................ ................................ . 8 4. pin de scription ................................ ................................ ................................ ................................ ................................ .. 9 5. pin circuit type ................................ ................................ ................................ ................................ ............................... 11 6. i/o circuit type ................................ ................................ ................................ ................................ ................................ 14 7. memory map ................................ ................................ ................................ ................................ ................................ .... 20 8. ramstart addresses ................................ ................................ ................................ ................................ ................... 21 9. user rom memory map for flash devices ................................ ................................ ................................ .................. 22 10 . serial programming communication interface ................................ ................................ ................................ ............ 23 11. interrupt vector table ................................ ................................ ................................ ................................ ..................... 24 12. handling precautions ................................ ................................ ................................ ................................ ..................... 28 12.1 precautions for product design ................................ ................................ ................................ ................................ ... 28 12.2 precautions for package mounting ................................ ................................ ................................ .............................. 29 12.3 precautions for use environment ................................ ................................ ................................ ................................ 30 13. handling devices ................................ ................................ ................................ ................................ ............................ 31 13.1 latch - up prevention ................................ ................................ ................................ ................................ ..................... 31 13 .2 unused pins handling ................................ ................................ ................................ ................................ .................. 31 13.3 external clock usage ................................ ................................ ................................ ................................ ................... 31 13.3.1 single phase external clock for main oscillator ................................ ................................ ................................ ............. 31 13.3.2 single phase external clock for sub oscillator ................................ ................................ ................................ .............. 32 13.3.3 opposite phase external clock ................................ ................................ ................................ ................................ ..... 32 13.4 notes on pll clock mode operation ................................ ................................ ................................ ............................ 32 13.5 power supply pins (v cc /v ss ) ................................ ................................ ................................ ................................ ......... 32 13.6 crystal oscillator and ceramic resonator circui t ................................ ................................ ................................ ........... 32 13.7 turn on sequence of power supply to a/d converter and analog inputs ................................ ................................ ...... 32 13.8 pin handling when not using the a/d converter ................................ ................................ ................................ ........... 33 13.9 notes on power - on ................................ ................................ ................................ ................................ ...................... 33 13.10 stabilization of power supply voltage ................................ ................................ ................................ ........................... 33 13.11 smc power supply pins ................................ ................................ ................................ ................................ ............... 33 13.12 serial communication ................................ ................................ ................................ ................................ .................. 33 13.13 mode pin (md) ................................ ................................ ................................ ................................ ............................ 33 14. electrical characteristics ................................ ................................ ................................ ................................ ............... 34 14.1 absolute maximum ratings ................................ ................................ ................................ ................................ ......... 34 14.2 recommended operating conditions ................................ ................................ ................................ .......................... 36 14.3 dc characteristics ................................ ................................ ................................ ................................ ....................... 37 14.3.1 current rating ................................ ................................ ................................ ................................ .............................. 37 14.3.2 pin characteristics ................................ ................................ ................................ ................................ ....................... 41 14.4 ac characteristics ................................ ................................ ................................ ................................ ....................... 44 14.4.1 main clock input characteristics ................................ ................................ ................................ ................................ .. 44 14.4.2 s ub clock input characteristics ................................ ................................ ................................ ................................ ... 45 14.4.3 built - in rc oscillation characteristics ................................ ................................ ................................ .......................... 46 14.4.4 internal clock timing ................................ ................................ ................................ ................................ ................... 46 14.4.5 operating conditions of pll ................................ ................................ ................................ ................................ ........ 47 14.4.6 reset input ................................ ................................ ................................ ................................ ................................ ... 47 14.4.7 power - on reset timing ................................ ................................ ................................ ................................ ................ 48
document number: 002 - 04705 rev.*a page 5 of 68 mb96680 series 14.4.8 usart timing ................................ ................................ ................................ ................................ ............................. 49 14.4.9 external input timing ................................ ................................ ................................ ................................ ................... 51 14.4.10 i 2 c timin g ................................ ................................ ................................ ................................ ................................ . 52 14.5 a/d converter ................................ ................................ ................................ ................................ .............................. 53 14.5.1 electrical characteristics for the a/d converter ................................ ................................ ................................ ........... 53 14.5.2 accuracy and setting of the a/d converter sampling time ................................ ................................ ......................... 54 14.5.3 definition of a/d converter terms ................................ ................................ ................................ ............................... 55 14.6 high c urrent output slew rate ................................ ................................ ................................ ................................ ... 57 14.7 low voltage detection function characteristics ................................ ................................ ................................ ......... 58 14.8 flash memory write/erase characteristics ................................ ................................ ................................ ................. 60 15. example characteristics ................................ ................................ ................................ ................................ ................ 61 16. ordering information ................................ ................................ ................................ ................................ ...................... 64 17. package dimen sion ................................ ................................ ................................ ................................ ........................ 65 18. major changes ................................ ................................ ................................ ................................ ................................ 66 document history ................................ ................................ ................................ ................................ ................................ . 67
document number: 002 - 04705 rev.*a page 6 of 68 mb96680 series 1. p roduct l ineup features mb96680 remark product t ype flash memory product subclock subclock can be set by software dual operation flash memory ram - 64.5kb + 32kb 4kb mb96f683r, mb96f683a product options r: mcu with can a: mcu without can 128.5kb + 32kb 4kb mb96f685r, mb96f685a package lqfp - 80 f pt - 80p - m21 dma 2ch usart 2ch lin - usart 0/1 with automatic lin - header transmission/reception yes (only 1ch) lin - usart 0 with 16 byte rx - and tx - fifo no i 2 c 1ch i 2 c 0 8/10 - bit a/d converter 14ch an 8 to 13/16 to 23 with data buffer no with r ange comparator yes with scan disable yes with adc pulse detection yes 16 - bit reload timer (rlt) 3ch rlt 1/2/6 16 - bit free - running timer (frt) 2ch frt 0/1 16 - bit input capture unit (icu) 4ch (2 channels for lin - usart) icu 0/1/4/5 (icu 0/1 for l in - usart) 8/16 - bit programmable pulse generator (ppg) 4ch (16 - bit) / 8ch (8 - bit) ppg 0 to 3 with timing point capture yes with start delay no with ramp no can interface 1ch can 0 32 message buffers stepping motor controller (smc) 2ch smc 0/1 e xternal interrupts (int) 7ch int 0 to 4/6/7 non - maskable interrupt (nmi) 1ch sound generator (sg) 1ch sg 0 lcd controller 4com 32seg com 0 to 3 seg 1 to 12/19 to 24/ 30/36 to 39/42/45 to 47/ 52 to 56 real time clock (rtc) 1ch i/o ports 63 (dual cl ock mode) 65 (single clock mode) clock calibration unit (cal) 1ch clock output function 2ch low voltage detection function yes low voltage detection function can be disabled by software hardware watchdog timer yes on - chip rc - oscillator yes on - c hip debugger yes note : all signals of the peripheral function in each product cannot be allocated by limiting the pins of package. it is necessary to use the port relocate function of the g eneral i/o port according to your function use.
document number: 002 - 04705 rev.*a page 7 of 68 mb96680 series 2. block diagram i 2 c 1 ch s d a0 scl 0 d m a controller boot r om p e r iphe r al bus b r i d ge p e r iphe r al bus b r i d ge 16fx cor e b u s (c l kb) usa r t 2 ch 8/10-bit ad c 14 ch i/ o t i m e r 0 f r t 0 icu 0/1 ca n int e r f a c e 1 ch real tim e clo c k w atchdog ra m v ol t a ge regulator s i n0, s i n 1 s o t0, s o t1 sck0, sck1 a vcc a vss a v r h an8 t o an13 adt g frck0 , frck0_ r i n 0 , i n 0_ r , i n 1 , i n 1_ r tx 0 vcc vss c 16f x cp u int e r r u p t controller clo c k & mode controller flas h memo r y a n m i 16-bit reloa d time r 1/2/6 3ch t i n1 , t i n2 to t 1 , to t 2 ppg0, p p g1, ppg 3 ttg0 , ttg 1 c k o t x0 , c k o t x 1 x0, x 1 x0a, x1a rst x m d ppg 4 ch (16-b i t ) / 8 ch (8-b i t ) p p g0_r to ppg3_r ppg0_ b to p p g3_b an1 6 to an23 i/ o t i m e r 1 f r t 1 icu 4/5 frck 1 in4_r, in5_ r exte r nal int e r r u p t i n t 0 t o i nt 4 i nt 1_ r , i n t 2_r, int3_ r i nt 6 , i nt 7 ocd debug i / f gene r a t or sgo0 sga0 sound 1 ch 7 ch lc d d r i v er controlle r / com0 t o com 3 seg1 t o seg12 2 ch pwm1m0 , pwm 1 m 1 pwm1p0, pwm1 p 1 pwm2m0 , pwm 2 m 1 pwm2p0, pwm2 p 1 d vcc d vss stepping mo t or controller seg19 t o seg 2 4 seg30, seg3 6 to seg39 seg52 t o seg 5 6 4 c o m 32se g w o t , w o t _ r to t 1_r , to t 2_r t i n1_r , t i n2_ r rx 0 p e r iphe r al b us 2 (clkp2) p e r iphe r al b us 1 (clkp1) seg42, seg4 5 to seg47 v0 to v3 c k o t 0 _ r , c k o t 1
document number: 002 - 04705 rev.*a page 8 of 68 mb96680 series 3. pin assignment (top view) (fpt - 80p - m21) * 1 : cmos input level only * 2 : cmos input level only for i 2 c * 3 : please set rom configuration block (rcb) to use the sub clock . other than those above, general - purpose pins have only automotive input level . p 12_ 0 / s e g 4 / i n 1_ r v s s p 11_ 3 / c o m 3 / pp g 2 _ r p 11_ 2 / c o m 2 / pp g 1 _ r p 11_ 1 / c o m 1 / pp g 0 _ r p 11_ 0 / c o m 0 p 11_ 7 / s e g 3 / i n 0_ r p 11_ 6 / s e g 2 / f rc k 0 _ r p 11_ 5 / s e g 1 p 11_ 4 / p p g 3_ r r s t x p 04_ 1 / x 1 a * 3 p 04_ 0 / x 0 a * 3 v s s x 1 x 0 m d p 17_ 0 d e b u g i/ f p 04_ 5 / s c l 0 * 2 p 1 2 _1 / se g 5 / t i n 1 _r / pp g 0_ b 6 1 4 0 p 0 4_4 / pp g 3 / s d a 0 * 2 p 1 2_2 / se g 6 / t o t 1 _ r / pp g 1_ b 6 2 3 9 p 1 3_6 / s c k 0 / c k o t x 0 / se g 4 7 * 1 p 12 _ 3 / se g 7 6 3 3 8 p 1 3_5 / s o t 0 / a d t g / i n t 7 / se g 4 6 p 12 _ 4 / se g 8 6 4 3 7 p 1 3_4 / s i n 0 / i n t 6 / se g 4 5 * 1 p 1 2 _5 / se g 9 / t i n 2 _r / pp g 2_ b 6 5 3 6 p 1 3_3 / pp g 1 / w o t p 1 2_6 / se g 1 0 / t o t 2 _ r / p p g 3_ b 6 6 3 5 p 1 3_2 / pp g 0 / f r c k 1 p 12_ 7 / se g 11 / i n t 1 _ r 6 7 3 4 p 0 8_7 / p w m 2 m 1 / a n 2 3 p 00_ 0 / se g 12 / i n t 3 _ r 6 8 3 3 p 0 8_6 / p w m 2 p 1 / a n 2 2 p 01 _ 1 / se g 2 1 / c k o t 1 6 9 3 2 p 0 8_5 / p w m 1 m 1 / a n 2 1 p 01_ 2 / se g 22 / c k o t x 1 7 0 3 1 p 0 8_4 / p w m 1 p 1 / a n 2 0 p 01 _ 3 / se g 2 3 7 1 3 0 d v s s p 01 _ 4 / se g 2 4 7 2 2 9 d v c c p 0 3 _0 / se g 3 6 / v 0 7 3 2 8 p 0 8_3 / p w m 2 m 0 / a n 1 9 p 0 3 _1 / se g 3 7 / v 1 7 4 2 7 p 0 8_2 / p w m 2 p 0 / a n 1 8 p 0 3 _2 / se g 3 8 / v 2 7 5 2 6 p 0 8_1 / p w m 1 m 0 / a n 1 7 p 0 3 _3 / se g 3 9 / v 3 7 6 2 5 p 0 8_0 / p w m 1 p 0 / a n 1 6 p 03_ 4 / r x 0 / i n t 4 * 1 7 7 2 4 p 0 5_7 / t o t 2 p 0 3_5 / t x 0 7 8 2 3 p 0 5_6 / t i n 2 p 03_ 6 / i n t 0 / n m i 7 9 2 2 p 0 5_5 / a n 1 3 vc c 8 0 2 1 p 0 5_4 / a n 12 / i n t 2 _ r / w o t _ r v s s c p 03 _ 7 / i n t 1 / s i n 1 * 1 p 13_ 0 / i n t 2 / s o t 1 p 13_1 / i n t 3 / s c k 1 / se g 42 * 1 p 0 0_7 / se g 1 9 / s g o 0 p 01_0 / s e g 20 / s g a 0 p 02_ 2 / s e g 30 / c k o t 0 _ r p 0 6_3 / f rc k 0 / se g 5 2 p 0 6 _4 / i n 0 / se g 5 3 / tt g 0 p 0 6 _5 / i n 1 / se g 5 4 / tt g 1 p 0 6_6 / t i n 1 / se g 55 / i n 4_ r p 06_ 7 / t o t 1 / se g 56 / i n 5_ r p 05_ 0 / a n 8 p 05_ 1 / a n 9 av c c av r h a v s s p 05_2 / a n 1 0 p 05_3 / a n 1 1 l q f p - 8 0 1 6 1 7 1 8 1 9 2 0 1 5 1 4 1 3 1 2 1 1 1 0 9 8 7 6 5 4 3 2 1 4 5 4 4 4 3 4 2 4 1 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0
document number: 002 - 04705 rev.*a page 9 of 68 mb96680 series 4. pin description pin name feature description adtg adc a/d converter trigger input pin ann adc a/d converter channel n input pin avcc supply analog circuits power supply pin avrh adc a/d converter high reference voltage input pin avss supply analog circuits power supply pin c voltage regulator internally regulated power supply stabilization capacitor pin ckotn clock output function clock output function n output pin ckotn_r clock output function relocated clock output function n output pin ckotx n clock output function clock output function n inverted output pin comn lcd lcd common driver pin debug i/f ocd on chip debugger input/output pin dvcc supply smc pins power supply dvss supply smc pins power supply frckn free - running timer free - runnin g timer n input pin frckn_r free - running timer relocated free - running timer n input pin inn icu input capture unit n input pin inn_r icu relocated input capture unit n input pin intn external interrupt external interrupt n input pin intn_r external in terrupt relocated external interrupt n input pin md core input pin for specifying the operating mode nmi external interrupt non - maskable interrupt input pin pnn_m gpio general purpose i/o pin ppgn ppg programmable pulse generator n output pin (16bit/8b it) ppgn_r ppg relocated programmable pulse generator n output pin (16bit/8bit) ppgn_b ppg programmable pulse generator n output pin (16bit/8bit) pwmn smc smc pwm high current output pin rstx core reset input pin rxn can can interface n rx input pin sckn usart usart n serial clock input/output pin scln i 2 c i 2 c interface n clock i/o input/output pin sdan i 2 c i 2 c interface n serial data i/o input/output pin segn lcd lcd segment driver pin sgan sound generator sound generator amplitude output pin sg on sound generator sound generator sound/tone output pin sinn usart usart n serial data input pin sotn usart usart n serial data output pin tinn reload timer reload timer n event input pin tinn_r reload timer relocated reload timer n event input pin t otn reload timer reload timer n output pin totn_r reload timer relocated reload timer n output pin
document number: 002 - 04705 rev.*a page 10 of 68 mb96680 series pin name feature description ttgn ppg programmable pulse generator n trigger input pin txn can can interface n tx output pin vn lcd lcd voltage reference pin vcc supply power supply pin vss supply power supply pin wot rtc real time clock output pin wot_r rtc relocated real time clock output pin x0 clock oscillator input pin x0a clock subclock oscillator input pin x1 clock oscillator output pin x1a clock subclock oscillator out put pin
document number: 002 - 04705 rev.*a page 11 of 68 mb96680 series 5. pin circuit type pin no. i/o circuit type * pin name 1 supply v ss 2 f c 3 m p03_7 / int1 / sin1 4 h p13_0 / int2 / sot1 5 p p13_1 / int3 / sck1 / seg42 6 j p00_7 / seg19 / sgo0 7 j p01_0 / seg20 / sga0 8 j p02_2 / seg30 / ckot0_r 9 j p 06_3 / frck0 / seg52 10 j p06_4 / in0 / seg53 / ttg0 11 j p06_5 / in1 / seg54 / ttg1 12 j p06_6 / tin1 / seg55 / in4_r 13 j p06_7 / tot1 / seg56 / in5_r 14 k p05_0 / an8 15 k p05_1 / an9 16 supply av cc 17 g avrh 18 supply av ss 19 k p05_2 / an10 20 k p05_3 / an11 21 k p05_4 / an12 / int2_r / wot_r 22 k p05_5 / an13 23 h p05_6 / tin2 24 h p05_7 / tot2 25 r p08_0 / pwm1p0 / an16 26 r p08_1 / pwm1m0 / an17 27 r p08_2 / pwm2p0 / an18 28 r p08_3 / pwm2m0 / an19 29 supply dv cc 30 supply dv ss 31 r p08_4 / pwm1p1 / an20 32 r p08_5 / pwm1m1 / an21 33 r p08_6 / pwm2p1 / an22 34 r p08_7 / pwm2m1 / an23 35 h p13_2 / ppg0 / frck1 36 h p13_3 / ppg1 / wot 37 p p13_4 / sin0 / int6 / seg45
document number: 002 - 04705 rev.*a page 12 of 68 mb96680 series pin no. i/o circuit type * pin name 38 j p13_5 / sot0 / adtg / int7 / seg46 39 p p13_6 / sck0 / ckotx0 / seg47 40 n p04_4 / ppg3 / sda0 41 n p04_5 / scl0 42 supply v ss 43 o debug i/f 44 h p17_0 45 c md 46 a x0 47 a x1 48 supply v ss 49 b p04_0 / x0a 50 b p04_1 / x1a 51 c rstx 52 h p11_4 / ppg3_r 53 j p11_5 / seg1 54 j p11_6 / seg2 / frck0_r 55 j p11_7 / seg3 / in0_r 56 j p11_0 / com0 57 j p11_1 / com1 / ppg0_r 58 j p11_2 / com2 / ppg1_r 59 j p11_3 / com3 / ppg2_r 60 j p12_0 / seg4 / in1_r 61 j p12_1 / seg5 / tin1_r / ppg0_b 62 j p12_2 / seg6 / tot1_r / ppg1_b 63 j p12_3 / seg 7 64 j p12_4 / seg8 65 j p12_5 / seg9 / tin2_r / ppg2_b 66 j p12_6 / seg10 / tot2_r / ppg3_b 67 j p12_7 / seg11 / int1_r 68 j p00_0 / seg12 / int3_r 69 j p01_1 / seg21 / ckot1 70 j p01_2 / seg22 / ckotx1 71 j p01_3 / seg23 72 j p01_4 / seg24 73 l p03_0 / seg36 / v0 74 l p03_1 / seg37 / v1 75 l p03_2 / seg38 / v2 76 l p03_3 / seg39 / v3
document number: 002 - 04705 rev.*a page 13 of 68 mb96680 series pin no. i/o circuit type * pin name 77 m p03_4 / rx0 / int4 78 h p03_5 / tx0 79 h p03_6 / int0 / nmi 80 supply v cc *: see i/o circuit type for details on the i/o c ircuit types.
document number: 002 - 04705 rev.*a page 14 of 68 mb96680 series 6. i/o circuit type type circuit remarks a high - speed oscillation circuit: ? programmable between oscillation mode (external crystal or resonator connected to x0/x1 pins) and fast external clock input (fci) mode (external clock connected to x 0 pin) ? feedback resistor = approx. 1.0 m ? ? the amplitude : 1.8v 0.15v to operate by the internal supply voltage r fci x out 0 1 x1 x0 f c i or o sc d i sab l e
document number: 002 - 04705 rev.*a page 15 of 68 mb96680 series type circuit remarks b low - speed oscillation circuit shared with gpio functionality: ? feedback resistor = approx. 5.0 m ? ? gpio functionality selectable (cmos level outp ut (i ol = 4ma, i oh = - 4ma), automotive input with input shutdown function and p rogrammable pull - up resistor) c cmos hysteresis input pin r fci x out 0 1 pout r nout automotive input fci or osc disable standby control for input shutdown standby control for input shutdown automotive input x1a x0a r p-ch p-ch n-ch pull-up control pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04705 rev.*a page 16 of 68 mb96680 series type circuit remarks f power supply input protection circuit g ? a/d converter ref+ (avrh) power supply input pin with protection cir cuit ? without protection circuit against v cc for pins avrh h ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor j ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? seg or com output p-ch n-ch p-ch n-ch standby control for input shutdown automotive input r pull-up control pout nout p-ch p-ch n-ch standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch seg or co m output automotive input
document number: 002 - 04705 rev.*a page 17 of 68 mb96680 series type circuit remarks k ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automotive input with input shutdown function ? programmable pull - up resistor ? analog input l ? cmos level output (i ol = 4ma, i oh = - 4ma) ? automo tive input with input shutdown function ? programmable pull - up resistor ? v n input or seg output m ? cmos level output (i ol = 4ma, i oh = - 4ma) ? cmos h ysteresis input with input shutdown function ? programmable pull - up resistor standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch analog input automotive input standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch vn input or s e g output automotive input standby control for input shutdown h y s t e r e s i s in put r pull-up control pout nout p-ch p-ch n-ch
document number: 002 - 04705 rev.*a page 18 of 68 mb96680 series type circuit remarks n ? cmos level output (i ol = 3ma, i oh = - 3ma) ? cmos hysteresis input with input shutdown function ? programmable pull - up resistor *: n - channel transistor has slew rate control according to i 2 c spec, irrespective of usage. o ? open - drain i/o ? output 25ma, v cc = 2.7v ? ttl input p ? cmos lev el output (i ol = 4ma, i oh = - 4ma) ? cmos h ysteresis inputs with input shutdown function ? programmable pull - up resistor ? seg or com output standby control for input shutdown h y s t e r e s i s in put r pull-up control pout nout* p-ch p-ch n-ch standby control for input shutdown t t l input r nout n-ch standby control for input shutdown r pull-up control pout nout p-ch p-ch n-ch seg or co m output h y s t e r e s i s in put
document number: 002 - 04705 rev.*a page 19 of 68 mb96680 series type circuit remarks r ? cmos level output (programmable i ol = 4ma, i oh = - 4ma and i ol = 30ma, i oh = - 30ma) ? automotive input with input shutd own function ? programmable pull - up / pull - down resistor ? analog input standby control for input shutdown r pull-up control pull-down control pout nout p-ch p-ch n-ch n-ch analog input automotive input
document number: 002 - 04705 rev.*a page 20 of 68 mb96680 series 7. memory map *1: for details about user rom area, see u ser rom memory map for flash devices on the following pages. *2: for ramstart addresses see the table on the next page. *3: unused gpr banks can be used as ram area . gpr: general - purpose register the dma area is only available if the device contains the corresponding resource. the available ram and rom area depends on the device. ff:ffff h de:0000 h dd:ffff h 10:0000 h 0f:c000 h 0e:9000 h 01:0000 h 00:8000 h rams t a r t0* 2 00:0c00 h 00:0380 h 00:0180 h 00:0100 h 00:00f0 h 00:0000 h gpr* 3 dm a reserved peripheral reserved user rom* 1 reserved boot-rom peripheral rom/ram mirror internal ram bank0 peripheral reserved
document number: 002 - 04705 rev.*a page 21 of 68 mb96680 series 8. rams tart addres ses devices bank 0 ram size ramstart0 mb96f683 mb96f685 4kb 00:7200 h
document number: 002 - 04705 rev.*a page 22 of 68 mb96680 series 9. u ser rom memory map for flash devices *: physical address area of sas - 512b is from df:0000 h to df:01ff h . others (from df:0200 h to df:1fff h ) is m irror area of sas - 512b. sector s as contains the rom configuration block rcba at cpu address df: 0000 h - df:01ff h . sas cannot be used for e 2 prom emulation. mb96f683 mb96f685 flash size flash size 64.5kb + 32kb 128.5kb + 32kb cpu mode address flash memory mode address df:a000 h df:9fff h 1f:9fff h df:8000 h 1f:8000 h df:7fff h 1f:7fff h df:6000 h 1f:6000 h df:5fff h 1f:5fff h df:4000 h 1f:4000 h df:3fff h 1f:3fff h df:2000 h 1f:2000 h df:1fff h 1f:1fff h df:0000 h 1f:0000 h de:ffff h de:0000 h sas - 512b* sa2 - 8kb sa1 - 8kb reserved reserved sa39 - 64kb reserved sa4 - 8kb sa3 - 8kb sa2 - 8kb sa1 - 8kb sas - 512b* reserved sa4 - 8kb sa3 - 8kb sa39 - 64kb sa38 - 64kb ff:ffff h 3f:ffff h ff:0000 h 3f:0000 h fe:ffff h 3e:ffff h fe:0000 h 3e:0000 h fd:ffff h bank b of flash a bank a of flash a bank a of flash a
document number: 002 - 04705 rev.*a page 23 of 68 mb96680 series 10. serial programming communication interface usart pins for flash serial programming (md = 0, debug i/f = 0, serial communication mode ) mb96680 pin number usart number normal function 37 usart0 sin0 38 sot0 39 sck0 3 usart1 sin1 4 sot1 5 sck1
document number: 002 - 04705 rev.*a page 24 of 68 mb96680 series 11. interrupt vector table vector number offset in vector table vector name cleared by dma index in icr to program description 0 3fc h c allv0 no - callv instruction 1 3f8 h callv1 no - callv instruction 2 3f4 h callv2 no - callv instruction 3 3f0 h callv3 no - callv instruction 4 3ec h callv4 no - callv instruction 5 3e8 h callv5 no - callv instruction 6 3e4 h callv6 no - callv instruction 7 3e0 h callv7 no - callv instruction 8 3dc h reset no - reset vector 9 3d8 h int9 no - int9 instruction 10 3d4 h exception no - undefined instruction execution 11 3d0 h nmi no - non - maskable interrupt 12 3cc h dly no 12 delayed interrupt 13 3c8 h rc_time r no 13 rc clock timer 14 3c4 h mc_timer no 14 main clock timer 15 3c0 h sc_timer no 15 sub clock timer 16 3bc h lvdi no 16 low voltage detector 17 3b8 h extint0 yes 17 external interrupt 0 18 3b4 h extint1 yes 18 external interrupt 1 19 3b0 h extint2 yes 19 external interrupt 2 20 3ac h extint3 yes 20 external interrupt 3 21 3a8 h extint4 yes 21 external interrupt 4 22 3a4 h - - 22 reserved 23 3a0 h extint6 yes 23 external interrupt 6 24 39c h extint7 yes 24 external interrupt 7 25 398 h - - 25 reserved 2 6 394 h - - 26 reserved 27 390 h - - 27 reserved 28 38c h - - 28 reserved 29 388 h - - 29 reserved 30 384 h - - 30 reserved 31 380 h - - 31 reserved 32 37c h - - 32 reserved 33 378 h can0 no 33 can controller 0 34 374 h - - 34 reserved 35 370 h - - 35 reser ved 36 36c h - - 36 reserved 37 368 h - - 37 reserved 38 364 h ppg0 yes 38 programmable pulse generator 0 39 360 h ppg1 yes 39 programmable pulse generator 1
document number: 002 - 04705 rev.*a page 25 of 68 mb96680 series vector number offset in vector table vector name cleared by dma index in icr to program description 40 35c h ppg2 yes 40 programmable pulse generator 2 41 358 h ppg3 yes 41 programmable pulse genera tor 3 42 354 h - - 42 reserved 43 350 h - - 43 reserved 44 34c h - - 44 reserved 45 348 h - - 45 reserved 46 344 h - - 46 reserved 47 340 h - - 47 reserved 48 33c h - - 48 reserved 49 338 h - - 49 reserved 50 334 h - - 50 reserved 51 330 h - - 51 reserved 52 32c h - - 52 reserved 53 328 h - - 53 reserved 54 324 h - - 54 reserved 55 320 h - - 55 reserved 56 31c h - - 56 reserved 57 318 h - - 57 reserved 58 314 h - - 58 reserved 59 310 h rlt1 yes 59 reload timer 1 60 30c h rlt2 yes 60 reload timer 2 61 308 h - - 61 reserved 62 304 h - - 62 reserved 63 300 h - - 63 reserved 64 2fc h rlt6 yes 64 reload timer 6 65 2f8 h icu0 yes 65 input capture unit 0 66 2f4 h icu1 yes 66 input capture unit 1 67 2f0 h - - 67 reserved 68 2ec h - - 68 reserved 69 2e8 h icu4 yes 69 input capture unit 4 70 2e4 h icu5 yes 70 input capture unit 5 71 2e0 h - - 71 reserved 72 2dc h - - 72 reserved 73 2d8 h - - 73 reserved 74 2d4 h - - 74 reserved 75 2d0 h - - 75 reserved 76 2cc h - - 76 reserved 77 2c8 h - - 77 reserved 78 2c4 h - - 78 r eserved 79 2c0 h - - 79 reserved 80 2bc h - - 80 reserved
document number: 002 - 04705 rev.*a page 26 of 68 mb96680 series vector number offset in vector table vector name cleared by dma index in icr to program description 81 2b8 h - - 81 reserved 82 2b4 h - - 82 reserved 83 2b0 h - - 83 reserved 84 2ac h - - 84 rese rved 85 2a8 h - - 85 reserved 86 2a4 h - - 86 reserved 87 2a0 h - - 87 reserved 88 29c h - - 88 reserved 89 298 h frt0 yes 89 free - running timer 0 90 294 h frt1 yes 90 free - running timer 1 91 290 h - - 91 reserved 92 28c h - - 92 reserved 93 288 h rtc0 no 93 real time clock 94 284 h cal0 no 94 clock calibration unit 95 280 h sg0 no 95 sound generator 0 96 27c h iic0 yes 96 i 2 c interface 0 97 278 h - - 97 reserved 98 274 h adc0 yes 98 a/d converter 0 99 270 h - - 99 reserved 100 26c h - - 100 reserved 101 2 68 h linr0 yes 101 lin usart 0 rx 102 264 h lint0 yes 102 lin usart 0 tx 103 260 h linr1 yes 103 lin usart 1 rx 104 25c h lint1 yes 104 lin usart 1 tx 105 258 h - - 105 reserved 106 254 h - - 106 reserved 107 250 h - - 107 reserved 108 24c h - - 108 reserve d 109 248 h - - 109 reserved 110 244 h - - 110 reserved 111 240 h - - 111 reserved 112 23c h - - 112 reserved 113 238 h - - 113 reserved 114 234 h - - 114 reserved 115 230 h - - 115 reserved 116 22c h - - 116 reserved 117 228 h - - 117 reserved 118 224 h - - 118 reserved 119 220 h - - 119 reserved 120 21c h - - 120 reserved
document number: 002 - 04705 rev.*a page 27 of 68 mb96680 series vector number offset in vector table vector name cleared by dma index in icr to program description 121 218 h - - 121 reserved 122 214 h - - 122 reserved 123 210 h - - 123 reserved 1 24 20c h - - 124 reserved 125 208 h - - 125 reserved 126 204 h - - 126 reserved 127 200 h - - 127 reserved 128 1fc h - - 128 reserved 129 1f8 h - - 129 reserved 130 1f4 h - - 130 reserved 131 1f0 h - - 131 reserved 132 1ec h - - 132 reserved 133 1e8 h flash a yes 133 flash memory a interrupt 134 1e4 h - - 134 reserved 135 1e0 h - - 135 reserved 136 1dc h - - 136 reserved 137 1d8 h - - 137 reserved 138 1d4 h - - 138 reserved 139 1d0 h adcrc0 no 139 a/d converter 0 - range comparator 140 1cc h adcpd0 no 140 a/d converter 0 - pulse detection 141 1c8 h - - 141 reserved 142 1c4 h - - 142 reserved 143 1c0 h - - 143 reserved
document number: 002 - 04705 rev.*a page 28 of 68 mb96680 series 12. handling precautions any semiconductor devices have inherently a certain rate of failure. the possibility of failure is gre atly affected by the conditions in which they are used (circuit conditions, environmental conditions, etc.). this page describes precautions that must be observ ed to minimize the chance of failure and to obtain higher reliability from your cypress semicond uctor devices. 12.1 precautions for product design this section describes precautions when designing electronic equipment using semiconductor devices. ? absolute maximum ratings semiconductor devices can be permanently damaged by application of stress (voltage, c urrent, temperature, etc.) in excess of certain established limits, called absolute maximum ratings. do not exceed these ratings. ? recommended operating conditions recommended operating conditions are normal operating ranges for the semiconductor device. al l the device's electrical characteristics are warranted when operated within these ranges. always use semiconductor devices within the recommended operating conditions. operation outside these ranges may adversely affect reliability and could result in dev ice failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their sales representative beforehand. ? proces sing and protection of pins these precautions must be followed when handling the pins which connect semiconductor devices to power supply and input/outpu t functions. 1. preventing over - voltage and over - current conditions exposure to voltage or current levels in excess of maximum ratings at any pin is likely to cause deterioration within the device, and in extreme cases leads to permanent damage of the device. try to prevent such overvoltage or over - current conditions at the design stage. 2. protection of output p ins shorting of output pins to supply pins or other output pins, or connection to large capacitance can cause large current flows . such conditions if present for extended periods of time can damage the device. therefore, avoid this type of connection. 3. hand ling of unused input pins unconnected input pins with very high impedance levels can adversely affect stability of operation. such pins should be connected through an appropriate resistance to a power supply pin or ground pin. ? latch - up semiconductor device s are constructed by the formation of p - type and n - type areas on a substrate. when subjected to abnormally high voltages, internal parasitic pnpn junctions (called thyristor structures) may be formed, causing large current levels in excess of several hundr ed ma to flow continuously at the power supply pin. this condition is called latch - up. caution: the occurrence of latch - up not only causes loss of reliability in the semiconductor device, but can cause injury or damage from high heat, smoke or flame. to pr event this from happening, do the following: 1. be sure that voltages applied to pins do not exceed the absolute maximum ratings. this should include attention to abnormal noise, surge levels, etc. 2. be sure that abnormal current flows do not occur during the p ower - on sequence. ? observance of safety regulations and standards most countries in the world have established standards and regulations regarding safety, protection from electromagnetic interference, etc. customers are requested to observe applicable regu lations and standards in the design of products. ? fail - safe design any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from suc h failures by incorporating safety design measures into your faci lity and equipment such as redundancy, fire protection, and prevention of over - current levels and other abnormal operating conditions.
document number: 002 - 04705 rev.*a page 29 of 68 mb96680 series ? precautions related to usage of devices cypress semiconductor devices are intended for use in standard applications (co mputers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal ope ration may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (s uch as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devi ces for life support, etc.) are requested to consult with sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 12.2 precautions for package mounting package mounting may be either lead insertion type or surface mount type. in either case, for heat resistance during soldering, you should only mount under cypress 's recommended conditions. for detailed information about mount conditions, contact your sales representative. ? lead insertio n type mounting of lead insertion type packages onto printed circuit boards may be done by two methods: direct soldering on the boar d, or mounting by using a socket. direct mounting onto boards normally involves processes for inserting leads into through - h oles on the board and using the flow soldering (wave soldering) method of applying liquid solder. in this case, the soldering process usually causes leads to be s ubjected to thermal stress in excess of the absolute ratings for storage temperature. mounting processes should conform to cypress recommended mounting conditions. if socket mounting is used, differences in surface treatment of the socket contacts and ic lead surfaces can lead to contact deterioration after long periods. for this reason it is recom mended that the surface treatment of socket contacts and ic leads be verified before mounting. ? surface mount type surface mount packaging has longer and thinner leads than lead - insertion packaging, and therefore leads are more easily deformed or bent. the use of packages with higher pin counts and narrower pin pitch results in increased susceptibility to open connections caused by deformed pins, or shorting due to solder bridges. you must use appropriate mounting techniques. cypress recommends the solder re flow method, and has established a ranking of mounting conditions for each product. users are advised to mount packages in accordance with cypress ranking of recommended conditions. ? lead - free packaging caution: when ball grid array (bga) packages with sn - a g - cu balls are mounted using sn - pb eutectic soldering, junction strength may be reduced under some conditions of use. ? storage of semiconductor devices because plastic chip packages are formed from plastic resins, exposure to natural environmental condition s will cause absorption of moisture. during mounting, the application of heat to a package that has absorbed moisture can cause surfaces to peel, reduci ng moisture resistance and causing packages to crack. to prevent, do the following: 1. avoid exposure to ra pid temperature changes, which cause moisture to condense inside the product. store products in locations where temperature changes are slight. 2. use dry boxes for product storage. products should be stored below 70% relative humidity, and at temperatures be tween 5 c and 30 c . when you open dry package that recommends humidity 40% to 70% relative humidity. 3. when necessary, cypress packages semiconductor devices in highly moisture - resistant aluminum laminate bags, with a silica gel desiccant. devices should be sealed in their aluminum laminate bags for storage. 4. avoid storing packages where they are exposed to corrosive gases or high levels of dust. ? baking packages that have absorbed moisture may be de - moisturized by baking (heat drying). follow the cypress reco mmended conditions for baking. condition: 125 c /24 h
document number: 002 - 04705 rev.*a page 30 of 68 mb96680 series ? static electricity because semiconductor devices are particularly susceptible to damage by static electricity, you must take the following preca utions: 1. maintain relative humidity in the working environ ment between 40% and 70%. use of an apparatus for ion generation may be needed to remove electricity. 2. electrically ground all conveyors, solder vessels, soldering irons and peripheral equipment. 3. eliminate static body electricity by the use of rings or brac elets connected to ground through high resistance (on the level of 1 m ). wearing of conductive clothing and shoes, use of conductive floor mats and other measures to minimize shock loads is recommended. 4. ground all fixtures and instruments, or protect wit h anti - static measures. 5. avoid the use of styrofoam or other highly static - prone materials for storage of completed board assemblies. 12.3 precautions for use environment reliability of semiconductor devices depends on ambient temperature and other conditions a s described above. for reliable performance, do the following: 1. humidity prolonged use in high humidity can lead to leakage in devices as well as printed circuit boards. if high humidity levels are anticipated, consider anti - humidity processing. 2. discharge o f static electricity when high - voltage charges exist close to semiconductor devices, discharges can cause abnormal operation. in such cases, use anti - static measures or processing to prevent discharges. 3. corrosive gases, dust, or oil exposure to corrosive g ases or contact with dust or oil may lead to chemical reactions that will adversely affect the device. if you use devices in such conditions, consider ways to prevent such exposure or to protect the devices. 4. radiation, including cosmic radiation most devic es are not designed for environments involving exposure to radiation or cosmic radiation. users should provide shielding as appropriate. 5. smoke, flame caution: plastic molded devices are flammable, and therefore should not be used near combustible subst ances. if devices begin to smoke or burn, there is danger of the release of toxic gases. customers considering the use of cypress products in other special environmental conditions should consult with sales representatives.
document number: 002 - 04705 rev.*a page 31 of 68 mb96680 series 13. handling devices spe cial care is required for the following when handling the device: ? latch - up prevention ? unused pins handling ? external clock usage ? notes on pll clock mode operation ? power supply pins ( v cc /v ss ) ? crystal oscillator and ceramic resonator circuit ? turn on sequence of power supply to a/d converter and analog inputs ? pin handling when not using the a/d converter ? notes on power - on ? stabilization of power supply voltage ? smc power supply pins ? serial communication ? mode pin (md) 13.1 latch - up prevention cmos ic chips may suffer l atch - up under the following conditions: ? a voltage higher than v cc or lower than v ss is applied to an input or output pin. ? a voltage higher than the rated voltage is applied between v cc pins and v ss pins. ? the av cc power supply is applied before the v cc volt age. latch - up may increase the power supply current dramatically, causing thermal damages to the device. for the same reason, extra care is required to not let the analog power - supply voltage (av cc , avrh) exceed the digital power - supply voltage. 13.2 unused pi ns handling unused input pins can be left open when the input is disabled (corresponding bit of port input enable register pier = 0). leaving unused input pins open when the input is enabled may result in misbehavior and possible permanent damage of the de vice. to prevent latch - up, they must therefore be pulled up or pulled down through resistors which should be more than 2 k ? . unused bidirectional pins can be set either to the output state and be then left open, or to the input state with either input disabled or external pull - up/pull - down resistor as described above. 13.3 external clock usage the permitted frequency range of an e xternal clock depends on the oscillator type and configuration. see ac characteristics for detailed modes and frequency limits. single and opposite phase external clocks must be connected as follows: 13.3.1 single phase external clock fo r main oscillator when using a single phase external clock for the main oscillator, x0 pin must be driven and x1 pin left open. and supply 1.8v power to the external clock. x0 x1
document number: 002 - 04705 rev.*a page 32 of 68 mb96680 series 13.3.2 single phase external clock for sub oscillator when using a single phase ext ernal clock for the s ub oscillator, external clock mode must be selected and x0a/p04_0 pin must be driven. x1a/p04_1 pin can be configured as gpio. 13.3.3 opposite phase external clock when using an opposite phase external clock, x1 (x1a) pin s must be supplied with a clock signal which has the opposite phase to the x0 (x0a) pins. supply level on x0 and x1 pins must be 1.8v. 13.4 notes on pll clock mode operation if the m icrocont r oller is operated with pll clock mode and no external oscillator is operating or no e xternal clock is supplied, the microcontroller attempts to work with the free oscillating pll. performance of this operation, however, cannot be guaranteed. 13.5 power supply pins ( v cc /v ss ) it is required that all v cc - level as well as all v ss - level power supp ly pins are at the same potential. if there is more than one v cc or v ss level, the device may operate incorrectly or be damaged even within the guaranteed operating range. v cc and v ss pins must be connected to the device from the power supply with lowest p ossible impedance. the smoothing capacitor at v cc pin must use the one of a capacit y value that is larger than cs. besides this, as a measure against power supply noise, it is required to connect a bypass capacitor of about 0. 1 ? f between v cc and v ss pins a s close as possible to v cc and v ss pins. 13.6 crystal oscillator and ceramic resonator circuit noise at x0, x1 pins or x0a, x1a pins might cause abnormal operation. it is required to provide bypass capacitors with shortest possible distance to x0, x1 pins and x0a, x1a pins, crystal oscillator (or ceramic resonator) and ground lines, and, to the utmost effort, that the lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board art work surro unding x0, x1 pins and x0a, x1a pins with a ground area for stabilizing the operation. it is highly recommended to evaluate the quartz/mcu or resonator/mcu system at the quartz or resonator manufacturer, especial ly when using low - q resonators at higher fre quencies. 13.7 turn on sequence of power supply to a/d converter and analog inputs it is required to turn the a/d converter power supply (av cc , avrh) and analog inputs (ann) on after turning the digital power supply (v cc ) on. it is also required to turn the di gital power off after turning the a/d converter supply and analog inputs off. in this case, avrh must not exceed av cc . input voltage for ports shared with analog input ports also must not exceed av cc (turning the analog and digital power supplies simultan eously on or off is acceptable). x0 x1
document number: 002 - 04705 rev.*a page 33 of 68 mb96680 series 13.8 pin handling w hen not using the a/d converter if the a/d converter is not used, the power supply pins for a/d converter should be connected such as av cc = v cc , av ss = avrh = v ss . 13.9 notes on power - on to prevent malfunction of the internal voltage regulator, supply voltage profile while turning the power supply on should be slower than 50 ? s from 0.2v to 2.7v. 13.10 stabilization of power supply voltage if the power supply voltage varies acutely even within the operation safety ra nge of the v cc power supply voltage, a malfunction may occur. the v cc power supply voltage must therefore be stabilized. as stabilization guidelines, the power supply voltage must be stabilized in such a way that v cc ripple fluctuations (peak to peak value ) in the commercial frequencies (5 0 hz to 6 0 hz) fall within 10% of the standard v cc power supply voltage and the transient fluctuation rate becomes 0.1v/ ? s or less in instantaneous fluctuation for power supply switching. 13.11 smc power supply pins all dvcc /dvss pins must be set to the same level as the vcc /vss pins. note that the smc i/o pin state is undefined if dv cc is powered on and v cc is below 3v. to av oid this, v cc must always be powered on before dv cc . dv cc /dv ss must be applied when using smc i/o pin as gpio. 13.12 serial communication there is a possibility to receive wrong data due to noise or other causes on the serial communication. therefore, design a printed circuit board so as to avoid noise. consider receiving of wrong data when designing the system. for example apply a checksum and retransmit the data if an error occurs. 13.13 mode pin (md) connect the mode pin directly to v cc or v ss pin . to prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pin to v cc or v ss pin and provide a low - impedance connection.
document number: 002 - 04705 rev.*a page 34 of 68 mb96680 series 14. electrical characteristics 14.1 absolute maximum ratings parame ter symbol condition rating unit remarks min max power supply voltage* 1 v cc - v ss - 0.3 v ss + 6.0 v analog power supply voltage* 1 av cc - v ss - 0.3 v ss + 6.0 v v cc = av cc * 2 analog reference voltage* 1 avrh - v ss - 0.3 v ss + 6.0 v av cc avrh, avrh av ss smc power supply* 1 dv cc - v ss - 0.3 v ss + 6.0 v v cc = av cc = dv cc *2 lcd power supply voltage* 1 v0 to v3 - v ss - 0.3 v ss + 6.0 v v0 to v3 must not exceed v cc input voltage* 1 v i - v ss - 0.3 v ss + 6.0 v v i (d)v cc + 0.3v* 3 output volt age* 1 v o - v ss - 0.3 v ss + 6.0 v v o (d)v cc + 0.3v* 3 maximum clamp current i clamp - - 4.0 +4.0 ma applicable to general purpose i/o pins * 4 total maximum clamp current |i clamp | - - 21 ma applicable to general purpose i/o pins * 4 "l" level maximum outpu t current i ol - - 15 ma normal port i olsmc t a = - 40c - 52 ma high current port t a = +25c - 39 ma t a = +85c - 32 ma t a = +105c - 30 ma "l" level average output current i olav - - 4 ma normal port i olavsmc t a = - 40c - 40 ma high current port t a = +25c - 30 ma t a = +85c - 25 ma t a = +105c - 23 ma "l" level maximum overall output current i ol - - 46 ma normal port i olsmc - - 180 ma high current port "l" level average overall output current i olav - - 23 ma normal port i olavsmc - - 90 ma high current port "h" level maximum output current i oh - - - 15 ma normal port i ohsmc t a = - 40c - - 52 ma high current port t a = +25c - - 39 ma t a = +85c - - 32 ma t a = +105c - - 30 ma "h" level average output current i ohav - - - 4 ma normal port i ohavsmc t a = - 40c - - 40 ma high current port t a = +25c - - 30 ma t a = +85c - - 25 ma t a = +105c - - 23 ma "h" level maximum overall output current i oh - - - 46 ma normal port i ohsmc - - - 180 ma high current port "h" level average overall output current i ohav - - - 23 ma normal port i ohavsmc - - - 90 ma high current port power consumption* 5 p d t a = +105c - 317 *6 mw operating ambient temperatu re t a - - 40 +105 c storage temperature t stg - - 55 +150 c
document number: 002 - 04705 rev.*a page 35 of 68 mb96680 series *1: this parameter is based on v ss = av ss = dv ss = 0v. *2: av cc and v cc and d vcc must be set to the same voltage. it is required that avcc does not exceed v cc , dv cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3: v i and v o should not exceed v cc + 0.3v. vi should also not exceed the specified ratings. however if the maximum current to/from an input is limited by some means with externa l components, the iclamp rating supersedes the vi rating. input/ o utput voltages of high current ports depend on dv cc . input/ o utput voltages of standard ports depend on v cc . *4 : ? applicable to all general purpose i/o pins (pnn_m). ? use within recommended operating conditions. ? use at dc voltage (current) . ? the +b signal should always be applied a limiting resistance placed between the +b signal and the m icrocontroller . ? the v alue of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass throu gh the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontroller power supply is off (not fixed at 0v), the power supply is provided from the pins, so that inc omplete operation may result. ? note that if the +b input is applied during power - on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power reset. ? the debug i/f pin has only a protective diode against v ss . hence it is only permitted to input a negative clamping current (4ma). for protection against positive input voltages, use an external clamping diode which limits the input voltage to maximum 6. 0 v. ? sample recommended circuits: *5: the m aximum permitted power dissipation depends on the ambient temperature, the air flow velocity and the thermal conductance of the package on the pcb. the actual power dissipation depends on the customer application and can be calculated as follows: pd = p io + p int pio = (v ol ? i ol + v oh ? i oh ) (i/o load power dissipation, sum is performed on all i/o ports) p int = v cc ? (i cc + i a ) (internal power dissipation) i cc is the total core current consumption into v cc as described in the dc characteristics and depen ds on the selected operation mode and clock frequency and the usage of functions like flash programming. i a is the analog current consumption into av cc . *6: worst case value for a package mounted on single layer pcb at specified t a without air flow. warning semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. v cc r +b input (0v to 16v) limiting resistance protective diode p-ch n-ch
document number: 002 - 04705 rev.*a page 36 of 68 mb96680 series 14.2 recommended operating conditions (v ss = av ss = dv ss = 0v) paramet er symbol value unit remarks min typ max power supply voltage v cc , av cc , dv cc 2.7 - 5.5 v 2.0 - 5.5 v maintains ram data in stop mode smoothing capacitor at c pin c s 0.5 1.0 to 3.9 4.7 f 1.0f (allowance within 50%) 3.9f (allowance within 20%) please use the ceramic capacitor or the capacitor of the frequency response of this level. the smoothing capacitor at v cc must use the one of a capacity value that is larger than c s . warning the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditio ns, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand.
document number: 002 - 04705 rev.*a page 37 of 68 mb96680 series 14.3 dc characteristics 14.3.1 current r ating (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions v alue unit remarks min typ max power supply current in run modes *1 i ccpll v cc pll run mode with clks1/2 = clkb = clkp1/2 = 32mhz flash 0 wait (clkrc and clksc stopped) - 25 - ma t a = +25 c - - 34 ma t a = +105 c i ccmain main run mode with c lks1/2 = clkb = clkp1/2 = 4mhz flash 0 wait (clkpll, clksc and clkrc stopped) - 3.5 - ma t a = +25 c - - 7.5 ma t a = +105 c i ccrch rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 2mhz flash 0 wait (clkmc, clkpll and clksc stopped) - 1.7 - ma t a = +25 c - - 5.5 ma t a = +105 c i ccrcl rc run mode with clks1/2 = clkb = clkp1/2 = clkrc = 100khz flash 0 wait (clkmc, clkpll and clksc stopped) - 0.15 - ma t a = +25 c - - 3.2 ma t a = +105 c i ccsub sub run mode with clks1/2 = clkb = cl kp1/2 = 32khz flash 0 wait (clkmc, clkpll and clkrc stopped) - 0.1 - ma t a = +25 c - - 3 ma t a = +105 c
document number: 002 - 04705 rev.*a page 38 of 68 mb96680 series parameter symbol pin name conditions value unit remarks min typ max power supply current in sleep modes *1 i ccspll v cc pll sleep mode with clks1/2 = clkp1/2 = 32mhz (clkrc and clksc stopped) - 6.5 - ma t a = +25 c - - 13 ma t a = +105 c i ccsmain main sleep mode with clks1/2 = clkp1/2 = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 0.9 - ma t a = +25 c - - 4 ma t a = + 105 c i ccsrch rc sleep mode with clks1/2 = clkp1/2 = clkrc = 2mhz, smcr:lpmss = 0 (clkmc, clkpll and clksc stopped) - 0.5 - ma t a = +25 c - - 3.5 ma t a = +105 c i ccsrcl rc sleep mode with clks1/2 = clkp1/2 = clkrc = 100khz (clkmc, clkpll and clk sc stopped) - 0.06 - ma t a = +25 c - - 2.7 ma t a = +105 c i ccssub sub sleep mode with clks1/2 = clkp1/2 = 32khz, (clkmc, clkpll and clkrc stopped) - 0.04 - ma t a = +25 c - - 2.5 ma t a = +105 c
document number: 002 - 04705 rev.*a page 39 of 68 mb96680 series parameter symbol pin name conditions value uni t remarks min t yp max power supply current in timer modes *2 i cctpll v cc pll timer mode with clkpll = 32mhz (clkrc and clksc stopped) - 1800 2245 ? a t a = +25 c - - 3140 ? a t a = +105 c i cctmain main timer mode with clkmc = 4mhz, smcr:lpmss = 0 (clkpll, clkrc and clksc stopped) - 285 325 ? a t a = +25 c - - 1055 ? a t a = +105 c i cctrch rc timer mode with clkrc = 2mhz, smcr:lpmss = 0 (clkpll, clkmc and clksc stopped) - 160 210 ? a t a = +25 c - - 970 ? a t a = +105 c i cctrcl rc timer mo de with clkrc = 100khz (clkpll, clkmc and clksc stopped) - 30 70 ? a t a = +25 c - - 820 ? a t a = +105 c i cctsub sub timer mode with clksc = 32khz (clkmc, clkpll and clkrc stopped) - 25 55 ? a t a = +25 c - - 800 ? a t a = +105 c
document number: 002 - 04705 rev.*a page 40 of 68 mb96680 series parameter symbol pin name conditions value unit remarks min typ max power supply current in stop mode *3 i cch vcc - - 20 55 ? a t a = + 25 c - - 800 ? a t a = + 105 c flash power down current i cc flashpd vcc - - 36 70 ? a ? power supply current for active low voltage detector* 4 i cclvd vcc low voltage detector enabled - 5 - ? a ? t a = + 25 c - - 12.5 ? a ? t a = + 105 c flash write/ erase current* 5 i ccflash vcc - - 12.5 - ma ? t a = + 25 c - - 20 ma ? t a = + 105 c *1: the power supply current is measured with a 4mhz exte rnal clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. see chapter standby mode and voltage regulator control circuit of the hardware manual for further details about voltage regulator control. curre nt for "on chip debugger" part is not included. power supply current in run mode does not include flash write / erase current. *2: the power supply current in timer mode is the value when flash is in power - down / reset mode. when flash is not in powe r - down / reset mode, i ccflashpd must be added to the power supply current. the power supply current is measured with a 4mhz external clock connected to the main oscillator and a 32khz external clock connected to the sub oscillator. the current for "o n chip debugger" part is not included. *3: the power supply current in stop mode is the value when flash is in power - down / reset mode. when flash is not in power - down / reset mode , i ccflashpd must be added to the power supply current. *4: when low volt age detector is enabled, i cclvd must be added to power supply current. *5: when flash write / erase program is executed, i ccflash must be added to power supply current.
document number: 002 - 04705 rev.*a page 41 of 68 mb96680 series 14.3.2 pin characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max "h" level input voltage v ih port inputs pnn_m - v cc ? cc + 0.3 v cmos hysteresis input - v cc ? cc + 0.3 v automotive hysteresis input v ihx0s x0 external clock in " fast clock input mode " vd ? ihx0as x0a external clock in " oscillation mode " v cc ? cc + 0.3 v v ihr rstx - v cc ? cc + 0.3 v cmos hysteresis input v ihm md - v cc - 0.3 - v cc + 0.3 v cmos hysteresis input v ihd debug i/f - 2.0 - v cc + 0.3 v ttl input "l" level input voltage v il port inputs pnn_m - v ss - 0.3 - v cc ? ss - 0.3 - v cc ? ilx0s x0 external clock in " fast clock input mode " v ss - vd ? ilx0as x0a external clock in " oscillation mode " v ss - 0.3 - v cc ? ilr rstx - v ss - 0.3 - v cc ? ilm md - v ss - 0.3 - v ss + 0.3 v cmos hysteresis input v ild debug i/f - v ss - 0.3 - 0.8 v ttl input
document number: 002 - 04705 rev.*a page 42 of 68 mb96680 series parameter symbol pin name conditions value unit remarks min typ max "h" level output voltage v oh4 4ma type 4.5v (d)v cc 5.5v i oh = - 4ma (d)v cc - 0.5 - (d)v cc v 2.7v (d)v cc < 4.5v i oh = - 1.5ma v oh30 high drive type * 4.5v dv cc 5.5v i oh = - 52ma dv cc - 0.5 - dv cc v t a = - 40 c 2.7v dv cc < 4.5v i oh = - 18ma 4.5v dv cc 5.5v i oh = - 39ma t a = +25 c 2.7v dv cc < 4.5v i oh = - 16ma 4.5v dv cc 5.5v i oh = - 32ma t a = +85 c 2.7v dv cc < 4.5v i oh = - 14.5ma 4.5v dv cc 5.5v i oh = - 30ma t a = +105 c 2.7v dv cc < 4.5v i oh = - 14ma v oh3 3ma t ype 4.5v v cc 5.5v i oh = - 3ma v cc - 0.5 - v cc v 2.7v v cc < 4.5v i oh = - 1.5ma "l" level output voltage v ol4 4ma type 4.5v (d)v cc 5.5v i ol = +4ma - - 0.4 v 2.7v (d)v cc < 4.5v i ol = +1.7ma v ol30 high drive type * 4.5v dv cc 5.5v i ol = +52ma - - 0.5 v t a = - 40 c 2.7v dv cc < 4.5v i ol = +22ma 4.5v dv cc 5.5v i ol = +39ma t a = +25 c 2.7v dv cc < 4.5v i ol = +18ma 4.5v dv cc 5.5v i ol = +32ma t a = +85 c 2.7v d v cc < 4.5v i ol = +14ma 4.5v d v cc 5.5v i ol = +30ma t a = +105 c 2.7v d v cc < 4.5v i ol = +13.5ma v ol3 3ma type 2.7v v cc < 5.5v i ol = +3ma - - 0.4 v v old debug i/f v cc = 2.7v i ol = +25ma 0 - 0.25 v
document number: 002 - 04705 rev.*a page 43 of 68 mb96680 series parameter symbol pin name conditions value unit remarks min typ max input leak current i il pnn_m v ss < v i < v cc av ss < v i < a v cc , avrh - 1 - + 1 ? a single port pin except high current output i/o for smc p08_m dv ss < v i < d v cc av ss < v i < a v cc , avrh - 3 - + 3 ? a total lcd leak current |i il cd | all seg/ com pin v cc = 5.0v - 0.5 10 ? a maximum leakage current of all lcd pins internal lcd divide resistance r lcd between v3 and v2, v2 and v1, v1 and v0 v cc = 5.0v 6.25 12.5 25 k ? pull - up resistance value r pu pnn_m v cc = 5.0v 10% 25 50 100 k ? pull - down resistance value r down p08_m v cc = 5.0v 10% 25 50 100 k ? input capacitance c in other than c, vcc, vss, dvcc dvss, avcc, avss, avrh, p08_m - - 5 15 pf p08_m - - 15 30 pf *: in the case of driving stepping motor directly or high current ou tputs, set "1" to the bit in the port high drive register (phdrnn:hdx="1").
document number: 002 - 04705 rev.*a page 44 of 68 mb96680 series 14.4 ac characteristics 14.4.1 main clock input characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, vd=1.8v0.15v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min typ max input frequency f c x0, x1 4 - 8 mhz when using a crystal oscillator, pll off - - 8 mhz when using an opposite phase external clock, pll off 4 - 8 mhz when using a crystal oscillator or opposite phase external c lock, pll on input frequency f fci x0 - - 8 mhz when using a single phase external clock in fast clock input mode, pll off clock in fast clock input mode, pll on cylh - 125 - - ns i nput clock pulse width p wh , p wl - 55 - - ns
document number: 002 - 04705 rev.*a page 45 of 68 mb96680 series 14.4.2 sub clock input characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name conditions value unit remarks min typ max input frequ ency f cl x0a, x1a - - 32.768 - khz when using an oscillation circuit - - - 100 khz when using an opposite phase external clock x0a - - - 50 khz when using a single phase external clock input clock cycle t cyll - - 10 - - ? s input clock pulse width - - p wh /t cyll , p wl /t cyll 30 - 70 %
document number: 002 - 04705 rev.*a page 46 of 68 mb96680 series 14.4.3 built - in rc oscillation characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit remarks min typ max clock frequency f rc 50 100 200 khz when using slow frequency of rc oscillator 1 2 4 mhz when using fast frequency of rc oscillator rc clock stabilization time t rcstab 80 160 320 ? ? 14.4.4 internal clock timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit min max internal system clock frequency (clks1 and clks2) f clk s1 , f clks2 - 54 mhz internal cpu clock frequency (clkb), internal peripheral clock frequency (clkp1) f clkb , f clkp1 - 32 mh z internal peripheral clock frequency (clkp2) f clkp2 - 32 mh z
document number: 002 - 04705 rev.*a page 47 of 68 mb96680 series 14.4.5 operating conditions of pll (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol value unit remarks min typ max pll oscillation stabilization wait time t lock 1 - 4 ms for clkmc = 4mhz pll input clock frequency f plli 4 - 8 mhz pll oscillation clock frequency f clkvc o 56 - 108 mhz permitted vco output frequency of pll (clkvco) pll phase jitter t pskew - 5 - +5 ns for clkmc (pll input clock) 4mhz 14.4.6 reset input (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit min max reset input time t rstl rstx 10 - ? ? rstx 0.2v cc 0.2v cc t rstl
document number: 002 - 04705 rev.*a page 48 of 68 mb96680 series 14.4.7 power - on reset timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit min typ max power on rise time t r v cc 0.05 - 30 ms power off time t off v cc 1 - - ms
document number: 002 - 04705 rev.*a page 49 of 68 mb96680 series 14.4.8 usart timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c, c l =50pf) parameter symbol pin name conditions 4.5v ? v cc ?? 5.5v 2.7v ? v cc ? 4.5v unit min max min max serial clock cycle time t scyc sckn inte rnal shift clock mode 4t clkp1 - 4t clkp1 - ns sck ? ? sot delay time t slovi sckn, sotn - 20 + 20 - 30 + 30 ns sot ? ? ovshi sckn, sotn n ? clkp1 C * - n ? clkp1 C * - ns sin ? ? ? ivshi sckn, sinn t clkp1 + 45 - t clkp1 + 55 - ns sck ? ? shixi sckn, sinn 0 - 0 - ns serial clock "l" pulse width t slsh sckn external shift clock mode t clkp1 + 10 - t clkp1 + 10 - ns serial clock "h" pulse width t shsl sckn t clkp1 + 10 - t clkp1 + 10 - ns sck ? ? slove sckn, sotn - 2t clkp1 + 45 - 2t clkp1 + 55 ns sin ? ? ivshe sckn, sinn t clkp1 /2 + 10 - t clkp1 /2 + 10 - ns sck ? ? shixe sckn, sinn t clkp1 + 10 - t clkp1 + 10 - ns sck fall time t f sckn - 20 - 20 ns sck rise time t r sckn - 20 - 20 ns notes: ? ac characteristic in clk synchronized mode. ? c l is the load capacity value of pins when testing. ? depending on the used machine clock frequency, the maximum possible baud rate can be limited by some parameters. these parameters are shown in mb96 600 series hardware manual . ? tclkp1 indicates the peripheral clock 1 (clkp1), unit: ns ? these characteristics only guarantee the same relocate port number. for example, the combination of sckn and sotn_r is not guaranteed. *: parameter n depends on t scyc and can be calculated as follows: ? if t scyc = 2 ? k ? t clkp1 , then n = k, where k is an integer > 2 ? if t scyc = (2 ? k + 1) ? t clkp1 , then n = k + 1, where k is an intege r > 1
document number: 002 - 04705 rev.*a page 50 of 68 mb96680 series examples: t scyc n 4 ? t clkp1 2 5 ? t clkp1 , 6 ? t clkp1 3 7 ? t clkp1 , 8 ? t clkp1 4 ... ... t scyc v ol v ol v oh v oh v ih v ih v il v il t slovi t ivshi t shixi v ol sck sot sin internal shift clock mode t ovshi t slsh v ih v ih v ih v ih v il v ih v il v il v il v ol v oh t slove t r t shixe t ivshe t f sck sot sin t shsl external shift clock mode
document number: 002 - 04705 rev.*a page 51 of 68 mb96680 series 14.4.9 external input timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min max input pulse width t inh , t inl pnn_m 2 t clkp1 +200 (t clkp1 = 1/f clkp1 )* - ns general purpose i/o adtg a/d converter trigger input tinn, tinn_r reload timer ttgn ppg trigger input frckn, frckn_r free - running timer input clock i nn, inn_r input capture intn, intn_r 200 - ns external interrupt nmi non - maskable interrupt *: t clkp1 indicates the peripheral clock1 (clkp1) cycle time except stop when in stop mode. v ih v il t inl t inh v il external input timing v ih
document number: 002 - 04705 rev.*a page 52 of 68 mb96680 series 14.4.10 i 2 c timing (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c ) parameter symbol conditions typical mode high - speed mode * 4 unit min max min max scl clock frequency f scl c l = 50pf, r = (vp/i ol )* 1 0 100 0 400 khz (repeated) start condition hold time sda ? ? scl ? hdsta 4.0 - 0.6 - ? l ow 4.7 - 1.3 - ? s scl clock " h " width t high 4.0 - 0.6 - ? s (repeated) start condition setup time scl ? ? sda ? susta 4.7 - 0.6 - ? s data hold time scl ? ? sda ? ? hddat 0 3.45* 2 0 0.9* 3 ? s data setup time sda ? ? ? scl ? sudat 250 - 100 - ns s top condition setup time scl ? ? sda ? susto 4.0 - 0.6 - ? s bus free time between "stop condition" and "start condition" t bus 4.7 - 1.3 - ? s pulse width of spikes which will be suppressed by input noise filter t sp - 0 (1 - 1.5) ??? clkp1 *5 0 (1 - 1.5) ?? clkp1 *5 ns *1: r and c l represent the pull - up resistance and load capacitance of the s cl and sda lines, respectively . vp indicates the power supply voltage of the pull - up resistance and i ol indicates v ol guaranteed current. *2: the maximum t hddat only has to be met if the device does not extend the "l" width (t low ) of the scl signal. *3: a high - speed mode i 2 c bus device can be used on a standard mode i 2 c bus system as long as the device satisfies the requirement of "t sudat 250ns". *4: for use at over 100 khz , set the peripheral clock1 (clkp1) to at least 6mhz. *5: t clkp1 indicates the peripheral clock1 (clkp1) cycle time. s da s c l t h d s t a t low t h ddat t s u dat t h i gh t s u s t a t h d s t a t s p t b us t s u s to
document number: 002 - 04705 rev.*a page 53 of 68 mb96680 series 14.5 a/d converter 14.5.1 electrical characteristics for the a/d converter (v cc = av cc = dv cc = 2.7v to 5. 5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol pin name value unit remarks min typ max resolution - - - - 10 bit total error - - - 3.0 - + 3.0 lsb nonlinearity error - - - 2.5 - + 2.5 lsb differential nonlinearity error - - - 1.9 - + 1.9 lsb zero transition voltage v ot ann typ - 20 av ss + 0.5lsb typ + 20 mv full scale transition voltage v fst ann typ - 20 avrh - 1.5lsb typ + 20 mv compare time * - - 1.0 - 5.0 ? 4.5v v cc 5.5v ? 2.7v v cc ? * - - 0.5 - - ? 4.5v v cc 5.5v ? 2.7v v cc ? 4.5v power supply current i a av cc - 2.0 3.1 ma a/d converter active i ah - - 3.3 ? ss ) i r avrh - 520 810 ? rh - - 1.0 ? vin an8 to 13 - - 15.5 pf normal outputs an16 to 23 - - 17.4 pf high current outputs anal og impedance r vin ann - - 1450 ? 4.5v av cc 5.5v ? 2.7v av cc < 4.5v analog port input current (during conversion) i ain an8 to 13 - 1.0 - + 1.0 ? ss ? ain ? cc , avrh an16 to 23 - 3.0 - + 3.0 ? ain ann av ss - avrh v reference voltage range - avrh av cc - 0.1 - av cc v variation between channels - ann - - 4.0 lsb *: time for each channel .
document number: 002 - 04705 rev.*a page 54 of 68 mb96680 series 14.5.2 accuracy and setting of the a/d converter sampling time if the external impedance is too high or the samplin g time too short, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting the a/d conversion precision. to satisfy the a/d conversion precision, a sufficient sampling time must be selected. the required sam pling time (t samp ) depends on the external driving impedance r ext , the board capacitance of the a/d converter input pin c ext and the av cc voltage level. the following replacement model can be used for the calculation: rext: external driving impedance cext: capacitance of pcb at a/d converter input c vin: analog input capacity (i/o, analog switch and adc are contained) r vin: analog input impedance (i/o, analog switch and adc are contained) the following approximation formula for the replacement model a bove can be used: t samp = 7.62 ? (r ext ? c ext + (r ext + r vin ) ? c vin ) ? do not select a sampling time below the absolute minimum permitted value . (0.5 ? s for 4.5v av cc 5.5v , 1.2 ? s for 2.7 v av cc < 4.5v) ? if the sampling time cannot be sufficient, connect a capacitor of about 0.1 ? f to the analog input pin. ? a big external driving impedance also adversely affects the a/d conversion precision due to the pin input leakage current iil (static current before the sampling switch) or the analog input leakage curren t iain (total leakage current of pin input and comparator during sampling). the effect of the pin input leakage current iil cannot be compensated by an external capacitor. ? the accuracy gets worse as |avrh - av ss | becomes smaller. sampling switch (d u r i n g s a m p l i n g : o n) c vin r vin analog i n put mcu r ext c ext source c o m p a r a t o r
document number: 002 - 04705 rev.*a page 55 of 68 mb96680 series 14.5.3 definition of a/d conve rter terms ? resolution : analog variation that is recognized by an a/d converter. ? nonlinearity error : deviation of the actual conversion characteristics from a straight line that connects the zero transition point (0b0000000000 0b0000000001) to the full - scale transition point (0b1111111110 0b1111111111). ? differential nonlinearity error: deviation from the ideal value of the input voltage that is required to c hange the output code by 1lsb. ? total error : difference between the actual value and the theoretical value. the total error includes zero transition error, full - scale transition error and nonlinearity er ror. ? zero transition voltage : input voltage which results in the minimum conversion value. ? full scale transition voltage: input voltage which results in the maximum conversion value. nonl inearity error of digital output n = v nt - {1lsb ? (n - 1) + v ot } [lsb] 1lsb differential non linearity error of digital output n = v (n + 1) t - v nt - 1 [lsb] 1lsb 1lsb = v fst - v ot 1022 n : a/d converter digital output value. v ot : voltage at which the digital output changes from 0x000 to 0 x001. v fst : voltage at which the digital output changes from 0x3fe to 0x3ff. v nt : voltage at which the digital output changes from 0x(n ? 1) to 0xn .
document number: 002 - 04705 rev.*a page 56 of 68 mb96680 series 1lsb (ideal value) = avrh - av ss [v] 1024 total error of digital output n = v nt - {1lsb ? ( n - 1) + 0.5lsb} 1lsb n : a/d converter digital output value. v nt : voltage at which the digital output changes from 0x(n + 1) to 0xn. v ot (ideal value) = av ss + 0.5lsb[v] v fst (ideal value) = avrh - 1.5lsb[v]
document number: 002 - 04705 rev.*a page 57 of 68 mb96680 series 14.6 high current output slew rate (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c ) parameter symbol pin name conditi o ns value unit remarks min typ max output rise/fall time t r30 , t f30 p08_m outputs driving strength set to "30ma" 15 - 75 ns c l =85pf v h v h voltage time v l v l v h =v ol30 +0.9 (v oh30 -v ol30 ) v l =v ol30 +0.1 (v oh30 -v ol30 ) t r30 t f30
document number: 002 - 04705 rev.*a page 58 of 68 mb96680 series 14.7 low voltage detection function characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter symbol conditions value unit min typ max detected voltage *1 v dl0 cilcr:lvl = 0000 b 2.70 2.90 3.10 v v dl1 cilcr:lvl = 0001 b 2.79 3.00 3.21 v v dl2 cilcr:lvl = 0010 b 2.98 3.20 3.42 v v dl3 cilcr:lvl = 0011 b 3.26 3.50 3.74 v v dl4 cilcr:lvl = 0100 b 3.45 3.70 3.95 v v dl5 cilcr:lvl = 0111 b 3.73 4.00 4.27 v v dl6 cilcr:lvl = 1001 b 3.91 4.20 4.49 v pow er supply voltage change rate *2 dv/dt - - 0.004 - + 0.004 v/ ? hys cilcr:lvhys=0 - - 50 mv cilcr:lvhys=1 80 100 120 mv stabilization time t lvdstab - - - 75 ? d - - - 30 ? d ), there is a possibility that the low voltage detection will occur or stop after the power supply voltage passes the detection range. *2 : in order to perform the low voltage detection at the detection voltage (v dlx ), be sure to suppress fluctuation of the power supply voltage within the limits of the change ration of power supply voltage.
document number: 002 - 04705 rev.*a page 59 of 68 mb96680 series t i m e v c c v dlx m i n v o l t a g e v dlx m a x d v d t d e t e c t e d v o l t a g e rcr: l v de lo w v o l t age detection function enab l e low voltage detection function disable s t ab ili z a t i on t i m e t l v d s t a b lo w v o l t age detection function enab l e
document number: 002 - 04705 rev.*a page 60 of 68 mb96680 series 14.8 flash memory write/erase characteristics (v cc = av cc = dv cc = 2.7v to 5.5v, v ss = av ss = dv ss = 0v, t a = - 40c to + 105c) parameter conditions value unit remarks min typ max sector erase time large sector - - 1.6 7.5 s includes write time prior to internal erase. small sector - - 0.4 2.1 s security sector - - 0.31 1.65 s w ord (16 - bit) write time - - 25 400 ? note: while the flash memory is written or erased, shutdown of the external power (v cc ) is p rohibited. in the application system where the external power (v cc ) might be shut down while writing or erasing, be sure to turn the power off by using a low voltage detection function . to put it concrete, change the external power in the range of change r ation of power supply voltage ( - 0.004v/ ? s to +0.004v/ ? s) after the external power falls below the detection voltage (v dlx ) *1 . write/erase cycles and data hold time write/erase cycles (cycle) data hold time (year) 1,000 20 *2 10,000 10 *2 100,000 5 *2 *1: see " 14.7 low voltage detection function characteristics " . * 2 : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into norm alized value at + 85 ? c ).
document number: 002 - 04705 rev.*a page 61 of 68 mb96680 series 15. example characteristics this characteristic is an actual value of the arbitrary sample. it is not the guaranteed value. ? mb96f685 0 . 0 1 0 . 1 0 1 . 0 0 1 0 . 0 0 1 0 0 . 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] r un m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 1 0 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s l eep m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v )
document number: 002 - 04705 rev.*a page 62 of 68 mb96680 series ? mb96f685 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 1 0 . 0 0 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] t i m e r m od e p ll c l o c k ( 32 m h z ) m a i n o s c . ( 4 m h z ) rc c l o c k ( 2 m h z ) rc c l o c k ( 100k h z ) s u b o s c . ( 32k h z ) ( v c c = 5 . 5 v ) 0 . 00 1 0 . 01 0 0 . 10 0 1 . 00 0 - 5 0 0 5 0 1 0 0 1 5 0 i c c [ m a ] t a [ o c] s t op m od e ( v c c = 5 . 5 v )
document number: 002 - 04705 rev.*a page 63 of 68 mb96680 series ? used setting mode selected source clock clock/regulator and flash settings run mode pll clks1 = clks2 = clkb = clkp1 = clkp2 = 32mhz main osc. clks1 = clks2 = clkb = clkp1 = clkp2 = 4mhz rc clock fast clks1 = clks2 = clkb = clkp1 = clkp2 = 2mhz rc clock slow clks1 = clks2 = clkb = clkp1 = clkp2 = 100khz sub osc. clks1 = clks 2 = clkb = clkp1 = clkp2 = 32khz sleep mode pll clks1 = clks2 = clkp1 = clkp2 = 32mhz regulator in high power mode, (clkb is stopped in this mode) main osc. clks1 = clks2 = clkp1 = clkp2 = 4mhz regulator in high power mode, (clkb is stopped in this mode ) rc clock fast clks1 = clks2 = clkp1 = clkp2 = 2mhz regulator in high power mode, (clkb is stopped in this mode) rc clock slow clks1 = clks2 = clkp1 = clkp2 = 100khz regulator in low power mode, (clkb is stopped in this mode) sub osc. clks1 = clks2 = clkp1 = clkp2 = 32khz regulator in low power mode, (clkb is stopped in this mode) timer mode pll clkmc = 4mhz, clkpll = 32mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode main osc. clkmc = 4mh z (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock fast clkmc = 2mhz (system clocks are stopped in this mode) regulator in high power mode, flash in power - down / reset mode rc clock slow c lkmc = 100khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode sub osc. clkmc = 32 khz (system clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode stop mode stopped (all clocks are stopped in this mode) regulator in low power mode, flash in power - down / reset mode
document number: 002 - 04705 rev.*a page 64 of 68 mb96680 series 16. ordering information mcu with can controller part number flash memory package * mb96f683rbpmc - gse1 flash a (96.5kb) 80 - pin plastic lqfp (fpt - 8 0p - m21) mb96f683rbpmc - gse2 mb96f6 8 5rbpmc - gse1 flash a (160.5kb) 80 - pin plastic lqfp (fpt - 80p - m21) mb96f6 8 5rbpmc - gse2 *: for details about package, see " package dimension ". mcu without can controller part number flash memo ry package * mb96f683abpmc - gse1 flash a (96.5kb) 80 - pin plastic lqfp (fpt - 80p - m21) mb96f683abpmc - gse2 mb96f685abpmc - gse1 flash a (160.5kb) 80 - pin plastic lqfp (fpt - 80p - m21) mb96f685abpmc - gse2 *: for details about package, see " package dimension ".
document number: 002 - 04705 rev.*a page 65 of 68 mb96680 series 17. package dimension 80-pin plastic lqfp lead pitch 0.50 mm pa ck age width pa ck age length 12 mm 12 mm lead shape gullwing sealing method plastic mold mounting height 1.70 mm ma x we ight 0.47 g code (reference ) p-lfqfp80-1 2 12-0.50 80-pin plastic lqfp (fpt-80p-m21) (fpt-80p-m21) c 2006-2010 fujitsu semiconductor limited f80035s-c-2-4 1 20 40 21 60 41 80 61 index 12.000.10(.472.004)sq 14.000.20(.551.008)sq 0.50(.020) 0.200.05 (.008.002) m 0.08(.003) 0.1450.055 (.006.002) 0.08(.003) "a" 0~8 .059 C.004 +.008 C0.10 +0.20 1.50 0.500.20 (.020.008) 0.600.15 (.024.006) 0.100.05 (.004.002) (stand off) 0.25(.010) details of "a" part lead no. (mounting height) * dimensions in mm (inches). note: the values in parentheses are reference values note 1) * : these dimensions do not include resin protrusion. note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder.
document number: 002 - 04705 rev.*a page 66 of 68 mb96680 series 18. major changes spansion publication number: mb96680_ds704 - 00002 page section change results revision 2.0 40 electrical characteristics 3. dc characteristics (1) current rating changed the value of po wer supply current in timer modes i cct pll typ: 1880 a 1800 a (t a = +25c) revision 2.1 - - company name and layout design change note: please see document history about later revised information.
document number: 002 - 04705 rev.*a page 67 of 68 mb96680 series document history document title: mb9668 0 series f 2 mc - 16fx 16 - bit microcontroller document number: 002 - 04705 revision ecn orig. of change submission date description of change ** - tors 01/31/2014 migrated to cypress and assigned document number 002 - 04705 no change to document contents or form at . *a 5147098 tors 0 8 / 2 2 /201 6 updated to cypress format.
document number: 002 - 04705 rev.*a august 22, 2016 page 68 of 68 mb96680 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors . to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com /clocks interface cypress.com/interface lighting & power control cypress.com /powerpsoc memory cypress.com /memory psoc cypress.com /psoc touch sensing cypress .com /touch usb controllers cypress.com /usb wireles s/rf cypress.com /wireless psoc ? solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 4 | psoc 5lp cypress developer community community | forums | blogs | video | training technical support c ypress.com/go/support arm and cortex are the trademarks of arm limited in the eu and other countries. ? cypres s semiconductor corporation 2013 - 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