supertex inc. supertex inc. www.supertex.com md2134 doc.# dsfp-md2134 c102412 dac a b dgnd agnd c3a ka c1a c3b c2b c1b vref +v ref m0m1 m2 m3 en sdi sdo sck cs ld vll sub data latch & control logic beamform switch matrix vdd +5.0v +2.5v pa xdrc pb t1 +3.3v +3.3v +70 to 100v v pp gnd kb c2a rfb d2 d1 +5.0v m1 m2 dn2625 +5.0v level translator pam level select dn2625 block diagram high speed ultrasound beamforming source driver features ? multiple-level ultrasound pulser ? fast switching current source for push-pull topology ? 250mhz maximum frequency, 4.0ns input to output delay ? 15 independent programmable output level registers ? pulse amplitude modulation (pam) with 8-bit resolution ? 8-bit apodization dac for peak output current via spi ? very low second order harmonic distortion ? picoseconds time-jitter from input to output ? fast spi write and read-back of level & dac registers ? +5.0v power supply, 2.5v cmos logic interface ? drives dn2625 mosfets output up to 230v p-p ? programmable aperture windowing applications ? medical imaging ultrasound beamforming transmitter ? dynamic focusing b-scan cw pw doppler & fm chirp ? ultrasonic phase array focusing transmitter ? piezoelectric & mems transducer waveform drivers ? high speed arbitrary waveform generator ? high resolution ndt phase array ultrasound pulser general description the md2134 is a high-speed source driver for use in a pulsed current waveform generator. this programmable, fast, arbitrary current level driver is designed for medical ultrasound imaging beamforming applications. it also can be used in hifu, ndt ultrasound and other instrument applications. the md2134 consists of cmos digital logic input circuits, an eight-bit current dac for aperture weighting amplitude control, and a programmable 15-level pulse amplitude modulation (pam) current-source that does not include a zero level. the fast current sources are constructed with current-switch array, controlled by the lv0~lv15 level-register as the waveform data points. four logic inputs m[3:0] are used for transmit data level selecting, as well as the transmitting timing control pins. each level can be programmed to a resolution of +/-127 including zero (8-bit) in addition to an 8-bit spi apodization dac. the outputs pa and pb are controlled by m[3:0] pins directly, as well as the polarity-lip bit s1 in the spi register. the high-speed spi interface will achieve per-scan-line fast data updating for dynamically changing delay time, weighting and waveforms. the md2134 outputs are designed to drive two very low-threshold, high-voltage depletion n-mosfets, such as supertexs dn2625s, as source drivers. the two dn2625 drains are connected to a center-tap rf pulse transformer. the transformers secondary output connects to a cable and piezoelectric or capacitive transducer as a load with a good impedance match. downloaded from: http:///
2 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 absolute maximum ratings parameter value v ll , logic supply -0.5v to +3.5v v dd , positive supply -0.5v to +6v v pa , v pb driver outputs -0.5v to +6v v sub , ground 0v operating temperature 0c to +70c storage temperature -65c to +150c absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. continuous operation of the device at the absolute rating level may affect device reliability. all voltages are referenced to device ground. operating supply voltages (over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5v, v ref = 2.5v, r fb = 71.1k, t a = 25c, dac = 0) sym parameter min typ max units conditions v ll logic supply 2.25 - 2.75 v t a = 0 to 70c v dd power supply 4.75 5.0 5.25 v i llq v ll supply current en = 0 - 0.1 1.0 a standby condition i ddq v dd supply current en = 0 - 0.2 1.0 i llen v ll supply current en = 1 - 5.0 20 a f sck = 0, all logic input, no transit i dden v dd supply current en = 1 - 5.0 12 ma i ll50 v ll supply current en = 1 - 1.0 3.0 ma f sck = 50mhz, cw, m[0:3] = 0 i dd50 v dd supply current en = 1 - 40 85 ma f sck = 0 , input = 50mhz, cw output characteristics (over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5v, v ref = 2.5v, r fb = 71.1k, t a = 25c) sym parameter min typ max units conditions i max-a/b full scale output peak current 2.88 - 3.52 a dac = 255, level = 127 i oo-a/b output current offset - 0.5 2.0 ma dac = 0 v pa/b output voltage range, +10% of i pa/b 5.3 5.8 - v i pa/b = 1.0a 5.0 5.5 - i pa/b = 1.5a 4.5 5.0 - i pa/b = 3.0a output voltage range, -10% of i pa/b - 1.0 1.5 i pa/b = 1.0a - 1.2 1.7 i pa/b = 1.5a - 1.8 2.3 i pa/b = 3.0a pin coniguration package marking md2134 llllll yyww aaaccc l = lot number yy = year sealed ww = week sealed a = assembler id c = country of origin = ?green? packaging 1 40 package may or may not include the following marks: si or 40-lead qfn (k7) 40-lead qfn (k7) (top view) ordering information part number package packing MD2134K7-G 40-lead (5x5) qfn 490/ tray typical thermal resistance package ja 40-lead qfn 26 o c/w downloaded from: http:///
3 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 aperture dac characteristics(over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5v, r fb = 71.1k, t a = 25c) sym parameter min typ max units conditions reso resolution - 8 8 bits --- e linear linearity error - 1.0 3.0 % % of fsr e diff differential nonlinearity error - 0.6 1.0 % % of fsr mon monotonicity - 8 8 bits --- v ref external reference voltage 1.25 - 2.5 v --- clock and data input/output characteristics(over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5v, r fb = 71.1k, t a = 25c) sym parameter min typ max units conditions v ih input logic high voltage 0.8v ll - v ll v --- v il input logic low voltage 0 - 0.2v ll v --- i ih input logic high current - - 1.0 a --- i il input logic low current -1.0 - - a --- c in input capacitance - 2.0 - pf --- i oh output logic high current - - -5.0 ma --- i ol output logic low current - - 5.0 ma --- v oh output logic high voltage 1.95 - - v i oh = -5.0ma v ol output logic low voltage - - 0.35 v i ol = 5.0ma ac electrical characteristics(over operating conditions unless otherwise speciied, v ll = +2.5v, v dd = +5v, r fb = 71.1k, t a = 25c) sym parameter min typ max units conditions t st dac to output setup time - - 10 s all caps 10nf, dac = 0 to 255, settle to 1lsb, t r output current rise time - 2.0 3.0 ns with 1.0 resistor load to v dd , dac = 85, v ref = 2.5v, lv=127 t f output current fall time - 2.0 3.0 t dr input to output delay on rise - 4.0 5.0 t df input to output delay on fall - 4.0 5.0 t m delay time matching - 2.0 3.0 ns from pa to pb and device to device t j output jitter - 50 - ps --- t 1 sdi valid to sck setup time 0 2.0 - ns see serial interface timing diagram t 2 sdi valid to sck hold time 4.0 - - t 3 sck high time % of 1/f clk 45 - 55 % see serial interface timing diagram t 4 sck low time % of 1/f clk 45 - 55 t 5 cs pulse width 4.0 - - ns see serial interface timing diagram t 6 lsb sck high to cs high 7.0 - - t 7 cs low to sck high 7.0 - - t 8 sdo propagation delay from sck failing edge - - 10 t 9 cs high to sck rising edge 7.0 - - t 10 cs high to ld rising edge 10 - - downloaded from: http:///
4 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 dac input and output description msb dac value register lsb pa or pb output current d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 (0/255)i max-a/b + i oo-a/b 0 0 0 0 0 0 0 1 (1/255)i max-a/b + i oo-a/b 0 1 1 1 1 1 1 1 (127/255)i max-a/b + i oo-a/b 1 0 0 0 0 0 0 0 (128/255)i max-a/b + i oo-a/b 1 1 1 1 1 1 1 0 (254/255)i max-a/b + i oo-a/b 1 1 1 1 1 1 1 1 (255/255)i max-a/b + i oo-a/b ac electrical characteristicsoutput current level control data register lax or lbx msb current level data register lax or lbx lsb ratio of full scale output polarity control d6 d5 d4 d3 d2 d1 d0 1 1 1 1 1 1 1 127/127 m3 = 0 output to pa m3 = 1 output to pb 1 1 1 1 1 1 0 126/127 ... ... 0 0 0 0 0 0 1 1/127 0 0 0 0 0 0 0 0 sym parameter min typ max units conditions f sck serial clock maximum frequency 40 50 - mhz --- t csr clock input slew rate 1.0 - - v/ns --- t dsr control / data input slew rate 1.0 - - v/ns --- thd total harmonic distortion - -45 -40 db --- t en-off en fall to pa/pb turn-off time - 5.0 8.0 ns 50% to 90% t en-on en rise to pa/pb turn-on time - 13.5 20.0 s 50% to 10% downloaded from: http:///
5 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 input control pin name pam current level description m3 m2 m1 m0 0 0 0 0 lv0 pa & pb both off, zero current 0 0 0 1 lv1 select lv1 current magnitude to pa 0 0 1 0 lv2 select lv2 current magnitude to pa 0 0 1 1 lv3 select lv3 current magnitude to pa 0 1 0 0 lv4 select lv4 current magnitude to pa 0 1 0 1 lv5 select lv5 current magnitude to pa 0 1 1 0 lv6 select lv6 current magnitude to pa 0 1 1 1 lv7 select lv7 current magnitude to pa 1 0 0 0 lv8 select lv8 current magnitude to pb 1 0 0 1 lv9 select lv9 current magnitude to pb 1 0 1 0 lv10 select lv10 current magnitude to pb 1 0 1 1 lv11 select lv11 current magnitude to pb 1 1 0 0 lv12 select lv12 current magnitude to pb 1 1 0 1 lv13 select lv13 current magnitude to pb 1 1 1 0 lv14 select lv14 current magnitude to pb 1 1 1 1 lv15 select lv15 current magnitude to pb note: turning on pa & pb simultaneously can cause over-current and permanent damage to the ic, high voltage mosfets, or to the trans- former. fast output current level control pin description downloaded from: http:///
6 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 data c1 c0 ra3 ra2 ra1 ra0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 write data 0 0 0 0 0 0 x s1 dac[7:0] data write 0 0 0 0 0 1 x x x lv1[6:0] pam current level data write 0 0 0 0 1 0 x x x lv2[6:0] pam current level data write 0 0 0 0 1 1 x x x lv3[6:0] pam current level data write 0 0 0 1 0 0 x x x lv4[6:0] pam current level data write 0 0 0 1 0 1 x x x lv5[6:0] pam current level data write 0 0 0 1 1 0 x x x lv6[6:0] pam current level data write 0 0 0 1 1 1 x x x lv7[6:0] pam current level data write 0 0 1 0 0 0 x x x lv8[6:0] pam current level data write 0 0 1 0 0 1 x x x lv9[6:0] pam current level data write 0 0 1 0 1 0 x x x lv10[6:0] pam current level data write 0 0 1 0 1 1 x x x lv11[6:0] pam current level data write 0 0 1 1 0 0 x x x lv12[6:0] pam current level data write 0 0 1 1 0 1 x x x lv13[6:0] pam current level data write 0 0 1 1 1 0 x x x lv14[6:0] pam current level data write 0 0 1 1 1 1 x x x lv15[6:0] pam current level data write read back data 0 1 0 0 0 0 x s1 dac[7:0] data read 0 1 0 0 0 1 x x x lv1[6:0] pam current level data read 0 1 0 0 1 0 x x x lv2[6:0] pam current level data read 0 1 0 0 1 1 x x x lv3[6:0] pam current level data read 0 1 0 1 0 0 x x x lv4[6:0] pam current level data read 0 1 0 1 0 1 x x x lv5[6:0] pam current level data read 0 1 0 1 1 0 x x x lv6[6:0] pam current level data read 0 1 0 1 1 1 x x x lv7[6:0] pam current level data read 0 1 1 0 0 0 x x x lv8[6:0] pam current level data read 0 1 1 0 0 1 x x x lv9[6:0] pam current level data read 0 1 1 0 1 0 x x x lv10[6:0] pam current level data read 0 1 1 0 1 1 x x x lv11[6:0] pam current level data read 0 1 1 1 0 0 x x x lv12[6:0] pam current level data read 0 1 1 1 0 1 x x x lv13[6:0] pam current level data read 0 1 1 1 1 0 x x x lv14[6:0] pam current level data read 0 1 1 1 1 1 x x x lv15[6:0] pam current level data read pwdn 1 0 x x x x d[9:0] = x power down state n.a. 1 1 x x x x (reserved, do not use) note: s1 is tx polarity swapping control bit. when s1 = 0 lv1~7 output to pa and lv8~15 output to pb, when s1 = 1 lv1~7 output to pb and lv8~15 output to pa. spi control registers description downloaded from: http:///
7 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 serial port interface (spi) read write timing for control register tx output timing diagram pa and pb output current equations lv 0 lv 1 lv2 lv3 lv4 lv 5 lv 6 t r t f t df t dr 90%10% 90%10% 90%10% 90%10% t r t f t df t dr i( lv 5) i( lv 1) i( lv 2) i( lv 3) i( lv 4) i( lv 15) i( lv 9) i( lv 8) i( lv 12) i( lv 13) i = 0 i = 0 if lv 6 = 0 i = 0 i = 0 pa current pa current m3 = 1, m[2:0] m3 = 0, m[2:0] lv 0 lv 9 lv8 lv12 lv 13 lv15 lv 0 1 16 15 3 2 t6 t4 t3 t2 t1 t9 t7 t5 t8 t10 sck sdi cs sdo ld the in-phase pa and 180 o pb output sinking current mag- nitudes i a and i b can be calculated by the following equa- tions. i a = 48 ? v ref ? dac ? (2 6 - 1) ? lax 127 9 ? r fb i b = 48 ? v ref ? dac ? (2 6 - 1) ? lbx 127 9 ? r fb where the v ref is the voltage reference, dac is the deci- mal value of the data in the dac register, r fb is the setting resistor value in ohms, lax or lbx is the decimal value of the data in the level register. the values of the results from the equations represent the magnitude of the output current. the current low into the port pa or pb is controlled by m0, m1, m2 or m3 are turned on. note that the maximum full scale peak current at pa or pb port only can be obtained at dac = 255, v ref = 2.5v, r fb = 71.1k , lax[6:0] = 127 for pa or lbx[6:0] = 127 for pb. downloaded from: http:///
8 md2134 supertex inc. www.supertex.com doc.# dsfp-md2134 c102412 pin description pin name description 1 ka kelvin connection a 2 gnd high current output ground 3 c1a bypass cap to ka, 10nf low esr x7r ceramic cap. 4 gnd high current output ground 5 vdd supplies voltage of the gate driver and internal analog circuit. 6 c3a bypass cap to gnd of pin #7, 10nf low esr x7r ceramic cap. 7 gnd high current output ground 8 vll supply voltage of logic circuit. 9 dgnd digital logic ground. 10 sck serial clock input. 11 sdi serial data input. 12 m3 control logic for selecting output current level. see fast output current level control pin description 13 m2 control logic for selecting output current level. see fast output current level control pin description 14 m1 control logic for selecting output current level. see fast output current level control pin description 15 m0 control logic for selecting output current level. see fast output current level control pin description 16 vdd supplies voltage of the gate driver and internal analog circuit. 17 agnd analog reference ground. 18 sdo serial data output. 19 cs serial chip select, active low, and buffer register loading clock on rising edge. 20 ld dac data register loading clock on rising edge. 21 en enable, en = low, pa = pb = hi-z and all internal registers freeze until next clock rising edge. 22 vref external reference voltage input. 23 rfb resistor to gnd, 71.1k 0.1% for the best accuracy. 24 gnd high current output ground. 25 c3b bypass cap to gnd of pin #24, 10nf low esr x7r ceramic cap. 26 vdd supplies voltage of the gate driver and internal analog circuit. 27 gnd high current output ground. 28 c1b bypass cap to kb, 10nf low esr x7r ceramic cap. 29 gnd high current output ground. 30 kb kelvin connection b. 31 c2b bypass cap to kb, 10nf low esr x7r ceramic cap. 32 pb current sinking source driver output b, external schottky diode to vdd. 33 pb current sinking source driver output b, external schottky diode to vdd. 34 pb current sinking source driver output b, external schottky diode to vdd. 35 vsub substrate voltage must connect to the lowest potential of the ic, the ground. 36 vsub substrate voltage must connect to the lowest potential of the ic, the ground. 37 pa current sinking source driver output a, external schottky diode to vdd. 38 pa current sinking source driver output a, external schottky diode to vdd. 39 pa current sinking source driver output a, external schottky diode to vdd. 40 c2a bypass cap to ka, 10nf low esr x7r ceramic cap. notes: 1. pin # 35 & #36 are v sub connected to the center thermal pad internally in the package. 2. all bypass capacitors need be very close to the pins downloaded from: http:///
supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate ?product liability indemnification insurance agreement.? supertex inc. does not assume responsibility for use of devices described, and limits its liabilit y to the replacement of the devices determined defective due to workmanship. no responsibility is assumed for possible omissions and inaccuracies. circuitry an d specifications are subject to change without notice. for the latest product specifications refer to the supertex inc . (website: http//ww w. supertex.com ) ?2012 supertex inc. all rights reserved. unauthorized use or reproduction is prohibited. supertex inc. 1235 bordeaux drive, sunnyvale, ca 94089 t el: 408-222-8888 www.supertex.co m 9 md2134 (the package drawing(s) in this data sheet may not relect the most current speciications. for the latest package outline information go to http://www.supertex.com/packaging.html .) doc.# dsfp-md2134 c102412 40-lead qfn package outline (k7) 5.00x5.00mm body, 0.80mm height (max), 0.40mm pitch symbol a a1 a3 b d d2 e e2 e l l1 dimension (mm) min 0.70 0.00 0.20 ref 0.15 4.85* 3.45 4.85* 3.45 0.40 bsc 0.25 ? 0.00 0 o nom 0.75 0.02 0.20 5.00 3.60 5.00 3.60 0.35 ? - - max 0.80 0.05 0.25 5.15* 3.70 ? 5.15* 3.70 ? 0.45 ? 0.15 14 o jedec registration mo-220, variation whhe-1, issue k, june 2006 * this dimension is not speciied in the jedec drawing. ? this dimension differs from the jedec drawing. drawings not to scale. supertex doc. #: dspd-40qfnk75x5p040, version c041009. notes: 1. a pin 1 identiier must be located in the index area indicated. the pin 1 identiier can be: a molded mark/identiier; an embedded metal marker; or a printed indicator. 2. depending on the method of manufacturing, a maximum of 0.15mm pullback (l1) may be present. 3. the inner tip of the lead may be either rounded or square. seating plane top vi ew side view bottom view view b vi ew b 1 note 3 note 2 40 1 40 d e d2 e2 note 1 (index area d/2 x e/2) note 1 (index area d/2 x e/2) e b l l1 a a1 a3 downloaded from: http:///
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