nxp semiconductors data sheet: technical data document number: imx8mdqlqcec rev. 0.1, 05/2018 ordering information see table 2 on page 6 ? 2018 nxp b.v. MIMX8MQ7DVAJZAA mimx8mq6dvajzaa mimx8md7dvajzaa mimx8md6dvajzaa mimx8mq5dvajzaa package information plastic package fbga 17 x 17 mm, 0.65 mm pitch 1 i.mx 8m dual / 8m quadlite / 8m quad introduction the i.mx 8m dual / 8m quadlite / 8m quad processors represent nxps latest market of connected streaming audio/video devices, scanning/imaging devices, and various devices requiring hi gh-performance, low-power processors. the i.mx 8m dual / 8m quadlite / 8m quad processors feature advanced impleme ntation of a quad arm ? cortex ? -a53 core, which operates at speeds of up to 1.5 ghz. a general purpose cortex ? -m4 core processor is for low-power processing. the dram controller supports 32-bit/16-bit lp ddr4, ddr4, and ddr3l memory. there are a number of other interfaces for connecting peripherals, such as wlan, bluetooth, gps, displays, and camera sensors. the i.mx 8m quad and i.mx 8m dual processors have hardware acceleration for video playback up to 4k, and can drive the video outputs up to 60 fps. although the i.mx 8m quadlite processor does not have hardwa re acceleration for video decode, it allows for video playback with software decoders if needed. i.mx 8m dual / 8m quadlite / 8m quad applications processors data sheet for consumer products 1. i.mx 8m dual / 8m quadlite / 8m quad introduction . . . . . . 1 1.1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2. modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1. recommended connections for unused interfaces . . . . 12 3. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1. chip-level conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2. power supplies requirements and restrictions . . . . . . . 24 3.3. pll electrical characteristics . . . . . . . . . . . . . . . . . . . . 26 3.4. on-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.5. i/o dc parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.6. i/o ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.7. output buffer impedance parameters . . . . . . . . . . . . . . 34 3.8. system modules timing . . . . . . . . . . . . . . . . . . . . . . . . 36 3.9. external peripheral interface parameters . . . . . . . . . . . 37 4. boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 4.1. boot mode configuration pins . . . . . . . . . . . . . . . . . . . 71 4.2. boot device interface allocation . . . . . . . . . . . . . . . . . . 72 5. package information and contact assignments . . . . . . . . . . . . 73 5.1. 17 x 17 mm package information . . . . . . . . . . . . . . . . . 73 5.2. ddr pin function list for 17 x 17 mm package . . . . . . 9 2 6. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 2 nxp semiconductors i.mx 8m dual / 8m quadlite / 8m quad introduction table 1. features subsystem feature arm cortex-a53 mpcore platform qua d symmetric cortex-a53 process ors: ? 32 kb l1 instruction cache ? 32 kb l1 data cache ? support l1 cache rams pr otection with parity/ecc support of 64-bit armv8-a architecture: ? 1 mb unified l2 cache ? support l2 cache ra ms protection with ecc ? frequency of 1.5 ghz arm cortex-m4 core platform 1 6 kb l1 instruction cache 16 kb l1 data cache 256 kb tightly coupled memory (tcm) connectivity two pci e xpress gen2 interfaces two usb 3.0/2.0 cont rollers with integrated phy interfaces two ultra secure digital host controller (usdhc) interfaces one gigabit ethernet controller with support for eee, ethernet avb, and ieee 1588 four universal asynchronous recei ver/transmitter (uart) modules four i 2 c modules three spi modules external memory interface 32/16- bit dram inte rface: lpddr4-3200, ddr4-2400, ddr3l-1600 8-bit nand-flash emmc 5.0 flash spi nor flash quadspi flash with support for xip gpio and pin multiplexing gpio m odules with inte rrupt capability input/output multiplexing controll er (iomuxc) to provide centra lized pad control on-chip memory boot rom (128 kb) on-chip ram (128 kb + 32 kb) power management temperature sens or with programmable trip point s flexible power domain partitioning with int ernal power switches to support efficient power management
i.mx 8m dual / 8m quadlite / 8m quad introduction i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 3 multimedia video processing unit: ? 4kp60 hevc/h.265 main, and main 10 decoder ? 4kp60 vp9 decoder ? 4kp30 avc/h.264 decoder ? 1080p60 mpeg-2, mpeg-4p2, vc-1, vp8, rv9, avs, mjpeg, h.263 d ecoder graphic processing unit: ? 4 shader ? 267 million triangles/sec ? 1.6 giga pixel/sec ? 32 gflops 32-bit or 64 gflops 16-bit ? support opengl es 1.1, 2.0, 3. 0, 3.1, open cl 1.2, and vulkan hdmi display interface: ? hdmi 2.0a supporting one display: resolution up to 4096 x 216 0 at 60 hz, support hdcp 2.2 and hdcp 1.4 1 ? 20+ audio interface s 32-bit @ 384 khz fs, with time division multiplexing (tdm) support ? s/pdif input and output ? audio return channel (arc) on hdmi ? upscale hd graphics to 4k for display ? downscale 4k video to hd for display ? display port ? embedded display port mipi-dsi display interface: ? mipi-dsi 4 channels supporting one display, resolution up to 1920 x 1080 at 60 hz ? lcdif display controller ? output can be lcdi f output or dc display controller output audio: ? s/pdif input and output ? five synchronous audio interfa ce (sai) modules supporting i2s , ac97, tdm, and codec/dsp interfaces, including one sai with 16 tx and 16 rx ch annels, one sai with 8 tx and 8 rx channels, a nd three sai with 2 t x and 2 rx channels ? one sai for 8 tx channe ls for hdmi output audio ? one s/pdif input for hdmi arc input camera inputs: ? two mipi-csi2 camera inputs (4-lane each) security resource dom ain controller (rdc) supports four domains and up to eight regions arm trustzone (tz) architecture on-chip ram (ocram) secure regi on protection using ocram contro ller high assurance boot (hab) cryptographic accele ration and assura nce (caam) module secure non-volatile st orage (snvs): secure real-time clock (rtc ) secure jtag controller (sjc) table 1. features (continued) subsystem feature
i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 4 nxp semiconductors i.mx 8m dual / 8m quadlite / 8m quad introduction note the actual feature set depends on the part numbers as described in table 2 . functions such as display and camera interfaces, and connectivi ty interfaces, may not be enable d for specific part numbers. system debug arm coresight d ebug and trace architecture tpiu to support off-chi p real-time trace etf with 4 kb internal stora ge to provide trace buffering unified trace capabilit y for quad cortex-a53 and cortex-m4 cpus cross triggering interface (cti) support for 5-pin (jtag) debug interface 1 please contact the nxp sales and marketing team for order detai ls on hdcp enable parts. table 1. features (continued) subsystem feature
i.mx 8m dual / 8m quadlite / 8m quad introduction i.mx 8m dual / 8m quadlite / 8m quad applications processors da ta sheet for consumer pr oducts, rev. 0.1, 05/2018 nxp semiconductors 5 1.1 block diagram figure 1 shows the functional modules in the i.mx 8m dual / 8m quadlite / 8m quad processor system. figure 1. i.mx 8m dual / 8m quadl ite / 8m quad sy stem block diag ram ^???u }v??}o ^u?? d ?? du???? ^v?}? d]u? ?? ^? : d ' t?z}p ?? >} w}?u ^?]?? w h }vv?]]?? v /l k ' ?z?v? ~ / ???u u v s w t d ?e do?]u] h ^ ?xl?x k d ' ?? ^l w / & |