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rev. 1.14 7/16 copyright ? 2016 by si licon laboratories si7050/1/3/4/5-a20 si7050/1/3/4/5-a20 i 2 c t emperature s ensors features applications description the si705x digital temperature sensors offer industry-leading low power consumption and high accuracy across the entire operating voltage and temperature range. these monolithic cmos ics feature a band-gap temperature sensor element, an analog-to-digital converter with up to 14- bit resolution, signal processing, calibration data, and an i 2 c interface. the patented use of novel signal processing and analog design enables the sensors to maintain their accuracy over a wide temperature and voltage range, while consuming very little current. the temperature sensors are factory-calibrated and the calibration data is stored in the on-chip non-volatile memory. this ensures that the sensors are fully interchangeable, with no recalibration or software changes required. the si705x devices are available in a 3x3 mm dfn package, and the industry-standard i 2 c interface can operate at up to 400 khz. requiring just 195 na of average current when sampled once per second, the si705x can operate for several years with just a single coin cell battery. the si705x devices offer an accurate, low-power, factory-calibrated digital solution ideal for measuring temperature in applications ranging from hvac/r and asset tracking to industrial and consumer platforms. ? high accuracy temperature sensors ?? si7051: 0.1 c (max) ?? si7053: 0.3 c (max) ?? si7054: 0.4 c (max) ?? SI7055: 0.5 c (max) ?? si7050: 1.0 c (max) ? wide operating voltage (1.9 to 3.6 v) ? ?40 to +125 c operating range ? accuracy maintained over the entire operating temperature and voltage range ? low power consumption ?? 195 na average current @ 1 hz sample rate ? 14-bit resolution ? factory calibrated ? i 2 c interface ? 3x3 mm dfn package ? hvac/r ? thermostats ? white goods ? computer equipment ? portable consumer devices ? asset tracking ? cold chain storage ? battery protection ? industrial controls ? medical equipment patent protected. patents pending ordering information: see page 19. pin assignments top view 1 dnc 2 3 6 5 4 vdd scl sda gnd dnc
si7050/1/3/4/5-a20 2 rev. 1.14 functional block diagram adc gnd scl si705x temp sensor sda vdd i 2 c interface 1.25v ref voltage regulator calibration memory control logic
si7050/1/3/4/5-a20 rev. 1.14 3 t able of c ontents section page 1. electrical specificat ions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. typical application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 5. i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5.1. issuing a measurement command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2. reading and writing user registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3. electronic serial number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 5.4. firmware revision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6. control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 6.1. register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7. pin descriptions: si705x (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8. ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9. package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 9.1. package outline: 3x3 6- pin dfn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 10. pcb land pattern and solder mask d esign . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 11. top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 11.1. si705x top marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.2. top marking explana tion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11.3. SI7055-a20-zm (matte tin finish lead frame) top marking . . . . . . . . . . . . . . . . . 23 11.4. SI7055-a20-zm (matte tin finish lead frame) top marki ng explanation . . . . . . . 23 12. additional reference resour ces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 document change list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
si7050/1/3/4/5-a20 4 rev. 1.14 1. electrical specifications unless otherwise specified, all mi n/max specifications apply over the recommended operating conditions. table 1. recommended operating conditions parameter symbol test condition min typ max unit power supply v dd 1.9 ? 3.6 v operating temperature t a ?40 ? +125 c table 2. general specifications 1.9 < v dd < 3.6 v; t a = ?40 to 125 c default conversion time unless otherwise noted. parameter symbol test condition min typ max unit input voltage high v ih scl, sda pins 0.7 x v dd ??v input voltage low v il scl, sda pins ? ? 0.3 x v dd v input voltage range v in scl, sda pins with respect to gnd 0.0 ? v dd v input leakage i il scl, sda pins ? ? 1 a output voltage low v ol sda pin; i ol =2.5ma; v dd = 3.3 v ? ? 0.6 v sda pin; i ol =1.2ma; v dd =1.9v ??0.4v current consumption i dd temperature conversion in progress ? 90 120 a standby, ?40 to +85 c 1 ?0.060.62 a standby, ?40 to +125 c 1 ?0.063.8 a peak idd during powerup 2 ?3.54.0ma peak idd during i 2 c operations 3 ?3.54.0ma conversion time t conv 14-bit temperature ? 7 10.8 ms 13-bit temperature ? 4 6.2 ms 12-bit temperature ? 2.4 3.8 ms 11-bit temperature ? 1.5 2.4 ms powerup time t pu from v dd 1.9 v to ready for a conversion, 25 c ?1825 ms from v dd 1.9 v to ready for a conversion, full temperature range ??80 after issuing a software reset command ?515 notes: 1. no conversion or i 2 c transaction in progress. typical values measured at 25 c. 2. occurs once during poweru p. duration is <5 msec. 3. occurs during i 2 c commands for reset, read/write user registers, read eid, and read firmware version. duration is <100 s when i 2 c clock speed is >100 khz (> 200 khz for 2-byte commands).
si7050/1/3/4/5-a20 rev. 1.14 5 table 3. i 2 c interface specifications 1 1.9 ? v dd ? 3.6 v; t a = ?40 to +125 c unless otherwise noted. parameter symbol test condition min typ max unit hysteresis v hys high-to-low versus low-to- high transition 0.05 x v dd ??v sclk frequency 2 f scl ? ? 400 khz scl high time t skh 0.6 ? ? s scl low time t skl 1.3 ? ? s start hold time t sth 0.6 ? ? s start setup time t sts 0.6 ? ? s stop setup time t sps 0.6 ? ? s bus free time t buf between stop and start 1.3 ? ? s sda setup time t ds 100 ? ? ns sda hold time t dh 100 ? ? ns sda valid time t vd;dat from scl low to data valid ? ? 0.9 s sda acknowledge valid time t vd;ack from scl low to data valid ? ? 0.9 s suppressed pulse width 3 t sps 50 ? ? ns notes: 1. all values are referenced to v il and/or v ih . 2. depending on the conversion command, the si705x may hold th e master during the conver sion (clock stretch). at above 100 khz scl, the si705x may also hold the master brie fly for user register and device id transactions. at the highest i 2 c speed of 400 khz the stretching will be <10 s. 3. pulses up to and including 50 ns will be suppressed.
si7050/1/3/4/5-a20 6 rev. 1.14 figure 1. i 2 c interface timing diagram scl d6 1/f scl t skh sda t skl t sth d5 d4 d0 r/w ack t ds t dh start bit stop bit t buf t sts t vd : ack t sps t sp
si7050/1/3/4/5-a20 rev. 1.14 7 table 4. temperature sensor 1.9 v dd 3.6 v; t a = ?40 to +125 c default conversi on time unless otherwise noted. parameter symbol test condition min typ max unit operating range ?40 ? +125 c accuracy 1 si7051 ? ? 0.1 2 c si7053 ? 0.2 0.3 c si7054 ? 0.3 0.4 c SI7055 ? 0.4 0.5 c si7050 ? 0.5 1.0 c repeatability/noise 14- bit resolution ? 0.01 ? c rms 13-bit resolution ? 0.02 ? 12-bit resolution ? 0.04 ? 11-bit resolution ? 0.08 ? response time 3 63% unmounted device ? 0.7 ? s si705x-eb board ? 5.1 ? s long term stability ? ? 0.01 ? c/yr notes: 1. 14b measurement resolution (default). values apply to t he full operating temperature and voltage range of the device. 2. 0.1 c: +35.8 c to 41 c; 0.13 c: 20.0 c to 70.0 c; 0.25 c: ?40 c to +125 c. 3. time to reach 63% of final value in response to a step change in temperature. actual response time will vary dependent on system thermal mass and air-flow.
si7050/1/3/4/5-a20 8 rev. 1.14 table 5. thermal characteristics parameter symbol test condition dfn-6 unit junction to air thermal resistance ? ja jedec 2-layer board, no airflow 256 c/w junction to air thermal resistance ? ja jedec 2-layer board, 1 m/s airflow 224 c/w junction to air thermal resistance ? ja jedec 2-layer board, 2.5 m/s airflow 205 c/w junction to case thermal resistance ? jc jedec 2-layer board 22 c/w junction to board thermal resistance ? jb jedec 2-layer board 134 c/w table 6. absolute maximum ratings 1 parameter symbol test condition min typ max unit ambient temperature under bias ?55 ? 125 c storage temperature 2 ?65 ? 150 c voltage on i/o pins ?0.3 ? vdd+0.3 v v voltage on vdd with respect to gnd ?0.3 4.2 v esd tolerance hbm ? ? 2 kv cdm ? ? 1.25 kv mm ? ? 250 v notes: 1. absolute maximum ratings are stress ratings only, operation at or beyond these conditio ns is not implied and may shorten the life of the device or alter its performance. 2. special handling considerations apply; see application note, ?an607: si70xx humidity and temperature sensor designer?s guide?.
si7050/1/3/4/5-a20 rev. 1.14 9 2. typical application circuits figure 2 demonstrates the typical a pplication circuit for si705x sensors. figure 2. typical application circuit for temperature measurement 0.1 f v dd scl sda si705x scl sda 1.9 to 3.6 v 6 1 2 gnd 10 k ? 10 k ? 5
si7050/1/3/4/5-a20 10 rev. 1.14 3. bill of materials table 7. typical application circuit bom for temperature measurement reference description mfr part number manufacturer r1 resistor, 10 k ? , 5%, 1/16 w, 0603 cr0603-16w-103jt venkel r2 resistor, 10 k ? , 5%, 1/16 w, 0603 cr0603-16w-103jt venkel c1 capacitor, 0.1 f, 16 v, x7r, 0603 c0603x7r160-104m venkel u1 ic, digital temperature se nsor si705x-a20 -im silicon labs
si7050/1/3/4/5-a20 rev. 1.14 11 4. functional description figure 3. si705x block diagram the si705x digital temperature sensors offer industry-leading low power consumption and high accuracy across the entire operating voltage and temperature range. th ese monolithic cmos ics feature a band-gap temperature sensor element, an analog-to-digital converter with up to 14-bit resolution, signal processing, calibration data, and an i 2 c interface. the patented use of no vel signal processing and analog design enables the sensors to maintain their accuracy over a wide temperature and voltage range, while consuming very little current. the temperature sensors are factory-calibrated and the calibration data is stored in the on-chip non-volatile memory. this ensures that the sensors are fully interc hangeable, with no recalibration or software changes required. the si705x devices are available in a 3x3 mm dfn package, and the industry-standard i 2 c interface can operate at up to 400 khz. requiring just 195na of average current when sampled once per second, the si705x can operate for several years with just a single coin cell battery. the si705x devices offer an accurate, low-power, factory-calibrated digital solution ideal for measuring temperature in applications ranging from hvac/r and asset tracking to industrial and consumer platforms. adc gnd scl si705x temp sensor sda vdd i 2 c interface 1.25v ref voltage regulator calibration memory control logic
si7050/1/3/4/5-a20 12 rev. 1.14 5. i 2 c interface the si705x communicates with the host controller over a digital i 2 c interface. the 7-bit base slave address is 0x40. when sending commands to the device, the r/w bit is set high for a read command and low for a write command. master i 2 c devices communicate with the si705x using a comm and structure. the comma nds are listed in the i 2 c command table. commands other than those documented below are undefined and should not be sent to the device. when sending commands to the device, the r/w bi t is set high for a read command and low for a write command. table 8. i 2 c slave address byte a6 a5 a4 a3 a2 a1 a0 r/w 10000000 table 9. i 2 c command table command description command code measure temperature, hold master mode 0xe3 measure temperature, no hold master mode 0xf3 reset 0xfe write user register 1 0xe6 read user register 1 0xe7 read electronic id 1st byte 0xfa 0x0f read electronic id 2nd byte 0xfc 0xc9 read firmware revision 0x84 0xb8
si7050/1/3/4/5-a20 rev. 1.14 13 5.1. issuing a measurement command the measurement command instructs the si705x to perform a temperature measurement. while the measurement is in progress, the option of either clock stretching (h old master mode) or not acknowledging read requests (no hold master mode) is available to indicate to the master that the measurement is in progress; the chosen command code determines which mode is used. optionally, a checksum byte can be returned from the slave for use in checking for transmission errors. the checksum byte will follow the least sign ificant measurement byte if it is acknowledg ed by the master. the checksum byte is not returned if the master ?not acknowledges? the least significant measurement byte. the checksum byte is calculated using a crc generator polynomial of x 8 + x 5 + x 4 + 1, with an initialization of 0x00. the checksum byte is optional after initiating a te mperature measurement with commands 0xe3, and 0xf3. the checksum byte is required for reading the electronic id with commands 0xfa 0x0f and 0xfc 0xc9. for all other commands, the checksum byte is not supported. in the i 2 c sequence diagrams in the following sections, bits produced by the master and slave are color coded as shown: table 10. i 2 c bit descriptions name symbol description start s sda goes low while scl high stop p sda goes high while scl high repeated start sr sda goes low while scl high. it is allowable to generate a stop before the repeated start. sda can transition to high before or after scl goes high in preparation for generating the start. read r read bit = 0 write w write bit = 1 all other bits ? sda value must rema in high or low during the entire time scl is high (this is the set up and hold time in figure 1) master slave sequence to perform a measurement and read back result (hold master mode) s slave address w a measure cmd a sr slave address r a clock stretch during measurement ms byte a ls byte na p a checksum na p
si7050/1/3/4/5-a20 14 rev. 1.14 *note: device will nack the slave address byte until conversion is complete. 5.1.1. measuring temperature the measure temper ature commands 0xe3 an d 0xf3 will perform a temperatur e measurement and return the measurement value. the results of the temperature measurement may be conver ted to temperature in degrees celsius (c) using the following expression: where: temperature (c) is the measured temperature value in c temp_code is the 16-bit word returned by the si705x a temperature measurement will always return xxxxxx00 in the lsb field. 5.2. reading and wr iting user registers there is one user register on the si705x that allows the user to set the conf iguration of the si705x. the procedure for accessing that register is described below. the checksum byte is not supported after reading a user register. sequence ? to ? read ? a ? register s slave ? address w a read ? reg ? cmd asr slave ? address r a read ? data na p sequence ? to ? write ? a ? register sslave ? address w awrite ? reg ? cmd awrite ? data ap temperature ( ? c ? 175.72 ? temp_code 65536 ------------------------------------------------------- - 46.85 ? =
si7050/1/3/4/5-a20 rev. 1.14 15 5.3. electronic serial number the si705x provides a serial number individua lized for each device that can be read via the i 2 c serial interface. two i 2 c commands are required to access the device memory and retrieve the complete serial number. the command sequence, and format of the serial numb er response is described in the figure below: first access: the format of the complete serial number is 64-bits in length, divided into 8 data bytes. the complete serial number sequence is shown below: the snb3 field contains the device i dentification to distinguis h between the diff erent silicon labs devices. the value of this field maps to the follo wing devices according to this table: 0x00 or 0xff engineering samples 50 = 0x32 = si7050 51 = 0x33 = si7051 53 = 0x35 = si7053 54 = 0x36 = si7054 55 = 0x37 = SI7055 master slave sslave ? address w ack 0xfa ack 0x0f ack sslave ? address r ack sna_3 ack crc ack sna_2 ack crc ack sna_1 ack crc ack sna_0 ack crc nack p 2nd access: sslave ? address w ack 0xfc ack 0xc9 ack sslave ? address r ack snb_3 ack snb_2 ack crc ack snb_1 ack snb_0 ack crc nack p sna_3 sna_2 sna_1 sna_0 snb_3 snb_2 snb_1 snb_0
si7050/1/3/4/5-a20 16 rev. 1.14 5.4. firmware revision the internal firmware revision can be read with the following i 2 c transaction: the values in this field are encoded as follows: 0xff = firmware version 1.0 0x20 = firmware version 2.0 s slave ? address w a0x84 a0xb8 a s slave ? address r a fwrev na p
si7050/1/3/4/5-a20 rev. 1.14 17 6. control registers 6.1. register descriptions reset settings = 0011_1010 table 11. register summary register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 user register 1 res1 vdds rsvd rsvd rsvd rsvd rsvd res0 notes: 1. any register not listed here is reserved and must not be wr itten. the result of a read operation on these bits is undefined. 2. except where noted, reserved register bits will always read back as ?1,? and are not affected by write operations. for future compatibility, it is recommended that prior to a write oper ation, registers should be read. then the values read from the rsvd bits should be written back unchanged during the write operation. register 1. user register 1 bit d7 d6 d5 d4d3d2 d1 d0 name res1 vdds rsvd rsvd rsvd rsvd rsvd res0 type r/w r r/w r/w r/w r/w r/w bit name function d7; d0 res[1:0] measurement resolution: 00: 14 bit 01: 12 bit 10: 13 bit 11: 11 bit d6 vdds vdd status: 0: v dd ok 1: v dd low the minimum recommended operating voltage is 1.9 v. a transi- tion of the vdd status bit from 0 to 1 indicates that vdd is between 1.8 v and 1.9 v. if the vdd drops below 1.8 v, the device will no longer operate correctly. d5, d4, d3, d2, d1 rsvd reserved
si7050/1/3/4/5-a20 18 rev. 1.14 7. pin descriptions: si705x (top view) pin name pin # pin description sda 1 i 2 c data gnd 2 ground. this pin is connected to ground on the circuit board through a trace. do not connect directly to gnd plane. vdd 5 power. this pin is connected to power on the circuit board. scl 6 i 2 c clock dnc 3,4 these pins should be soldered to pads on the pcb for mechanical stability; they can be electrically floating or tied to vdd (do not tie to gnd). t gnd paddle this pad is connected to gnd internally. this pad is t he main thermal input to the on- chip temperature sensor . the paddle should be soldered to a floating pad. 1 dnc 2 3 6 5 4 vdd scl sda gnd dnc
si7050/1/3/4/5-a20 rev. 1.14 19 8. ordering guide table 12. device ordering guide part number description max. accuracy pkg packing format si7050-a20-im digital temperature sensor 1 c dfn 6 tube si7050-a20-imr digital temperature sensor 1 c dfn 6 tape and reel si7051-a20-im digital temperature sensor 0.1 c dfn 6 tube si7051-a20-imr digital temperature sensor 0.1 c dfn 6 tape and reel si7053-a20-im digital temperature sensor 0.3 c dfn 6 tube si7053-a20-imr digital temperature sensor 0.3 c dfn 6 tape and reel si7054-a20-im digital temperature sensor 0.4 c dfn 6 tube si7054-a20-imr digital temperature sensor 0.4 c dfn 6 tape and reel SI7055-a20-im digital temperature sensor 0.5 c dfn 6 tube SI7055-a20-imr digital temperature sensor 0.5 c dfn 6 tape and reel SI7055-a20-zm digital temperature sensor ? matte tin finish lead frame 0.5 c dfn 6 tube SI7055-a20-zmr digital temperature sensor ? matte tin finish lead frame 0.5 c dfn 6 tape and reel note: the ?a? denotes product revision a and ?20? denotes firmware version 2.0.
si7050/1/3/4/5-a20 20 rev. 1.14 9. package outline 9.1. package outl ine: 3x3 6-pin dfn figure 10. 3x3 6-pin dfn table 13. package diagram dimensions dimension min nom max a 0.70 0.75 0.80 a1 0.00 0.02 0.05 b 0.35 0.40 0.45 d 3.00 bsc. d2 1.40 1.50 1.60 e 1.00 bsc. e 3.00 bsc. e2 2.30 2.40 2.50 l 0.35 0.40 0.45 aaa 0.10 bbb 0.10 ccc 0.05 ddd 0.10 eee 0.05 notes: 1. all dimensions shown are in millimeters (mm). 2. dimensioning and tolerancing per ansi y14.5m-1994. ?
si7050/1/3/4/5-a20 rev. 1.14 21 10. pcb land pattern and solder mask design figure 4. si705x pcb land pattern table 14. pcb land pattern dimensions symbol mm c1 2.90 e1.00 p1 1.60 p2 2.50 x1 0.45 y1 0.85 notes: general 1. all dimensions shown are at maximum material condition (mmc). least material condition (lmc) is calculated based on a fabrication allowance of 0.05 mm. 2. this land pattern design is based on the ipc-7351 guidelines. solder mask design 3. all metal pads are to be non-solder mask defined (nsmd). clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. stencil design 4. a stainless steel, laser-cut and electr o-polished stencil with trapezoidal walls should be used to assure good solder paste release. 5. the stencil thickness should be 0.125 mm (5 mils). 6. the ratio of stencil aperture to land pa d size should be 1:1 for all perimeter pins. 7. a 2x1 array of 1.00 mm square openings on 1.30 mm pitch should be used for the center ground pad to achieve a target solder coverage of 50%. card assembly 8. the recommended card reflow profile is per the jedec/ipc j-std-020 specification for small body components. ?
si7050/1/3/4/5-a20 22 rev. 1.14 11. top marking 11.1. si705x top marking 11.2. top marking explanation mark method: laser pin 1 mark: circle = 0.30 mm diameter (upper- left corner) font size: 0.05 mm line 1 mark format: device code si705 line 2 mark format: tttt manufacturing code from the assembly purcha se order form. line 3 mark format: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly release.
si7050/1/3/4/5-a20 rev. 1.14 23 11.3. SI7055-a20-zm (matte tin finish lead frame) top marking 11.4. SI7055-a20-zm (matte tin finish lead frame) top marking explanation mark method: laser pin 1 mark: circle = 0.30 mm diameter (upper- left corner) font size: 0.05 mm line 1 mark format: device code SI7055 line 2 mark format: tttt manufacturing code from the assembly purcha se order form. line 3 mark format: yy = year ww = work week assigned by the assembly house. corresponds to the year and work week of the assembly release.
si7050/1/3/4/5-a20 24 rev. 1.14 12. additional reference resources ?? an607: si70xx humidity and temperature sensor designer?s guide
si7050/1/3/4/5-a20 rev. 1.14 25 d ocument c hange l ist revision 0.9 to revision 1.0 ? updated section "5. i2c interface" on page 12 ? updated table 12, ?device ordering guide,? on page 19 revision 1.0 to revision 1.1 ? added part number si7051 ? updated "9. package outline" on page 20 revision 1.1 to revision 1.11 ? added new opn: SI7055-a20-zm with matte tin finish lead frame revision 1.11 to revision 1.12 ? removed erroneous typical value for si7051 accuracy from table 4. revision 1.12 to revision 1.13 ? removed ?ym0? and ?ym0r? automotive qualified part numbers from table 12, ?device ordering guide,? on page 19. revision 1.13 to revision 1.14 ? updated ?no hold master mode? diagram in "5.1. issuing a measurement command" on page 13. ? updated diagram in "5.4. firmware revision" on page 16.? ? updated notes in table 14, ?pcb land pattern dimensions,? on page 21.
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