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| this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 1 EN25F20A rev. a, issue date: 2013 / 11 / 18 features ? single power supply operation - full voltage range: 2.7-3.6 volt ? serial interface architecture - spi compatible: mode 0 and mode 3 ? 2 m-bit serial flash - 2 m-bit/256 k-byte/1,024 pages - 256 bytes per programmable page ? standard, dual or quad spi - standard spi: clk, cs#, di, do, wp#, hold# - dual spi: clk, cs#, dq 0 , dq 1 , wp#, hold# - quad spi: clk, cs#, dq 0 , dq 1 , dq 2 , dq 3 ? high performance - 104mhz clock rate for standard spi - 104mhz clock rate for two data bits - 104mhz clock rate for four data bits ? low power consumption - 10ma typical active current - 1 a typical power down current ? uniform sector architecture: - 64 sectors of 4-kbyte - 8 blocks of 32-kbyte - 4 blocks of 64-kbyte - any sector or block can be erased individually ? software and hardware write protection: - write protect all or portion of memory via software - enable/disable protection with wp# pin ? high performance program/erase speed - page program time: 0.8ms typical - sector erase time: 30ms typical - 32kb block erase time 100ms typical - 64kb block erase time 200ms typical - chip erase time: 0.8 seconds typical ? lockable 512 byte otp security sector ? support serial flash discoverable parameters (sfdp) signature ? read unique id number ? minimum 100k endurance cycle ? package options - 8 pins sop 150mil body width - 8 pins vsop 150mil body width - 8 contact uson 2x3 mm - 8 contact vdfn 5x6 mm - all pb-free packages are compliant rohs, halogen-free and reach. ? industrial temperature range general description the EN25F20A is a 2 megabit (256 k-byte) serial flash memory, with enhanced write protection mechanisms. the EN25F20A supports the standard serial peripheral interface (spi), and a high performance dual/quad output as well as dual/quad i/o using spi pins: serial clock, chip select, serial dq 0 (di), dq 1 (do), dq 2 (wp#) and dq 3 (hold#). spi clock frequencies of up to 104mhz are supported allowing equivalent clock rates of 208mhz (104mhz x 2) for dual output and 416mhz (104mhz x 4) for quad output when using the dual/quad i/o fast read instructions. the memory can be programmed 1 to 256 bytes at a time, using the page program instruction. the EN25F20A is designed to allow either single sector/block at a time or full chip erase operation. the EN25F20A can be configured to protect part of the memory as the software protected mode. the device can sustain a minimum of 100k program/erase cycles on each sector or block . EN25F20A 2 me g abit se r ial flash memor y with 4kb y te uniform sector
this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 2 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure.1 connection diagrams 8 - lead sop / vsop do (dq 1 ) wp# (dq 2 ) vss cs# di (dq 0 ) clk hold# (dq 3 ) vcc 1 2 3 4 8 7 6 5 8 - lead uson / vdfn do (dq 1 ) wp# (dq 2 ) vss cs# di (dq 0 ) clk hold# (dq 3 ) vcc 1 2 3 4 8 7 6 5 this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 3 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 2. block diagram serial interface x-decoder address buffer and latches cs# clk di (dq0) do (dq1) hold# (dq3) wp# (dq2) flash memory y-decoder i/o buffers and data latches control logic note: 1. dq 0 and dq 1 are used for dual and quad instructions. 2. dq 0 ~ dq 3 are used for quad instructions. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 4 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 1. pin names symbol pin name clk serial clock input di (dq 0 ) serial data input (data input output 0) *1 do (dq 1 ) serial data output (data input output 1) *1 cs# chip select wp# (dq 2 ) write protect (data input output 2) *2 hold# (dq 3 ) hold# pin (data input output 3) *2 vcc supply voltage (2.7-3.6v) vss ground nc no connect note: 1. dq 0 and dq 1 are used for dual and quad instructions. 2. dq 2 ~ dq 3 are used for quad instructions. signal description serial data input, output and ios (di, do and dq 0 , dq 1 , dq 2 , dq 3 ) the EN25F20A support standard spi, dual spi and quad spi operation. standard spi instructions use the unidirectional di (input) pin to serially write in structions, addresses or data to the device on the rising edge of the serial clock (clk) input pin. standard spi also uses the unidirectional do (output) to read data or status from the device on the falling edge clk. dual and quad spi instruction use the bidirectional io pins to serially write instruction, addresses or data to the device on the rising ed ge of clk and read data or status from the device on the falling edge of clk. serial clock (clk) the spi serial clock input (clk) pin provides the timing for serial input and output operations. ("see spi mode") chip select (cs#) the spi chip select (cs#) pin enables and disables device operation. when cs# is high the device is deselected and the serial data output (do, or dq 0 , dq 1 , dq 2 and dq 3 ) pins are at high impedance. when deselected, the device s power consumption will be at standby levels unless an internal erase, program or status register cycle is in progress. wh en cs# is brought low the device will be selected, power consumption will increase to active levels and instructions can be written to and data read from the device. after power-up , cs# must transition from high to low before a new instruction will be accepted. hold (hold#) the hold# pin allows the device to be paused while it is actively selected. when hold# is brought low, while cs# is low, th e do pin will be at high impedance and signals on the di and clk pins will be ignored (don?t care). the hold function can be useful when multiple devices are sharing the same spi signals. the hold# function is only available for standard spi and dual spi operation, when during quad spi, this pin is the serial data io (dq 3 ) for quad i/o operation. write protect (wp#) the write protect (wp#) pin can be used to prevent the status register from being written. used in conjunction with the status register?s block protect (bp0, bp1, bp2 and bp3) bits and status register protect (srp) bits, a portion or the entire memory array can be hardware protected. the wp# function is only available for standard spi and dual spi operation, when during quad spi, this pin is the serial data io (dq 2 ) for quad i/o operation. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 5 EN25F20A rev. a, issue date: 2013 / 11 / 18 memory organization the memory is organized as: z 262,144 bytes z uniform sector architecture 8 blocks of 32-kbyte 4 blocks of 64-kbyte 64 sectors of 4-kbyte 1,024 pages (256 bytes each) each page can be individually programmed (bits are programmed from 1 to 0). the device is sector, block or chip erasable but not page erasable. table 2. uniform block sector architecture 64kb block 32kb block sector address range 63 03f000h 03ffffh 7 ?. ?. ?. 3 6 48 030000h 030fffh 47 02f000h 02ffffh 5 ?. ?. ?. 2 4 32 020000h 020fffh 31 01f000h 01ffffh 3 ?. ?. ?. 1 2 16 010000h 010fffh 15 00f000h 00ffffh 1 ?. ?. ?. 0 0 0 000000h 000fffh this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 6 EN25F20A rev. a, issue date: 2013 / 11 / 18 operating features standard spi modes the EN25F20A is accessed through a spi compatible bus consisting of four signals: serial clock (clk), chip select (cs#), serial data input (di) and serial data output (do). both spi bus operation modes 0 (0,0) and 3 (1,1) are supported. the primary difference between mode 0 and mode 3, as shown in figure 3, concerns the normal state of the clk signal when the spi bus master is in standby and data is not being transferred to the serial flash. for mode 0 the clk signal is normally low. for mode 3 the clk signal is normally high. in either case data input on the di pin is sampled on the rising edge of the clk. data output on the do pi n is clocked out on the falling edge of clk. figure 3. spi modes dual spi instruction the EN25F20A supports dual spi operation when using the ?dual output fast read and dual i/o fast read ? (3bh and bbh) instruct ions. these instructions allow data to be transferred to or from the serial flash memory at two to three times the rate possible with the standard spi. the dual read instructions are ideal for quickly downloading code from flash to ram upon power-up (code-shadowing) or for application that cache code-segments to ram for execution. the dual output feature simply allows the spi input pin to also serve as an output during this instruction. when using dual spi instructions the di and do pins become bidirectional i/o pins; dq 0 and dq 1 . all other operations use the standard spi interface with single output signal. quad i/o spi modes the EN25F20A supports quad input / output operation when using the quad i/o fast read (ebh).this instruction allows data to be transferred to or from the serial flash memory at four to six times the rate possible with the standard spi. the quad read instruction offer a significant improvement in continuous and random access transfer rates allowing fast code-shadowing to ram or for application that cache code-segments to ram for execution. when using quad spi instruction the di and do pins become bidirectional i/o pins; dq 0 and dq 1, and the wp# and hold# pins become dq 2 and dq 3 respectively. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 7 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 4. quad i/o spi modes full quad spi modes (qpi) the EN25F20A also supports full quad spi mode (qpi) function while using the enable quad peripheral interface mode (eqpi) (38h). when using quad spi instruction the di and do pins become bidirectional i/o pins; dq 0 and dq 1, and the wp# and hold# pins become dq 2 and dq 3 respectively. figure 5. full quad spi modes this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 8 EN25F20A rev. a, issue date: 2013 / 11 / 18 page programming to program one data byte, two instructions are required: write enable (wren), which is one byte, and a page program (pp) or quad input page program (qpp) sequence, which consists of four bytes plus data. this is followed by the internal program cycle (of duration t pp ). to spread this overhead, the page program (pp) or quad input page program (qpp) instruction allows up to 256 bytes to be programmed at a time (changing bits from 1 to 0) provided that they lie in consecutive addresses on the same page of memory. sector erase, half block erase, block erase and chip erase the page program (pp) or quad input page program (qpp) instruction allows bi ts to be reset from 1 to 0. before this can be applied, the bytes of memory need to have been erased to all 1s (ffh). this can be achieved a sector at a time, using the sector erase (se) instruction, half a block at a time using the half block erase (hbe) instruction, a block at a time using the block erase (be) instruction or throughout the entire memory, using the chip erase (ce) instruction. this starts an internal erase cycle (of duration t se , t hbe , t be or t ce ). the erase instruction must be preceded by a write enable (wren) instruction. polling during a write, program or erase cycle a further improvement in the time to write status register (wrsr), program (pp, qpp) or erase (se, hbe, be or ce) can be achieved by not waiting for the worst case delay (t w , t pp , t se , t hbe , t be or t ce ). the write in progress (wip) bit is provided in the status register so that the application program can monitor its value, polling it to esta blish when the previous write cycle, program cycle or erase cycle is complete. active power, stand-by power and deep power-down modes when chip select (cs#) is low, the device is enabled, and in the active power mode. when chip select (cs#) is high, the device is disabled, but could remain in the active power mode until all internal cycles have completed (program, erase, and write status register). the device then goes into the stand-by power mode. the device consumption drops to i cc1 . the deep power-down mode is entered when the specific instruction (the enter deep power-down mode (dp) instruction) is executed. the device consumption drops further to i cc2 . the device remains in this mode until another specif ic instruction (the release from deep power-down mode and read device id (rdi) instruction) is executed. all other instructions are ignored while the device is in the deep power-down mode. this can be used as an extra software protection mechanism, when the device is not in active use, to protect the device from inadvertent write, program or erase instructions. status register the status register contain a number of status and control bits that can be read or set (as appropriate) by specific instructions. wip bit. the write in progress (wip) bit indicates whethe r the memory is busy with a write status register, program or erase cycle. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. whdis bit. the wp# and hold# disable bit (whdis bit), non-volatile bit, it indicates the wp# and hold# are enabled or not. when it is ?0? (factory default), the wp# and hold# are enabled. on the other hand, while whdis bit is ?1?, the wp# and hold# are disabled. no matter whdis is 0 or 1 , the system can executes quad input/output fast_read (ebh), quad input page program (32h) or eqpi (38h) command directly. user can use flash programmer to set whdis bit as 1 and then the host system can let wp# and hold# keep floating in spi mode. srp bit / otp_lock bit the status register protect (srp) bit operates in conjunction with the write protect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode. in this mode, the non-volatile bits of the status register (srp, bp3, bp2, bp1, bp0) become read-only bits. in otp mode, this bit serves as otp_lock bit, user can read/program/erase otp sector as normal this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 9 EN25F20A rev. a, issue date: 2013 / 11 / 18 sector while otp_lock bit value is equal 0, after otp_lock bit is programmed with 1 by wrsr command, the otp sector is protected from program and erase operation. the otp_lock bit can only be programmed once. note : in otp mode, the wrsr command will ignore any input data and program otp_lock bit to 1, user must clear the protect bits before entering otp mode and program the otp code, then execute wrsr command to lock the otp sector before leaving otp mode. write protection applications that use non-volatile me mory must take into consideratio n the possibility of noise and other adverse system conditions that may compromise data integrity. to address this concern the EN25F20A provides the following data protection mechanisms: z power-on reset and an internal timer (t puw ) can provide protection against inadvertent changes while the power supply is outside the operating specification. z program, erase and write status register instructions are checked that they consist of a number of clock pulses that is a multiple of eight, before they are accepted for execution. z all instructions that modify data must be preceded by a write enable (wren) instruction to set the write enable latch (wel) bit. this bit is returned to its reset state by the following events: ? power-up ? write disable (wrdi) instruction completion or write status register (wrsr) instruction completion or page program (pp), quad input page program (qpp) instruction completion or sector erase (se) instruction completion or half block erase (hbe) / block erase (be) instruction completion or chip erase (ce) instruction completion z the block protect (bp3, bp2, bp1, bp0) bits allow part of the memory to be configured as read- only. this is the software protected mode (spm). z the write protect (wp#) signal allows the block protect (bp3, bp2, bp1, bp0) bits and status register protect (srp) bit to be protected. this is the hardware protected mode (hpm). z in addition to the low power consumption feature, the deep power-down mode offers extra software protection from inadvertent write, program and erase instructions, as all instructions are ignored except one particular instruction (the release from deep power-down instruction). table 3. protected area sizes sector organization status register content memory content bp3 bit bp2 bit bp1 bit bp0 bit protect areas addresses density(kb) portion 0 0 0 0 none none none none 0 0 0 1 block 3 030000h-03ffffh 64kb upper 1/4 0 0 1 0 block 2 to 3 020000h-03ffffh 128kb upper 2/4 0 0 1 1 block 1 to 3 010000h-03ffffh 192kb upper 3/4 0 1 0 0 all 000000h-03ffffh 256kb all 0 1 0 1 all 000000h-03ffffh 256kb all 0 1 1 0 all 000000h-03ffffh 256kb all 0 1 1 1 all 000000h-03ffffh 256kb all 1 0 0 0 none none none none 1 0 0 1 block 0 000000h-00ffffh 64kb lower 1/4 1 0 1 0 block 0 to 1 000000h-01ffffh 128kb lower 2/4 1 0 1 1 block 0 to 2 000000h-02ffffh 192kb lower 3/4 1 1 0 0 all 000000h-03ffffh 256kb all 1 1 0 1 all 000000h-03ffffh 256kb all 1 1 1 0 all 000000h-03ffffh 256kb all 1 1 1 1 all 000000h-03ffffh 256kb all this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 10 EN25F20A rev. a, issue date: 2013 / 11 / 18 instructions all instructions, addresses and data are shifted in and out of the device, most significant bit first. serial data input (di) is sampled on the first rising edge of serial clock (clk) after chip select (cs#) is driven low. then, the one-byte instruction code must be shifted in to the device, most significant bit first, on serial data input (di), each bit being latched on the rising edges of serial clock (clk). the instruction set is listed in tabl e 4. every instruction sequence st arts with a one-byte instruction code. depending on the instruction, this might be followed by address bytes, or by data bytes, or by both or none. chip select (cs#) must be driven high after the last bit of the instruction sequence has been shifted in. in the case of a read data bytes (read), read data bytes at higher speed (fast_read), dual output fast read (3bh), dual i/o fast read (bbh), quad input/output fast_read (ebh), read status register (rdsr), read information register (rdifr) or release from deep power-down, and read device id (rdi) in struction, the shifted-in instruction sequence is followed by a data-out sequence. chip select (cs#) can be driven high after any bit of the data-out sequence is being shifted out. in the case of a page program (pp), quad input page program (qpp), sector erase (se), half block erase (hbe), block erase (be), chip erase (ce), write status register (wrsr), write enable (wren), write disable (wrdi) or deep power-down (dp) instruction, chip select (cs#) must be driven high exactly at a byte boundary, otherwise the instruction is rejected, and is not executed. that is, chip select (cs#) must driven high when the number of clock pulses after chip select (cs#) being driven low is an exact multiple of eight. for page program, if at any time the input byte is not a full byte, nothing will happen and wel will not be reset. in the case of multi-byte commands of page program (pp), quad input page program (qpp) and release from deep power down (res ) minimum number of bytes specified has to be given, without which, the command will be ignored. in the case of page program, if the number of byte after the command is less than 4 (at least 1 data byte), it will be ignored too. in the case of se, hbe and be, exact 24-bit address is a must, any less or more will cause the command to be ignored. all attempts to access the memory array during a writ e status register cycle, program cycle or erase cycle are ignored, and the internal write status register cycle, program cycle or erase cycle continues unaffected. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 11 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 4a. instruction set instruction name byte 1 code byte 2 byte 3 byte 4 byte 5 byte 6 n-bytes eqpi 38h rstqio (1) release quad i/o or fast read enhanced mode ffh rsten 66h rst (2) 99h write enable 06h write disable / exit otp mode 04h read status register 05h (s7-s0) (3) continuous (4) write status register 01h s7-s0 page program 02h a23-a16 a15-a8 a7-a0 d7-d0 next byte continuous quad input page program 32h a23-a16 a15-a8 a7-a0 (d7-d0, ?) (5) (one byte per 2 clocks, continuous) sector erase 20h a23-a16 a15-a8 a7-a0 32kb half block erase (hbe) 52h a23-a16 a15-a8 a7-a0 64kb block erase d8h a23-a16 a15-a8 a7-a0 chip erase c7h/ 60h deep power-down b9h release from deep power-down, and read device id dummy dummy dummy (id7-id0) (6) release from deep power-down abh 00h (m7-m0) (id7-id0) manufacturer/ device id 90h dummy dummy 01h (id7-id0) (m7-m0) (7) read identification 9fh (m7-m0) (id15-id8) (id7-id0) (8) enter otp mode 3ah read sfdp mode and unique id number 5ah a23-a16 a15-a8 a7-a0 dummy (d7-d0) (next byte) continuous notes: 1. device accepts eight-clocks command in standard spi mode, or two-clocks command in quad spi mode 2. rst command only executed if rsten command is exec uted first. any intervening command will disable reset. 3. data bytes are shifted with most significant bit first. byte fields with data in parenthesis ?( )? indicate data being read from the device on the do pin 4. the status register contents will repeat continuously until cs# terminate the instruction 5. quad data dq 0 = (d4, d0, ?? ) dq 1 = (d5, d1, ?? ) dq 2 = (d6, d2, ?... ) dq 3 = (d7, d3, ?... ) 6. the device id will repeat continuously until cs# terminates the instruction 7. the manufacturer id and device id bytes will repeat continuously until cs# terminates the instruction. 00h on byte 4 starts with mid and alternate with did, 01h on byte 4 starts with did and alternate with mid 8. (m7-m0) : manufacturer, (id15-id8) : memory type, (id7-id0) : memory capacity this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 12 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 4b. instruction set (read instruction) instruction name op code address bits dummy bits / clocks (default) data out remark read data 03h 24 bits 0 (d7-d0, ?) (next byte) continuous fast read 0bh 24 bits 8 bits / 8 clocks (d7-d0, ?) (next byte) continuous dual output fast read 3bh 24 bits 8 bits / 8 clocks (d7-d0, ?) (one byte per 4 clocks, continuous) dual i/o fast read bbh 24 bits 8 bits / 4 clocks (d7-d0, ?) (one byte per 4 clocks, continuous) quad i/o fast read ebh 24 bits 24 bits / 6 clocks (d7-d0, ?) (one byte per 2 clocks, continuous) table 4c. instruction set (read instruction support mode and dummy cycle setting) start from spi/qpi dummy cycle instruction name op code spi qpi spi qpi read data 03h yes no n/a n/a fast read 0bh yes yes 8 clocks 6 clocks dual output fast read 3bh yes no 8 clocks n/a dual i/o fast read bbh yes no 4 clocks n/a quad i/o fast read ebh yes yes 6 clocks 6 clocks quad input/output fast read enhance performance mode ebh yes yes 6 clocks ( 2 clocks are performance enhance indicator) 6 clocks ( 2 clocks are performance enhance indicator) note: 1. ?start from spi/qpi' means if this command is initiated from spi or qpi mode. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 13 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 5. manufacturer and device identification op code (m7-m0) (id15-id0) (id7-id0) abh 11h 90h 1ch 11h 9fh 1ch 3112h enable quad peripheral interface mode (eqpi) (38h) the enable quad peripheral interface mode (eqpi) instruction will enable the flash device for quad spi bus operation. upon completion of the instruction, all inst ructions thereafter will be 4-bit multiplexed input/output until a power cycle or ? reset quad i/o instruction ? instruction, as shown in figure 6. the device did not support the read data bytes (read) (03h) , dual output fast read (3bh), dual input/output fast_read (bbh) and quad input page program (32h) modes while the enable quad peripheral interface mode (eqpi) (38h) turns on. figure 6. enable quad peripheral interface mode sequence diagram reset quad i/o (rstqio) or release quad i/o fast read enhancement mode (ffh) the reset quad i/o instruction resets the device to 1-bit standard spi operation. to execute a reset quad i/o operation, the host drives cs# low, sends the reset quad i/o command cycle (ffh) then, drives cs# high. this command can?t be used in standard spi mode. user also can use the 0xffh command to release the quad i/o fast read enhancement mode. the detail description, please see the quad i/o fast read enhancement mode section. note: if the system is in the quad i/o fast read enhance mode in qpi mode, it is necessary to execute 0xffh command by two times. the first 0xffh command is to release quad i/o fast read enhance mode, and the second 0xffh command is to release qpi mode. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 14 EN25F20A rev. a, issue date: 2013 / 11 / 18 reset-enable (rsten) (66h) and reset (rst) (99h) the reset operation is used as a system (software) reset that puts the device in normal operating ready mode. this operation consists of two commands: reset-enable (rsten) and reset (rst). to reset the EN25F20A the host drives cs# low, sends the reset-enable command (66h), and drives cs# high. next, the host drives cs# low again, sends the reset command (99h), and drives cs# high. the reset operation requires the reset-enable command followed by the reset command. any command other than the reset command after the reset-enable command will disable the reset- enable. a successful command execution will re set the status register and the information register to data = 00h, see figure 7 for spi mode and figure 7.1 for qpi mode. a device reset during an active program or erase operation aborts the operation, which can cause the data of the targeted address range to be corrupted or lost. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more software latency time (t sr ) than recovery from other operations. please figure 7.2. figure 7. reset-enable and reset sequence diagram figure 7.1 reset-enable and reset sequence diagram in qpi mode figure 7.2 software reset recovery this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 15 EN25F20A rev. a, issue date: 2013 / 11 / 18 software reset flow initial command = 66h ? reset enable command = 99h ? reset start wip = 0 ? reset done embedded reset cycle yes no no yes no yes note: 1. reset-enable (rsten) (66h) and reset (rst) (99h) commands need to match standard spi or qpi (full quad) mode. 2. continue (enhance) eb mode need to use quad reset-enable (rsten) (66h) and quad reset (rst) (99h) commands. 3. if user is not sure it is in spi or quad mode, we suggest to execute sequence as follows: quad reset-enable (rsten) (66h) -> quad reset (rst) (99h) -> spi reset-enable (rsten) (66h) -> spi reset (rst) (99h) to reset. 4. the reset command could be executed during embedded program and erase process, qpi mode and continue eb mode to back to spi mode. 5. this flow cannot release the device from deep power down mode. 6. the status register bit and information register bit will reset to default value after reset done. 7. if user reset device during erase, the embedded reset cycle software reset latency will take about 28us in worst case. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 16 EN25F20A rev. a, issue date: 2013 / 11 / 18 write enable (wren) (06h) the write enable (wren) instruction (figure 8) sets the write enable latch (wel) bit. the write enable latch (wel) bit must be set prior to every page program (pp), quad input page program (qpp), sector erase (se), half block erase (hbe), block erase (be), chip erase (ce) and write status register (wrsr) instruction. the write enable (wren) instruction is entered by driving chip select (cs#) low, sending the instruction code, and then driving chip select (cs#) high. the instruction sequence is shown in figure 9.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 8. write enable instruction sequence diagram write disable (wrdi) (04h) the write disable instruction (figure 9) resets the write enable latch (wel) bit in the status register to a 0 or exit from otp mode to normal mode. the write disable instruction is entered by driving chip select (cs#) low, shifting the instruction code ?04h? into the di pin and then driving chip select (cs#) high. note that the wel bit is automatically reset after power-up and upon completion of the write status register, page program (pp), quad input page program (qpp), sector erase, half block erase (hbe), block erase (be) and chip erase instructions. the instruction sequence is shown in figure 9.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 9. write disable instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 17 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 9.1 write enable/disable instruction sequence in qpi mode read status register (rdsr) (05h) the read status register (rdsr) instruction allows the status register to be read. the status register may be read at any time, even while a program, erase or write status register cycle is in progress. when one of these cycles is in progress, it is recommended to check the write in progress (wip) bit before sending a new instruction to the device. it is also possible to read the status register continuously, as shown in figure 10. the instruction sequence is shown in figure 10.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 10. read status register instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 18 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 10.1 read status register instruction sequence in qpi mode table 6. status register bit locations s7 s6 s5 s4 s3 s2 s1 s0 srp status register protect otp_lock bit (note 1) whdis wp# & hold# disable bit bp3 (block protected bits) bp2 (block protected bits) bp1 (block protected bits) bp0 (block protected bits) wel (write enable latch) wip (write in progress bit) (note 3) 1 = status register write disable 1 = otp sector is protected 1 = wp# and hold# disable 0 = wp# and hold# enable (note 2) (note 2) (note 2) (note 2) 1 = write enable 0 = not write enable 1 = write operation 0 = not in write operation non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit non-volatile bit volatile bit volatile bit note 1. in otp mode, srp bit is served as otp_lock bit. 2. see the table ? protected area sizes sector organization?. the status and control bits of the status register are as follows: wip bit. the write in progress (wip) bit indicates whether the memory is busy with a write status register, program or erase cycle. when set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress. wel bit. the write enable latch (wel) bit indicates the status of the internal write enable latch. when set to 1 the internal write enable latch is set, when set to 0 the internal write enable latch is reset and no write status register, program or erase instruction is accepted. bp3, bp2, bp1, bp0 bits. the block protect (bp3, bp2, bp1, bp0) bits are non-volatile. they define the size of the area to be software protected against program and erase instructions. these bits are written with the write status register (wrsr) instruction. when one or both of the block protect (bp3, bp2, bp1, bp0) bits is set to 1, the relevant memory area (as defined in table 3.) becomes protected against page program (pp), quad input page program (qpp), sector erase (se) and , block erase (be), instructions. the block protect (bp3, bp2, bp1, bp0) bits can be written provided that the hard- ware protected mode has not been set. the chip erase (ce) instruction is executed if, and only if, all block protect (bp3, bp2, bp1, bp0) bits are 0. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 19 EN25F20A rev. a, issue date: 2013 / 11 / 18 whdis bit. the wp# and hold# disable bit (whdis bit), non-volatile bit, it indicates the wp# and hold# are enabled or not. when it is ?0? (factory default), the wp# and hold# are enabled. on the other hand, while whdis bit is ?1?, the wp# and hold# are disabled. no matter whdis is 0 or 1 , the system can executes quad input/output fast_read (ebh), quad input page program (32h) or eqpi (38h) command directly. user can use flash programmer to set whdis bit as 1 and then the host system can let wp# and hold# keep floating in spi mode. srp bit / otp_lock bit. the status register protect (srp) bit operates in conjunction with the write protect (wp#) signal. the status register write protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (when the status register protect (srp) bit is set to 1, and write protect (wp#) is driven low). in this mode, the non-volatile bits of the status register (srp, bp3, bp2, bp1, bp0) become read-only bits and the write status register (wrsr) instruction is no longer accepted for execution. in otp mode, this bit serves as otp_lock bit, user can read/program/erase otp sector as normal sector while otp_lock bit value is equal 0, after otp_lock bit is programmed with 1 by wrsr command, the otp sector is protected from program and erase operation. the otp_lock bit can only be programmed once. note : in otp mode, the wrsr command will ignore any input data and program otp_lock bit to 1, user must clear the protect bits before enter otp mode and program the otp code, then execute wrsr command to lock the otp sector before leaving otp mode. write status register (wrsr) (01h) the write status register (wrsr) instruction allows new values to be written to the status register. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded and executed, the device sets the write enable latch (wel). the write status register (wrsr) instruction is entered by driving chip select (cs#) low, followed by the instruction code and the data byte on serial data input (di). the instruction sequence is shown in figure 11. the write status register (wrsr) instruction has no effect on s1 and s0 of the status register. chip select (cs#) must be driven high after the eighth bit of the data byte has been latched in. if not, the write status register (wrsr) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed write status register cycle (whose duration is t w ) is initiated. while the write status register cycle is in progress, the status register may still be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed write status register cycle, and is 0 when it is completed. when the cycle is completed, the write enable latch (wel) is reset. the write status register (wrsr) instruction allows the user to change the values of the block protect (bp3, bp2, bp1, bp0) bits, to define the size of the area that is to be treated as read-only, as defined in table 3. the write status register (wrsr) instruction also allows the user to set or reset the status register protect (srp) bit in accordance with the write protect (wp#) signal. the status register protect (srp) bit and write protect (wp#) signal allow the device to be put in the hardware protected mode (hpm). the write status register (wrsr) instruction is not executed once the hardware protected mode (hpm) is entered. the instruction sequence is shown in figure 11.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. note : in the otp mode, wrsr command will igno re input data and program otp_lock bit to 1. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 20 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 11. write status register instruction sequence diagram figure 11.1 write status register instruction sequence in qpi mode this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 21 EN25F20A rev. a, issue date: 2013 / 11 / 18 read data bytes (read) (03h) the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes (read) instruction is followed by a 3-byte address (a23-a0), each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 12. the first byte addresses can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes (read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes (read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes (read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 12. read data instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 22 EN25F20A rev. a, issue date: 2013 / 11 / 18 read data bytes at higher speed (fast_read) (0bh) the device is first selected by driving chip select (cs#) low. the instruction code for the read data bytes at higher speed (fast_read) instruction is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency f r , during the falling edge of serial clock (clk). the instruction sequence is shown in figure 13. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single read data bytes at higher speed (fast_read) instruction. when the highest address is reached, the address counter rolls over to 000000h, allowing the read sequence to be continued indefinitely. the read data bytes at higher speed (fast_read) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes at higher speed (fast_read) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. the instruction sequence is shown in figure 13.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 13. fast read instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 23 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 13.1 fast read instruction sequence in qpi mode dual output fast read (3bh) the dual output fast read (3bh) is similar to the standard fast read (0bh) instruction except that data is output on two pins, dq 0 and dq 1 , instead of just dq 0 . this allows data to be transferred from the EN25F20A at twice the rate of standard spi devices. the dual output fast read instruction is ideal for quickly downloading code from to ram upon power-up or for applications that cache code- segments to ram for execution. similar to the fast read instruction, the dual output fast read instruction can operation at the highest possible frequency of fr (see ac electrical characteristics). this is accomplished by adding eight ?dummy clocks after the 24-bit address as shown in figure 14. the dummy clocks allow the device?s internal circuits additional time for setting up the initial address. the input data during the dummy clock is ?don?t care?. however, the di pin should be high-impedance prior to the falling edge of the first data out clock. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 24 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 14. dual output fast read instruction sequence diagram dual input / output fast_read (bbh) the dual i/o fast read (bbh) instruction allows for improved random access while maintaining two io pins, dq 0 and dq 1 . it is similar to the dual output fast read (3bh) instruction but with the capability to input the address bits (a23-a0) two bits per clock. this reduced instruction overhead may allow for code execution (xip) directly from the dual spi in some applications. the dual i/o fast read instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of clk, and data of every two bits (interleave 2 i/o pins) shift out on the falling edge of clk at a maximum frequency. the first address can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dual i/o fast read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing dual i/o fast read instruction, the following address/dummy/data out will perform as 2-bit instead of previous 1-bit, as shown in figure 15. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 25 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 15. dual input / output fast read instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 26 EN25F20A rev. a, issue date: 2013 / 11 / 18 quad input / output fast_read (ebh) the quad input/output fast_read (ebh) instruction is similar to the dual i/o fast read (bbh) instruction except that address and data bits are input and output through four pins, dq 0 , dq 1 , dq 2 and dq 3 and six dummy clocks are required prior to the data output. the quad i/o dramatically reduces instruction overhead allowing faster random access for code execution (xip) directly from the quad spi. the quad input/output fast_read (ebh) instruction enable quad throughput of serial flash in read mode. the address is latching on rising edge of clk, and data of every four bits (interleave on 4 i/o pins) shift our on the falling edge of clk at a maximum frequency f r . the first address can be any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single quad input/output fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. once writing quad input/output fast_read instruction, the following address/dummy/data out will perform as 4-bit instead of previous 1-bit. the sequence of issuing quad input/output fast_read (ebh) instruction is: cs# goes low -> sending quad input/output fast_read (ebh) instruction -> 24-bit address interleave on dq 3 , dq 2 , dq 1 and dq 0 -> 6 dummy cycles -> data out interleave on dq 3 , dq 2 , dq 1 and dq 0 -> to end quad input/output fast_read (ebh) operation can use cs# to high at any time during data out, as shown in figure 16. the instruction sequence is shown in figure 16.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 16. quad input / output fast read instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 27 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 16.1. quad input / output fast read instruction sequence in qpi mode another sequence of issuing quad input/output fast_read (ebh) instruction especially useful in random access is : cs# goes low -> sending quad input/output fast_read (ebh) instruction -> 24- bit address interleave on dq 3 , dq 2 , dq 1 and dq 0 -> performance enhance toggling bit p[7:0] -> 4 dummy cycles -> data out interleave on dq 3 , dq 2 , dq 1 and dq 0 till cs# goes high -> cs# goes low (reduce quad input/output fast_read (ebh) instruction) -> 24-bit access address, as shown in figure 17. in the performance ? enhancing mode, p[7:4] must be toggling with p[3:0] ; likewise p[7:0] = a5h, 5ah, f0h or 0fh can make this mode continue and reduce the next quad input/output fast_read (ebh) instruction. once p[7:4] is no longer toggling with p[3:0] ; likewise p[7:0] = ffh, 00h, aah or 55h. and afterwards cs# is raised, the system then will escape from performance enhance mode and return to normal operation. while program/ erase/ write status register is in progress, quad input/output fast_read (ebh) instruction is rejected without impact on the program/ erase/ write status register current cycle. the instruction sequence is shown in figure 17.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 28 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 17. quad input/output fast read enhance performance mode sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 29 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 17.1 quad input/output fast read en hance performance mode sequence in qpi mode this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 30 EN25F20A rev. a, issue date: 2013 / 11 / 18 page program (pp) (02h) the page program (pp) instruction allows bytes to be programmed in the memory. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the page program (pp) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, three address bytes and at least one data byte on serial data input (di). if the 8 least significant address bits (a7-a0) are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits (a7-a0) are all zero). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 18. if more than 256 bytes are sent to the device, pre- viously latched data are discarded and the last 256 data bytes are guaranteed to be programmed cor- rectly within the same page. if less than 256 data bytes are sent to device, they are correctly pro- grammed at the requested addresses without having any effects on the other bytes of the same page. chip select (cs#) must be driven high after the eighth bit of the last data byte has been latched in, otherwise the page program (pp) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed page program cycle (whose duration is t pp ) is initiated. while the page program cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed page program cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a page program (pp) instruction applied to a page which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 18.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 18. page program instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 31 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 18.1 program instruction sequence in qpi mode quad input page program (qpp) (32h) the quad page program (qpp) instruction allows up to 256 bytes of data to be programmed at previously erased (ffh) memory locations using four pins: dq 0 , dq 1 , dq 2 and dq 3 . the quad page program can improve performance for prom programmer and applications that have slow clock speeds < 5mhz. systems with faster clock speed will not realize much benefit for the quad page program instruction since the inherent page program time is much greater than the time it take to clock- in the data. a write enable instruction must be executed before the device will accept the quad page program (qpp) instruction (status register-1, wel=1). the instruction is initiated by driving the cs# pin low then shifting the instruction code ?32h? followed by a 24-bit address (a23-a0) and at least one data byte, into the io pins. the cs# pin must be held low for the entire length of the instruction while data is being sent to the device. all other functions of quad page program (qpp) are identical to standard page program. the quad page program (qpp) instruction sequence is shown in figure 19. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 32 EN25F20A rev. a, issue date: 2013 / 11 / 18 cs# clk dq0 dq1 dq2 dq3 32h command 3 address bytes (24 clocks) 089102829 a23 a21 a22 a3 a2 1 234567 cs# clk dq0 dq1 dq2 dq3 31 data byte 255 data byte 256 data byte 1 data byte 2 data byte 3 d4 d5 d6 d7 d0 d1 d2 d3 32 33 34 35 36 37 30 31 a1 a0 * * = msb a0 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 534 535 536 537 538 539 data byte 252 data byte 253 data byte 254 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 d4 d5 d6 d7 d0 d1 d2 d3 543 542 541 540 *** ***** figure 19. quad input page program instruction sequence diagram (spi mode only) sector erase (se) (20h) the sector erase (se) instruction sets to 1 (ffh) all bits inside the chosen sector. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the sector erase (se) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, and three address bytes on serial data input (di). any address inside the sector (see table 2) is a valid address for the sector erase (se) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 20. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the sector erase (se) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed sector erase cycle (whose du- ration is t se ) is initiated. while the sector erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 33 EN25F20A rev. a, issue date: 2013 / 11 / 18 self-timed sector erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a sector erase (se) instruction applied to a sector which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 22.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 20. sector erase instruction sequence diagram 32kb half block erase (hbe) (52h) the half block erase (hbe) instruction sets to 1 (ffh) all bits inside the chosen block. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the half block erase (hbe) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, and three address bytes on serial data input (di). any address inside the block (see table 2) is a valid address for the half block erase (hbe) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 21. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the half block erase (hbe) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed half block erase cycle (whose duration is t hbe ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed half block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a half block erase (hbe) instruction applied to a block which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 22.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 34 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 21. 32kb half block erase instruction sequence diagram 64kb block erase (be) (d8h) the block erase (be) instruction sets to 1 (ffh) all bits inside the chosen block. before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the block erase (be) instruction is entered by driving chip select (cs#) low, followed by the in- struction code, and three address bytes on serial data input (di). any address inside the block (see table 2) is a valid address for the block erase (be) instruction. chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 22. chip select (cs#) must be driven high after the eighth bit of the last address byte has been latched in, otherwise the block erase (be) instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed block erase cycle (whose du- ration is t be ) is initiated. while the block erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self- timed block erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. a block erase (be) instruction applied to a block which is protected by the block protect (bp3, bp2, bp1, bp0) bits (see table 3) is not executed. the instruction sequence is shown in figure 22.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 35 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 22. 64kb block erase instruction sequence diagram figure 22.1 half block/block/sector erase instruction sequence in qpi mode this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 36 EN25F20A rev. a, issue date: 2013 / 11 / 18 chip erase (ce) (c7h/60h) the chip erase (ce) instruction sets all bits to 1 (ffh). before it can be accepted, a write enable (wren) instruction must previously have been executed. after the write enable (wren) instruction has been decoded, the device sets the write enable latch (wel). the chip erase (ce) instruction is entered by driving chip select (cs#) low, followed by the instructio n code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 23. chip select (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the chip erase instruction is not executed. as soon as chip select (cs#) is driven high, the self-timed chip erase cycle (whose duration is t ce ) is initiated. while the chip erase cycle is in progress, the status register may be read to check the value of the write in progress (wip) bit. the write in progress (wip) bit is 1 during the self-timed chip erase cycle, and is 0 when it is completed. at some unspecified time before the cycle is completed, the write enable latch (wel) bit is reset. the chip erase (ce) instruction is executed only if all block protect (bp3, bp2, bp1, bp0) bits are 0. the chip erase (ce) instruction is ignored if one, or more blocks are protected. the instruction sequence is shown in figure 23.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 23. chip erase instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 37 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 23.1 chip erase sequence in qpi mode deep power-down (dp) (b9h) executing the deep power-down (dp) instruction is the only way to put the device in the lowest con- sumption mode (the deep power-down mode). it can also be used as an extra software protection mechanism, while the device is not in active use, since in this mode, the device ignores all write, program and erase instructions. driving chip select (cs#) high deselects the device, and puts the device in the standby mode (if there is no internal cycle currently in progress). but this mode is not the deep power-down mode. the deep power-down mode can only be entered by executing the deep power-down (dp) instruction, to reduce the standby current (from i cc1 to i cc2 , as specified in table 12.) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) instruction. this releases the device from this mode. the release from deep power-down and read device id (rdi) instruction also allows the device id of the device to be output on serial data output (do). the deep power-down mode automatically stops at power-down, and the device always powers-up in the standby mode. the deep power-down (dp) instruction is entered by driving chip select (cs#) low, followed by the instruction code on serial data input (di). chip select (cs#) must be driven low for the entire duration of the sequence. the instruction sequence is shown in figure 24. chip select (cs#) must be driven high after the eighth bit of the instruction code has been latched in, otherwise the deep power-down (dp) instruction is not executed. as soon as chip select (cs#) is driven high, it requires a delay of t dp before the supply current is reduced to i cc2 and the deep power-down mode is entered. any deep power-down (dp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 38 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 24. deep power-down instruction sequence diagram release from deep power-down and read device id (rdi) once the device has entered the deep power-down mode, all instructions are ignored except the release from deep power-down and read device id (rdi) instruction. executing this instruction takes the device out of the deep power-down mode. please note that this is not the same as, or even a subset of, the jedec 16-bit electronic signature that is read by the read identifier (rdid) instruction. the old-style electronic signature is supported for reasons of backward compatibility, only, and should not be used for new designs. new designs should, instead, make use of the jedec 16-bit electronic signature, and the read identifier (rdid) instruction. when used only to release the device from the power-down state, the instruction is issued by driving the cs# pin low, shifting the instruction code ?abh? and driving cs# high as shown in figure 25. after the time duration of t res1 (see ac characteristics) the device will resume normal operation and other instructions will be accepted. the cs# pin must remain high during the t res1 time duration. when used only to obtain the device id while not in the power-down state, the instruction is initiated by driving the cs# pin low and shifting the instruction code ?abh? followed by 3-dummy bytes. the device id bits are then shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 26. the device id value for the EN25F20A are listed in table 5. the device id can be read continuously. the instruction is completed by driving cs# high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the standby power mode is delayed by t res2 , and chip select (cs#) must remain high for at least t res2 (max), as specified in table 14. once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. except while an erase, program or write status register cycle is in progress, the release from deep power-down and read device id (rdi) instruction always provides access to the 8bit device id of the device, and can be applied even if the deep power-down mode has not been entered. any release from deep power-down and read device id (rdi) instruction while an erase, program or write status register cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 39 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 25. release power-down instruction sequence diagram figure 26. release power-down / device id instruction sequence diagram read manufacturer / device id (90h) the read manufacturer/device id instruction is an alternative to the release from power-down / device id instruction that provides both the jedec assigned manufacturer id and the specific device id. the read manufacturer/device id instruction is very similar to the release from power-down / device id instruction. the instruction is initiated by driving the cs# pin low and shifting the instruction code ?90h? followed by a 24-bit address of 000000h. after which, the manufacturer id for eon (1ch) and the device id are shifted out on the falling edge of clk with most significant bit (msb) first as shown in figure 27. the device id values for the EN25F20A are listed in table 5. if the 24-bit address is initially set to 000001h the device id will be read first the instruction sequence is shown in figure 27.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 40 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 27. read manufacturer / device id diagram figure 27.1. read manufacturer / device id diagram in qpi mode this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 41 EN25F20A rev. a, issue date: 2013 / 11 / 18 read identification (rdid) (9fh) the read identification (rdid) instruction allows the 8-bit manufacturer identification to be read, followed by two bytes of device identification. the device identification indicates the memory type in the first byte , and the memory capacity of the device in the second byte . any read identification (rdid) instruction while an erase or program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress. the read identification (rdid) instruction should not be issued while the device is in deep power down mode. the device is first selected by driving chip select low. then, the 8-bit instruction code for the instruction is shifted in. this is followed by the 24-bit device identification, stored in the memory, being shifted out on serial data output, each bit being shifted out during the falling edge of serial clock. the instruction sequence is shown in figure 28. the read identification (rdid) instruction is terminated by driving chip select high at any time during data output. when chip select is driven high, the device is put in the standby power mode. once in the standby power mode, the device waits to be selected, so that it can receive, decode and execute instructions. the instruction sequence is shown in figure 28.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. figure 28. read identification (rdid) this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 42 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 28.1. read identification (rdid) in qpi mode enter otp mode (3ah) this flash has an extra 512 bytes otp sector, user must issue enter otp mode command to read, program or erase otp sector. after entering otp mode, the otp sector is mapping to sector 63, srp bit becomes otp_lock bit and can be read with rdsr command. the chip erase, bank erase and half bank erase commands are also disabled. in otp mode, user can read other sectors, but program/erase other sectors only allowed when otp_lock bit equal to ?0?. wrsr command will ignore the input data and program otp_lock bit to 1. user can use wrdi (04h) command to exit otp mode. the instruction sequence is shown in figure 28.1 while using the enable quad peripheral interface mode (eqpi) (38h) command. erase otp command (20h) user only can use sector erase (20h) command to erase otp data. table 7. otp sector address sector sector size address range 63 512 byte 03f000h ? 03f1ffh note: the otp sector is mapping to sector 63. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 43 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 29. enter otp mode sequence figure 29.1 enter otp mode sequence in qpi mode this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 44 EN25F20A rev. a, issue date: 2013 / 11 / 18 read sfdp mode and unique id number (5ah) read sfdp mode EN25F20A features serial flash discoverable parameters (sfdp) mode. host system can retrieve the operating characteristics, structure and vendor specified information such as identifying information, memory size, operating voltage and timing information of this device by sfdp mode. the device is first selected by driving chip select (cs#) low. the instruction code for the read sfdp mode is followed by a 3-byte address (a23-a0) and a dummy byte, each bit being latched-in during the rising edge of serial clock (clk). then the memory contents, at that address, is shifted out on serial data output (do), each bit being shifted out, at a maximum frequency fr, during the falling edge of serial clock (clk). the instruction sequence is shown in figure 30. the first byte addressed can be at any location. the address is automatically incremented to the next higher address after each byte of data is shifted out. the whole memory can, therefore, be read with a single serial flash discoverable parameters (sfdp) instruction. when the highest address is reached, the address counter rolls over to 0x00h, allowing the read sequence to be continued indefinitely. the serial flash discoverable parameters (sfdp) instruction is terminated by driving chip select (cs#) high. chip select (cs#) can be driven high at any time during data output. any read data bytes at serial flash discoverable parameters (sfdp) instruction, while an erase, program or write cycle is in progress, is rejected without having any effects on the cycle that is in progress. figure 30. read sfdp mode and unique id number instruction sequence diagram this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 45 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 8. serial flash discoverable parameters (sfdp) signature and parameter identification data value (advanced information) description address (h) (byte mode) address (bit) data comment 00h 07 : 00 53h 01h 15 : 08 46h 02h 23 : 16 44h sfdp signature 03h 31 : 24 50h signature [31:0]: hex: 50444653 sfdp minor revision number 04h 07 : 00 00h star from 0x00 sfdp major revision number 05h 15 : 08 01h star from 0x01 number of parameter headers (nph) 06h 23 : 16 00h 1 parameter header unused 07h 31 : 24 ffh reserved id number 08h 07 : 00 00h jedec id parameter table minor revision number 09h 15 : 08 00h star from 0x00 parameter table major revision number 0ah 23 : 16 01h star from 0x01 parameter table length (in dw) 0bh 31 : 24 09h 9 dwords 0ch 07 : 00 30h 0dh 15 : 08 00h parameter table pointer (ptp) 0eh 23 : 16 00h 000030h unused 0fh 31 : 24 ffh reserved this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 46 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 9. parameter id (0) (advanced information) 1/9 description address (h) (byte mode) address (bit) data comment 00 block / sector erase sizes identifies the erase granularity for all flash components 01 01b 00 = reserved 01 = 4kb erase 10 = reserved 11 = 64kb erase write granularity 02 1b 0 = no, 1 = yes write enable instru ction required for writing to volatile status register 03 write enable opcode select for writing to volatile status register 04 00b 00 = n/a 01 = use 50h opcode 11 = use 06h opcode 05 06 unused 30h 07 111b reserved 08 09 10 11 12 13 14 4 kilo-byte erase opcode 31h 15 20h 4 kb erase support (ffh = not supported) supports (1-1-2) fast read device supports single input opcode & address and dual output data fast read 16 1b 0 = not supported 1 = supported 17 address byte n umber of bytes used in addressing for flash arr a w rite and erase. 18 00b 00 = 3-byte 01 = 3- or 4-byte (e.g. defaults to 3-byte mode; enters 4-byte mode on command) 10 = 4-byte 11 = reserved supports double transfer rate (dtr) clocking indicates the device supports some type of double transfer rate clocking. 19 0b 0 = not supported 1 = supported supports (1-2-2) fast read device supports single input opcode, dual input address, and dual output data fast read 20 1b 0 = not supported 1 = supported supports (1-4-4) fast read device supports single input opcode, quad input address, and quad output data fast read 21 1b 0 = not supported 1 = supported supports (1-1-4) fast read device supports single input opcode & address and quad output data fast read 22 0b 0 = not supported 1 = supported unused 32h 23 1b reserved 24 25 26 27 28 29 30 unused 33h 31 ffh reserved this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 47 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 9. parameter id (0) (advanced information) 2/9 description address (h) (byte mode) address (bit) data comment flash memory density 37h : 34h 31 : 00 001fffffh 2 mbits table 9. parameter id (0) (advanced information) 3/9 description address (h) (byte mode) address (bit) data comment 00 01 02 03 (1-4-4) fast read number of wait states (dummy clocks) needed before valid output 04 00100b 4 dummy clocks 05 06 quad input address quad output (1-4- 4) fast read number of mode bits 38h 07 010b 8 mode bits 08 09 10 11 12 13 14 (1-4-4) fast read opcode opcode for single input opcode, quad input address, and quad output data fast read. 39h 15 ebh 16 17 18 19 (1-1-4) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (1-1-4) fast read number of mode bits 3ah 23 000b not supported (1-1-4) fast read opcode opcode for single input opcode & address and quad output data fast read. 3bh 31 : 24 ffh not supported this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 48 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 9. parameter id (0) (advanced information) 4/9 description address (h) (byte mode) address (bit) data comment 00 01 02 03 (1-1-2) fast read number of wait states (dummy clocks) needed before valid output 04 01000b 8 dummy clocks 05 06 (1-1-2) fast read number of mode bits 3ch 07 000b not supported (1-1-2) fast read opcode opcode for single input opcode & address and dual output data fast read. 3dh 15 : 08 3bh 16 17 18 19 (1-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (1-2-2) fast read number of mode bits 3eh 23 000b not supported (1-2-2) fast read opcode opcode for single input opcode, dual input address, and dual output data fast read. 3fh 31 : 24 bbh table 9. parameter id (0) (advanced information) 5/9 description address (h) (byte mode) address (bit) data comment supports (2-2-2) fast read device supports dual input opcode & address and dual output data fast read. 00 0b 0 = not supported 1 = supported 01 02 reserved. these bits default to all 1?s 03 111b reserved supports (4-4-4) fast read device supports quad input opcode & address and quad output data fast read. 04 1b 0 = not supported 1 = supported (qpi mode) 05 06 reserved. these bits default to all 1?s 40h 07 111b reserved reserved. these bits default to all 1?s 43h : 41h 31 : 08 ffh reserved this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 49 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 9. parameter id (0) (advanced information) 6/9 description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 45h : 44h 15 : 00 ffh reserved 16 17 18 19 (2-2-2) fast read number of wait states (dummy clocks) needed before valid output 20 00000b not supported 21 22 (2-2-2) fast read number of mode bits 46h 23 000b not supported (2-2-2) fast read opcode opcode for dual input opcode & address and dual output data fast read. 47h 31 : 24 ffh not supported table 9. parameter id (0) (advanced information) 7/9 description address (h) (byte mode) address (bit) data comment reserved. these bits default to all 1?s 49h : 48h 15 : 00 ffh reserved 16 17 18 19 (4-4-4) fast read number of wait states (dummy clocks) needed before valid output 20 00100b 4 dummy clocks 21 22 (4-4-4) fast read number of mode bits 4ah 23 010b 8 mode bits (4-4-4) fast read opcode opcode for quad input opcode/address, quad output data fast read. 4bh 31 : 24 ebh must enter qpi mode firstly table 9. parameter id (0) (advanced information) 8/9 description address (h) (byte mode) address (bit) data comment sector type 1 size 4ch 07 : 00 0ch 4 kb sector type 1 opcode 4dh 15 : 08 20h sector type 2 size 4eh 23 : 16 0fh 32 kb sector type 2 opcode 4fh 31 : 24 52h table 9. parameter id (0) (advanced information) 9/9 description address (h) (byte mode) address (bit) data comment sector type 3 size 50h 07 : 00 10h 64 kb sector type 3 opcode 51h 15 : 08 d8h sector type 4 size 52h 23 : 16 00h not supported sector type 4 opcode 53h 31 : 24 ffh not supported this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 50 EN25F20A rev. a, issue date: 2013 / 11 / 18 read unique id number the read unique id number instruction accesses a factory-set read-only 96-bit number that is unique to each EN25F20A device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the read unique id instruction is initiated by driving the cs# pin low and shifting the instruction code ?5ah? followed by a three bytes of addresses, 0x80h, and one byte of dummy clocks. after which, the 96-bit id is shifted out on the falling edge of clk as shown in figure 30. table 10. unique id number description address (h) (byte mode) address (bit) data comment unique id number 80h : 8bh 95 : 00 by die power-up timing figure 31. power-up timing table 11. power-up timing and write inhibit threshold symbol parameter min. max. unit t vsl (1) vcc(min) to cs# low 10 s t puw (1) time delay to write instruction 1 10 ms vwi (1) write inhibit voltage 1 2.2 v note: 1.the parameters are characterized only. 2. vcc (max.) is 3.6v and vcc (min.) is 2.7v initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 51 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 12. dc characteristics (t a = - 40c to 85c; v cc = 2.7-3.6v) symbol parameter test conditions min. typ. max. unit i li input leakage current - 1 2 a i lo output leakage current - 1 2 a i cc1 standby current cs# = v cc , v in = v ss or v cc - 1 20 a i cc2 deep power-down current cs# = v cc , v in = v ss or v cc - 1 20 a clk = 0.1 v cc / 0.9 v cc at 104mhz, dq = open - 8 15 ma clk = 0.1 v cc / 0.9 v cc at 33mhz, dq = open 5 8 ma clk = 0.1 v cc / 0.9 v cc at 104mhz in quad mode, dq = open - 12 18 ma i cc3 operating current (read) clk = 0.1 v cc / 0.9 v cc at 33mhz in quad mode, dq = open 6 10 ma i cc4 operating current (pp) cs# = v cc - 10 28 ma i cc5 operating current (wrsr) cs# = v cc - 5 12 ma i cc6 operating current (se) cs# = v cc - 10 25 ma i cc7 operating current (be) cs# = v cc - 10 25 ma v il input low voltage ? 0.5 0.2 v cc v v ih input high voltage 0.7v cc v cc +0.4 v v ol output low voltage i ol = 1.6 ma - 0.4 v v oh output high voltage i oh = ?100 a v cc -0.2 - v note : typical condition at vcc 3.3v, t = 25 . as our design target table 13. ac measurement conditions symbol parameter min. max. unit c l load capacitance 30 pf input rise and fall times 5 ns input pulse voltages 0.2 v cc to 0.8 v cc v input timing refe rence voltages 0.3 v cc to 0.7 v cc v output timing reference voltages v cc / 2 v figure 32. ac measurement i/o waveform this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 52 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 14. ac characteristics (t a = - 40c to 85c; v cc = 2.7-3.6v) symbol alt parameter min typ max unit serial clock frequency for: fast_read, pp, qpp, se, hbe, be, dp, res, wren, wrdi, wrsr, rdsr d.c. - 104 mhz f r f c serial clock frequency for: rdid, dual output fast read and quad i/o fast read d.c. - 104 mhz f r serial clock frequency for read d.c. - 50 mhz t ch 1 serial clock high time 4 - - ns t cl 1 serial clock low time 4 - - ns t clch 2 serial clock rise time (slew rate) 0.1 - - v / ns t chcl 2 serial clock fall time (slew rate) 0.1 - - v / ns t slch t css cs# active setup time (relative to clk) 5 - - ns t chsh cs# active hold time (relative to clk) 5 - - ns t shch cs# not active setup time (relative to clk) 5 - - ns t chsl cs# not active hold time (relative to clk) 5 - - ns t shsl t csh cs# high time for read cs# high time for program/erase 7 30 - - ns ns t shqz 2 t dis output disable time - - 6 ns t clqx t ho output hold time 0 - - ns t dvch t dsu data in setup time 2 - - ns t chdx t dh data in hold time 5 - - ns t hlch hold# low setup time ( relative to clk ) 5 ns t hhch hold# high setup time ( relative to clk ) 5 ns t chhh hold# low hold time ( relative to clk ) 5 ns t chhl hold# high hold time ( relative to clk ) 5 ns t hlqz 2 t hz hold# low to high-z output 6 ns t hhqx 2 t lz hold# high to low-z output 6 ns t clqv t v output valid from clk for 30 pf output valid from clk for 15 pf - - 8 6 ns t whsl 3 write protect setup time before cs# low 20 - - ns t shwl 3 write protect hold time after cs# high 100 - - ns t dp 2 cs# high to deep power-down mode - - 3 s t res1 2 cs# high to standby mode without electronic signature read - - 3 s t res2 2 cs# high to standby mode with electronic signature read - - 1.8 s t w write status register cycle time - 2 15 ms t pp page programming time - 0.8 3 ms t se sector erase time - 0.03 0.2 s t hbe 32kb block erase time 0.1 0.8 s t be 64kb block erase time - 0.2 1 s t ce chip erase time - 0.8 4 s wip = write operation - - 28 s t sr software reset latency wip = not in write operation - - 0 s note: 1. t ch + t cl must be greater than or equal to 1/ f c 2. value guaranteed by characterization, not 100% tested in production. 3. only applicable as a constraint for a write status register instruction when status register protect bit is set at 1. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 53 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 33. serial output timing figure 34. input timing figure 35. hold timing this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 54 EN25F20A rev. a, issue date: 2013 / 11 / 18 absolute maximum ratings stresses above the values so mentioned above may cause permanent damage to the device. these values are for a stress rating only and do not imply that the device should be operated at conditions up to or above these values. exposure of the device to the maximum rating values for extended periods of time may adversely affect the device reliability. parameter value unit storage temperature -65 to +150 c plastic packages -65 to +125 c output short circuit current 1 200 ma input and output voltage (with respect to ground) 2 -0.5 to +4.0 v vcc -0.5 to +4.0 v notes: 1. no more than one output shorted at a time. duration of the short circuit should not be greater than one second. 2. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, inputs may undershoot v ss to ?1.0v for periods of up to 50ns and to ?2.0 v for periods of up to 20ns. see figure below. maximum dc voltage on output and i/o pins is v cc + 0.5 v. during voltage transitions, outputs may overshoot to v cc + 1.5 v for periods up to 20ns. see figure below. recommended operating ranges 1 parameter value unit ambient operating temperature industrial devices -40 to 85 c operating supply voltage vcc full: 2.7 to 3.6 v notes: 1. recommended operating ranges define those limits between which the functionality of the device is guaranteed. vcc +1.5v maximum negative overshoot waveform maximum positive overshoot waveform this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 55 EN25F20A rev. a, issue date: 2013 / 11 / 18 table 15. data retention and endurance parameter description test conditions min unit data retention time 85c 20 years erase/program endurance -40 to 85 c 100k cycles table 16. capacitance ( v cc = 2.7-3.6v) parameter symbol parameter description test setup max unit c in input capacitance v in = 0 6 pf c out output capacitance v out = 0 8 pf note : sampled only, not 100% tested, at t a = 25c and a frequency of 20mhz. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 56 EN25F20A rev. a, issue date: 2013 / 11 / 18 package mechanical figure 36. sop 8 ( 150 mil ) min. nor max a 1.35 - - - 1.75 a1 0.10 - - - 0.25 a2 - - - - - - 1.50 d 4.80 - - - 5.00 e 5.80 - - - 6.20 e1 3.80 - - - 4.00 e - - - 1.27 - - - b 0.33 - - - 0.51 l0.4- - -1.27 0 0 - - - 8 0 note : 1. coplanarit y : 0.1 mm 2. max. allowable mold flash is 0.15 mm at the p k g ends, 0.25 mm between leads. symbol dimension in mm b detail a detail a e1 e e this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 57 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 37. vsop 8 ( 150 mil ) min. nor max a----0.90 a1 0.05 0.1 0 0.15 a2 0.65 0.7 0 0.75 d 4.80 4.90 5.00 e 5.80 6.00 6.20 e1 3.80 3.9 0 4.00 e - - - 1.27 - - - b 0.33 0.41 0.51 l 0.40 0.71 1.27 0--10 n ote : 1. co planarity: 0 .1 mm 2. max. allowable mold flash is 0.15 mm at the pk g ends, 0.25 m m betwee n le ads. symbol dimen sion in mm this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 58 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 38. uson (8l 2x3mm) min. nor max a 0.50 0.55 0.60 a1 0.00 0.035 0.05 a2 - - - 0.40 0.425 a3 d 2.953.003.05 e 1.952.002.05 j 0.100.200.30 k 1.501.601.70 e b 0.200.250.30 l 0.30 - - - - - - l1 0.40 0.45 0.50 l2 - - - - - - 0.15 symbol dimension in mm 0.152 ref 0.5 bsc notice: this package can?t contact to metal trace or pad on board due to expose metal pad underneath the p acka g e. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 59 EN25F20A rev. a, issue date: 2013 / 11 / 18 figure 39. vdfn8 ( 5x6mm ) controlling dimensions ar e in millimeters (mm). dimension in mm symbol min. nor max a 0.70 0.75 0.80 a1 0.00 0.02 0.04 a2 - - - 0.20 - - - d 5.90 6.00 6.10 e 4.90 5.00 5.10 d2 3.30 3.40 3.50 e2 3.90 4.00 4.10 e - - - 1.27 - - - b 0.35 0.40 0.45 l 0.55 0.60 0.65 note : 1. coplanarity: 0.1 mm notice: this package can?t contact to metal trace or pad on board due to expose metal pad underneath the p acka g e. this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 60 EN25F20A rev. a, issue date: 2013 / 11 / 18 ordering information EN25F20A - 104 g i p packaging content p = rohs, halogen-free and reach compliant temperature range i = industrial (-40 c to +85 c) package g = 8-pin 150mil sop rb = 8-pin 150mil vsop x = 8-pin uson (2x3 mm) w = 8-pin vdfn (5x6 mm) speed 104 = 104 mhz base part number en = eon silicon solution inc. 25f = 3v serial flash with 4kb uniform-sector, dual and quad i/o 20 = 2 megabit (256k x 8) a = version identifier this data sheet may be revised by subsequent versions ?2013 eon silicon solution, inc., www.eonssi .com or modifications due to changes in technical specifications. 61 EN25F20A rev. a, issue date: 2013 / 11 / 18 revisions list revision no description date preliminary 0.0 initial release 2013/03/07 preliminary 0.1 update table 3. protected area sizes sector organization on page 10. 2013/03/18 preliminary 0.2 1. update table 12. dc characteristics on page on page 51. (1) update i cc3 (read / in spi mode) from 10 to 8 ma (typ.) (2) update i cc5 (wrsr) from 10 / 18 ma to 5 / 12 ma (typ. / max.) 2. update table 14. ac characteristics on page 52. (1) update page program time (t pp ) from 0.7 to 0.8ms (typ.) (2) update 32k half block erase time (t hbe ) from 0.5 to 0.8s (max.) 2013/10/31 a release a version. 2013/11/18 |
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