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| mb39c0 31 2ch buck dc/dc converter + 1ch ldo with i 2 c interface and sw fet cypress semiconductor corporation ? 1 98 champion court ? san jose, ca 95134 - 1709 ? 408 - 943 - 2600 document number: 002 - 08407 rev. *b revised may 18, 2017 description the MB39C031 contains 2ch buck dc/dc converter and 1ch ldo. it is possible to supply the main power supply line in a system by using only one chip. the current mode system is adopted for the dc/dc converter, and it is possible to use the chip i nductor with the high switching frequency operation which contains internal sw fet. the MB39C031 contains the output setting resistor and the the phase compensation circuit, and contributes to reduce the number of external components and the mounting area. also, it contains the ctl input pin which can control the on/off for each ch, the power good signal output pin and the i 2 c communication interface, therefore it is easy to design the power supply sequence. it is possible to tune in the output voltage exa ctly using the i 2 c communication and possible to correspond to the dvs/asv system. f eatures ? operating input voltage range:2.5 v to 5.5 v (maximum rating: 7 v) ? output voltage setting range, maximum output current: dd1*:1.0 v to 1.3 v (20 mv/step), 1.4 a ( dc) dd2*:1.2 v to 1.95 v (50 mv/step), 0.6 a (dc) ldo:2.8 v/2.85 v/3.0 v/3.3 v, 0.25 a (dc) note: each channel has selective preset voltage (lineup for a total of 32 kinds) . ? soft - start time setting range: 0.9 ms to 14.3 ms (approximately 0.9 ms/step) ? swit ching frequency for the dc/dc block:3 mhz (fixed) ? communication interface: i 2 c (on/off, output voltage, soft - start time setting) ? built - in pfm/pwm auto switching mode ? built - in function: output setting resistor, phase compensation circuit, discharge resistor , soft - start ? each channel power good output function (open - drain) ? protection function: under voltage lockout protection circuit (uvlo), over current protection circuit (ocp), thermal shutdown protection circuit (tsd) ? error signal output pin installed (open - drain) ? small package: qfn28 (4 mm 4 mm 0.8 mm, 0.4 mm pitch) *: dd1,dd2 : dc/dc converter block 1, 2 applications network equipment : wifi - tuner, surveillance camera data - storage device : hdd, ssd, picture recording equipment image and voice output equ ipment : mfp, printer, s canner, p rojector , e lectrophone , stb various terminals : pos, fa, hems etc.
document number: 002 - 08407 rev. *b page 2 of 69 MB39C031 contents description ................................ ................................ ................................ ................................ .......................... 1 features ................................ ................................ ................................ ................................ ............................. 1 applications ................................ ................................ ................................ ................................ ........................ 1 1. application circuit example ................................ ................................ ................................ ......................... 3 2. recommended application specifications ................................ ................................ ................................ .. 4 3. pin assignment ................................ ................................ ................................ ................................ ............ 6 4. pin descriptions (pkg) ................................ ................................ ................................ ............................... 7 5. block diagram ................................ ................................ ................................ ................................ ............. 9 6. absolute maximum ratings ................................ ................................ ................................ ....................... 10 7. recommended operating conditions ................................ ................................ ................................ ........ 11 8. electrical characteristics ................................ ................................ ................................ ........................... 12 9. operation mode list ................................ ................................ ................................ ................................ .. 17 10. state transiti on diagram ................................ ................................ ................................ ........................... 18 11. turning on and off sequence (turning on ctl*:ctl1, ctl2, ctlmain=vcc simultaneously) .......... 19 12. ctl* turning on an d off sequence 1 (vcc ctl*: ctl1, ctl2, ctlmain) ................................ ...... 20 13. ctl* turning on and off sequence 2(vccctlmainctl1ctl2) ................................ ................ 21 14. ctl* pin threshold voltage ................................ ................................ ................................ ...................... 22 15. protection operation sequence ................................ ................................ ................................ ................ 23 16. operation condition, stop circuit and release condition for pr otection circuit ................................ ...... 25 17. dd soft - start operation ................................ ................................ ................................ ............................ 26 18. discharge operation ................................ ................................ ................................ ................................ . 27 19. pg1/pg2/pgl pin and err pin ................................ ................................ ................................ ............. 29 20. i 2 c interface ................................ ................................ ................................ ................................ ............... 30 21. structure of i 2 c interface and data ................................ ................................ ................................ ........... 36 22. i/o pin equivalent circuit diagram ................................ ................................ ................................ ............ 41 23. i/o circuit type ................................ ................................ ................................ ................................ .......... 42 24. typical o peration characteristic measurement circuit ................................ ................................ ............. 43 25. reference data ................................ ................................ ................................ ................................ ......... 45 26. usage precaution ................................ ................................ ................................ ................................ ...... 65 27. ordering information ................................ ................................ ................................ ................................ . 66 28. preset code (MB39C031) ................................ ................................ ................................ ......................... 66 29. package dimensions ................................ ................................ ................................ ................................ . 67 document history ................................ ................................ ................................ ................................ ............. 68 sales, solutions, and legal information ................................ ................................ ................................ ........... 69 document number: 002 - 08407 rev. *b page 3 of 69 MB39C031 1. application circuit example 0.1f 0.1f 0.1f 0.1f 0.47f ctl signal i 2 c signal 4.7f 4.7f 4.7f vin 5.0v MB39C031 lx2 ctl1 pgnd1 lx1 pvcc1 in1 ctlmain vcc vcci2c scl sda addsel gnd vr vref in2 pvcc2 pgnd2 ctl2 gnd ctll ldo pvccl vcc 1.5h 10f vo1 1.2v 1.4a 1.5h 10f vo2 1.8v 0.6a 10f ldo 3.3v 0.25a 100k 100k 100k 100k pg1 pg2 pgl err document number: 002 - 08407 rev. *b page 4 of 69 MB39C031 2. recommended application specifications [ input voltage range ] input voltage vcc (v) min typ m ax 2.5 3.6 5.5 [ output specification ] (ta=+25 c ) channel symbol accuracy output voltage (v) output current (ma) l imit current (ma) mode switching frequency (mhz) coil (h) output capacitance (f) soft - start time (ms) discharge resist ance (k) remarks min typ max max min dd1 vo1 1.2% 0.99 * 1.00 * 1.01 * 1400 2000 buck (synchronous rectification) c - mode 3.0 1.5 10 14.3 5 built - in sw fet built - in output setting resistors operation mode switching (fixed pwm, pfm/pwm) 1.01 1.02 1.03 0.9 * 1.03 1.04 1.05 1.8 1.05 1.06 1.07 2.7 1.07 1.08 1.09 3.6 1.09* 1.10* 1.11* 4.5 1.11 1.12 1.13 5.4 1.13 1.14 1.15 6.3 1.15 1.16 1.17 7.2 1.17 1.18 1.19 8.1 1.19* 1.20* 1.21* 9.0 1.21 1.22 1.23 9.9 1.23 1.24 1.25 10.8 1.24 1.26 1.28 11.6 1.26 1.28 1.30 12.5 1.28* 1.30* 1.32* 13.4 dd2 vo2 1.2% 1.19 * 1.20 * 1.21 * 600 900 buck (synchronous re ctification) c - mode 3.0 1.5 10 14.3 5 built - in sw fet built - in output setting resistors operation mode switching (fixed pwm, pfm/pwm) 1.24 1.25 1.27 0.9* 1.28 1.30 1.32 1.8 1.33* 1.35* 1.37* 2.7 1.38 1.40 1.42 3.6 1.43 1.45 1.47 4.5 1.48* 1.50* 1.52* 5.4 1.53 1.55 1.57 6.3 1.58 1.60 1.62 7.2 1.63 1.65 1.67 8.1 1.68 1.70 1.72 9.0 1.73 1.75 1.77 9.9 1.78* 1.80* 1.82* 10 .8 1.83 1.85 1.87 11.6 1.88 1.90 1.92 12.5 1.93 1.95 1.97 13.4 document number: 002 - 08407 rev. *b page 5 of 69 MB39C031 channel symbol accuracy output voltage (v) output current (ma) l imit current (ma) mode switching frequency (mhz) coil (h) output capacitance (f) soft - start time (ms) discharge resist ance (k) remarks min typ max max min ldo l do 1.8% 2.75 2.80 2.85 2 50 300 ldo - - 4.7 14.3 5 2.80* 2.85* 2.90* 0.9 2.95 3.00 3.05 1.8 3.24* 3.30* 3.36* 2.7* - - - 3.6 - - - 4.5 - - - 5.4 - - - 6.3 - - - 7.2 - - - 8.1 - - - 9.0 - - - 9.9 - - - 10.8 - - - 11.6 - - - 12.5 - - - 13.4 *: preset value note: it is possible to set the output voltage and to change the soft - start time using i 2 c. document number: 002 - 08407 rev. *b page 6 of 69 MB39C031 3. pin assignment (top view) ( wno028 ) vcc err pvccl ldo pgl ctll gnd ctl1 1 21 ctl2 pg1 2 20 pg2 pgnd1 3 19 pgnd2 lx1 4 top view 18 lx2 pvcc1 5 17 pvcc2 in1 6 ep(exposed pad) 16 in2 ctlmain 7 15 vref vcc vcci2c scl sda addsel gnd vr 8 9 10 11 12 13 14 28 27 26 25 24 23 22 document number: 002 - 08407 rev. *b page 7 of 69 MB39C031 4. pin descriptions (pkg) circuit block pin name numb er of pin for pkg pin no i/o description (pkg) pull - down resist ance pad treatment when not using dd1 pad treatment when not using dd2 pad tr eatment when not using ldo pad treatment when not using i 2 c communi cation dd1 in1 1 6 i dd1 output voltage feedback pin. - gnd connection - - - pvcc1 1 5 - dd1output block power supply pin - vcc connection - - - lx1 1 4 o dd1 p in for indu ctance connection . - open - - - pg1 1 2 o dd1powergoo d output pin - open - - - pgnd1 1 3 - dd1output block ground pin - gnd connection - - - dd2 in2 1 16 i dd2 output voltage feedback pin. - - gnd connection - - pvcc2 1 17 - dd2output block power supply pin - - vcc connection - - lx2 1 18 o dd2 p in for inductance connection . - - open - - pg2 1 20 o dd2powergoo d output pin - - open - - pgnd2 1 19 - dd2output block ground pin - - gnd connection - - ldo pvccl 1 26 - ldopower supply pin - - - vcc connection - ldo 1 25 o ldo o utput pin - - - open - pgl 1 24 o ldopowergoo d output pin - - - open - ctl ctl1 1 1 i dd1 control pin ? open - - - ctl2 1 21 i dd2 control pin ? - open - - ctll 1 23 i ldo control pin ? - - open - ctlmain 1 7 i control pin for common block and digital block * ? - - - - err err 1 27 o err signal output pin - - - - - document number: 002 - 08407 rev. *b page 8 of 69 MB39C031 circuit block pin name numb er of pin for pkg pin no i/o description (pkg) pull - down resist ance pad treatment when not using dd1 pad treatment when not using dd2 pad tr eatment when not using ldo pad treatment when not using i 2 c communi cation i 2 c vcci2c 1 9 - power supply pin for i 2 c . - - - - gnd connection scl 1 10 i i 2 c clock pin - - - open sda 1 11 i/o i 2 c data i/o pin - - - open addsel 1 12 i switch pin for slave address ? - - - open commo n vcc 2 8, 28 - control circuit block p ower supply pin - - - - - vref 1 15 o reference voltage (2.4v) output pin - - - - - vr 1 14 o reference voltage (0.6v) output pin - - - - - gn d 2 13, 22 - control circuit block ground pin - - - - - - gnd 1 ep - g round pin - - - - - *: when turning on dd1, dd2 and ldo, it is also necessary to set ctlmain to "h". see 9. operation mode list for the details. document number: 002 - 08407 rev. *b page 9 of 69 MB39C031 5. block diagram common block v r e f b gr common block power supply l o g i c control block pv cc l l d o < < l d o > > l d o : 2 .80 v /2. 8 5 v / i o( m ax ) :25 0 m a ( 2 . 4 v ) r t v r e f scp (counter & latch) u v l o c t o t p scp1/2/l o s c s c l s d a v r ( 0 . 6 v ) v o 1 : 1.00v to 1. 3 0v ( 2 0 m v s t e p ) i o( m ax ) : 1400 m a a a e rr a m p 0 . 6v < document number: 002 - 08407 rev. *b page 10 of 69 MB39C031 6. absolute maximum ratings parameter symbol condition rating unit min max power supply voltage v cc vcc, pvcc1, pvcc2, p vccl, vcci2c pin s - 7 v input voltage v ctl ctlmain, 1, 2, l pin s - 7 v v out in1, in2 pin s - 7 v vlogic sda, scl pin s - 7 v lx voltage v lx lx1, lx2 pin s - 0.3 + 7 v power dissipation p d ta +25 c thermal resistor value ( j - a): ( 50 c /w *) - 1720 mw max imum junction temperature t jmax - - + 125 c storage temperature t stg - - 55 + 125 c *: when mounted on a qfn28 ( wno028 ) pkg, 4 layers 0.8 mm thickness 117 mm 84 mm warning: semiconductor devices can be permanently damaged by application of stress (voltag e, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. document number: 002 - 08407 rev. *b page 11 of 69 MB39C031 7. recommended operating conditions parameter symbol condition value unit m in t yp max general power supply voltage v cc vcc pin 2.5 3.6 5.5 v reference voltage output current i ref vref pin - 1 - 0 ma i r vr pin - 1 - 0 a operating temperature ta - - 30 + 25 + 85 c dc/dc ch p ower supply voltage v cc v cc, pvcc1, pvcc 2 pin s 2.5 3.6 5.5 v input voltage v out in1, in2 pin s 0 - vcc v ldo ch p ower supply v oltage v cc vcc, pvccl pin s output voltage setting : default (3.3v) 3.5 3.6 5.5 v ctl block i nput voltage v ctl ctl* pin 0 - vcc v digital block (i 2 c) p ower supply voltage v cc vcci2c pin 1.76 - 3.37 v logic i nput voltage vlogic sda, scl pin 0 - vcci2c v *: ctlmain, ctl1, ctl2, ctll warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating co nditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. document number: 002 - 08407 rev. *b page 12 of 69 MB39C031 8. electrical characteristics common block (ta= + 25 c , vcc=pvcc1, pvcc2, l=3.6v) parameter symbol condition value unit min typ max reference voltage block [vr, vref] output voltage v r vr pin =0ma 0.594 0.600 0.606 v v ref1 vref pin =0ma 2.376 2.400 2.424 v v ref2 vcc pin =2.5v to 5.5v 2.370 2.400 2.430 v v ref3 vref pin =0 ma to - 1ma 2.370 2.400 2.430 v under voltage lockout protection circuit block [vcc uvlo] threshold voltage v th vcc pin = 2.156 2.20 2.244 v hysteresis width v h - - 0.20 - v o ver c urrent protection circuit block [ocp ] timer time t ocp1 dd1, dd2, ldo default value 0.5 1 1.5 ms thermal shutdown protection circuit block [tsd ] stop temperature t tsdh - - 15 0 * - c control block (ctl) [ctl] input voltage v ih ctl* pin vcc 0.7 - vcc v v il ctl* pin 0 - 0.4 v i nput current i ctlh ctl* pin =3.6v 2.7 3.6 5.1 a i ctll ctl* pin =0v - - 1 a input pull - down resistor r p ctl* pin - 1 - m general (dc/dc block ) power supply current i vccs1 ctl* pin =0v - 0 1.0 a i vccs2 ctlmain=3.6v ctl1, ctl2.l pins =0v - 80 120 a i vcc ctlmain, l pins =3.6v only ldo o peration no load - 200 300 a i vcc ctl* pin = 3.6v all ch no load (dd operation mode : pfm/pwm mode) - 450 680 a i vcc ctl* pin = 3.6v all ch no load (dd operation mode: fixed pwm mode) - 10.8 16.2 ma i vcci2c ctlmain, l pin=3.6v vcci2c pin = 1 .8v - 7 . 2 1 2 . 0 a *: these are not the rated values. use these values as reference when planning. document number: 002 - 08407 rev. *b page 13 of 69 MB39C031 dd1, dd2 (ta= + 25 c , vcc=pvcc1, pvcc2, l=3.6v) parameter symbol condition value unit min typ max dc/dc converter block [dd1] output voltage v out output voltage setting : 1.2v iout= - 10ma 1.186 1.20 1.214 v input stability v line iout= - 10ma, vcc=2.5v to 5.5v - 5 - + 5 mv load stability v load iout= - 1ma to - 1400ma ( when in fixed pwm mode ) - 10 - - mv iout= - 1ma to - 1400ma ( when in pfm/pwm mode ) - 10 - + 15 m v in1 pin input impedance r in in1 pin =1.5v output voltage setting : 1.2v - 400 - k sw pmos - tr on resistance r pmos lx1 pin= - 30ma - 0.12 * - sw nmos - tr on resistance r nmos lx1 pin= 30ma - 0.09 * - sw pmos - tr leak current i leak lx1 pin =0v - 1 - - a sw nmos - tr leak current i leak lx1 pin =3.6v - - 1 a overcurrent protection val ue i limit l=1.5 h 2000 - - ma pfm/pwm reshuffling electric current i pfm l=1.5 h - 40 * - ma discharge resistor r dis - - 5 - k soft - start time t ss preset value 0.8 0.9 1.0 ms switching frequency f osc - 2.7 3.0 3.3 mhz document number: 002 - 08407 rev. *b page 14 of 69 MB39C031 parameter symbol condition v alue unit min typ max dc/dc converter block [dd2] output voltage v out output voltage setting : 1. 8 v iout= - 10ma 1.778 1.80 1.822 v input stability v line iout= - 10ma vcc=2.5v to 5.5v - 5 - + 5 mv load stability v load iout= - 1ma to - 600ma ( when in fixed pwm mode ) - 10 - - mv iout= - 1ma to - 600ma ( when in pfm/pwm mode ) - 10 - + 20 mv in2 pin input impedance r in in2 pin =2.0v output voltage setting : 1. 8 v - 300 - k sw pmos - tr on resistance r pmos lx2 pin = - 30ma - 0.16 * - sw nmos - tr on resistance r nmos lx2 pin = 30ma - 0.14 * - sw pmos - tr leak current i leak lx2 pin =0v - 1 - - a sw nmos - tr leak current i leak lx2 pin =3.6v - - 1 a overcurrent protection value i limit l=1.5 h 900 - - ma pfm/pwm reshuffling electric current i pfm l=1 .5 h - 70* - ma discharge resistor r dis - - 5 - k soft - start time t ss preset value 0.8 0.9 1.0 ms switching frequency f osc - 2.7 3.0 3.3 mhz *: these are not the rated values. use these values as reference when pla n ning. document number: 002 - 08407 rev. *b page 15 of 69 MB39C031 ldo (ta= + 25 c , vcc=pvcc1, pvcc2, l=3.6v) parameter symbol condition value unit min typ max ldo block [ldo ] output voltage v out output voltage setting : 3.3v iout= - 10ma 3.241 3.300 3.359 v i/o v oltage difference v dif iout= - 10ma - - 0.20 v input stability v line iout= - 10ma, vcc=3.5v to 5.5v - 5 - + 5 mv load stability v load iout= - 1ma to - 150ma - 30 - 20 - mv ripple remove ratio rr pvc cl=0.2vrms, f=10hz, iout= - 150ma 35 75 - db pvccl=0.2vrms, f =10khz, iout= - 150ma 15 50 - db overcurrent protection value i limit vout0.9 300 - - ma control macro consumption current i pvccls at stand - by - 0 1 a i pvccl iout=0ma - 80 105 a discharge resistor r dis - - 5 - k soft - start time t ss preset valu e 2.4 2.7 3.0 ms document number: 002 - 08407 rev. *b page 16 of 69 MB39C031 digital block (ta= + 25 c , vcc=pvcc1, pvcc2, l=3.6v) parameter symbol condition value unit min typ max power - good block [power good ] output voltage v ol pg1, pg2, l pins i ol =1ma - - 0.4 v output current i ol pg1, pg2, l pins 1 - - ma low - voltage detection v th in1, in2, ldo pins = - vo 0.75* - v power - on detection voltage v th in1, in2, ldo pins = - vo 0.85* - v error block [err ] output voltage v ol err pin i ol = 1ma - - 0. 4 v output current i ol err pin 1 - - ma i 2 c block [i 2 c] input voltage v ih scl, sda pins vcci2c=3.3v vcci2c 0.7 - vcci2c v v il scl, sda pins vcci2c=3.3v 0 - vcci2c 0.3 v input current i ih scl, sda pins vcci2c=3.3v - - 10 a i il scl, sda pins vcci2c=3.3v - 10 - - a output voltage v ol sda pin i ol =3ma - - 0.4 v output current i ol sda pin 3 - - ma input pull - down resistor r p addsel pin - 1 - m *: these are not the rated values. use these values as reference when pl a n ning. document number: 002 - 08407 rev. *b page 17 of 69 MB39C031 9. operation mode list mode stand - by stand - by 2 general err detection ctl signal ctlmain (external) l h h h ctl1 (external / i 2 c) l l h/l x ctl2 (external / i 2 c) l l h/l x ctll (external / i 2 c) l l h/l x operation block general off on on on digital block off on on on osc, vr block off off on* 2 off dd1 off off on/off off dd2 off off on/off off ldo off off on/off off i 2 c communication i 2 c communication disabled enabled enabled enabled protection operating thermal shutdown protectio n (tsd) not available not available available *1 over current protection (ocp) not available not available available *1 *1: this is the state after detection of err. it is possible to release the err detection mode by turning the power supply on again o r turning ctlmain on again. *2: when only ldo is operating, the osc block stops (off) after ldo activation. also, the vr block keeps operating (on) after ldo activation. ? priority of the external pin/ i 2 c communication for ctl1, ctl2 and l ctlmain (external pin) ctl* (external pin) ctl* (i 2 c communication) relevant ch h h h unavailable h h l on h l h on h l l off l x communication disabled off ? *: the i 2 c communication is enabled after the common block and digital block activation setting the exte rnal c tlmain pin to "h". ? when executing the on/off control for dd1, dd2 and ldo using the external pin, don't execute the on/off control using i 2 c . aside from the on/off control, it is possible to control everything else using i 2 c . ? when executing the on/off co ntrol for dd1, dd2 and ldo using i 2 c , input "l" to the ctl* pin (the pin is open or in the gnd connection condition). document number: 002 - 08407 rev. *b page 18 of 69 MB39C031 10. state transition diagram (1) external ctlmain pin "h" (2) external ctlmain pin "l" (3) external ctl pin "h" / i 2 c communication " relevant ch_on" (4) external ctl pin "l" / i 2 c communication " relevant ch_off" (5) error detection (ocp, ocp_1ms continuation ) (6) turning on the power supply again (equal to or less than uvlo_vcc reset voltage) or setting ctlmain to "l" notes: ? when executing the on/off control for dd1, dd2 and ldo using the external pin, don't execute the on/off cont rol using i 2 c. aside from the on/off control, it is possible to control everything else using i 2 c. ? when executing the on/off control for dd1, dd2 and ldo using i 2 c, input "l" to the ctl* pin (the pin is open or in the gnd connection condition). stand-by stand-by 2 general error detection (1) (2) (6) (5) (4) (3) document number: 002 - 08407 rev. *b page 19 of 69 MB39C031 11. turning on and off sequence ( t urning on ctl*:ctl1, ctl2, ctlmain=vcc simultaneously ) *: vref and vr activations depend on the vref pin capacitance and vr pin capacitance. time in the sequence figure above is applied for the following condition. ? vref pin capacitance : 0.1 f ? vr pin capacitance : 0.47 f v c c v r o s c ( i c internal signal ) 2 . 2 v 0 . 6 v 85 % dd 1 p g 1 c t l * c t l * ( i c internal signal ) 2 . 0 v v cc i 2 c 85 % dd 2 p g 2 0 v u v l o release to d d * activation time till start * t yp: 2 00 s max :30 0 s soft-start time u v l o _ v c c (ic internal signal ) v r e f 2 . 4v discharge discharge 9 0 % document number: 002 - 08407 rev. *b page 20 of 69 MB39C031 12. ctl* turning on and off sequence 1 (vcc *: vref and vr activations depend on the vref pin capacitance and vr pin capacitance. time in the sequence figure above is applied for the following condition. ? vref pin capacitance : 0.1 f ? vr pin capacitance : 0.47 f v c c v r o s c ( i c internal signal ) 3 . 6 v 0 . 6 v 85 % dd 1 p g 1 c t l * c t l * ( i c internal signal ) v cc i 2 c 85 % dd 2 p g 2 0 v turning on ctl * to d d * activation typ:2 7 0 s m ax :45 0 s soft-start time u v l o _ v c c ( i c internal signal ) v r e f 2 . 4v discharge 9 0 % discharge t ime till start * document number: 002 - 08407 rev. *b page 21 of 69 MB39C031 13. ctl* turning on a nd off sequence 2 (vcc (1) time from turning on ctlmain to vref activ ation completion (=communication enabled)* t yp : 130 s , m ax : 200 s (2) time from turning on ctl1 to ctll (ic internal signal) "h" t yp : 150 s , m ax : 250 s *: vref and vr activations depend on the vref pin capacitance and vr pin capacitance. time in the s equence figure above is applied for the following condition. ? vref pin capacitance : 0.1 f ? vr pin capacitance : 0.47 f v c c vr o s c (ic internal signal) 3 . 6 v 0 . 6 v 85 % d d 1 p g 1 c t l m a i n c t l 1 ( ic internal signal ) v c c i 2 c 8 5 % d d 2 p g 2 0 v soft-start time u v l o _ v c c ( i c internal signal) v r e f 2 . 4 v discharge discharge 90 % c tl 1 c t l 2 c t l 2 ( ic internal signal ) soft-start time (1) (2) document number: 002 - 08407 rev. *b page 22 of 69 MB39C031 14. ctl * pin threshold voltage the input circuit structure for the ctl* pin is the schmitt trigger style, and the threshold voltage shows t he hysteresis characteristics when ctl* off on and on off. (see " ctl* pin equivalent circuit diagram" below.) also, the threshold voltage level depends on the vcc pin voltage. moreover, make sure to input either the "h" level (> "vcc0.7"v ) or " l " lev el ( < 0.4 v) to the ctl * pin when in use. ctl * pin e quivalent circuit diagram document number: 002 - 08407 rev. *b page 23 of 69 MB39C031 15. protectio n operation sequence dd channel the dd channel monitors the fet current peak value at any time during the operation. when the dd output becomes the over current state, the output voltage is decreased. afterward, the timer operation is performed and the ou tput stops after about 1ms progress. ldo channel it contains the fold - back type over current protection circuit in order to prevent destroy because of the over load and the output over current. it limits the output current and the output voltage from the peak around the over current protection value for ldo (ilimit) to the over current current (is). at this time, if the output voltage vo gets lower than the detection voltage vd (vd: vo0.5), the timer operation starts and the output stops after about 1ms p rogress. moreover, because the over current protection circuit does not operate at the soft - start (0v to vo 0.7), neither the output stops nor the error signal outputs. however, the fold - back type over current protection characteristic functions. the fol lowing shows the fold - back type over current protection characteristic. thermal shutdown prot ection if the temperature at the junction part reaches +150 c , the thermal shutdown protection circuit turns all channels off. document number: 002 - 08407 rev. *b page 24 of 69 MB39C031 error detection sequence err detection mode release it is necessary to turn the power supply on again, or to turn ctlmain on again to release the err detection mode. d d1 , d d2 , ldo e rr detection mode e r r o r signal output ( e rr pin ) voltage drop 1 m s continue for 1ms ? no normal operation y e s over current detection normal operation thermal shutdown protection the whoie i c document number: 002 - 08407 rev. *b page 25 of 69 MB39C031 16. operation condition, stop circuit and re lease condition for protection circuit channel operation whilst under protection over voltage protection (ocp) under voltage lockout protection (uvlo) thermal shutdown protection (tsd) dd1, dd2 discharge operating condition : after about 1 ms progress in t he over current condition proc ess during protection operation : dd1, dd2, ldo stop recovery condition : (1) power supply re asserted (2) ctlmain re asserted operating condition : input voltage drop proc ess during protection operation : dd1, dd2, ldo stop recove ry condition : input voltage rise uvlo operates only when ctl main is "h" (normal operation). operating condition: chip temperature increment process during protection operation: dd1, dd2, ldo stop recovery condition: (1) power supply reasserted (2) ctlmain reasserted only when ctlmain is in the "h" state and one of ctl1, ctl2 or l is in the "h" state, tsd will operate. ldo discharge operating condition : after about 1 ms progress in the over current condition proc ess during protection operation : dd1, dd2, ldo stop recovery condition : (1) power supply re - asserted (2) ctlmain re asserted err output (err pin ) - "l" output when detecting ocp at ch of dd1, dd2, or ldo no change "l" output when detecting tsd thermal shutdown protection (tsd) operation during o ver current protection timer operation when the thermal shutdown protection (tsd) operated during the over current protection (ocp) timer operation, the thermal shutdown protection has priority. operation when releasing u nder voltage lockout protection (uv lo) dd1, dd2 and ldo: activation following the condition for ctl* pin document number: 002 - 08407 rev. *b page 26 of 69 MB39C031 17. dd soft - start operation the soft - start operation for dd1, dd2 and ldo is enabled in order to prevent the rush current during the dd activation. the soft - start time can be controlled by i 2 c. soft - start control: enabled to set at dd1, dd2 and ldo dd, ldo soft - start document number: 002 - 08407 rev. *b page 27 of 69 MB39C031 18. discharge o peration dd channel when executing the dd off operation at the ch on/off signal, the dc/dc smooth capacitance charged for each output voltage is discharged using resistor for discharge which is set in the ic and the output voltage is decreased gradually. h owever, the discharge time changes depending on the dc/dc converter load current. the discharge time is calculated by the following equation. discharge time (time till the output becomes 10% without load) toff(s) 2.3 r dis cout(f) note: see the table in electrical characteristics for the discharge resistor value. ldo channel when executing the ld off operation at the ch on/off signal, the output capacitance charged for the output voltage is discharged using resistor for discharge which is set in the ic and the output voltage is decreased gradually. however, the discharge time changes depending on the output load current. the discharge time is calculated by the following equation. discharge time (time till the output becomes 10 % without load) . toff(s) 2.3 r dis cout(f) note: see the table in electrical characteristics for the discharge resistor value. error amp 0.6v r1 r2 inx ch on/off cont. a pvccx pgndx a resistor for discharge cout lxx document number: 002 - 08407 rev. *b page 28 of 69 MB39C031 ldo pvccl 0.6v ch on/off cont. resistor for discharge + - cout document number: 002 - 08407 rev. *b page 29 of 69 MB39C031 19. pg1/pg2/pgl pin and err pin the following pins for each ch power good output are prepared. pg1 it is the pin for dd1 power good output. when the output voltage exceeds 85 % of the setting value at the dd1 on mode, "h" is output. also, whe n the output voltage becomes equal to or lower than 75 % of the setting value after the "h" output, "l" is output. "l" is output at the dd1 off mode. pg2 it is the pin for dd2 power good output. when the output voltage exceeds 85% of the setting value at the dd2 on mode, "h" is output. also, when the output voltage becomes equal to or lower than 75% of the setting value after the "h" output, "l" is output. "l" is output at the dd2 off mode. pgl it is the pin for ldo power good output. when the output vol tage exceeds 85 % of the setting value at the ldo on mode, "h" is output. also, when the output voltage becomes equal to or lower than 75 % of the setting value after the "h" output, "l" is output. "l" is output at the ldo off mode. the following pin for the error state output is prepared. err pin it is the pin for the error state output. "l" is output during the error detection mode. the err detection mode is released by turning on the power supply or ctlmain again. document number: 002 - 08407 rev. *b page 30 of 69 MB39C031 20. i 2 c interface 1. structure of i 2 c in terface the i 2 c interface executes the data communication in 1 byte (8 - bit) units using two signal lines (bus), a scl (serial clock line) and a sda (serial data line). this bus is connected to multiple devices; master: device to generate the clock signal a nd to control the data transfer (cpu and so on) slave: device that an address is specified by a master. this ic is set as the slave and has no function to be the master. each device is defined due to the communication direction as described below. t ran smitter: device to send data to bus receiver : device to receive data from bus the ic has the function both transmitter and receiver. the ic defines the followings; write : data is transmitted from master and the ic receives data read : the ic transmits data and master receives data. 2. definition of signal lines scl and sda are connected to the pow er supply by the pull - up resistor. the output circuit is the open drain output. when a bus is not used (waiting state), the open "h" is set changing the open drain to the off state. note: scl and sda pins adopt a different esd protection system from sta ndard i 2 c specification because of esd enhancement (see 2.3 i/o circuit type). when the power supply is in the bus line, don't shut off the power supply for an ic (vcci2c). scl sda master slave1 transmitter transmitter receiver receiver slave2 document number: 002 - 08407 rev. *b page 31 of 69 MB39C031 3. validity of data data has the following characteristics; change when scl is the "l" level valid if the state is kept while scl is the "h" level. moreover, the sda signal change means the start or stop condition when scl is the "h" level. 4. definition of start and stop con dition the start and stop conditions are output from the master and shows start and stop of communications to the slave. start : sda changes from "h" to "l" when scl is "h". stop : sda changes from "l" to "h" when scl is "h". 5 . ack signal this is a signal to confirm the data reception during communication. the receiv er replies the ack signal to show the data reception to a transmitter every time 1 byte (8 - bit) of data is received. the ack signal is sent in 9clk after sending data 8 - bit matching to the scl signal that the master generates. ? a transmitter keeps sda outpu t " open h " in scl9 clk . ? a receiver informs the data reception situation to a transmitter outputting the followings in scl 9 clk ; when data was received : sda output "l" (ack) when no data was received : sda output "open h" (nack) however, if the mast er is changed to the receiver, ack is not replied after the last data reception because the bus keeps open stopping the data transmission to the slave transmitter. in this case, the slave transmitter opens the bus (open h) and is se t to the stop condition reception waiting state from the master. document number: 002 - 08407 rev. *b page 32 of 69 MB39C031 6. i 2 c i nterface input timing ( within recommended oper ating conditions ) parameter symbol value unit scl=100khz scl=400khz min max min max scl clock frequency fscl - 100 - 400 khz s tart condition hold time t hd : start 4.0 - 0.6 - s r estart condition setup time t su : start 4.7 - 0.6 - s s top condition setup time t su : stop 4.0 - 0.6 - s s top to s tart bus open time t buf 4.7 - 1.3 - s scl "l" time t low 4.7 - 1.3 - s scl "h" time t high 4.0 - 0.6 - s scl/sda rising time t r - 1.0 - 0.3 s scl/sda falling time t f - 0.3 - 0.3 s d ata hold time t hd:data 0.0 - 0.0 - s d ata setup time t su: data 0.25 - 0.10 - s scl/sda capacitor load c b - 400 - 400 pf ? vih/vil level reference ? conform to i 2 c bus specifications document number: 002 - 08407 rev. *b page 33 of 69 MB39C031 7. slave address this is a slave address when communicating with the i 2 c interface. the slave add ress of this ic is set by the first seven bits as shown below. the seventh bit follows the addsel pin and "0"/"1" are variable. the eight h bit is called the least significant bit (lsb) and determines the message direction. the bit "0" shows that informatio n will be written from the master to the slave. the bit "1" shows that the master reads information from the slave. this does not support the general call address. ? when the addsel pin is in "h" ? when the addsel pin is in "l" s t a r t msb lsb 1 1 1 r/w 1 0 1 0 s t o p slave address s t a r t msb lsb 1 1 0 r/w 1 0 1 0 s t o p slave address document number: 002 - 08407 rev. *b page 34 of 69 MB39C031 8. b it structure of data on i 2 c interface (1) writing data to register and reading data the data line is sent/ received in the order from the most significant bit (msb) to the least significant bit (lsb). *when the addsel pin is in "h" register data d 07 d 06 d 05 d 04 d 03 d 02 d 01 d 00 00 h 01 h 02 h a b c d e f g h addre ss 10 h 11 h .. .. output the "stop" condition after sending the write data. ( 2 ) i 2 c i nterface d ata f ormat i 2 c communication 1. when a different slave address comes, non - matching id is informed by not replying ack after receiving the slave address. 2. all registers write to internal registers in the ack signal after receiving the 8 - bit data of each setting. 3. if a non - existing register address is specified, data is not written to a register. 4. output the "stop " condition after sending the write data. < during write (w)> document number: 002 - 08407 rev. *b page 35 of 69 MB39C031 w rite is allowed per one addr ess. ( sequential writing is not allowed. ) send register address and data as one unit. < during read (r) > read is allowed per one address. be sure to perform read by specifying the register addresses. (sequential reading is not allowed.) document number: 002 - 08407 rev. *b page 36 of 69 MB39C031 21. structure of i 2 c interface and data register map address data writing timing remarks d07 d06 d05 d04 d03 d02 d01 d00 default output voltage 00 h x x x x d03 d02 d01 d00 0 0 h * 0 5 h * 0a h * 0 f h * ack dd1 output voltage setting 01 h x x x x d03 d02 d01 d00 0 0 h * 0 3 h * 0 6 h * 0c h * ack dd2 output voltage setting 02 h x x x x x x d01 d00 03 h ack ldo output voltage sett ing soft start 10 h x x x x d03 d02 d01 d00 01 h ack dd1 soft - start time setting 11 h x x x x d03 d02 d01 d00 01 h */ 0 3 h * ack dd2 soft - start time setting 12 h x x x x d03 d02 d01 d00 03 h ack ldo soft - start time setting dd operation mode 20 h x x x x x x d0 1 d00 00 h ack dd1, dd2 operation mode setting "0": fixed pwm mode , "1": pfm/pwm mode on/off 30 h x x x x x d02 d01 d00 00 h ack dd1, dd2, ldo output on/off setting "0": output off/ "1": output on for test fx h - - - - - - - - - - disabled *: the value depen ds on the preset value. ? because the "x" block in the register map has no register, "0" is returned when in reading. ? the address fx h is used for tests. it is normally disabled. don't read/write to the fx h address. document number: 002 - 08407 rev. *b page 37 of 69 MB39C031 ( 1 ) dd1 and dd2 output voltage control 1. addresses 00 h , 0 1 h are allocated as registers for the dc/dc output voltage control. 2. the dc/dc output voltage control is controlled by writ ing data to addresses 00 h , 0 1 h . address 00 h : for dd1 output voltage setting address 01 h : for dd2 output voltage setting d 03 to d 00 : set the output voltage dd1 output voltage setting table dd2 output vol tage setting table data o utput voltage data o utput voltage 00 h 1.00 * 00 h 1.20 * 01 h 1.02 01 h 1.25 02 h 1.04 02 h 1.30 03 h 1.06 03 h 1.35 * 04 h 1.08 04 h 1.40 05 h 1.10 * 05 h 1.45 06 h 1.12 06 h 1.50 * 07 h 1.14 07 h 1.55 08 h 1.16 08 h 1.60 09 h 1.18 09 h 1.65 0a h * 1.20 * 0a h 1.70 0b h 1.22 0b h 1.75 0c h 1.24 0c h * 1.80 * 0d h 1.26 0d h 1.85 0e h 1.28 0e h 1.90 0f h 1.30 * [v] 0f h 1.95 [v] *: the selectable output voltage setting as preset value. data msb lsb s t a r t s t o p a c k 0 0 0 0 d 03 d 02 d 01 d 00 document number: 002 - 08407 rev. *b page 38 of 69 MB39C031 ( 2 ) ldo output voltage control 1. ad dress 02 h is allocated as a register for the ldo output voltage control. 2. the ldo output voltage control is controlled by writ ing data to addresse 02 h . address 0 2 h : for ldo output voltage setting d 01 to d 00 : set the output voltage ldo output voltage setting table data output voltage 00 h 2.80 01 h 2.85 * 02 h 3.00 03 h * 3.30 * [v] *: the selec table output voltage using the preset value changing products msb data lsb s t a r t s t o p d 01 0 0 0 0 0 0 d 00 a c k document number: 002 - 08407 rev. *b page 39 of 69 MB39C031 ( 3 ) s oft start time 1. address 10 h to 12 h are allocated as registers for the soft start time control. 2. the soft start time control is controlled by writing data to address es 10 h to 12 h . address10 h : for dd1 soft start time setting address11 h : for dd2 soft start time setting address12 h : for ldo soft start time setting d 03 to d 00 : set the soft start time soft start time setting table data1 soft start time d efault setting 00 h 14.3m s 01 h 0.9m s dd1, dd2 02 h 1.8m s 03 h 2.7m s ldo 04 h 3.6m s 05 h 4.5m s 06 h 5.4m s 07 h 6.3m s 08 h 7 .2m s 09 h 8.1m s 0a h 9.0m s 0b h 9.9m s 0c h 10.8m s 0d h 11.6m s 0e h 12.5m s 0f h 13.4m s msb data lsb s t a r t s t o p d 01 0 0 d 03 d 02 0 0 d 00 a c k document number: 002 - 08407 rev. *b page 40 of 69 MB39C031 ( 4 ) dc/dc operation mode 1. address 20 h is allocated as a register for the dc/dc operation mode control. 2. the dc/dc operation mode is controlled by writing data to address 20 h . address 20 h : for dc/dc operation mode setting d 01 to d 00 : set the dc/dc op eration mode address bit value description value description 20 h d00 0 * dd1 fixed pwm * 1 dd1 pfm/pwm 20 h d01 0 * dd2 fixed pwm * 1 dd2 pfm/pwm *: it is a preset value. ( 5 ) on/off for dc/dc and ldo 1. address 30 h is allocated as a register for the dc/ dc and ldo on/off. 2. the dc/dc and ldo on/off is controlled by writing data to address 30 h . add ress30 h : for dc/dc and ldo on/off d 02 to d 00 : set on/off for dc/dc and ldo address bit value description value description 30 h d00 0 * dd1 output off * 1 dd1 output on 30 h d01 0 * dd2 output off * 1 dd2 output on 30 h d02 0 * ldo output off * 1 ldo output on *: it is a preset value. msb data lsb s t a r t s t o p d 01 0 0 0 0 0 0 d 00 a c k msb data lsb s t a r t s t o p 0 0 0 d 02 d 01 0 0 d 00 a c k document number: 002 - 08407 rev. *b page 41 of 69 MB39C031 22. i/o pin equivalent circuit diagram document number: 002 - 08407 rev. *b page 42 of 69 MB39C031 23. i/o circuit type ctlmain/ctl1/ctl2/ctll/addsel pins scl pin sda pin pg1/pg2/pgl/err pin s v cc c t l * a d d s el g n d v cc i 2 c s cl g n d v cc i 2 c s d a g n d g n d v cc p g * / err document number: 002 - 08407 rev. *b page 43 of 69 MB39C031 24. typical operation characteristic measurement circuit document number: 002 - 08407 rev. *b page 44 of 69 MB39C031 part list symbol (circuit diagram notation) parts part number specifications vendor l1 metal alloy inductor 1299as - h - 1r5n 1.5 h toko l2 metal alloy inductor 1299as - h - 1r5n 1.5 h toko c1 ceramic capacitor c1608x5r1h104k 0.1 f tdk c2 ceramic capacitor c1608x5r1h104k 0.1 f tdk c3 ceramic capacitor c1608x5r1v475k 4.7f tdk c4 ceramic capacitor c1608x5r1v475k 4.7f tdk c5 ceramic capacitor c1608x5r1v475k 4.7f tdk c6 ceramic capacitor c1608x5r1h104k 0.1 f tdk c7 ceramic capacitor c16 08x5r1h474k 0.47 f tdk c8 ceramic capacitor c1608x5r1v475k 4.7 f tdk c9 ceramic capacitor c1608x5r1a106k 10 f tdk c10 ceramic capacitor c1608x5r1a106k 10 f tdk r1 resistor rr0816p - 104 - d 100k ssm r2 resistor rr0816p - 104 - d 100k ssm r3 resistor rr0816 p - 104 - d 100k ssm r4 resistor rr0816p - 104 - d 100k ssm toko : toko, inc. tdk : tdk corporation ssm : susumu co., ltd. note: the list above is recommended parts. document number: 002 - 08407 rev. *b page 45 of 69 MB39C031 25. reference data ? dc/dc load efficiency characteristics ? dd1 vo=1.0v ( m in) vo=1.2v vo=1.3 v ( m ax) load efficiency load efficiency load efficiency vin=2.5v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] load efficiency load efficiency load efficiency vin=3.6v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] load efficien cy load efficiency load efficiency vin=5.5v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] 0 10 20 30 40 50 60 70 80 90 100 0 . 001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 10 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 46 of 69 MB39C031 ? dd 2 vo=1.2v ( m in) vo=1.8v vo=1.95v ( m ax) load efficiency load efficiency load efficiency vin=2.5v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] load efficiency load efficiency load efficiency vin=3.6v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] load efficiency load efficiency load efficiency vin=5.5v efficiency [%] efficiency [%] efficiency [%] load current [a] load current [a] load current [a] 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm 0 10 20 30 40 50 60 70 80 90 100 0.001 0.01 0.1 1 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 47 of 69 MB39C031 ? dc/dc line e fficiency characteristics ? dd 1 vo=1.0v ( m in) vo=1.2v vo=1.3v ( m ax) line efficiency characteristics (io=400ma) line efficiency characteristics (io=400ma) line efficiency characteristics (io=400ma) efficiency [%] efficiency [%] efficiency [%] input voltage vin[v] input voltage vin[v] input voltage v in[v] ? dd 2 vo=1.2v ( m in) vo=1.8v vo=1.95v ( m ax) line efficiency characteristics (io=400ma) line efficiency characteristics (io=400ma) line efficiency characteristics (io=400ma) efficiency [%] efficiency [%] efficiency [%] input voltage vin[v] input voltage vin[v] input voltage vin[v] 60 65 70 75 80 85 90 95 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 fixed pwm pfmpwm 60 65 70 75 80 85 90 95 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 fixed pwm pfmpwm 60 65 70 75 80 85 90 95 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 fixed pwm pfmpwm 6 0 6 5 7 0 7 5 8 0 8 5 9 0 9 5 1 0 0 2 .5 3 .0 3 .5 4 .0 4 .5 5 .0 5 .5 fixed pwm pfmpwm 60 65 70 75 80 85 90 95 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 fixed pwm pfmpwm 60 65 70 75 80 85 90 95 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 48 of 69 MB39C031 ? dc/dc l ine regulation characteristics ? dd 1 vo=1.0v ( m in) vo=1.2v vo=1.3v ( m ax) line regulation (io=400ma) line regulation (io=400ma) line regulation (io=400ma) output voltage vout[v] output voltage vout[v] output voltage vout[v] input voltage vin[v] input voltage vin[v] input volta ge vin[v] ? dd 2 vo=1.2v ( m in) vo=1.8v vo=1.95v ( m ax) line regulation (io=400ma) line regulation (io=400ma) line regulation (io=400ma) output voltage vout[v] output voltage vout[v] output voltage vout[v] input voltage vin[v] input voltage vin[v] input voltage vin[v] 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm 1.280 1.285 1.290 1.295 1.300 1.305 1.310 1.315 1.320 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm 1.930 1.935 1.940 1.945 1.950 1.955 1.960 1.965 1.970 2.50 3.00 3.50 4.00 4.50 5.00 5.50 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 49 of 69 MB39C031 ? ldo line regulation characteristics ? ldo vo=2.8v ( m in) vo=3.3v ( max ) line regulation ( io=50ma ) line regulation ( io=50ma ) output voltage vout[v] output voltage vout[v] input voltage vin[v] in put voltage vin[v] 2 . 740 2 . 760 2 . 780 2 . 800 2 . 820 2 . 840 2 . 860 3 3.5 4 4.5 5 5.5 3 . 240 3 . 260 3 . 280 3 . 300 3 . 320 3 . 340 3 . 360 3 3.5 4 4.5 5 5.5 document number: 002 - 08407 rev. *b page 50 of 69 MB39C031 ? dc/dc l oad regulation characteristics ? dd1 vo=1.0v ( m in) vo=1.2v vo=1.3v ( m ax) load regulation load regulation load regulation vin=2.5v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load current [a] lo ad regulation load regulation load regulation vin= 3.6 v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load current [a] load regulation load regulation load regulation vin= 5.5 v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load c urrent [a] 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.280 1.285 1.290 1.295 1.300 1.305 1.310 1.315 1.320 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.280 1.285 1.290 1.295 1.300 1.305 1.310 1.315 1.320 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 0.980 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm 1.280 1.285 1.290 1.295 1.300 1.305 1.310 1.315 1.320 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 51 of 69 MB39C031 ? dd 2 vo=1.2v ( m in) vo=1.8v vo=1.95v ( m ax) load regulation load regulation load regulation vin=2.5v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load current [a] load regulation load regulation load reg ulation vin= 3.6 v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load current [a] load regulation load regulation load regulation vin= 5.5 v output voltage [v] output voltage [v] output voltage [v] load current [a] load current [a] load current [a] 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.930 1.935 1.940 1.945 1.950 1.955 1.960 1.965 1.970 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.930 1.935 1.940 1.945 1.950 1.955 1.960 1.965 1.970 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.180 1.185 1.190 1.195 1.200 1.205 1.210 1.215 1.220 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.780 1.785 1.790 1.795 1.800 1.805 1.810 1.815 1.820 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm 1.930 1.935 1.940 1.945 1.950 1.955 1.960 1.965 1.970 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 fixed pwm pfmpwm document number: 002 - 08407 rev. *b page 52 of 69 MB39C031 ? ldo load regulati on characteristics ? ldo vo= 2.8 v ( m in) vo=3.3v ( m ax) load regulation load regulation vin= 3.0 v output voltage [v] vin=3.5v output voltage [v] load current [a] load current [a] load regulation load regulation vin= 3.6 v output voltage [v] vin= 3.6 v output voltage [v] load current [a] load current [a] load regulation load regulation vin= 5.5 v output voltage [v] vin= 5.5 v output voltage [v] load current [a] load current [a] 2 . 750 2 . 760 2 . 770 2 . 780 2 . 790 2 . 800 2 . 810 2 . 820 2 . 830 2 . 840 2 . 850 0 0.05 0.1 0.15 0.2 0.25 0 0.05 0.1 0.15 0.2 0.25 3 . 240 3 . 260 3 . 280 3 . 300 3 . 320 3 . 340 3 . 360 0 0.05 0.1 0.15 0.2 0.25 2 . 750 2 . 760 2 . 770 2 . 780 2 . 790 2 . 800 2 . 810 2 . 820 2 . 830 2 . 840 2 . 850 0 0.05 0.1 0.15 0.2 0.25 3 . 240 3 . 260 3 . 280 3 . 300 3 . 320 3 . 340 3 . 360 0 0.05 0.1 0.15 0.2 0.25 2 . 750 2 . 760 2 . 770 2 . 780 2 . 790 2 . 800 2 . 810 2 . 820 2 . 830 2 . 840 2 . 850 0 0.05 0.1 0.15 0.2 0.25 3 . 240 3 . 260 3 . 280 3 . 300 3 . 320 3 . 340 3 . 360 document number: 002 - 08407 rev. *b page 53 of 69 MB39C031 ? dc/dc output ripple waveform ? dd1 ( fixed pwm mode ) output voltage =1.2v setting io=0ma io=400ma io=1400ma vin= 2.5v vin=3.6v vin=5.5v document number: 002 - 08407 rev. *b page 54 of 69 MB39C031 ? dd1 (pfm/pwm mode ) output voltage =1.2v setting io=0ma io=400ma io=1400ma vin=2.5v vin=3.6v vin=5.5v document number: 002 - 08407 rev. *b page 55 of 69 MB39C031 ? dd2 (fixed pwm mode ) output voltage =1.8v setting io=0ma io=400ma io=600ma vin=2.5v vin=3.6v vin=5.5v document number: 002 - 08407 rev. *b page 56 of 69 MB39C031 ? dd2 (pfm/pwm mode ) output voltage =1.8v setting io=0ma io=400ma io= 600 ma vin=2.5v vin=3.6v vin=5.5v document number: 002 - 08407 rev. *b page 57 of 69 MB39C031 ? dd1 startup/shutdown waveform output voltage =1.2v setting soft - start setting=0.9m s fixed pwm mode control usi ng the external pin (ctl1) vcc = 2.5v io=1400ma io=0ma vcc = 3.6v io=1400ma io=0ma vcc = 5.5v io= 140 0 ma io=0ma document number: 002 - 08407 rev. *b page 58 of 69 MB39C031 ? dd2 startup/shutdown waveform output voltage =1.8v setting soft - start setting=0.9m s fixed pwm mode control using the external pin (ctl2) vcc = 2.5v io=600ma io=0ma vcc = 3.6v io=600ma io=0ma vcc = 5.5v io= 600ma io=0ma document number: 002 - 08407 rev. *b page 59 of 69 MB39C031 ? ldo startup/shutdown waveform output voltage =3.3v setting soft - start setting =2.7ms control using the external pin (ctll) vcc = 3.6v io= 250 ma io=0ma vcc = 5 .5v io= 250 ma io=0ma document number: 002 - 08407 rev. *b page 60 of 69 MB39C031 ? dc/dc sudden load change c haracteristics ? dd1( fixed pwm mode ) 0ma ? 1400ma/10 s output voltage =1.2v setting vcc =2.5v vcc =3.6v vcc =5.5v document number: 002 - 08407 rev. *b page 61 of 69 MB39C031 ? dd2 ( fixed pwm mode ) 0ma ? 600ma/10 s output voltage =1.8v setting vcc =2.5v vcc =3.6v vcc =5.5v document number: 002 - 08407 rev. *b page 62 of 69 MB39C031 ? dd1 (pfm/pwm mode ) 0ma ? 1400ma/10 s output voltage =1.2v setting vcc =2.5v vcc =3.6v vcc =5.5v document number: 002 - 08407 rev. *b page 63 of 69 MB39C031 ? dd2 (pfm/pwm mode ) 0ma ? 600ma/10 s output voltage =1.8v setting vcc =2.5v vcc =3.6v vcc =5.5v document number: 002 - 08407 rev. *b page 64 of 69 MB39C031 ? ldo sudden load change c haracteristics ? ldo 0ma ? 150ma/2 s output voltage = 3.3v setting vcc =3.6v vcc =5.5v ? power d issipation power dissipation vs. operati on am bient temperature t emperature [ c ] document number: 002 - 08407 rev. *b page 65 of 69 MB39C031 26. usage precaution 1. do not configure the ic over the maximum ratings . i f the lc is used over the maximum ratings, the lsl may be permanently damaged. it is preferable for the device to be normally operated within the recommended usage conditions. usage outside of these conditions can have a bad effect on th e reliability of the lsi. 2. use the devices within recommended operating conditions . the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's electrical characteristics are war ranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their representatives beforehand. 3. printed circuit board ground lines sho uld be set up with consideration for common impedance. 4. take appropriate measures against static electricity . ? containers for semiconductor materials should have anti - static protection or be made of conductive material. ? after mounting, printed circuit board s should be stored and shipped in conductive bags or containers. ? work platforms, tools, and instruments should be properly grounded. ? working personnel should be grounded with resistance of 250 k to 1 m in series between body and ground. 5. do not apply neg ative voltages . the use of negative voltages below - 0.3 v may cause the parasitic transistor to be activated on lsi lines, which can cause malfunctions. 6. when all channels are operating, the reliability level is designed under the condition that the average ambient temperature ta=+60 c , the typical input voltage, the typical output voltage and the typical output current condition are used. document number: 002 - 08407 rev. *b page 66 of 69 MB39C031 27. ordering information part number pack a ge remarks mb39c31wqn 28 - pin plastic qfn ( wno028 ) C 28. preset c ode (MB39C031) preset code dd1 output voltage p reset code value dd2 output voltage p reset code value ldo output voltage p reset code value 111 1.00v 1.20v 2.85v 112 1.00v 1.20v 3.30v 121 1.00v 1.35v 2.85v 122 1.00v 1.35v 3.30v 131 1.00v 1.50v 2.85v 13 2 1.00v 1.50v 3.30v 141 1.00v 1.80v 2.85v 142 1.00v 1.80v 3.30v 211 1.10v 1.20v 2.85v 212 1.10v 1.20v 3.30v 221 1.10v 1.35v 2.85v 222 1.10v 1.35v 3.30v 231 1.10v 1.50v 2.85v 232 1.10v 1.50v 3.30v 241 1.10v 1.80v 2.85v 242 1.10v 1.80v 3.30v 311 1 .20v 1.20v 2.85v 312 1.20v 1.20v 3.30v 321 1.20v 1.35v 2.85v 322 1.20v 1.35v 3.30v 331 1.20v 1.50v 2.85v 332 1.20v 1.50v 3.30v 341 1.20v 1.80v 2.85v 342 1.20v 1.80v 3.30v 411 1.30v 1.20v 2.85v 412 1.30v 1.20v 3.30v 421 1.30v 1.35v 2.85v 422 1.30 v 1.35v 3.30v 431 1.30v 1.50v 2.85v 432 1.30v 1.50v 3.30v 441 1.30v 1.80v 2.85v 442 1.30v 1.80v 3.30v document number: 002 - 08407 rev. *b page 67 of 69 MB39C031 29. package dimensions package code: wno028 002 - 15159 rev. ** document number: 002 - 08407 rev. *b page 68 of 69 MB39C031 document history document title: MB39C031 2ch buck dc/dc converter + 1ch ldo with i 2 c i nterface and sw fet document number: 002 - 08407 revision ecn orig. of change submission date description of change ** ? taoa 11/2 0/201 3 migrated to cypress and assig ned document number 002 - 08407 . no change to document contents or format. * a 5132 453 taoa 03/08 /2016 updated to cypress template * b 5734750 hixt 0 5 / 1 8 /201 7 updated pin assignment : change the package name from lcc - 28p - m70 to wno028 updated ordering information : change the package name from lcc - 28p - m70 to wno028 deleted ev board ordering information deleted marking format (lead free version) deleted labeling sample (lead free version) deleted MB39C031 recommended conditions of moisture sensitivity level updated package dimensions : updated to cypress format document number: 002 - 08407 rev. *b may 18, 2017 page 69 of 69 MB39C031 sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturers representatives, and distributors. to find the office closest to you, visit us at cypress locations . products arm ? cortex ? microcontrollers cypress.com/arm automotive cypress.com/automotive clocks & buffers cypress.com/clocks int erface cypress.com/interface internet of things cypress.com/iot memory cypre ss.com/memory microcontrollers cypress.com/mcu psoc cypress.com/psoc power management ics cypress.com/p mic touch sensing cypress.com/touch usb controllers cypress.com/usb wireless/rf cypress.com/wireless psoc ? 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