32k x 36 dual i/o dual address synchronous sra m cy7c1299 a cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-05138 rev. *c revised may 14, 2003 features ? fast clock speed: 100 and 83 mhz fast access times: 5.0/6.0 ns max. single clock operation single 3.3v ?5% and +5% power supply v cc separate v ccq for output buffer two chip enables for simple depth expansion address, data input, ce1 , ce2, ptx , pty , wex , wey , and data output registers on-chip concurrent reads and writes two bidirectional data buses can be configured as separate i/o pass-through feature asynchronous output enables (oex , oey ) lvttl-compatible i/o self-timed write automatic power-down 176-pin tqfp package functional description the cy7c1299a sram integrates 32,768 36 sram cells with advanced synchronous peripheral circuitry. it employs high-speed, low-power cmos designs using advanced triple-layer polysilicon, double-layer metal technology. each memory cell consists of four transistors and two high-valued resistors. the cy7c1299a allows the user to concurrently perform reads, writes, or pass-through cycles in combination on the two data ports. the two address ports (ax, ay) determine the read or write locations for their respective data ports (dqx, dqy). all input pins except output enable pins (oex , oey ) are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, depth-expansion chip enables (ce1 , ce2), pass-through controls (ptx and pty ), and read-write control (wex and wey ). the pass-through feature allows data to be passed from one port to the other, in either direction. the ptx input must be asserted to pass data from port x to port y. the pty will likewise pass data from port y to port x. a pass-through operation takes precedence over a read operation. for the case when ax and ay are the same, certain protocols are followed. if both ports are read, the reads occur normally. if one port is written and the other is read, the read from the array will occur before the data is written. if both ports are written, only the data on dqy will be written to the array. the cy7c1299a operates from a +3.3v power supply. all inputs and outputs are lvttl compatible. these dual i/o, dual address synchronous srams are well suited for atm, ethernet switches, routers, cell/frame buffers, sna switches and shared memory applications. the cy7c1299a needs one extra cycle after power for proper power-on reset. the extra cycle is needed after v cc is stable on the device. this device is available in a 176-pin tqfp package. note: 1. for 32k x 36 devices, ax and ay are 15-bit-wide buses. logic block diagram [1] oey# ce2 ce1# oey# ce2 ce1#
cy7c1299 a document #: 38-05138 rev. *c page 2 of 11 package description selection guide -100 -83 unit maximum access time 5.0 6.0 ns maximum operating current 500 430 ma maximum cmos standby current 100 100 ma 176-pin tqfp 132 vss 45 vss notes: 1. ax17 and ay17 at pins 141 and 140 are for 256k x 36 devices only . for 128k x 36 devices, pins 141 and 140 are vss. 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 133 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 vss vccq dqy35 dqx35 vss vss ay5 ax5 vss vcc ax14 ay14 vccq vss dqx1 dqy1 vss dqx0 dqy0 ax13 ay13 ax12 ay12 ax11 ay11 ax10 ay10 ay4 ax4 ay3 ax3 ay2 ax2 ay1 ax1 ay0 ax0 dqy34 dqx34 dqx20 dqy20 vss vccq dqx21 dqy21 dqx22 dqy22 vss vccq dqx23 dqy23 dqx24 dqy24 vss vccq dqx25 dqy25 dqx26 dqy26 vss vcc dqy27 dqx27 dqy28 dqx28 vss vccq dqy29 dqx29 dqy30 dqx30 vss vccq dqy31 dqx31 dqy32 dqx32 vss vccq dqy33 dqx33 vss vss dqx1 5 dqy1 5 vccq vss dqx1 4 dqy1 4 dqx1 3 dqy1 3 vccq vss dqx1 2 dqy1 2 dqx1 1 dqy1 1 vccq vss dqx1 0 dqy1 0 dqx9 dqy9 vcc vss dqy8 dqx8 dqy7 dqx7 vccq vss dqy6 dqx6 dqy5 dqx5 vccq vss dqy4 dqx4 dqy3 dqx3 vccq vss dqy2 dqx2 vss vss vss vccq dqy18 dqx18 ax6 ay6 ax7 ay7 vcc vss ax8 ay8 ax9 vcc vss dqx16 dqy16 vss dqx17 dqy17 ay9 ax17* ay17* pty# ptx# wey# wex# ce2x ce1x# oey# oex# vss nc nc nc vss nc nc clk dqy19 dqx19 ax16 ay16 ax15 ay15 ce2y ce1y# nc nc nc nc nc ce1# nc nc nc nc nc
cy7c1299 a document #: 38-05138 rev. *c page 3 of 11 pin definitions name i/o description ax0 ? ax14 input- synchronous synchronous address inputs of port x : do not allow address pins to float. ay0 ? ay14 input- synchronous synchronous address inputs of port y : do not allow address pins to float. wex input- synchronous read write of port x : wex signal is a synchronous input that identifies whether the current loaded cycle is a read or write operation. wey input- synchronous read write of port y : wey signal is a synchronous input that identifies whether the current loaded cycle is a read or write operation. ptx input- synchronous pass-through of port x : ptx signal is synchronous input that enables passing port x input to port y output. pty input- synchronous pass-through of port y : pty signal is synchronous input that enables passing port y input to port x output. oex input asynchronous output enable of port x : oex must be low to read data. when oex is high, the dqxx pins are in high-impedance state. oey input asynchronous output enable of port y : oey must be low to read data. when oey is high, the dqyx pins are in high impedance state. dqx0? dqx35 input/ output data inputs/outputs of port x: both the data input path and data output path are registered and triggered by the rising edge of clk. dqy0? dqy35 input/ output data inputs/outputs of port y : both the data input path and data output path are registered and triggered by the rising edge of clk. clk input- synchronous clock : this is the clock input to this device. except for oex and oey , timing references of the address, data in, and all control signals for the device are made with respect to the rising edge of clk. ce1 input- synchronous synchronous active low chip enable : ce1 sampled high at the rising edge of clock initiates a deselect cycle. ce2 input- synchronous synchronous active high chip enable : ce2 sampled low at the rising edge of clock initiates a deselect cycle. vcc supply power supply: +3.3v ?5% and +5%. vss ground ground : gnd. vss ground ground : gnd. no chip current flows through these pins. however, user needs to connect gnd to these pins. vccq i/o supply output buffer supply : +3.3v ?5% and +5%. nc ? no connect : these signals are not internally connected. user can connect them to v cc , v ss , or any signal lines or simply leave them floating. cycle description truth table [2, 3, 4, 5, 6, 7, 8, 9] operation ce1 ce2 wex wey ptx pty deselect cycle h x x x x x deselect cycle x l x x x x write port x l h0xxx write port y l h x 0 x x pass-through from x to y l h x x 0 x pass-through from y to x l h x x x 0 read port x l h 1 x 1 1 read port y l hx111 notes: 2. x means ?don?t care.? h means logic high. l means logic low. 3. all inputs except oex and oey must meet set-up and hold times around the rising edge (low to high) of clk. 4. oex and oey must be asserted to avoid bus contention during write and pass-through cycles. for a write and pass-through operation followin g a read operation, oex /oey must be high before the input data required set-up time plus high-z time for oex /oey and staying high throughout the input data hold time. 5. operation number 3?6 can be used in any combination. 6. operation number 4 and 7, 3 and 8, 7 and 8 can be combined. 7. operation number 5 can not be combined with operation number 7 or 8 because pass-through operation has higher priority over a read operation. 8. operation number 6 can not be combined with operation number 7 or 8 because pass-through operation has higher priority over a read operation. 9. this device contains circuitry that will ensure the outputs will be in high-z during power-up.
cy7c1299 a document #: 38-05138 rev. *c page 4 of 11 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ..................................... ? 55c to +125c ambient temperature with power applied .................................................... ? 10c to +85c supply voltage on v cc relative to gnd .........? 0.5v to +4.6v dc voltage applied to outputs in high-z state [10] ....................................? 0.5v to v ccq + 0.5v dc input voltage [10] ................................? 0.5v to v ccq + 0.5v current into outputs (low)......................................... 20 ma static discharge voltage.......................................... > 1601v (per mil-std-883, method 3015) latch-up current.................................................... > 200 ma operating range range ambient temperature [11] v cc /v ccq [12,21,22] com?l 0c to +70c 3.3v 5% electrical characteristics over the operating range parameter description test conditions min. max. unit vcc power supply voltage 3.135 3.465 v vcc q i/o supply voltage 3.135 3.465 v v oh output high voltage vcc = min., i oh = ?4.0 ma 2.4 v v ol output low voltage vcc = min., i ol = 8.0 ma 0.4 v v ih input high voltage [13] 2.0 vcc + 0.5v v v il input low voltage [14] ? 0.5 0.8 v i x input load current gnd v in vcc q ? 5 5 a i oz output leakage current gnd v in vcc q, output disabled ? 5 5 a i cc vcc operating supply vcc = max., i out = 0 ma, f = f max = 1/t cyc 10-ns cycle, 100 mhz 500 ma 12-ns cycle, 83mhz 430 ma i sb automatic ce power-down current?cmos inputs max. vcc, device deselected [ 15 ] , v in 0.3v or v in > vcc q ? 0.3v, f = f max = 1/t cyc 10-ns cycle, 100 mhz 140 ma 12-ns cycle, 83mhz 120 ma capacitance [16] parameter description test conditions max. unit c in input capacitance t a = 25c, f = 1 mhz, vcc = 3.3v, vcc q = 3.3v 8 pf c clk clock input capacitance 9 pf c i/o input/output capacitance 8 pf notes: 10. minimum voltage equals ?2.0v for pulse duration less than 20 ns. 11. t a is the case temperature. 12. power supply ramp up should be monotonic. 13. overshoot: v ih +6.0v for t t kc /2. 14. undershoot: v il ?2.0v for t t kc /2. 15. ?device deselected? means the device is in power-down mode as defined in the truth table. 16. tested initially and after any design or process change that may affect these parameters.
cy7c1299 a document #: 38-05138 rev. *c page 5 of 11 ac test loads and waveforms [17] thermal resistance [16] parameter description test conditions tqfp typ. unit ja thermal resistance (junction to ambient) (@200 lfm) single-layer printed circuit board 40 c/w jc thermal resistance (junction to ambient) (@200 lfm) four-layer printed circuit board 35 c/w ja thermal resistance (junction to board) bottom 23 c/w jc thermal resistance (junction to case) to p 9 c/w switching characteristics over the operating range [17, 18, 19] parameter description -100 -83 unit min. max. min. max. clock t kc clock cycle time 10 12 ns t kh clock high time 3.5 4.0 ns t kl clock low time 3.5 4.0 ns output times t kq clock to output valid 5.0 6.0 ns t kqx clock to output invalid 1.5 1.5 ns t kqlz clock to output in low-z [20] 0 0 ns t kqhz clock to output in high-z [20] 3.0 3.0 ns t oeq oex /oey to output valid 5.0 6.0 ns t oelz oex /oey to output in low-z [20] 0 0 ns t oehz oex /oey to output in high-z [20] 3.0 3.0 ns set-up times ts addresses, controls and data in 1.8 2.0 ns hold times th addresses, controls and data in 0.5 0.5 ns notes: 17. overshoot: vih (ac) cy7c1299 a document #: 38-05138 rev. *c page 6 of 11 switching waveforms [23] note: 23. ce low means ce1 equals low and ce2 equals high. ce high means ce1 equals high or ce2 equals low. clk ax ce# (see note) oex# dqx 2 t kq t oelz t h t s t kh t kl t kc t oeq 1 4 3 6 5 8 7 9 q(1) q(2) q(3) q(5) q(6) q(7) oey# dqy q(12) q(13) q(14) q(16) q(6) q(7) ay 13 12 15 14 6 16 19 7 20 t h t s t kqhz t kq t oehz t kqlz port x port y read cycle timing from both ports (wex , wey , ptx , pty high) (see note 19)
cy7c1299 a document #: 38-05138 rev. *c page 7 of 11 switching waveforms (continued) [23] clk ax ce# (see note) oex# dqx 2 t h t s t kh t kl t kc 1 4 3 6 5 8 7 9 d(3) oey# dqy ay 13 12 15 14 6 5 19 18 20 t h t s wex# wey# port x port y d(2) d(4) d(8) d(9) d(14) d(15) d(19) d(5) d(6) d(18) t h t s port y takes priority over port x when ax=ay and writing to both ports. write cycle timing to both ports (ptx , pty high) (see note 19)
cy7c1299 a document #: 38-05138 rev. *c page 8 of 11 switching waveforms (continued) [23] clk ax ce# (see note) oex# dqx 2 t h t s t kh t kl t kc 1 4 3 6 5 8 7 9 d(3) oey# dqy ay 13 12 15 14 17 16 19 18 20 wex# wey# port x port y d(2) d(x) pty# pty# d(y) d(6) q(3) d(x) d(y) q(17) t kqhz t kq t kqx t s t h note: write to port x and pass-through to port y (see note 19) ptx
cy7c1299 a document #: 38-05138 rev. *c page 9 of 11 switching waveforms (continued) [23] 3 clk ax oex# dqx 2 t h t s t kh t kl t kc 1 1 2 oey# dqy ay wex# wey# port x port y d(def) port y takes priority over port x when ax=ay and writing to both ports. d(abc) q(pqr) q(xyz) q(jkl) d(xyz) d(pqr) q(jkl) d(jkl) q(pqr) try to write try to write read read read read read read 3 2 1 1 2 write write read read read read read read ptx# = pty# = high d(value) = value is the input of the data port. q(value) = value is the output of the data port. combination read/write with same address on each port write ordering information speed (mhz) ordering code package name package type operating range 100 cy7c1299a-100ac a176 176-pin tqfp commercial 83 CY7C1299A-83AC
cy7c1299 a document #: 38-05138 rev. *c page 10 of 11 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semi conductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support syst ems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies th at the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package diagram all product and company names mentioned in this document may be the trademarks of their respective holders. 176-lead thin quad flat pack (24 x 24 x 1.4 mm) a176 51-85132-**
cy7c1299 a document #: 38-05138 rev. *c page 11 of 11 document history page document title: cy7c1299a 32k x 36 dual i/o dual address synchronous sram document number: 38-05138 rev. ecn no. issue date orig. of change description of change ** 109817 10/16/01 nsl new data sheet *a 113014 04/09/02 kom corrected i cc data to 500 and 430 ma from 350 and 300 ma. updated logic block diagram *b 123151 01/18/03 rbi updated power-up requirements in ac test loads and waveforms and operating range *c 126196 05/14/03 apt corrected pinout on package description/pin definitions corrected cycle description truth table corrected logic block diagram added graph (d) in ac test loads and waveforms
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