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mp8848 6a, high-efficiency , synchronous, step-down switcher with i 2 c interface mp8848 rev. 1.0 www.monolithicpower.com 1 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. the future of analog ic technology description the mp8848 is a highly integrated, high- frequency, synchronous, step-down switcher with an i 2 c control interface. the mp8848 can support up to 6a of load current over an input supply range from 2.7v to 6v with excellent load and line regulation. constant-frequency hysteretic mode provides an extremely fast transient response without loop compensation to achieve high efficiency easily under light-load condition. the output voltage level can be controlled on- the-fly through a 3.4mbps i 2 c serial interface. the voltage range can be adjusted from 0.6v to 1.235v in 5mv steps. the voltage slew rate, switching frequency, and power-saving mode are also selectable through the i 2 c interface. full protection features include internal soft start, over-current protection (ocp), and over- temperature protection (otp). the mp8848 requires a minimal number of readily available, standard, external components and is available in a compact qfn-15 (2mmx3mm) package. features ? 2.7v to 6v input voltage range ? up to 6a load current ? internal 32m ? high-side and 15m ? low- side power mosfets ? i 2 c-compatible interface up to 3.4mbps ? i 2 c-programmable output range from 0.6v to 1.235v in 5mv steps ? factory adjustable switching frequency from 0.85mhz to 2.2mhz ? power-saving mode selectable via i 2 c ? internal 1ms soft start ? power good indicator ? current overload and thermal shutdown protection ? available in a qfn-15 (2mmx3mm) package applications ? processor core supplies ? micro converters a ll mps parts are lead-free, halogen-free, and adhere to the rohs directive. for mps green status , please visit the mps website unde r quality assurance. ?mps? and ?the future of analog ic technology? are registered trademarks of monolithic power systems, inc. typical application 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.01 0.1 1 10 pfm pwm
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 2 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. ordering information part number* package top marking MP8848GD qfn-15 (2mmx3mm) see below * for tape & reel, add suffix ?z (e.g. MP8848GD?z) top marking avv: product code of MP8848GD y: year code ww: week code lll: lot number package reference top view qfn-15 (2mmx3mm)
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 3 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. absolute maxi mum ratings (1) supply voltage (vin) ......................... -0.3v to 7v v sw ................................ -0.3v (-5v for <10ns) to 6.5v (8v for <10ns or 10v for <3ns) all other pins .................................. -0.3v to 6.5v junction temperature ................................ 150c lead temperature ..................................... 260c continuous power dissipation (t a = +25c) (2)(4) qfn-15 (2mmx3mm) ................................. 3.5w storage temperature .................. -65c to 150c recommended operating conditions (3) supply voltage (vin) .......................... 2.7v to 6v output voltage (vout) ............... 0.6v to 1.235v operating junction temp. (t j ) ... -40c to +125c thermal resistance ja jc qfn-15 (2mmx3mm) ev8848-d-00a (4) .................. 35 ........ 8 .... c/w jesd51-7 (5) .......................... 70 ....... 15 ... c/w notes: 1) exceeding these ratings may damage the device. 2) the maximum allowable power dissipation is a function of the maximum junction temperature t j (max), the junction-to- ambient thermal resistance ja , and the ambient temperature t a . the maximum allowable continuous power dissipation at any ambient temperature is calculated by p d (max) = (t j (max)-t a )/ ja . exceeding the maximum allowable powe r dissipation produces an excessive die temperature, causing the regulator to go into thermal shutdown. internal thermal shutdown circuitry protects the device from permanent damage. 3) the device is not guaranteed to function outside of its operating conditions. 4) measured on ev8848-d-00a, 4-layer pcb. 5) measured on jesd51-7, 4-layer pcb.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 4 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics vin = 5v, t j = -40c to +125c (6) , typical value is tested at t j = +25c. the limit over temperature is guaranteed by characterization, unless otherwise noted. parameter symbol condition min typ max units input voltage range v in 2.7 6 v quiescent current i q en = 1.8v, no switching, pfm mode 300 a shutdown current i s en = gnd, t j = 25c 1 a internal reference voltage vref t j = 25c 0.591 0.600 0.609 v -40c < t j < 125c 0.585 0.600 0.615 v lowest output voltage v low register = 00h, t j = 25c 0.591 0.600 0.609 v -40c < t j < 125c 0.585 0.600 0.615 v highest output voltage v high register = 7fh, t j = 25c 1.216 1.235 1.254 v -40c < t j < 125c 1.204 1.235 1.266 v output voltage step v step 5 mv high-side switch on resistance r hson 32 m ? low-side switch on resistance r lson 15 m ? uvlo rising threshold v uvlor 2.55 2.7 v uvlo hysteretic v uvlohy 150 mv switching frequency f sw 0.85 2.2 mhz frequency variation f sw 25% minimum on time ( 7 ) t minon 60 ns switch leakage i sw v en = 0v, vin = 5v, v sw = 0v and 5v, t j = 25c 1 a en input current i en v en = 5v 4 a en logic low voltage v enl 0.4 v en logic high voltage v enh 1.8 v power good uv threshold rising pgvth-hi good 0.9 vout power good uv threshold falling pgvth-lo fault 0.85 vout power good ov threshold rising pgvth-hi fault 1.1 vout power good ov threshold falling pgvth-lo good 1.05 vout power good pull-down voltage v pgl i sink = 1ma 0.4 v power good delay t pgd 30 s power good leakage i pgd 1 a
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 5 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. electrical characteristics (continued) vin = 5v, t j = -40c to +125c (6) , typical value is tested at t j = +25c. the limit over temperature is guaranteed by characterization, unless otherwise noted. parameter symbol condition min typ max units vout ovp threshold rising edge +10% v target high-side switch peak current limit (source) i peak 7 11 a high-side switch valley current limit (7) i valley 5.8 a low-side switch current limit (sink) pfm mode 0 a pwm mode ( 7 ) -5 a soft-start time t ss-on 0.4 1 1.6 ms discharge resistor 500 ? thermal warning ( 6 ) 130 ? c thermal shutdown ( 6 ) 150 ? c dac resolution ( 7 ) 7 bits note: 6) not tested in production, guaranteed by over-temperature correlation. 7) guaranteed by engineering sample characterization.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 6 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. i/o level characteristics parameter symbol condition hs-mode ls-mode units min max min max low-level input voltage v il -0.5 0.3vcc -0.5 0.3v cc v high-level input voltage v ih 0.7v cc v cc + 0.5 0.7v cc v cc + 0.5 v hysteresis of schmitt trigger inputs v hys v cc > 2v 0.05v cc - 0.05v cc - v v cc < 2v 0.1v cc - 0.1v cc - low-level output voltage (open drain) at 3ma sink current v ol v cc > 2v 0 0.4 0 0.4 v v cc < 2v 0 0.2v cc 0 0.2v cc low-level output current i ol - 3 - 3 ma transfer gate on resistance for currents between sda and scah, or scl and sclh r onl vol level, iol = 3ma - 50 - 50 ? transfer gate on resistance between sda and scah, or scl and sclh r onh both signals (sda and sdah, or scl and sclh) at v cc level 50 - 50 - k ? pull-up current of the sclh current source i cs sclh output levels between 0.3v cc and 0.7v cc 2 6 2 6 ma rise time of the sclh or scl signal t rcl output rise time (current source enabled) with an external pull-up current source of 3ma capacitive load from 10pf to 100pf 10 40 ns capacitive load of 400pf 20 80 ns fall time of the sclh or scl signal t fcl output fall time (current source enabled) with an external pull-up current source of 3ma capacitive load from 10pf to 100pf 10 40 ns capacitive load of 400pf 20 80 20 250 ns rise time of sdah signal t rda capacitive load from 10pf to 100pf 10 80 - - ns capacitive load of 400pf 20 160 20 250 ns fall time of sdah signal t fda capacitive load from 10pf to 100pf 10 80 - - ns capacitive load of 400pf 20 160 20 250 ns input current for each i/o pin i i input voltage between 0.1v cc and 0.9v cc - 10 -10 +10 a capacitance for each i/o pin c i - 10 - 10 pf
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 7 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. i 2 c port signal characteristics parameter symbol condition cb = 100pf cb = 400pf units min max min max sclh and scl clock frequency f schl 0 3.4 0 0.4 mhz set-up time for a repeated start condition t su;sta 160 - 600 - ns hold time (repeated) start condition t hd;sta 160 - 600 - ns low period of the scl clock t low 160 - 1300 - ns high period of the scl clock t high 60 - 600 - ns data set-up time t su:dat 10 - 100 - ns data hold time t hd ; dat 0 70 0 - ns rise time of sclh signal t rcl 10 40 20*0.1cb 300 ns rise time of sclh signal after a repeated start condition and after an acknowledge bit t fcl1 10 80 20*0.1cb 300 ns fall time of sclh signal t fcl 10 40 20*0.1cb 300 ns rise time of sdah signal t fda 10 80 20*0.1cb 300 ns fall time of sdah signal t fda 10 80 20*0.1cb 300 ns set-up time for a stop condition t su;sto 160 - 600 - ns bus free time between a stop and start condition t buf 160 - 1300 - ns data valid time t vd ; dat - 16 - 90 ns data valid acknowledge time t vd;ack - 160 - 900 ns capacitive load for each bus line c b sdah and sclh line - 100 - 400 pf sdah + sda line and sclh + scl line - 400 - 400 pf noise margin at the low level v nl for each connected device - 0.1v cc 0.1v cc - v noise margin at the high level v nh for each connected device - 0.2v cc 0.2v cc - v note: v cc is the i 2 c bus voltage in the 1.5v to 3.3v range.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 8 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical characteristics vin = 5v, vout = 0.94v, l = 0.47h, t a = 25c, unless otherwise noted. vin uvlo rising and falling threshold vs. temperature en rising and falling threshold vs. temperature highest vout vs. temperature 200 250 300 350 400 234567 0 0.05 0.1 0.15 0.2 234567 0.500 0.550 0.600 0.650 0.700 0.750 0.800 -60 -40 -20 0 20 40 60 80 100 1.000 1.050 1.100 1.150 1.200 1.250 1.300 -60 -40 -20 0 20 40 60 80 100 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 -60 -40 -20 0 20 40 60 80 100 rising falling 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -60 -40 -20 0 20 40 60 80 100 rising falling 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.01 0.1 1 10 pfm pwm 0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 0.01 0.1 1 10 pfm pwm -0.8% -0.6% -0.4% -0.2% 0.0% 0.2% 0.4% 0.6% 0.8% 01234567 v in =5v, v out =0.94v v in =3.6v, v out =0.94v
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 9 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical characteristics (continued) vin = 5v, vout = 0.94v, l = 0.47h, t a = 25c, unless otherwise noted. v in power down i out = 0a v in power down i out = 5a en on i out = 0a
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 10 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical characteristics (continued) vin = 5v, vout = 0.94v, l = 0.47h, t a = 25c, unless otherwise noted.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 11 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pin functions package pin # name description 1 pg power good output. 2 sda i 2 c serial data. 3, thermal pad gnd power ground. 4, 5, 6 vin input supply voltage. 7, 8, 9 sw switch note. 10 en on and off control. 11 agnd analog ground. 12 vout output voltage sensing. 13 scl i 2 c serial clock. 14 avin analog input supply voltage and multi-usage of p3 function.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 12 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. registers and description register map add name r/w d7 d6 d5 d4 d3 d2 d1 d0 00 status r ilim uvlo ovp voov vouv pgood otw en stat 01 vsel r/w en output reference 02 syscntlreg1 r/w switching frequency transient response pglohi vinovp mode 03 syscntlreg2 r/w reserved go out-dis gl_filt slew rate p3 enable p3 set 04 id1 r vendor id die id 05 id2 r reserved die rev note: the burst write cannot be on reg 03. default value of registers add name r/w d7 d6 d5 d4 d3 d2 d1 d0 00 status r n/a n/a n/a n/a n/a n/a n/a n/a 01 vsel r/w 1 1 0 0 0 1 0 0 02 syscntlreg1 r/w 1 0 0 0 1 1 0 0 03 syscntlreg2 r/w 0 0 0 1 0 0 0 1 04 id1 r 0 0 0 1 0 0 0 1 05 id2 r 0 0 0 0 0 0 0 0 register description 1. reg00 status name bits description ilim d7 when the bit is high, ic is in the current limit. uvlo d6 when the bit is high, vin is less than the uvlo threshold. ovp d5 when the bit is high, vin is greater than the ovp threshold. voov d4 when the bit is high, a voltage higher than 110% of the regulation voltage is presented. vouv d3 when the bit is high, a voltage lower th an 90% of the regulation voltage is presented. pgood d2 when the bit is high, the output is in regulat ion; otherwise, the output voltage is out of the 10% regulation window. otw d1 when the junction temperature is higher than 130c, the bit is high; otherwise, the bit is low. en stat d0 when the bit is high, the smps is enabl ed; when the bit is low, the smps is disabled. 2. reg01 vsel name bits description en d7 i 2 c controlled enable. when en is low, the c onverter is off. when en is high, the en bit takes over. output reference d[6:0] sets the output voltage from 0.6v to 1.235v (see table 1).
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 13 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. table 1: output voltage chart d[6:0] vout d[6:0] vout d[6:0] vout d[6:0] vout 000 0000 0.600 010 0000 0.760 100 0000 0.920 110 0000 1.080 000 0001 0.605 010 0001 0.765 100 0001 0.925 110 0001 1.085 000 0010 0.610 010 0010 0.770 100 0010 0.930 110 0010 1.090 000 0011 0.615 010 0011 0.775 100 0011 0.935 110 0011 1.095 000 0100 0.620 010 0100 0.780 100 0100 0.940 110 0100 1.100 000 0101 0.625 010 0101 0.785 100 0101 0.945 110 0101 1.105 000 0110 0.630 010 0110 0.790 100 0110 0.950 110 0110 1.110 000 0111 0.635 010 0111 0.795 100 0111 0.955 110 0111 1.115 000 1000 0.640 010 1000 0.800 100 1000 0.960 110 1000 1.120 000 1001 0.645 010 1001 0.805 100 1001 0.965 110 1001 1.125 000 1010 0.650 010 1010 0.810 100 1010 0.970 110 1010 1.130 000 1011 0.655 010 1011 0.815 100 1011 0.975 110 1011 1.135 000 1100 0.660 010 1100 0.820 100 1100 0.980 110 1100 1.140 000 1101 0.665 010 1101 0.825 100 1101 0.985 110 1101 1.145 000 1110 0.670 010 1110 0.830 100 1110 0.990 110 1110 1.150 000 1111 0.675 010 1111 0.835 100 1111 0.995 110 1111 1.155 001 0000 0.680 011 0000 0.840 101 0000 1.000 111 0000 1.160 001 0001 0.685 011 0001 0.845 101 0001 1.005 111 0001 1.165 001 0010 0.690 011 0010 0.850 101 0010 1.010 111 0010 1.170 001 0011 0.695 011 0011 0.855 101 0011 1.015 111 0011 1.175 001 0100 0.700 011 0100 0.860 101 0100 1.020 111 0100 1.180 001 0101 0.705 011 0101 0.865 101 0101 1.025 111 0101 1.185 001 0110 0.710 011 0110 0.870 101 0110 1.030 111 0110 1.190 001 0111 0.715 011 0111 0.875 101 0111 1.035 111 0111 1.195 001 1000 0.720 011 1000 0.880 101 1000 1.040 111 1000 1.200 001 1001 0.725 011 1001 0.885 101 1001 1.045 111 1001 1.205 001 1010 0.730 011 1010 0.890 101 1010 1.050 111 1010 1.210 001 1011 0.735 011 1011 0.895 101 1011 1.055 111 1011 1.215 001 1100 0.740 011 1100 0.900 101 1100 1.060 111 1100 1.220 001 1101 0.745 011 1101 0.905 101 1101 1.065 111 1101 1.225 001 1110 0.750 011 1110 0.910 101 1110 1.070 111 1110 1.230 001 1111 0.755 011 1111 0.915 101 1111 1.075 111 1111 1.235
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 14 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. 3. reg02 syscntlreg1 name bits description switching frequency d[7:5] d[7:5] switching frequency d[7:5] switching frequency 000 2.2mhz 100 1.25mhz (default) 001 2mhz 101 1.11mhz 010 1.67mhz 110 0.85mhz 011 -- 111 -- transient response d[4:3] d[4:3] response speed d[4:3] response speed 00 ultra-fast 01 fast (default) 10 normal 11 slow pg_lohi d2 a ?0? here sets pg to sense only a negative voltage excursion of vo from the reference. a ?1? (default) sets pg to det ect both a positive and ne gative excursion of vo from the reference. vin_ovp d1 a ?1? disables the vin ovp function. the conv erter continues operating. a ?0? (default) turns off the converter when vin reaches vin max. mode d0 a ?0? enables pfm mode; a high disables pfm mode. 4. reg03 syscntlreg2 name bits description reserved d[7:6] reserved. go d5 writing to this bit starts a vout tr ansition regardless of its initial value. output discharge d4 a ?0? disables the output discharge. the output voltage must be discharged by the load. a high enables the internal pull-down. gl_filt d3 a ?0? disables the pg delay. slew rate d2 d2 slew rate d2 slew rate 0 32mv/ s 1 8mv/ s p3 enable d1 a ?1? enables the p3 set function. only a ?1? can make the p3 set bit control the avin voltage. p3 set d0 when the p3 enable bit = 1, the avin voltage is pulled high if p3 set = 0; otherwise, the avin voltage is pulled low. 5. reg04 id1 name bits description vendor id d[7:4] vendor id. die id d[3:0] ic type. 6. reg05 id2 name bits description reserved d[7:4] reserved. die rev d[3:0] die revision. operation status condition pg regulation latch-off status bit vin over-voltage low off no ovp vin under-voltage low off n/a uvlo thermal warning low on no otw thermal shutdown low off yes n/a current limit high on no ilim output under-voltage low off yes vouv output over voltage (>110% of target output) low on no voov
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 15 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. block diagram i 2 c if & registers dac + _ ramp diff. amp en vout agnd scl sda pg vin sw gnd uvlo & power status control ss clock pwm + driver & control pll + clock figure 1: functional block diagram
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 16 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. operation the mp8848 is a low-voltage, 6a, synchronous, step-down converter with a controllable i 2 c interface. the mp8848 applies mps?s patented constant-frequency hysteretic control to utilize fast transient response of the hysteretic control and keep the switching frequency constant. no compensation is required, which simplifies the design procedure. the mp8848 integrates an i 2 c-compatible interface that allows transfers of up to 3.4mbps. this communication interface can be used for dynamic voltage scaling with voltage steps down to 5mv with the output voltage from 0.6v to 1.235v. the voltage transition slew rate can be controlled as well. light-load operation in light-load condition, the mp8848 uses a proprietary control scheme to save power and improve efficiency. the mp8848 turns off the low-side switch when the inductor current begins reversing. the mp8848 then works in discontinuous conduction mode (dcm) operation. enable (en) when the input voltage is greater than the under-voltage lockout (uvlo) threshold (typically 2.55v), the mp8848 can be enabled by pulling en above 1.8v. pull en down to ground to disable the mp8848. the ic can also be disabled by floating en. there is an internal 1m ? resistor from en to ground. soft start (ss) the mp8848 has a built-in soft start that ramps up the output voltage at a controlled slew rate, preventing inrush current and output voltage overshoot at start-up. the soft-start time is about 1ms. power good (pg) indicator the mp8848 has an open-drain output for power good (pg) indication. when the output voltage is within 10% of the regulation voltage, pg is pulled up to vin by the external resistor. current limit the mp8848 has a typical 11a current limit for the high-side switch. when the high-side switch reaches the current limit, the mp8848 expands the minimum off time until the current drops to 5.8a before the high-side switch is turned on for the next switching cycle. this prevents the inductor current from continuing to build up and damaging the components. thermal protection the mp8848 employs thermal shutdown by monitoring the junction temperature of the ic internally. if the junction temperature exceeds the thermal warning threshold (around 130c), otw is set. if there is no action or response from the system, the junction temperature continues rising until it exceeds the thermal shutdown threshold (typically 150c). after thermal shutdown, a new power start-up cycle is needed to turn on the mp8848 again.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 17 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. i 2 c interface the mp8848 can communicate with the core and the i 2 c for smart design. mps has a gui control interface (see figure 2). the installation process and usage can be found in the mp884x family software guide. i 2 c address the i 2 c slave address of the mp8848 is 0xc0h/0xc1h internally (see table 2). if other slave addresses are needed, please contact the factory. table 2: i 2 c slave address hex a7 a6 a5 a4 a3 a2 a1 a0 w 0xc0 r 0xc1 1 1 0 0 0 0 0 r/w address 0x60 i 2 c enable the mp8848?s en pin can start up and shut down the converter, and the i 2 c en pin can control the converter as well. the reg01 vsel d7 bit is i 2 c-controlled enabled. when writing d7 = 0, the converter is off. when writing d7 = 1, the converter is on. both the external en and i 2 c en can control the converter. the converter works only when both en pins are high. output voltage select the mp8848 output voltage is i 2 c- programmable. there is no need to set feedback resistors to achieve different output voltages. the default output voltage is 0.94v but can be set from 0.6v to 1.235v in 5mv steps via the i 2 c. to change the output voltage, write the go bit (reg03 syscntlreg2 [d5]) to 1. this action means that the output voltage can be set to another value that is not the default vo voltage. then write the output reference bit (reg01 vsel [d6:d0]). the output voltage can be changed according to table 1. to guarantee a normal output voltage, the input voltage is suggested to be 1.5v higher than the pre-set output voltage. switching frequency the default switching frequency of the mp8848 is 1.25mhz. however, the frequency can also be changed based on the application. by writing the switching frequency bits (reg02 syscntlreg1 [d7:d5], the switching frequency can be programmed to one of six possible values. their corresponding data can be found in reg02 syscntlr eg1. figure 2: mp884x family control interface
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 18 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. pg configuration the mp8848 has an option to use the pg_lohi function. this function can be written in the pg_lohi bit (reg02 syscntlreg1 [d2]). the default value is 1, where pg senses both a positive and negative excursion of vo from the reference. if writing this bit to 0, pg only senses a negative voltage excursion of vo from the reference. input over-voltage protection (ovp) the mp8848 has an option to use the vin_ovp function. this function can be written in the vin_ovp bit (reg02 syscntlreg1 [d1]). the default value is 0, where the vin_ovp function is enabled. when vin is higher than 6.3v, the converter is disabled. after vin recovers to 6.2v, the converter restarts. if the vin_ovp bit is set to 1, vin ovp is disabled. the converter will not stop, even if vin exceeds its safe range. forced continuous conduction mode (ccm) the mp8848 has auto-pulse-frequency modulation (pfm) mode and forced continuous conduction mode (ccm). this function can be written in the mode bit (reg02 syscntlreg1 [d0]). the default value is 0, where auto-pfm mode is selected. considering a smaller vo ripple and regulation for a full load range, forced ccm is recommended. set this bit to 1 to disable pfm mode. output discharge the mp8848 has an output discharge function. writing the out-dis bit (reg03 syscntlreg2 [d4]) can change the output discharge mode. the default value is 1. discharge the internal vo resistance when en is low. writing d4 = 1 can enable the function, and then the output voltage can be discharged by the internal pull-down resistance. output voltage transition slew rate when the output voltage switches from low to high or from high to low, the transition slew rate can differ. there are two possible values for selection. through writing the slew rate bits (reg03 syscntlreg2 d2), the transition slew rate can be set at one possible value based on the application. the internal reference follows the set slew rate, but the output voltage slew rate does not always follow the internal reference. considering the output capacitor and inductor, the actual output voltage slew rate should be a little slower. avin multi-use the mp8848?s avin pin has multi-usage. when the p3 enable bit (reg03 syscntlreg2 d1) is 0, avin is an internal analog supply. when the p3 control bit (reg03 syscntlrge2 d1) is 1, the p3 voltage is controlled by the p3 set bit (reg03 syscntlrge2 d0). the p3 voltage is high if d0 = 0; otherwise, the p3 voltage is low (see table 3). table 3: avin multi-use d1 d0 avin 0 0 internal analog supply 0 1 1 0 forced to 1 1 1 forced to 0 i 2 c register hold on the mp8848 has a special function: the i 2 c register can hold on after en changes low. the updated register can be held for later application conditions, even if the external en pulls low.
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c mp8848 rev. 1.0 www.monolithicpower.com 19 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. typical application circuits figure 3: application circuit
mp8848 ? 6a, highly efficient, sync, step-down switcher with i 2 c notice: the information in this document is subject to change wi thout notice. please contact m ps for current specifications. users should warrant and guarantee that third party intellectual property rights ar e not infringed upon when integrating mps products into any application. mps will not assume any legal responsibility for any said applications. mp8848 rev. 1.0 www.monolithicpower.com 20 2/16/2017 mps proprietary information. patent protec ted. unauthorized photocopy and duplication prohibited. ? 2017 mps. all rights reserved. package information qfn-15 (2mmx3mm)

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