IRDC3073EVAL 1 rev. 1.0 06/30/03 www.irf.com specification data introduction iru3073 evaluation board user guide input/output connections the iru3073 controller ic is designed to provide a low cost synchronous buck regulator for on-board dc to dc converter for multiple output applications. the outputs can be programmed as low as 0.8v for low voltage applications. selectable over-current protection is provided by using external mosfet's on-resistance for optimum cost and performance. this device features a programmable frequency set from 200khz to 400khz, under-voltage lockout for all input supplies, an external programmable soft-start function as well as output under-voltage detection that latches off the device when an output short is detected. switcher: v in = 5v v out1 = 2.5v i out1 = 8a d v out = 50mv f s = 200khz the following is the input/output connections: inputs: jp3: input (+5v), gnd jp1: input (+12v) outputs: jp4: v out1 (+2.5v), gnd jp2: v out2 (+1.6v), gnd the connection points is shown in figure 1. connect the power supply cables according to this figure, minimize wire lengths to reduce losses in the wire. test point j1 provides easy connections for the oscilloscope voltage probe to monitor the output voltage. supply voltage: v cc = v c = 12v note: for proper operation, +5v supply should ramp up first. linear regulator: v in = 2.5v (from switch) v out2 = 1.6v i out2 = 2a
2 rev. 1.0 06/30/03 IRDC3073EVAL www.irf.com figure 1 - connection diagram of evaluation-board for iru3073. connection diagram power supply gnd +5v 10a supply power supply gnd +12v 1a supply load2 2a load1 0 - 10a
IRDC3073EVAL 3 rev. 1.0 06/30/03 www.irf.com the four layers for iru3073 evaluation board are shown in figures 2.1-2.4. the layout is designed both for direct fet package and soic package for power mosfets. the input capacitors are all located close to the mosfets. all the decoupling capacitors and feedback components are located close to ic. the feedback re- sistors are tied to the output voltage at the point of regu- lation. the middle layers are dedicated to power ground and analog ground. analog ground is kept separated from the power ground and it is connected at a single point as shown in figure 2.3. layout figure 2.1 - top layer of evaluation-board for iru3073.
4 rev. 1.0 06/30/03 IRDC3073EVAL www.irf.com figure 2.2 - middle layer 1. figure 2.3 - middle layer 2. figure 2.4 - bottom layer. layout
IRDC3073EVAL 5 rev. 1.0 06/30/03 www.irf.com figure 3 - schematic of evaluation-board for iru3073. schematic
6 rev. 1.0 06/30/03 IRDC3073EVAL www.irf.com bill of material ref desig description value qty part# manuf web site (www.) 2 1 1 1 1 1 4 1 2 1 1 2 7 2 1 3 7 1 1 1 1 1 7 5 2 5 2 4 q1,q2 q3 u1 d2 l1 l2 c1,c2a,b,c c2 c6,c10 c7 c8 c9b,c c11,12,15, 16,19,20,21 c13,c14 r1 r2,10,14 r3,5,11,16, 20,22,23 r4 r6 r7 r8 r9 r12,13,15, 17,18,19,21 c3,4,5,9,17 d1,d3 jp1,2,3,4,5 j1,j2 circuit board spacer mosfet mosfet controller schottky diode inductor inductor cap, poscap cap, ceramic cap, ceramic cap, ceramic cap, ceramic cap, poscap cap, ceramic cap, poscap resistor resistor resistor resistor resistor resistor resistor resistor resistor capacitor diode connector scope probe spacer irf7832 irlr2703 iru3073cq bat54 do3316p-102 do5022p-332hc 16tpb47m ecu-v1h330jcv ecj-2vf1e104 ecu-v1h222kbv ecj-2vc1h471j 6tpb330m ecj-2vf1c1o5z 6tpb150m ed1973-nd 131-5031-00 sj-67a3 black ir ir ir ir coilcraft coilcraft sanyo panasonic panasonic panasonic panasonic sanyo panasonic sanyo any any any any any any any any any digikey tetronix 3m irf.com coilcraft.com sanyo.com maco.panasonic.co.jp sanyo.com maco.panasonic.co.jp sanyo.com 1 m h, 5.6a 3.3 m h, 17a 47 m f, 16v 33pf, npo, 5% 0.1 m f, y5v, 25v 2200pf, x7r, 50v 470pf, x7r, 50v 330 m f, 40m v 1 m f, y5v, 16v 150 m f, 6.3v 10 v 1k, 1% 0 v 5.1k, 1% 100k 24k, 1% 4.7 v , 1% 2.15k, 1% na (open) na (open) na (open) 2-pos terminal bumpon
IRDC3073EVAL 7 rev. 1.0 06/30/03 www.irf.com typical operating characteristics figure 1 - normal condition at no load. ch1: hdrv ch2: ldrv ch4: inductor current figure 2 - gate signals when ss pin pulls low. ch1: hdrv ch2: ldrv figure 3 - gate signals when ss pin pulls low. ch1: hdrv ch2: ldrv figure 4 - soft-start. ch1: v in (5v) ch2: bias voltage (12v) ch3: v out ch4: i out
8 rev. 1.0 06/30/03 IRDC3073EVAL www.irf.com ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information data and specifications subject to change without notice. 02/01 typical operating characteristics figure 8 - load transient response (pwm section). figure 7 - output shorted at start-up. ch1: v out ch2: i out figure 6 - output shorted at start-up. ch1: v out ch2: i out figure 10 - load transient response (pwm section).
|
