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| kinetis k24 sub-family data sheet with 1 mb flash 120 mhz arm? cortex?-m4-based microcontroller with fpu the k24 product family members are optimized for cost-sensitive applications requiring low-power, usb connectivity, processing efficiency with floating point unit, optimized integration and high embedded memory densities. these devices share the comprehensive enablement and scalability of the kinetis family. this product offers: ? up to 1 mb flash, with 256 kb of embedded sram ? run power consumption down to 250 a/mhz. static power consumption down to 5.8 a with full state retention and 5 s wakeup. lowest static mode down to 339 na ? usb ls/fs otg 2.0 with embedded 3.3 v, 120 ma ldo voltage regulator with usb device crystal-less operation performance ? up to 120 mhz arm? cortex?-m4 core with dsp instructions and floating point unit delivering 1.25 dhrystone mips per mhz memories and memory interfaces ? up to 1 mb program flash memory and 256 kb ram ? flexbus external bus interface system peripherals ? multiple low-power modes, low-leakage wakeup unit ? memory protection unit with multi-master protection ? 16-channel dma controller ? external watchdog monitor and software watchdog clocks ? 3 to 32 mhz and 32 khz crystal oscillator ? multi-purpose clock generator ? 1 khz, 32 khz, and 4 mhz internal reference clock ? 48 mhz internal reference security and integrity modules ? hardware crc module ? hardware random-number generator ? hardware encryption supporting des, 3des, aes, md5, sha-1, and sha-256 algorithms ? 128-bit unique identification (id) number per chip communication interfaces ? usb full-/low-speed on-the-go controller ? controller area network (can) module ? three spi modules ? three i2c modules ? six uart modules ? secure digital host controller (sdhc) ? i2s module timers ? programmable delay block ? two 8-channel flextimers (pwm/motor control) ? two 2-channel flextimer (quad decoder/pwm) ? pit and 16-bit low-power timer ? carrier modulator transmitter ? real-time clock analog modules ? two 16-bit sar adcs ? two 12-bit dacs ? three analog comparators (cmp) ? voltage reference operating characteristics ? voltage range: 1.71 to 3.6 v ? flash write voltage range: 1.71 to 3.6 v ? temperature range (ambient): C40 to 85c MK24FN1M0CAJ12R 142 wlcsp 4.84 x 5.58 x 0.60 mm pitch 0.4 mm nxp semiconductors k24p142m120sf5 data sheet: technical data rev. 7, 10/2016 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
ordering information 1 part number memory maximum number of i\o?s flash sram (kb) MK24FN1M0CAJ12R 1 mb 256 100 1. to confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. related resources type description resource selector guide the nxp solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. k60pb 1 reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. k24p144m120sf5rm 1 data sheet the data sheet includes electrical characteristics and signal connections. this document package drawing package dimensions are provided in package drawings. wlcsp 142-pin: 98asa00639d 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. 2 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 nxp semiconductors memories and memory interfaces program flash ram 12-bit dac 6-bit dac x3 crc analog timers communication interfaces security and integrity spi x3 clocks frequency- core debug interfaces dsp interrupt controller comparator x3 analog voltage reference low power timer human-machine interface (hmi) gpio system dma internal watchdogs and external low-leakage wakeup locked loop phase- locked loop reference internal clocks programmable delay block timers interrupt periodic real-time independent clock oscillators low/high frequency uart x6 ? cortex?-m4 arm flexbus floating point memory protection sdhc x1 can x1 serial programming interface kinetis k24 family usb charger detect usb voltage regulator usb otg ls/fs usb ls/fs transceiver x1 i s 2 hardware encryption number random generator x2 x3 i c 2 timers x2 (8ch) x2 (2ch) 16-bit adc x2 figure 1. k24 block diagram kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 5 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 6 2.2.1 voltage and current operating requirements..... 6 2.2.2 lvd and por operating requirements............. 8 2.2.3 voltage and current operating behaviors.......... 8 2.2.4 power mode transition operating behaviors...... 10 2.2.5 power consumption operating behaviors.......... 11 2.2.6 emc radiated emissions operating behaviors... 16 2.2.7 designing with radiated emissions in mind....... 17 2.2.8 capacitance attributes...................................... 17 2.3 switching specifications................................................... 17 2.3.1 device clock specifications............................... 17 2.3.2 general switching specifications....................... 18 2.4 thermal specifications..................................................... 19 2.4.1 thermal operating requirements....................... 19 2.4.2 thermal attributes............................................. 20 3 peripheral operating requirements and behaviors.................. 20 3.1 core modules.................................................................. 20 3.1.1 debug trace timing specifications..................... 21 3.1.2 jtag electricals................................................ 21 3.2 system modules.............................................................. 24 3.3 clock modules................................................................. 24 3.3.1 mcg specifications........................................... 24 3.3.2 irc48m specifications...................................... 27 3.3.3 oscillator electrical specifications..................... 27 3.3.4 32 khz oscillator electrical characteristics......... 30 3.4 memories and memory interfaces................................... 30 3.4.1 flash (ftfe) electrical specifications............... 30 3.4.2 ezport switching specifications......................... 32 3.4.3 flexbus switching specifications....................... 33 3.5 security and integrity modules........................................ 36 3.6 analog............................................................................. 36 3.6.1 adc electrical specifications............................. 37 3.6.2 cmp and 6-bit dac electrical specifications..... 41 3.6.3 12-bit dac electrical characteristics................. 43 3.6.4 voltage reference electrical specifications........ 46 3.7 timers.............................................................................. 47 3.8 communication interfaces............................................... 47 3.8.1 usb electrical specifications............................. 48 3.8.2 usb dcd electrical specifications.................... 48 3.8.3 usb vreg electrical specifications.................. 48 3.8.4 can switching specifications............................ 49 3.8.5 dspi switching specifications (limited voltage range)................................................................ 49 3.8.6 dspi switching specifications (full voltage range)................................................................ 51 3.8.7 inter-integrated circuit interface (i2c) timing.... 53 3.8.8 uart switching specifications.......................... 54 3.8.9 sdhc specifications......................................... 54 3.8.10 i2s switching specifications.............................. 55 4 dimensions............................................................................. 61 4.1 obtaining package dimensions....................................... 61 5 pinout...................................................................................... 62 5.1 k24 signal multiplexing and pin assignments................. 62 5.2 unused analog interfaces................................................ 67 5.3 k24 pinouts..................................................................... 68 6 ordering parts......................................................................... 69 6.1 determining valid orderable parts.................................... 69 7 part identification..................................................................... 70 7.1 description....................................................................... 70 7.2 format............................................................................. 70 7.3 fields............................................................................... 70 7.4 example........................................................................... 71 8 terminology and guidelines.................................................... 71 8.1 definitions........................................................................ 71 8.2 examples......................................................................... 72 8.3 typical-value conditions.................................................. 72 8.4 relationship between ratings and operating requirements.................................................................... 72 8.5 guidelines for ratings and operating requirements.......... 73 9 revision history...................................................................... 73 4 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 nxp semiconductors 1 ratings 1.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature ?55 150 ?c 1 t sdr solder temperature, lead-free ? 260 ?c 2 solder temperature, leaded ? 245 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 1 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1. esd handling ratings symbol description min. max. unit notes hbm electrostatic discharge voltage, human body model -2000 2000 1 cdm electrostatic discharge voltage, charged-device model -500 500 2 i lat latch-up current at ambient temperature of 105c -100 100 ma 1. determined according to jedec standard jesd22-a11, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . . determined according to jedec standard jesd, ic latch-up test . 1. oltage and current operating ratings ratings inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 5 np semiconductors symbol description min. max. unit v dd digital supply voltage ?0.3 3.8 v i dd digital supply current ? 185 ma v dio digital input voltage (except reset, extal, and xtal) ?0.3 5.5 v v drtc_wakeu p rtc wakeup input voltage ?0.3 v bat + 0.3 v v aio analog 1 , reset, extal, and xtal input voltage ?0.3 v dd + 0.3 v i d maximum current single pin limit (applies to all digital pins) ?25 25 ma v dda analog supply voltage v dd ? 0.3 v dd + 0.3 v v usb0_dp usb0_dp input voltage ?0.3 3.63 v v usb0_dm usb0_dm input voltage ?0.3 3.63 v v regin usb regulator input ?0.3 6.0 v v bat rtc battery supply voltage ?0.3 3.8 v 1. analog pins are defined as pins that do not have an associated general purpose i/o port function. 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 2.2.1 voltage and current operating requirements table 1. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd ? v dda v dd -to-v dda differential voltage ?0.1 0.1 v v ss ? v ssa v ss -to-v ssa differential voltage ?0.1 0.1 v v bat rtc battery supply voltage 1.71 3.6 v v ih input high voltage ? 2.7 v ? v dd ? 3.6 v ? 1.7 v ? v dd ? 2.7 v 0.7 ? v dd 0.75 ? v dd ? ? v v v il input low voltage ? 2.7 v ? v dd ? 3.6 v ? 1.7 v ? v dd ? 2.7 v ? ? 0.35 ? v dd 0.3 ? v dd v v v hys input hysteresis 0.06 ? v dd ? v i icdio digital pin negative dc injection current ? single pin ? v in < v ss -0.3v -5 ? ma 1 i icaio analog 2 , extal, and xtal pin dc injection current ? single pin ? v in < v ss -0.3v (negative current injection) ? v in > v dd +0.3v (positive current injection) -5 ? ? +5 ma 3 i iccont contiguous pin dc injection current ?regional limit, includes sum of negative injection currents or sum of positive injection currents of 16 contiguous pins ? negative current injection ? positive current injection -25 ? ? +25 ma v odpu open drain pullup voltage level v dd v dd v 4 v ram v dd voltage required to retain ram 1.2 ? v v rfvbat v bat voltage required to retain the vbat register file v por_vbat ? v 1. all 5 v tolerant digital i/o pins are internally clamped to v ss through an esd protection diode. there is no diode connection to v dd . if v in is less than v dio_min , a current limiting resistor is required. if v in greater than v dio_min (=vss-0.3v) is observed, then there is no need to provide current limiting resistors at the pads. the negative dc injection current limiting resistor is calculated as r=(v dio_min -v in )/|i icdio |. 2. analog pins are defined as pins that do not have an associated general purpose i/o port function. additionally, extal and xtal are analog pins. 3. all analog pins are internally clamped to v ss and v dd through esd protection diodes. if v in is less than v aio_min or greater than v aio_max , a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r=(v aio_min -v in )/|i icaio |. the positive injection current limiting resistor is calculated as r=(v in - v aio_max )/|i icaio |. select the larger of these two calculated resistances if the pin is exposed to positive and negative injection currents. 4. open drain outputs must be pulled to vdd. general kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 7 nxp semiconductors 2.2.2 lvd and por operating requirements table 2. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling vdd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold ? high range (lvdv=01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds ? high range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis ? high range ? 80 ? mv v lvdl falling low-voltage detect threshold ? low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds ? low range ? level 1 falling (lvwv=00) ? level 2 falling (lvwv=01) ? level 3 falling (lvwv=10) ? level 4 falling (lvwv=11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis ? low range ? 60 ? mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period ? factory trimmed 900 1000 1100 ?s 1. rising threshold is the sum of falling threshold and hysteresis voltage table 3. vbat power operating requirements symbol description min. typ. max. unit notes v por_vbat falling vbat supply por detect voltage 0.8 1.1 1.5 v 2.2.3 voltage and current operating behaviors table 4. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage ? high drive strength table continues on the next page... general inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes ? 2.7 v ? v dd ? 3.6 v, i oh = -8ma ? 1.71 v ? v dd ? 2.7 v, i oh = -3ma v dd ? 0.5 v dd ? 0.5 ? ? v v output high voltage ? low drive strength ? 2.7 v ? v dd ? 3.6 v, i oh = -2ma ? 1.71 v ? v dd ? 2.7 v, i oh = -0.6ma v dd ? 0.5 v dd ? 0.5 ? ? v v i oht output high current total for all ports ? 100 ma v oh_rtc_wa keup output high voltage ? high drive strength ? 2.7 v ? v bat ? 3.6 v, i oh = -10ma ? 1.71 v ? v bat ? 2.7 v, i oh = -3ma v bat ? 0.5 v bat ? 0.5 ? ? v v output high voltage ? low drive strength ? 2.7 v ? v bat ? 3.6 v, i oh = -2ma ? 1.71 v ? v bat ? 2.7 v, i oh = -0.6ma v bat ? 0.5 v bat ? 0.5 ? ? v v i oh_rtc_wak eup output high current total for rtc_wakeup pins ? 100 ma v ol output low voltage ? high drive strength ? 2.7 v ? v dd ? 3.6 v, i ol = 9ma ? 1.71 v ? v dd ? 2.7 v, i ol = 3ma ? ? 0.5 0.5 v v output low voltage ? low drive strength ? 2.7 v ? v dd ? 3.6 v, i ol = 2ma ? 1.71 v ? v dd ? 2.7 v, i ol = 0.6ma ? ? 0.5 0.5 v v i olt output low current total for all ports ? 100 ma v ol_rtc_wa keup output low voltage ? high drive strength ? 2.7 v ? v bat ? 3.6 v, i ol = 10ma ? 1.71 v ? v bat ? 2.7 v, i ol = 3ma ? ? 0.5 0.5 v v output low voltage ? low drive strength ? 2.7 v ? v bat ? 3.6 v, i ol = 2ma ? 1.71 v ? v bat ? 2.7 v, i ol = 0.6ma ? ? 0.5 0.5 v v i ol_rtc_wak eup output low current total for rtc_wakeup pins ? 100 ma i in input leakage current (per pin) for full temperature range ? 1 ?a 1 i in input leakage current (per pin) at 25?c ? 0.025 ?a 1 i in_rtc_wak eup input leakage current (per rtc_wakeup pin) for full temperature range ? 1 ?a i in_rtc_wak eup input leakage current (per rtc_wakeup pin) at 25?c ? 0.025 ?a table continues on the next page... general inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 4. voltage and current operating behaviors (continued) symbol description min. max. unit notes i oz hi-z (off-state) leakage current (per pin) ? 0.25 ?a i oz_rtc_wak eup hi-z (off-state) leakage current (per rtc_wakeup pin) ? 0.25 ?a r pu internal pullup resistors (except rtc_wakeup pins) 20 50 k? 2 r pd internal pulldown resistors (except rtc_wakeup pins) 20 50 k? 3 1. measured at vdd=3.6v 2. measured at v dd supply voltage = v dd min and vinput = v ss 3. measured at v dd supply voltage = v dd min and vinput = v dd 2.2.4 power mode transition operating behaviors all specifications except t por , and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 100 mhz ? bus clock = 50 mhz ? flexbus clock = 50 mhz ? flash clock = 25 mhz table 5. power mode transition operating behaviors symbol description min. max. unit notes t por after a por event, amount of time from the point v dd reaches 1.71 v to execution of the first instruction across the operating temperature range of the chip. 300 s ? vlls0 2.2.5 power consumption operating behaviors note the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). table 6. power consumption operating behaviors symbol description min. typ. max. unit notes i dda analog supply current see note ma 1 i dd_run run mode current all peripheral clocks disabled, code executing from flash ? 1.8v ? 3.0v 31.1 31 35.3 35.3 ma ma 2 i dd_run run mode current all peripheral clocks enabled, code executing from flash ? 1.8v ? 3.0v ? 25c ? 85c 42.7 40 41.6 46.95 41.6 44.1 ma ma ma 3 , 4 i dd_wait wait mode high frequency current at 3.0 v all peripheral clocks disabled 17.9 ma 2 i dd_wait wait mode reduced frequency current at 3.0 v all peripheral clocks disabled 6.9 ma 5 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks disabled 1 ma 6 i dd_vlpr very-low-power run mode current at 3.0 v all peripheral clocks enabled 1.7 ma 7 i dd_vlpw very-low-power wait mode current at 3.0 v all peripheral clocks disabled 0.678 ma 8 i dd_stop stop mode current at 3.0 v ? '40 to 25c ? 70c ? 85c 0.49 1.18 1.76 1.24 4.3 7.7 ma ma ma i dd_vlps very-low-power stop mode current at 3.0 v ? '40 to 25c ? 70c ? 85c 57 291 494.5 139.31 679.33 850.6 a a a i dd_lls low leakage stop mode current at 3.0 v 9 table continues on the next page... general inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 11 np semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 5.8 26.7 50.2 10.48 47.99 88.55 ?a ?a ?a i dd_vlls3 very low-leakage stop mode 3 current at 3.0 v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 4.4 21 39.5 5.54 36.46 67.45 ?a ?a ?a i dd_vlls2 very low-leakage stop mode 2 current at 3.0 v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 2.1 6.84 12.6 2.34 10.36 19.0 ?a ?a ?a i dd_vlls1 very low-leakage stop mode 1 current at 3.0 v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 0.817 3.97 8.23 0.86 5.77 12.47 ?a ?a ?a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit enabled ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 0.520 3.67 7.94 0.62 5.7 11.7 ?a ?a ?a i dd_vlls0 very low-leakage stop mode 0 current at 3.0 v with por detect circuit disabled ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? 0.339 3.36 7.55 0.412 4.2 9.96 ?a ?a ?a i dd_vbat average current with rtc and 32khz disabled ? @ 1.8v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? @ 3.0v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? ? 0.16 0.55 1.28 0.18 0.66 1.52 0.19 0.72 1.88 0.21 0.86 2.24 ?a ?a ?a ?a ?a ?a table continues on the next page... general 12 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 6. power consumption operating behaviors (continued) symbol description min. typ. max. unit notes i dd_vbat average current when cpu is not accessing rtc registers ? @ 1.8v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? @ 3.0v ? @ ?40 to 25?c ? @ 70?c ? @ 85?c ? ? ? ? ? ? 0.59 1.0 1.76 0.71 1.22 2.08 0.70 1.30 2.59 0.84 1.59 3.06 ?a ?a ?a ?a ?a ?a 10 1. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module?s specification for its supply current. 2. 120 mhz core and system clock, 60 mhz bus, 40 mhz flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. all peripheral clocks disabled. 3. 120 mhz core and system clock, 60 mhz bus clock, 40 mhz flexbus clock, and 25 mhz flash clock. mcg configured for pee mode. all peripheral clocks enabled. 4. max values are measured with cpu executing dsp instructions. 5. 25 mhz core and system clock, 25 mhz bus clock, and 12.5 mhz flexbus and flash clock. mcg configured for fei mode. 6. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. code executing from flash. 7. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks enabled but peripherals are not in active operation. code executing from flash. 8. 4 mhz core, system, flexbus, and bus clock and 1 mhz flash clock. mcg configured for blpe mode. all peripheral clocks disabled. 9. data reflects devices with 256 kb of ram. 10. includes 32khz oscillator current and rtc operation. table 7. low power mode peripheral adders ? typical value symbol description temperature (?c) unit -40 25 50 70 85 i irefsten4mhz 4 mhz internal reference clock (irc) adder. measured by entering stop or vlps mode with 4 mhz irc enabled. 56 56 56 56 56 ?a i irefsten32khz 32 khz internal reference clock (irc) adder. measured by entering stop mode with the 32 khz irc enabled. 52 52 52 52 52 ?a i erefsten4mhz external 4 mhz crystal clock adder. measured by entering stop or vlps mode with the crystal enabled. 206 228 237 245 251 ua i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. table continues on the next page... general inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 1 np semiconductors table 7. low power mode peripheral adders ? typical value (continued) symbol description temperature (?c) unit -40 25 50 70 85 vlls1 vlls3 lls vlps stop 440 440 440 510 510 490 490 490 560 560 540 540 540 560 560 560 560 560 560 560 570 570 570 610 610 na i 48mirc 48 mhz internal reference clock 350 350 350 350 350 ?a i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 22 22 22 22 22 ?a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 432 357 388 475 532 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. mcgirclk (4 mhz internal reference clock) oscerclk (4 mhz external crystal) 66 214 66 237 66 246 66 254 66 260 ?a i bg bandgap adder when bgen bit is set and device is placed in vlpx, lls, or vllsx mode. 45 45 45 45 45 ?a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 42 42 42 42 42 ?a 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? no gpios toggled general 14 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors ? code execution from flash with cache enabled ? for the alloff curve, all peripheral clocks are disabled except ftfe temp (c)=25, v dd =3.6v, cache=enable, code residence=flash run mode current consumption vs core frequency all peripheral clk gates alloff allon clk ratio core-bus- flaxbus-flash core freq (mhz) current consumption on v dd (a) 40.00e-03 000.00e+00 10.00e-03 15.00e-03 20.00e-03 25.00e-03 30.00e-03 35.00e-03 5.00e-03 '1-1-1 1 '1-1-1 2 '1-1-1 4 '1-1-1 6.25 '1-1-1 12.5 '1-1-1 25 '1-2-3 75 '1-1-2 50 '1-2-4 100 '1-2-5 120 current consumption on v dd (a) all peripheral clk gates alloff allon clk ratio core-bus-flash core freq (mhz) very low power run (vlpr) current vs core frequency 1.40e-03 '1-1-1'1-1-2 1 '1-1-2'1-1-4'1-2-4 2 '1-1-4'1-2-4 4 000.00e+00 200.00e-06 400.00e-06 600.00e-06 800.00e-06 1.00e-03 1.20e-03 temp (c)=25, v dd =3.6v, cache=enable, code residence=flash integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 1: general conditions and definitions and iec standard 1-2, integrated circuits - measurement of electromagnetic emissions, 150 khz to 1 ghz part 2: measurement of radiated emissionstem cell and general 1 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors wideband tem cell method . measurements were made while the microcontroller was running basic application code. the reported emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the measured orientations in each frequency range. 2. dd . , t a 25 c, f osc 12 mhz (crystal), f ss mhz, f bus mhz . specified according to annex d of iec standard 1-2, measurement of radiated emissionstem cell and wideband tem cell method 2.2. designing with radiated emissions in mind to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.nxp.com . 2. perform a keyword search for emc design. 2.2.8 capacitance attributes table 9. capacitance attributes symbol description min. max. unit c in_a input capacitance: analog pins 7 pf c in_d input capacitance: digital pins 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 10. device clock specifications symbol description min. max. unit notes normal run mode f sys system and core clock 120 mhz system and core clock when full speed usb in operation 20 mhz f bus bus clock 60 mhz fb_clk flexbus clock 50 mhz f flash flash clock 25 mhz f lptmr lptmr clock 25 mhz vlpr mode 1 f sys system and core clock 4 mhz table continues on the next page... general inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 1 np semiconductors table 10. device clock specifications (continued) symbol description min. max. unit notes f bus bus clock ? 4 mhz fb_clk flexbus clock ? 4 mhz f flash flash clock ? 0.8 mhz f erclk external reference clock ? 16 mhz f lptmr_pin lptmr clock ? 25 mhz f lptmr_erclk lptmr external reference clock ? 16 mhz f flexcan_erclk flexcan external reference clock ? 8 mhz f i2s_mclk i2s master clock ? 12.5 mhz f i2s_bclk i2s bit clock ? 4 mhz 1. the frequency limitations in vlpr mode here override any frequency specification listed in the timing specification for any other module. 2.3.2 general switching specifications these general purpose specifications apply to all signals configured for gpio, uart, can, cmt, timers, and i 2 c signals. table 11. general switching specifications symbol description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 , 2 gpio pin interrupt pulse width (digital glitch filter disabled, analog filter enabled) asynchronous path 100 ns gpio pin interrupt pulse width (digital glitch filter disabled, analog filter disabled) asynchronous path 50 ns 3 external reset pulse width (digital glitch filter disabled) 100 ns 3 mode select ( ep_cs) hold time after reset deassertion 2 bus clock cycles port rise and fall time (high drive strength) - 3 v ? slew disabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v ? slew enabled ? 1.71 v dd 2.7v ? 2.7 v dd 3.6v 8 6 18 12 ns ns ns ns port rise and fall time (high drive strength) - 5 v ? slew disabled 4 table continues on the next page... general 1 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 11. general switching specifications (continued) symbol description min. max. unit notes ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? slew enabled ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? ? ? ? 6 4 24 14 ns ns ns ns port rise and fall time (low drive strength) - 3 v ? slew disabled ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? slew enabled ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? ? ? ? 12 6 24 16 ns ns ns ns port rise and fall time (low drive strength) - 5 v ? slew disabled ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? slew enabled ? 1.71 ? v dd ? 2.7v ? 2.7 ? v dd ? 3.6v ? ? ? ? 17 10 23 20 ns ns ns ns 5 1. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop, vlps, lls, and vllsx modes, the synchronizer is bypassed so shorter pulses can be recognized in that case. 2. the greater synchronous and asynchronous timing must be met. 3. this is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in stop, vlps, lls, and vllsx modes. 4. 25 pf load 5. 15 pf load 2.4 thermal specifications 2.4.1 thermal operating requirements table 12. thermal operating requirements symbol description min. max. unit t j die junction temperature ?40 95 ?c t a ambient temperature 1 ?40 85 ?c general kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 19 nxp semiconductors 1. maximum t a can be exceeded only if the user ensures that t j does not exceed maximum t j . the simplest method to determine t j is: t j = t a + r integrated circuits thermal test method environmental conditionsnatural convection (still air) with the single layer board horizontal. board meets jesd51- specification. . determined according to jedec standard jesd51-, integrated circuits thermal test method environmental conditionsforced convection (moving air) with the board horizontal. . determined according to jedec standard jesd51-, integrated circuit thermal test method environmental conditionsjunction-to-board . 5. determined according to method 1012.1 of mil-std , test method standard, microcircuits , with the cold plate temperature used for the case temperature. the value includes the thermal resistance of the interface material between the top of the package and the cold plate. . determined according to jedec standard jesd51-2, integrated circuits thermal test method environmental conditionsnatural convection (still air) . peripheral operating requirements and behaviors peripheral operating requirements and behaviors 20 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors 3.1 core modules 3.1.1 debug trace timing specifications table 14. debug trace operating behaviors symbol description min. max. unit t cyc clock period frequency dependent mhz t wl low pulse width 2 ? ns t wh high pulse width 2 ? ns t r clock and data rise time ? 3 ns t f clock and data fall time ? 3 ns t s data setup 1.5 ? ns t h data hold 1 ? ns traceclk t r t wh t f t cyc t wl figure 5. trace_clkout specifications th ts ts th trace_clkout trace_d[3:0] figure 6. trace data specifications 3.1.2 jtag electricals table 15. jtag limited voltage range electricals symbol description min. max. unit operating voltage 2.7 3.6 v j1 tclk frequency of operation mhz table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 21 np semiconductors table 15. jtag limited voltage range electricals (continued) symbol description min. max. unit ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 25 50 j2 tclk cycle period 1/j1 ? ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 20 10 ? ? ? ns ns ns j4 tclk rise and fall times ? 3 ns j5 boundary scan input data setup time to tclk rise 20 ? ns j6 boundary scan input data hold time after tclk rise 2.6 ? ns j7 tclk low to boundary scan output data valid ? 25 ns j8 tclk low to boundary scan output high-z ? 25 ns j9 tms, tdi input data setup time to tclk rise 8 ? ns j10 tms, tdi input data hold time after tclk rise 1 ? ns j11 tclk low to tdo data valid ? 17 ns j12 tclk low to tdo high-z ? 17 ns j13 trst assert time 100 ? ns j14 trst setup time (negation) to tclk high 8 ? ns table 16. jtag full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 tclk frequency of operation ? boundary scan ? jtag and cjtag ? serial wire debug 0 0 0 10 20 40 mhz j2 tclk cycle period 1/j1 ? ns j3 tclk clock pulse width ? boundary scan ? jtag and cjtag ? serial wire debug 50 25 12.5 ? ? ? ns ns ns j4 tclk rise and fall times ? 3 ns j5 boundary scan input data setup time to tclk rise 20 ? ns j6 boundary scan input data hold time after tclk rise 0 ? ns table continues on the next page... peripheral operating requirements and behaviors 22 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 16. jtag full voltage range electricals (continued) symbol description min. max. unit j7 tclk low to boundary scan output data valid ? 25 ns j8 tclk low to boundary scan output high-z ? 25 ns j9 tms, tdi input data setup time to tclk rise 8 ? ns j10 tms, tdi input data hold time after tclk rise 2.9 ? ns j11 tclk low to tdo data valid ? 22.1 ns j12 tclk low to tdo high-z ? 22.1 ns j13 trst assert time 100 ? ns j14 trst setup time (negation) to tclk high 8 ? ns j2 j3 j3 j4 j4 tclk (input) j7 j8 j7 j5 j6 input data valid output data valid output data valid tclk data inputs data outputs data outputs data outputs j11 j12 j11 j9 j10 input data valid output data valid output data valid tclk tdi/tms tdo tdo tdo there are no specifications necessary for the device's system modules. 3.3 clock modules peripheral operating requirements and behaviors 24 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 3.3.1 mcg specifications table 17. mcg specifications symbol description min. typ. max. unit notes f ints_ft internal reference frequency (slow clock) ? factory trimmed at nominal vdd and 25 ?c ? 32.768 ? khz f ints_t internal reference frequency (slow clock) ? user trimmed 31.25 ? 39.0625 khz i ints internal reference (slow clock) current ? 20 ? ?a table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 25 np semiconductors table 17. mcg specifications (continued) symbol description min. typ. max. unit notes 2197 ? f fll_ref high range (drs=11) 2929 ? f fll_ref ? 95.98 ? mhz j cyc_fll fll period jitter ? f dco = 48 mhz ? f dco = 98 mhz ? ? 180 150 ? ? ps t fll_acquire fll target frequency acquisition time ? ? 1 ms 7 pll f vco vco operating frequency 48.0 ? 120 mhz i pll pll operating current ? pll @ 96 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 48) ? 1060 ? ?a 8 i pll pll operating current ? pll @ 48 mhz (f osc_hi_1 = 8 mhz, f pll_ref = 2 mhz, vdiv multiplier = 24) ? 600 ? ?a 8 f pll_ref pll reference frequency range 2.0 ? 4.0 mhz j cyc_pll pll period jitter (rms) ? f vco = 48 mhz ? f vco = 120 mhz ? ? 120 80 ? ? ps ps 9 j acc_pll pll accumulated jitter over 1?s (rms) ? f vco = 48 mhz ? f vco = 120 mhz ? ? 1350 600 ? ? ps ps 9 d lock lock entry frequency tolerance ? 1.49 ? ? 2.98 % d unl lock exit frequency tolerance ? 4.47 ? ? 5.97 % t pll_lock lock detector detection time ? ? 150 ? 10 -6 + 1075(1/ f pll_ref ) s 10 1. this parameter is measured with the internal reference (slow clock) being used as a reference to the fll (fei clock mode). 2. 2 v <= vdd <= 3.6 v. 3. these typical values listed are with the slow internal reference clock (fei) using factory trim and dmx32=0. 4. the resulting system clock frequencies should not exceed their maximum specified values. the dco frequency deviation ( 3.3.2 irc48m specifications table 18. irc48m specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 ? 3.6 v i dd48m supply current ? 400 500 ?a f irc48m internal reference frequency ? 48 ? mhz 3.3.3.1 oscillator dc electrical specifications table 19. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 ? 3.6 v i ddosc supply current ? low-power mode (hgo=0) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz ? ? ? ? ? ? 500 200 300 950 1.2 1.5 ? ? ? ? ? ? na ?a ?a ?a ma ma 1 i ddosc supply current ? high-gain mode (hgo=1) ? 32 khz ? 4 mhz ? 8 mhz (range=01) ? 16 mhz ? 24 mhz ? 32 mhz ? ? ? ? ? ? 25 400 500 2.5 3 4 ? ? ? ? ? ? ?a ?a ?a ma ma ma 1 c x extal load capacitance ? ? ? 2 , 3 c y xtal load capacitance ? ? ? 2 , 3 r f feedback resistor ? low-frequency, low-power mode (hgo=0) ? ? ? m? 2 , 4 feedback resistor ? low-frequency, high-gain mode (hgo=1) ? 10 ? m? feedback resistor ? high-frequency, low-power mode (hgo=0) ? ? ? m? feedback resistor ? high-frequency, high-gain mode (hgo=1) ? 1 ? m? r s series resistor ? low-frequency, low-power mode (hgo=0) ? ? ? k? series resistor ? low-frequency, high-gain mode (hgo=1) ? 200 ? k? series resistor ? high-frequency, low-power mode (hgo=0) ? ? ? k? series resistor ? high-frequency, high-gain mode (hgo=1) ? 0 ? k? v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) ? low-frequency, low-power mode (hgo=0) ? 0.6 ? v table continues on the next page... peripheral operating requirements and behaviors 2 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 19. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes peak-to-peak amplitude of oscillation (oscillator mode) ? low-frequency, high-gain mode (hgo=1) ? v dd ? v peak-to-peak amplitude of oscillation (oscillator mode) ? high-frequency, low-power mode (hgo=0) ? 0.6 ? v peak-to-peak amplitude of oscillation (oscillator mode) ? high-frequency, high-gain mode (hgo=1) ? v dd ? v 1. v dd =3.3 v, temperature =25 ?c 2. see crystal or resonator manufacturer?s recommendation 3. c x and c y can be provided by using either integrated capacitors or external components. 4. when low-power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other device. 3.3.3.2 oscillator frequency specifications table 20. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency ? low- frequency mode (mcg_c2[range]=00) 32 ? 40 khz f osc_hi_1 oscillator crystal or resonator frequency ? high-frequency mode (low range) (mcg_c2[range]=01) 3 ? 8 mhz f osc_hi_2 oscillator crystal or resonator frequency ? high frequency mode (high range) (mcg_c2[range]=1x) 8 ? 32 mhz f ec_extal input clock frequency (external clock mode) ? ? 50 mhz 1 , 2 t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time ? 32 khz low-frequency, low-power mode (hgo=0) ? 750 ? ms 3 , 4 crystal startup time ? 32 khz low-frequency, high-gain mode (hgo=1) ? 250 ? ms crystal startup time ? 8 mhz high-frequency (mcg_c2[range]=01), low-power mode (hgo=0) ? 0.6 ? ms crystal startup time ? 8 mhz high-frequency (mcg_c2[range]=01), high-gain mode (hgo=1) ? 1 ? ms 1. other frequency limits may apply when external clock is being used as a reference for the fll 2. when transitioning from fei or fbi to fbe mode, restrict the frequency of the input clock so that, when it is divided by frdiv, it remains within the limits of the dco input clock frequency. 3. proper pc board layout procedures must be followed to achieve specifications. peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 29 nxp semiconductors 4. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. note the 32 khz oscillator works in low power mode by default and cannot be moved into high power/gain mode. 3.3.4 32 khz oscillator electrical characteristics 3.3.4.1 32 khz oscillator dc electrical specifications table 21. 32khz oscillator dc electrical specifications symbol description min. typ. max. unit v bat supply voltage 1.71 3.6 v r f internal feedback resistor 100 m c para parasitical capacitance of etal32 and tal32 5 7 pf v pp 1 peak-to-peak amplitude of oscillation 0.6 v 1. when a crystal is being used with the 32 khz oscillator, the etal32 and tal32 pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.4.2 32 khz oscillator frequency specifications table 22. 32 khz oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal 32.768 khz t start crystal start-up time 1000 ms 1 f ec_extal32 externally provided input clock frequency 32.768 khz 2 v ec_extal32 externally provided input clock amplitude 700 v bat mv 2 , 3 1. proper pc board layout procedures must be followed to achieve specifications. 2. this specification is for an externally supplied clock driven to etal32 and does not apply to any other clock input. the oscillator remains enabled and tal32 must be left unconnected. 3. the parameter specified is a peak-to-peak value and v ih and v il specifications do not apply. the voltage of the applied clock must be within the range of v ss to v bat . 3.4 memories and memory interfaces peripheral operating requirements and behaviors 30 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 3.4.1 flash (ftfe) electrical specifications this section describes the electrical characteristics of the ftfe module. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 23. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm8 program phrase high-voltage time 7.5 18 s t hversscr erase flash sector high-voltage time 13 113 ms 1 t hversblk512k erase flash block high-voltage time for 512 kb 416 3616 ms 1 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 24. flash command timing specifications symbol description min. typ. max. unit notes t rd1blk512k read 1s block execution time ? 512 kb program flash 1.8 ms t rd1sec4k read 1s section execution time (4 kb flash) 100 s 1 t pgmchk program check execution time 95 s 1 t rdrsrc read resource execution time 40 s 1 t pgm8 program phrase execution time 90 150 s t ersblk512k erase flash block execution time ? 512 kb program flash 435 3700 ms 2 t ersscr erase flash sector execution time 15 115 ms 2 t rd1alln read 1s all blocks execution time ? program flash only devices 3.4 ms t rdonce read once execution time 30 s 1 t pgmonce program once execution time 70 s t ersall erase all blocks execution time 870 7400 ms 2 t vfykey verify backdoor access key execution time 30 s 1 t swapx01 t swapx02 t swapx04 swap control execution time ? control code 0x01 ? control code 0x02 200 70 70 150 150 s s s peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 31 np semiconductors table 24. flash command timing specifications symbol description min. typ. max. unit notes t swapx08 ? control code 0x04 ? control code 0x08 ? ? 30 ?s 1. assumes 25mhz or greater flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 25. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation ? 3.5 7.5 ma i dd_ers average current adder during high voltage flash erase operation ? 1.5 4.0 ma 3.4.1.4 reliability specifications table 26. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 ? years t nvmretp1k data retention after up to 1 k cycles 20 100 ? years n nvmcycp cycling endurance 10 k 50 k ? cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25?c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40?c ? t j ? 125?c. 3.4.2 ezport switching specifications table 27. ezport switching specifications num description min. max. unit operating voltage 1.71 3.6 v ep1 ezp_ck frequency of operation (all commands except read) ? f sys /2 mhz ep1a ezp_ck frequency of operation (read command) ? f sys /8 mhz ep2 ezp_cs negation to next ezp_cs assertion 2 x t ezp_ck ? ns table continues on the next page... peripheral operating requirements and behaviors 2 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 27. ezport switching specifications (continued) num description min. max. unit ep3 ezp_cs input valid to ezp_ck high (setup) 5 ? ns ep4 ezp_ck high to ezp_cs input invalid (hold) 5 ? ns ep5 ezp_d input valid to ezp_ck high (setup) 2 ? ns ep6 ezp_ck high to ezp_d input invalid (hold) 5 ? ns ep7 ezp_ck low to ezp_q output valid ? 18 ns ep8 ezp_ck low to ezp_q output invalid (hold) 0 ? ns ep9 ezp_cs negation to ezp_q tri-state ? 12 ns ep2 ep3 ep4 ep5 ep6 ep7 ep8 ep9 ezp_ck ezp_cs ezp_q (output) ezp_d (input) all processor bus timings are synchronous; input setup/hold and output delay are given in respect to the rising edge of a reference clock, fb_clk. the fb_clk frequency may be the same as the internal system bus frequency or an integer divider of that frequency. peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 33 np semiconductors the following timing numbers indicate when data is latched or driven onto the external bus, relative to the flexbus output clock (fb_clk). all other timing relationships can be derived from these values. table 28. flexbus limited voltage range switching specifications num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation fb_clk mhz fb1 clock period 20 ns fb2 address, data, and control output valid 11.5 ns 1 fb3 address, data, and control output hold 0.5 ns 1 fb4 data and fb_ta input setup 8.5 ns 2 fb5 data and fb_ta input hold 0.5 ns 2 1. specification is valid for all fb_ad[31:0], fb_be/bwe n , fbcs n , fboe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. 2. specification is valid for all fbad1:0 and fbta. table 2. flexbus full voltage range switching specifications num description min. max. unit notes operating voltage 1.1 . frequency of operation fbcl mhz fb1 clock period 1/fbcl ns fb2 address, data, and control output valid 1.5 ns 1 fb address, data, and control output hold 0 ns 1 fb data and fbta input setup 15.5 ns 2 fb5 data and fbta input hold 0.5 ns 2 1. specification is valid for all fbad1:0, fbbe/bwe n , fbcs n , fboe, fbr/ w, fbtbst, fbtsi1:0, fbale, and fbts. 2. specification is valid for all fbad1:0 and fbta. peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors address address data tsiz aa=1 aa=0 aa=1 aa=0 fb3 fb5 fb4 fb4 fb5 fb1 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] fb2 address address data tsiz aa=1 aa=0 aa=1 aa=0 fb1 fb3 fb4 fb5 fb2 fb_clk fb_a[y] fb_d[x] fb_rw fb_ts fb_ale fb_csn fb_oen fb_ben fb_ta fb_tsiz[1:0] there are no specifications necessary for the device's security and integrity modules. 3.6 analog peripheral operating requirements and behaviors 36 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 3.6.1 adc electrical specifications the 16-bit accuracy specifications listed in table 30 and table 31 are achievable on the differential pins adcx_dp0, adcx_dm0. all other adc channels meet the 13-bit differential/12-bit single-ended accuracy specifications. 3.6.1.1 16-bit adc operating conditions table 30. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v table 30. 16-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes continuous conversions enabled, subsequent conversion time 1. typical values assume v dda = 3.0 v, temp = 25 ?c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. 3. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 ? analog source resistance. the r as /c as time constant should be kept to < 1 ns. 4. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 5. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 31. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/ f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes ? ? ?4 ?1.4 ?6.8 ?2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes ? ? ?0.7 ?0.2 ?1.1 to +1.9 ?0.3 to 0.5 lsb 4 5 inl integral non-linearity ? 12-bit modes ? <12-bit modes ? ? ?1.0 ?0.5 ?2.7 to +1.9 ?0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes ? ? ?4 ?1.4 ?5.4 ?1.8 lsb 4 v adin = v dda 5 e q quantization error ? 16-bit modes ? ?13-bit modes ? ? ?1 to 0 ? ? ?0.5 lsb 4 enob effective number of bits 16-bit differential mode ? avg = 32 ? avg = 4 16-bit single-ended mode ? avg = 32 ? avg = 4 12.8 11.9 12.2 11.4 14.5 13.8 13.9 13.1 ? ? ? ? bits bits bits bits 6 sinad signal-to-noise plus distortion see enob 6.02 ? enob + 1.76 db thd total harmonic distortion 16-bit differential mode ? avg = 32 16-bit single-ended mode ? avg = 32 ? ? -94 -85 ? ? db db 7 sfdr spurious free dynamic range 16-bit differential mode ? avg = 32 16-bit single-ended mode 82 78 95 90 ? ? db db 7 table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 31. 16-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 min. typ. 2 max. unit notes ? avg = 32 e il input leakage error i in ? r as mv i in = leakage current (refer to the mcu?s voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/?c 8 v temp25 temp sensor voltage 25 ?c 706 716 726 mv 8 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 ?c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. input data is 100 hz sine wave. adc conversion clock < 12 mhz. 7. input data is 1 khz sine wave. adc conversion clock < 12 mhz. 8. adc conversion clock < 3 mhz typical adc 16-bit differential enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 15.00 14.70 14.40 14.10 13.80 13.50 13.20 12.90 12.60 12.30 12.00 1 2 3 4 5 6 7 8 9 10 1211 hardware averaging disabled averaging of 4 samples averaging of 8 samples averaging of 32 samples typical adc 16-bit single-ended enob vs adc clock 100hz, 90% fs sine input enob adc clock frequency (mhz) 14.00 13.75 13.25 13.00 12.75 12.50 12.00 11.75 11.50 11.25 11.00 1 2 3 4 5 6 7 8 9 10 1211 averaging of 4 samples averaging of 32 samples 13.50 12.25 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd ?0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) 3.6.3.2 12-bit dac operating behaviors table 34. 12-bit dac operating behaviors symbol description min. typ. max. unit notes i dda_dacl p supply current ? low-power mode ? ? 150 ?a i dda_dach p supply current ? high-speed mode ? ? 700 ?a t daclp full-scale settling time (0x080 to 0xf7f) ? low-power mode ? 100 200 ?s 1 t dachp full-scale settling time (0x080 to 0xf7f) ? high-power mode ? 15 30 ?s 1 t ccdaclp code-to-code settling time (0xbf8 to 0xc08) ? low-power mode and high-speed mode ? 0.7 1 ?s 1 v dacoutl dac output voltage range low ? high- speed mode, no load, dac set to 0x000 ? ? 100 mv v dacouth dac output voltage range high ? high- speed mode, no load, dac set to 0xfff v dacr ?100 ? v dacr mv inl integral non-linearity error ? high speed mode ? ? ?8 lsb 2 dnl differential non-linearity error ? v dacr > 2 v ? ? ?1 lsb 3 dnl differential non-linearity error ? v dacr = vref_out ? ? ?1 lsb 4 v offset offset error ? ?0.4 ?0.8 %fsr 5 e g gain error ? ?0.1 ?0.6 %fsr 5 psrr power supply rejection ratio, v dda ? 2.4 v 60 ? 90 db t co temperature coefficient offset voltage ? 3.7 ? ?v/c 6 t ge temperature coefficient gain error ? 0.000421 ? %fsr/c a c offset aging coefficient ? ? 100 ?v/yr rop output resistance (load = 3 k?) ? ? 250 ? sr slew rate -80h 6. v dda = 3.0 v, reference select set for v dda (dacx_co:dacrfs = 1), high power mode (dacx_c0:lpen = 0), dac set to 0x800, temperature range is across the full range of the device digital code dac12 inl (lsb) 0 500 1000 1500 2000 2500 3000 3500 4000 2 4 6 8 -2 -4 -6 -8 0 temperature c dac12 mid level code voltage 25 55 85 105 125 1.499 -40 1.4985 1.498 1.4975 1.497 1.4965 1.496 table 36. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature= 25 ?c 1.192 1.195 1.198 v 1 v out voltage reference output with user trim at nominal v dda and temperature= 25 ?c 1.1945 1.195 1.1955 v 1 v step voltage reference trim step ? 0.5 ? mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range) ? 2 15 mv 1 i bg bandgap only current ? 60 80 ?a 1 i lp low-power buffer current ? 180 360 ua 1 i hp high-power buffer current ? 480 960 ma 1 see general switching specifications . 3.8 communication interfaces peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 47 np semiconductors 3.8.1 usb electrical specifications the usb electricals for the usb on-the-go module conform to the standards documented by the universal serial bus implementers forum. for the most up-to-date standards, visit usb.org . note the mcgpllclk meets the usb jitter and signaling rate specifications for certification with the use of an external clock/crystal for both device and host modes. the mcgfllclk does not meet the usb jitter or signaling rate specifications for certification. the irc48m meets the usb jitter and signaling rate specifications for certification in device mode when the usb clock recovery mode is enabled. it does not meet the usb signaling rate specifications for certification in host mode operation. 3.8.2 usb dcd electrical specifications table 39. usb0 dcd electrical specifications symbol description min. typ. max. unit v dp_src usb_dp source voltage (up to 250 a) 0.5 0.7 v v lgc threshold voltage for logic high 0.8 2.0 v i dp_src usb_dp source current 7 10 13 a i dm_sink usb_dm sink current 50 100 150 a r dm_dwn d- pulldown resistance for data pin contact detect 14.25 24.8 k v dat_ref data detect voltage 0.25 0.33 0.4 v 3.8.3 usb vreg electrical specifications table 40. usb vreg electrical specifications symbol description min. typ. 1 max. unit notes vregin input supply voltage 2.7 5.5 v table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 40. usb vreg electrical specifications (continued) symbol description min. typ. 1 max. unit notes i ddon quiescent current ? run mode, load current equal zero, input supply (vregin) > 3.6 v ? 125 186 ?a i ddstby quiescent current ? standby mode, load current equal zero ? 1.1 10 ?a i ddoff quiescent current ? shutdown mode ? vregin = 5.0 v and temperature=25 ?c ? across operating voltage and temperature ? ? 650 ? ? 4 na ?a i loadrun maximum load current ? run mode ? ? 120 ma i loadstby maximum load current ? standby mode ? ? 1 ma v reg33out regulator output voltage ? input supply (vregin) > 3.6 v ? run mode ? standby mode 3 2.1 3.3 2.8 3.6 3.6 v v v reg33out regulator output voltage ? input supply (vregin) < 3.6 v, pass-through mode 2.1 ? 3.6 v 2 c out external output capacitor 1.76 2.2 8.16 ?f esr external output capacitor equivalent series resistance 1 ? 100 m? i lim short circuit current ? 290 ? ma 1. typical values assume vregin = 5.0 v, temp = 25 ?c unless otherwise stated. 2. operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to i load . 3.8.4 can switching specifications see general switching specifications . peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 49 np semiconductors 3.8.5 dspi switching specifications (limited voltage range) the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provide dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 41. master mode dspi timing (limited voltage range) num description min. max. unit notes operating voltage 2.7 3.6 v frequency of operation 30 mhz ds1 dspi_sck output cycle time 2 x t bus ns ds2 dspi_sck output high/low time (t sck /2) 2 (t sck /2) + 2 ns ds3 dspi_pcs n valid to dspisc delay (t bus x 2) 2 ns 1 ds dspisc to dspipcs n invalid delay (t bus x 2) 2 ns 2 ds5 dspisc to dspisout valid .5 ns ds dspisc to dspisout invalid 2 ns ds dspisin to dspisc input setup 15 ns ds dspisc to dspisin input hold 0 ns 1. the delay is programmable in spixctarnpssc and spixctarncssc. 2. the delay is programmable in spixctarnpasc and spixctarnasc. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout table continues on the next page... peripheral operating requirements and behaviors 50 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 42. slave mode dspi timing (limited voltage range) (continued) num description min. max. unit ds9 dspi_sck input cycle time 4 x t bus ? ns ds10 dspi_sck input high/low time (t sck /2) ? 2 (t sck /2) + 2 ns ds11 dspi_sck to dspi_sout valid ? 10 ns ds12 dspi_sck to dspi_sout invalid 0 ? ns ds13 dspi_sin to dspi_sck input setup 2 ? ns ds14 dspi_sck to dspi_sin input hold 7 ? ns ds15 dspi_ss active to dspi_sout driven ? 14 ns ds16 dspi_ss inactive to dspi_sout not driven ? 14 ns 1. the maximum operating frequency is measured with non-continuous cs and sck. when dspi is configured with continuous cs and sck, there is a constraint that spi clock should not be greater than 1/6 of bus clock, for example, when bus clock is 60mhz, spi clock should not be greater than 10mhz first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin the dma serial peripheral interface (dspi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the tables below provides dspi timing characteristics for classic spi timing modes. refer to the dspi chapter of the reference manual for information on the modified transfer formats used for communicating with slower peripheral devices. table 43. master mode dspi timing (full voltage range) num description min. max. unit notes operating voltage 1.71 3.6 v 1 frequency of operation 15 mhz table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 51 np semiconductors table 43. master mode dspi timing (full voltage range) (continued) num description min. max. unit notes ds1 dspi_sck output cycle time 4 x t bus ? ns ds2 dspi_sck output high/low time (t sck /2) - 4 (t sck/2) + 4 ns ds3 dspi_pcs n valid to dspisc delay (t bus x 2) ns 2 ds dspisc to dspipcs n invalid delay (t bus x 2) ns ds5 dspisc to dspisout valid 10 ns ds dspisc to dspisout invalid -.5 ns ds dspisin to dspisc input setup 21 ns ds dspisc to dspisin input hold 0 ns 1. the dspi module can operate across the entire operating voltage for the processor, but to run across the full voltage range the maximum frequency of operation is reduced. 2. the delay is programmable in spixctarnpssc and spixctarncssc. . the delay is programmable in spixctarnpasc and spixctarnasc. ds3 ds4 ds1 ds2 ds7 ds8 first data last data ds5 first data data last data ds6 data dspi_pcsn dspi_sck (cpol=0) dspi_sin dspi_sout first data last data first data data last data data ds15 ds10 ds9 ds16 ds11 ds12 ds14 ds13 dspi_ss dspi_sck (cpol=0) dspi_sout dspi_sin 6. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat ? 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 7. c b = total capacitance of the one bus line in pf. table 46. i 2 c 1 mbps timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 ? ?s low period of the scl clock t low 0.5 ? ?s high period of the scl clock t high 0.26 ? ?s set-up time for a repeated start condition t su ; sta 0.26 ? ?s data hold time for i 2 c bus devices t hd ; dat 0 ? ?s data set-up time t su ; dat 50 ? ns rise time of sda and scl signals t r 20 +0.1c b , 2 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 ? ?s bus free time between stop and start condition t buf 0.5 ? ?s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbps can support maximum bus loading when using the high drive pins across the full voltage range. 2. c b = total capacitance of the one bus line in pf. ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl see general switching specifications . peripheral operating requirements and behaviors 54 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 3.8.9 sdhc specifications the following timing specs are defined at the chip i/o pin and must be translated appropriately to arrive at timing specs/constraints for the physical interface. table 47. sdhc switching specifications num symbol description min. max. unit operating voltage 1.71 3.6 v card input clock sd1 fpp clock frequency (low speed) 0 400 khz fpp clock frequency (sdsdio full speedhigh speed) 0 2550 mhz fpp clock frequency (mmc full speedhigh speed) 0 2050 mhz f od clock frequency (identification mode) 0 400 khz sd2 t wl clock low time 7 ns sd3 t wh clock high time 7 ns sd4 t tlh clock rise time 3 ns sd5 t thl clock fall time 3 ns sdhc output / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd6 t od sdhc output delay (output valid) -5 8.3 ns sdhc input / card inputs sdhc_cmd, sdhc_dat (reference to sdhc_clk) sd7 t isu sdhc input setup time 5.5 ns sd8 t ih sdhc input hold time 0 ns sd2sd3 sd1 sd6 sd8 sd7 sdhc_clk output sdhc_cmd output sdhc_dat[3:0] input sdhc_cmd input sdhc_dat[3:0] figure 26. sdhc timing peripheral operating requirements and behaviors kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 55 np semiconductors 3.8.10 i 2 s switching specifications this section provides the ac timings for the i 2 s in master (clocks driven) and slave modes (clocks input). all timings are given for non-inverted serial clock polarity (tcr[tsckp] = 0, rcr[rsckp] = 0) and a non-inverted frame sync (tcr[tfsi] = 0, rcr[rfsi] = 0). if the polarity of the clock and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal (i2s_bclk) and/or the frame sync (i2s_fs) shown in the figures below. table 48. i 2 s master mode timing num description min. max. unit operating voltage 2.7 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_bclk cycle time 80 ns s4 i2s_bclk pulse width high/low 45% 55% bclk period s5 i2s_bclk to i2s_fs output valid 15 ns s6 i2s_bclk to i2s_fs output invalid 0 ns s7 i2s_bclk to i2s_td valid 15 ns s8 i2s_bclk to i2s_td invalid 0 ns s9 i2s_rd/i2s_fs input setup before i2s_bclk 17 ns s10 i2s_rd/i2s_fs input hold after i2s_bclk 0 ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_bclk (output) i2s_fs (output) i2s_fs (input) i2s_txd i2s_rxd table 49. i 2 s slave mode timing num description min. max. unit operating voltage 2.7 3.6 v s11 i2s_bclk cycle time (input) 80 ? ns s12 i2s_bclk pulse width high/low (input) 45% 55% mclk period s13 i2s_fs input setup before i2s_bclk 5 ? ns s14 i2s_fs input hold after i2s_bclk 2 ? ns s15 i2s_bclk to i2s_txd/i2s_fs output valid ? 19.5 ns s16 i2s_bclk to i2s_txd/i2s_fs output invalid 0 ? ns s17 i2s_rxd setup before i2s_bclk 5 ? ns s18 i2s_rxd hold after i2s_bclk 2 ? ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 21 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_bclk (input) i2s_fs (output) i2s_fs (input) i2s_td i2s_rd s19 figure 28. i 2 s timing slave modes 3.8.10.1 normal run, wait and stop mode performance over the full operating voltage range this section provides the operating performance over the full operating voltage for the device in normal run, wait and stop modes. table 50. i2s/sai master mode timing num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 40 ns s2 i2s_mclk (as an input) pulse width high/low 45% 55% mclk period table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 5 np semiconductors table 50. i2s/sai master mode timing (continued) num. characteristic min. max. unit s3 i2s_tx_bclk/i2s_rx_bclk cycle time (output) 80 ? ns s4 i2s_tx_bclk/i2s_rx_bclk pulse width high/low 45% 55% bclk period s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid ? 15 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid -1 ? ns s7 i2s_tx_bclk to i2s_txd valid ? 15 ns s8 i2s_tx_bclk to i2s_txd invalid 0 ? ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 22.5 ? ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ? ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd table continues on the next page... peripheral operating requirements and behaviors 5 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 51. i2s/sai slave mode timing (continued) num. characteristic min. max. unit s14 i2s_tx_fs/i2s_rx_fs input hold after i2s_tx_bclk/i2s_rx_bclk 2 ? ns s15 i2s_tx_bclk to i2s_txd/i2s_tx_fs output valid ? 25.5 ns s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 3 ? ns s17 i2s_rxd setup before i2s_rx_bclk 5.8 ? ns s18 i2s_rxd hold after i2s_rx_bclk 2 ? ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 ? 25 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 this section provides the operating performance over the full operating voltage for the device in vlpr, vlpw, and vlps modes. table 52. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) num. characteristic min. max. unit operating voltage 1.71 3.6 v s1 i2s_mclk cycle time 62.5 ns s2 i2s_mclk pulse width high/low 45% 55% mclk period s3 i2s_t_bclk/i2s_r_bclk cycle time (output) 250 ns s4 i2s_t_bclk/i2s_r_bclk pulse width high/low 45% 55% bclk period table continues on the next page... peripheral operating requirements and behaviors inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 5 np semiconductors table 52. i2s/sai master mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s5 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output valid ? 45 ns s6 i2s_tx_bclk/i2s_rx_bclk to i2s_tx_fs/ i2s_rx_fs output invalid 0 ? ns s7 i2s_tx_bclk to i2s_txd valid ? 45 ns s8 i2s_tx_bclk to i2s_txd invalid ? ns s9 i2s_rxd/i2s_rx_fs input setup before i2s_rx_bclk 45 ? ns s10 i2s_rxd/i2s_rx_fs input hold after i2s_rx_bclk 0 ? ns s1 s2 s2 s3 s4 s4 s5 s9 s7 s9 s10 s7 s8 s6 s10 s8 i2s_mclk (output) i2s_tx_bclk/ i2s_rx_bclk (output) i2s_tx_fs/ i2s_rx_fs (output) i2s_tx_fs/ i2s_rx_fs (input) i2s_txd i2s_rxd table continues on the next page... peripheral operating requirements and behaviors 0 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 53. i2s/sai slave mode timing in vlpr, vlpw, and vlps modes (full voltage range) (continued) num. characteristic min. max. unit s16 i2s_tx_bclk to i2s_txd/i2s_tx_fs output invalid 0 ? ns s17 i2s_rxd setup before i2s_rx_bclk 30 ? ns s18 i2s_rxd hold after i2s_rx_bclk 11 ? ns s19 i2s_tx_fs input assertion to i2s_txd output valid 1 ? 72 ns 1. applies to first bit in each frame and only if the tcr4[fse] bit is clear s15 s13 s15 s17 s18 s15 s16 s16 s14 s16 s11 s12 s12 i2s_tx_bclk/ i2s_rx_bclk (input) i2s_tx_fs/ i2s_rx_fs (output) i2s_txd i2s_rxd i2s_tx_fs/ i2s_rx_fs (input) s19 package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 142-pin wlcsp 98asa00639d dimensions kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 61 np semiconductors 5 pinout 5.1 k24 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport c10 pte0 adc1_se4a adc1_se4a pte0 spi1_pcs1 uart1_t sdhc0_d1 trace_ clkout i2c1_sda rtc_ clkout d8 pte1/ llwu_p0 adc1_se5a adc1_se5a pte1/ llwu_p0 spi1_sout uart1_r sdhc0_d0 trace_d3 i2c1_scl spi1_sin d9 pte2/ llwu_p1 adc0_dp2/ adc1_se6a adc0_dp2/ adc1_se6a pte2/ llwu_p1 spi1_sck uart1_cts_ b sdhc0_ dclk trace_d2 c11 pte3 adc0_dm2/ adc1_se7a adc0_dm2/ adc1_se7a pte3 spi1_sin uart1_rts_ b sdhc0_cmd trace_d1 spi1_sout f6 vdd vdd vdd e6 vss vss vss d10 pte4/ llwu_p2 disabled pte4/ llwu_p2 spi1_pcs0 uart3_t sdhc0_d3 trace_d0 d11 pte5 disabled pte5 spi1_pcs2 uart3_r sdhc0_d2 ftm3_ch0 e7 pte6 disabled pte6 spi1_pcs3 uart3_cts_ b i2s0_mclk ftm3_ch1 usb_sof_ out e8 pte7 disabled pte7 uart3_rts_ b i2s0_rd0 ftm3_ch2 e9 pte8 disabled pte8 i2s0_rd1 uart5_t i2s0_r_fs ftm3_ch3 e10 pte9 disabled pte9 i2s0_td1 uart5_r i2s0_r_ bclk ftm3_ch4 e11 pte10 disabled pte10 uart5_cts_ b i2s0_td0 ftm3_ch5 f9 pte11 disabled pte11 uart5_rts_ b i2s0_t_fs ftm3_ch6 f10 pte12 disabled pte12 i2s0_t_ bclk ftm3_ch7 f7 vdd vdd vdd f11 vss vss vss g11 usb0_dp usb0_dp usb0_dp h11 usb0_dm usb0_dm usb0_dm g10 vout33 vout33 vout33 h10 vregin vregin vregin pinout 62 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport f8 adc0_dp1 adc0_dp1 adc0_dp1 g8 adc0_dm1 adc0_dm1 adc0_dm1 j11 adc1_dp1 adc1_dp1 adc1_dp1 k11 adc1_dm1 adc1_dm1 adc1_dm1 g9 adc0_dp0/ adc1_dp3 adc0_dp0/ adc1_dp3 adc0_dp0/ adc1_dp3 h9 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 adc0_dm0/ adc1_dm3 j10 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 adc1_dp0/ adc0_dp3 k10 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 adc1_dm0/ adc0_dm3 l11 vdda vdda vdda l10 vrefh vrefh vrefh m11 vrefl vrefl vrefl n11 vssa vssa vssa m10 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 adc1_se16/ cmp2_in2/ adc0_se22 k9 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 adc0_se16/ cmp1_in2/ adc0_se21 l9 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 n10 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 dac0_out/ cmp1_in3/ adc0_se23 m9 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 j9 rtc_ wakeup_b rtc_ wakeup_b rtc_ wakeup_b n9 xtal32 xtal32 xtal32 n8 extal32 extal32 extal32 m8 vbat vbat vbat h8 vdd vdd vdd g7 vss vss vss l8 pte24 adc0_se17 adc0_se17 pte24 uart4_tx i2c0_scl ewm_out_b k8 pte25 adc0_se18 adc0_se18 pte25 uart4_rx i2c0_sda ewm_in n7 pte26 disabled pte26 uart4_cts_ b rtc_ clkout usb_clkin pinout kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 63 nxp semiconductors 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport j8 pte27 disabled pte27 uart4_rts_ b m7 pte28 disabled pte28 l7 pta0 jtag_tclk/ swd_clk/ ezp_clk pta0 uart0_cts_ b/ uart0_col_ b ftm0_ch5 jtag_tclk/ swd_clk ezp_clk k7 pta1 jtag_tdi/ ezp_di pta1 uart0_rx ftm0_ch6 jtag_tdi ezp_di j7 pta2 jtag_tdo/ trace_ swo/ ezp_do pta2 uart0_tx ftm0_ch7 jtag_tdo/ trace_swo ezp_do n6 pta3 jtag_tms/ swd_dio pta3 uart0_rts_ b ftm0_ch0 jtag_tms/ swd_dio m6 pta4/ llwu_p3 nmi_b/ ezp_cs_b pta4/ llwu_p3 ftm0_ch1 nmi_b ezp_cs_b l6 pta5 disabled pta5 usb_clkin ftm0_ch2 cmp2_out i2s0_tx_ bclk jtag_trst_ b h7 vdd vdd vdd h6 vss vss vss n5 pta6 disabled pta6 ftm0_ch3 clkout trace_ clkout m5 pta7 adc0_se10 adc0_se10 pta7 ftm0_ch4 trace_d3 k6 pta8 adc0_se11 adc0_se11 pta8 ftm1_ch0 ftm1_qd_ pha trace_d2 l5 pta9 disabled pta9 ftm1_ch1 ftm1_qd_ phb trace_d1 n4 pta10 disabled pta10 ftm2_ch0 ftm2_qd_ pha trace_d0 j6 pta11 disabled pta11 ftm2_ch1 i2c2_sda ftm2_qd_ phb k5 pta12 cmp2_in0 cmp2_in0 pta12 can0_tx ftm1_ch0 i2c2_scl i2s0_txd0 ftm1_qd_ pha m4 pta13/ llwu_p4 cmp2_in1 cmp2_in1 pta13/ llwu_p4 can0_rx ftm1_ch1 i2c2_sda i2s0_tx_fs ftm1_qd_ phb j5 pta14 disabled pta14 spi0_pcs0 uart0_tx i2c2_scl i2s0_rx_ bclk i2s0_txd1 n3 pta15 disabled pta15 spi0_sck uart0_rx i2s0_rxd0 l4 pta16 disabled pta16 spi0_sout uart0_cts_ b/ uart0_col_ b i2s0_rx_fs i2s0_rxd1 m3 pta17 adc1_se17 adc1_se17 pta17 spi0_sin uart0_rts_ b i2s0_mclk n2 vdd vdd vdd pinout 64 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 nxp semiconductors 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport m2 vss vss vss n1 pta18 extal0 extal0 pta18 ftm0_flt2 ftm_clkin0 m1 pta19 xtal0 xtal0 pta19 ftm1_flt0 ftm_clkin1 lptmr0_ alt1 l1 reset_b reset_b reset_b l2 pta24 disabled pta24 fb_a15 fb_a29 l3 pta25 disabled pta25 fb_a14 fb_a28 k4 pta26 disabled pta26 fb_a13 fb_a27 k3 pta27 disabled pta27 fb_a12 fb_a26 k2 pta28 disabled pta28 fb_a25 k1 pta29 disabled pta29 fb_a24 j4 ptb0/ llwu_p5 adc0_se8/ adc1_se8 adc0_se8/ adc1_se8 ptb0/ llwu_p5 i2c0_scl ftm1_ch0 ftm1_qd_ pha j3 ptb1 adc0_se9/ adc1_se9 adc0_se9/ adc1_se9 ptb1 i2c0_sda ftm1_ch1 ftm1_qd_ phb j2 ptb2 adc0_se12 adc0_se12 ptb2 i2c0_scl uart0_rts_ b ftm0_flt3 j1 ptb3 adc0_se13 adc0_se13 ptb3 i2c0_sda uart0_cts_ b/ uart0_col_ b ftm0_flt0 h4 ptb4 adc1_se10 adc1_se10 ptb4 ftm1_flt0 h3 ptb5 adc1_se11 adc1_se11 ptb5 ftm2_flt0 h2 ptb6 adc1_se12 adc1_se12 ptb6 fb_ad23 h1 ptb7 adc1_se13 adc1_se13 ptb7 fb_ad22 g4 ptb8 disabled ptb8 uart3_rts_ b fb_ad21 g3 ptb9 disabled ptb9 spi1_pcs1 uart3_cts_ b fb_ad20 g1 ptb10 adc1_se14 adc1_se14 ptb10 spi1_pcs0 uart3_rx fb_ad19 ftm0_flt1 g2 ptb11 adc1_se15 adc1_se15 ptb11 spi1_sck uart3_tx fb_ad18 ftm0_flt2 h5 vss vss vss f3 vdd vdd vdd f1 ptb16 disabled ptb16 spi1_sout uart0_rx ftm_clkin0 fb_ad17 ewm_in f2 ptb17 disabled ptb17 spi1_sin uart0_tx ftm_clkin1 fb_ad16 ewm_out_b e1 ptb18 disabled ptb18 can0_tx ftm2_ch0 i2s0_tx_ bclk fb_ad15 ftm2_qd_ pha e2 ptb19 disabled ptb19 can0_rx ftm2_ch1 i2s0_tx_fs fb_oe_b ftm2_qd_ phb e3 ptb20 disabled ptb20 spi2_pcs0 fb_ad31 cmp0_out e4 ptb21 disabled ptb21 spi2_sck fb_ad30 cmp1_out d4 ptb22 disabled ptb22 spi2_sout fb_ad29 cmp2_out d1 ptb23 disabled ptb23 spi2_sin spi0_pcs5 fb_ad28 pinout kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 65 nxp semiconductors 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport d2 ptc0 adc0_se14 adc0_se14 ptc0 spi0_pcs4 pdb0_ extrg usb_sof_ out fb_ad14 i2s0_txd1 d3 ptc1/ llwu_p6 adc0_se15 adc0_se15 ptc1/ llwu_p6 spi0_pcs3 uart1_rts_ b ftm0_ch0 fb_ad13 i2s0_txd0 c1 ptc2 adc0_se4b/ cmp1_in0 adc0_se4b/ cmp1_in0 ptc2 spi0_pcs2 uart1_cts_ b ftm0_ch1 fb_ad12 i2s0_tx_fs b1 ptc3/ llwu_p7 cmp1_in1 cmp1_in1 ptc3/ llwu_p7 spi0_pcs1 uart1_rx ftm0_ch2 clkout i2s0_tx_ bclk f4 vss vss vss g5 vdd vdd vdd a1 ptc4/ llwu_p8 disabled ptc4/ llwu_p8 spi0_pcs0 uart1_tx ftm0_ch3 fb_ad11 cmp1_out c2 ptc5/ llwu_p9 disabled ptc5/ llwu_p9 spi0_sck lptmr0_ alt2 i2s0_rxd0 fb_ad10 cmp0_out ftm0_ch2 b2 ptc6/ llwu_p10 cmp0_in0 cmp0_in0 ptc6/ llwu_p10 spi0_sout pdb0_ extrg i2s0_rx_ bclk fb_ad9 i2s0_mclk a2 ptc7 cmp0_in1 cmp0_in1 ptc7 spi0_sin usb_sof_ out i2s0_rx_fs fb_ad8 b3 ptc8 adc1_se4b/ cmp0_in2 adc1_se4b/ cmp0_in2 ptc8 ftm3_ch4 i2s0_mclk fb_ad7 a3 ptc9 adc1_se5b/ cmp0_in3 adc1_se5b/ cmp0_in3 ptc9 ftm3_ch5 i2s0_rx_ bclk fb_ad6 ftm2_flt0 c3 ptc10 adc1_se6b adc1_se6b ptc10 i2c1_scl ftm3_ch6 i2s0_rx_fs fb_ad5 b4 ptc11/ llwu_p11 adc1_se7b adc1_se7b ptc11/ llwu_p11 i2c1_sda ftm3_ch7 i2s0_rxd1 fb_rw_b a4 ptc12 disabled ptc12 uart4_rts_ b ftm_clkin0 fb_ad27 ftm3_flt0 c4 ptc13 disabled ptc13 uart4_cts_ b ftm_clkin1 fb_ad26 b5 ptc14 disabled ptc14 uart4_rx fb_ad25 a5 ptc15 disabled ptc15 uart4_tx fb_ad24 f5 vss vss vss e5 vdd vdd vdd c5 ptc16 disabled ptc16 uart3_rx fb_cs5_b/ fb_tsiz1/ fb_be23_ 16_bls15_8_ b a6 ptc17 disabled ptc17 uart3_tx fb_cs4_b/ fb_tsiz0/ fb_be31_ 24_bls7_0_b b6 ptc18 disabled ptc18 uart3_rts_ b fb_tbst_b/ fb_cs2_b/ fb_be15_8_ bls23_16_b pinout 66 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 nxp semiconductors 142 csp pin name default alt0 alt1 alt2 alt3 alt4 alt5 alt6 alt7 ezport d5 ptc19 disabled ptc19 uart3_cts_ b fb_cs3_b/ fb_be7_0_ bls31_24_b fb_ta_b d6 ptd0/ llwu_p12 disabled ptd0/ llwu_p12 spi0_pcs0 uart2_rts_ b ftm3_ch0 fb_ale/ fb_cs1_b/ fb_ts_b a7 ptd1 adc0_se5b adc0_se5b ptd1 spi0_sck uart2_cts_ b ftm3_ch1 fb_cs0_b c6 ptd2/ llwu_p13 disabled ptd2/ llwu_p13 spi0_sout uart2_rx ftm3_ch2 fb_ad4 i2c0_scl b7 ptd3 disabled ptd3 spi0_sin uart2_tx ftm3_ch3 fb_ad3 i2c0_sda c7 ptd4/ llwu_p14 disabled ptd4/ llwu_p14 spi0_pcs1 uart0_rts_ b ftm0_ch4 fb_ad2 ewm_in spi1_pcs0 a8 ptd5 adc0_se6b adc0_se6b ptd5 spi0_pcs2 uart0_cts_ b/ uart0_col_ b ftm0_ch5 fb_ad1 ewm_out_b spi1_sck b8 ptd6/ llwu_p15 adc0_se7b adc0_se7b ptd6/ llwu_p15 spi0_pcs3 uart0_rx ftm0_ch6 fb_ad0 ftm0_flt0 spi1_sout a9 ptd7 disabled ptd7 cmt_iro uart0_tx ftm0_ch7 ftm0_flt1 spi1_sin b9 ptd8 disabled ptd8 i2c0_scl uart5_rx fb_a16 a10 ptd9 disabled ptd9 i2c0_sda uart5_tx fb_a17 d7 ptd10 disabled ptd10 uart5_rts_ b fb_a18 c8 ptd11 disabled ptd11 spi2_pcs0 uart5_cts_ b sdhc0_ clkin fb_a19 b10 ptd12 disabled ptd12 spi2_sck ftm3_flt0 sdhc0_d4 fb_a20 c9 ptd13 disabled ptd13 spi2_sout sdhc0_d5 fb_a21 a11 ptd14 disabled ptd14 spi2_sin sdhc0_d6 fb_a22 b11 ptd15 disabled ptd15 spi2_pcs1 sdhc0_d7 fb_a23 g6 nc nc nc 5.2 unused analog interfaces table 54. unused analog interfaces module name pins recommendation if unused adc adc0_dp1, adc0_dm1, adc1_dp1, adc1_dm1, adc0_dp0/adc1_dp3, adc0_dm0/adc1_dm3, adc1_dp0/ adc0_dp3, adc1_dm0/adc0_dm3, adc1_se16/adc0_se22, adc0_se16/adc0_se21, adc1_se18 ground table continues on the next page... pinout inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 54. unused analog interfaces (continued) module name pins recommendation if unused dac 1 dac0_out, dac1_out float usb vregin, usb0_gnd, vout33 2 connect vregin and vout33 together and tie to ground through a 10 k? resistor. do not tie directly to ground, as this causes a latch-up risk. usb0_dm, usb0_dp float 1. unused dac signals do not apply to all parts. see the pinout section for details. 2. usb0_vbus and usb0_gnd are board level signals 5.3 k24 pinouts the below figure shows the pinout diagram for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see the previous section. pinout 68 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 1 a ptc4/ llwu_p8 b ptc3/ llwu_p7 c ptc2 d ptb23 e ptb18 f ptb16 g ptb10 h ptb7 j ptb3 k pta29 l reset_b m pta19 1 n pta18 2 ptc7 ptc6/ llwu_p10 ptc5/ llwu_p9 ptc0 ptb19 ptb17 ptb11 ptb6 ptb2 pta28 pta24 vss 2 vdd 3 ptc9 ptc8 ptc10 ptc1/ llwu_p6 ptb20 vdd ptb9 ptb5 ptb1 pta27 pta25 pta17 3 pta15 4 ptc12 ptc11/ llwu_p11 ptc13 ptb22 ptb21 vss ptb8 ptb4 ptb0/ llwu_p5 pta26 pta16 pta13/ llwu_p4 4 pta10 5 ptc15 ptc14 ptc16 ptc19 vdd vss vdd vss pta14 pta12 pta9 pta7 5 pta6 6 ptc17 ptc18 ptd2/ llwu_p13 ptd0/ llwu_p12 vss vdd vss pta11 pta8 pta5 pta4/ llwu_p3 6 pta3 7 ptd1 ptd3 ptd4/ llwu_p14 ptd10 pte6 vdd vss vdd pta2 pta1 pta0 pte28 7 pte26 8 ptd5 ptd6/ llwu_p15 ptd11 pte1/ llwu_p0 pte7 adc0_dp1 adc0_dm1 vdd pte27 pte25 pte24 vbat 8 extal32 9 ptd7 ptd8 ptd13 pte2/ llwu_p1 pte8 pte11 adc0_dp0/ adc1_dp3 adc0_dm0/ adc1_dm3 rtc_ wakeup_b adc0_se16/ cmp1_in2/ adc0_se21 vref_out/ cmp1_in5/ cmp0_in5/ adc1_se18 dac1_out/ cmp0_in4/ cmp2_in3/ adc1_se23 9 xtal32 10 ptd9 ptd12 pte0 pte4/ llwu_p2 pte9 pte12 vout33 vregin adc1_dp0/ adc0_dp3 adc1_dm0/ adc0_dm3 vrefh adc1_se16/ cmp2_in2/ adc0_se22 10 dac0_out/ cmp1_in3/ adc0_se23 11 ptd14 ptd15 pte3 pte5 pte10 vss usb0_dp usb0_dm adc1_dp1 adc1_dm1 vdda vrefl 11 vssa a b c d e f g h j k l m n figure 33. 142 csp pinout diagram 6 ordering parts ordering parts kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 69 nxp semiconductors 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search for the following device numbers: mk24 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 7.2 format part numbers for this device have the following format: q k## a m fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? m = fully qualified, general market flow, full reels ? p = prequalification ? k = fully qualified, general market flow, 100 piece reels k## kinetis family ? k24 = usb with high ram density a key attribute ? d = cortex-m4 w/ dsp ? f = cortex-m4 w/ dsp and fpu m flash memory type ? n = program flash only ? = program flash and flexmemory fff program flash memory size ? 512 = 512 kb ? 1m0 = 1 mb r silicon revision ? = initial table continues on the next page... part identification 0 inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors field description values ? (blank) = main ? a = revision after main t temperature range (?c) ? c = ?40 to 85 pp package identifier ? aj = 142 wlcsp (4.8 mm x 5.6 mm) cc maximum cpu frequency (mhz) ? 12 = 120 mhz n packaging type ? r = tape and reel 7.4 example this is an example part number: MK24FN1M0CAJ12R 8 terminology and guidelines 8.1 definitions key terms are defined in the following table: term definition rating a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. handling ratings apply when the chip is not powered. note: the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. operating requirement a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip operating behavior a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions typical value a specified value for a technical characteristic that: lies within the range of values specified by the operating behavior is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions note: typical values are provided as design guidelines and are neither tested nor guaranteed. terminology and guidelines inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 1 np semiconductors 8.2 examples operating rating : operating requirement : operating behavior that includes a typical value : eample eample eample eample . typical-value conditions typical values assume you meet the following conditions (or other conditions as specified): symbol description value unit t a ambient temperature 25 c v dd supply voltage 3.3 v terminology and guidelines 72 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 np semiconductors 8.4 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 9 revision history the following table provides a revision history for this document. table 55. revision history rev. no. date substantial changes 2 01/2014 initial public release. 3 04/2014 ? format changes 4 09/2014 ? updated table 6 power consumption operating behavior. ? updated table 17 irc48m specifications ? updated table 35 vref full-range operating behavior table continues on the next page... revision history inetis 2 sub-family data sheet with 1 mb flash, rev. , 10/201 np semiconductors table 55. revision history (continued) rev. no. date substantial changes 5 12/2014 ? updated table 6 "power consumption operating behavior." ? added a note to the section "power consumption operating behaviors." 6 08/2015 ? added a footnote to the maximum scl clock frequency value in the table "i 2 c timing" ? changed the title of the table "i 2 c 1 mhz timing" to "i 2 c 1 mbps timing" ? added a footnote and updated the table "irc48m specifications" for open loop total deviation of irc48m frequency at high voltage and low voltage. ? added a footnote on the ambient temperature entry to the section "thermal operating requirements." ? added a note to the section "power consumption operating behaviors" and updated values in the table "power consumption operating behaviors." ? added a note to the maximum frequency value in the table "slave mode dspi timing (limited voltage range)." ? redeveloped the section "terminology and guidelines." 7 10/2016 ? updated the values of i dd_stop and i dd_vlls0 in the table "power consumption operating behavior." revision history 74 kinetis k24 sub-family data sheet with 1 mb flash, rev. 7, 10/2016 nxp semiconductors how to reach us: hoe ae: co e ot: cosot oato ths ocet s oe soe to eae sste a sotwae eetes to se octs hee ae o eess o e coht ceses ate heee to es o acate a teate ccts ase o the oato ths ocet esees the ht to ae chaes wthot the otce to a octs hee aes o waat eesetato o aatee ea the stat o ts octs o a atca ose o oes asse a at as ot o the acato o se o a oct o cct a secca scas a a a at c wthot tato coseeta o ceta aaes ca aaetes that a e oe ata sheets ao seccatos ca a o a eet acatos a acta eoace a a oe te oeat aaetes c tcas st e aate o each cstoe acato cstoes techca eets oes ot coe a cese e ts atet hts o the hts o othes ses octs sat to staa tes a cotos o sae whch ca e o at the oow aess: cosaestesacotos oo a ets ae taeas o othe oct o sece aes ae the oet o the esecte owes r a ote ae estee taeas o r te o ts ssaes the u ao esewhee he u oo s a estee taea o u eetes o c hts esee ocet e reso |
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