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cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 system-on-chip for 2.4-ghz rf applications 1 features ? rf section ? microcontroller ? single-chip 2.4-ghz rf transceiver and ? high-performance and low-power 8051 mcu microcontroller core with code prefetch ? supports 250 kbps, 500 kbps, 1 mbps and 2 ? 32-kb flash program memory mbps data rates ? 1 kb sram ? excellent link budget, enabling long ? hardware debug support range without external front-ends ? extensive baseband automation, including ? programmable output power up to 5 dbm auto-acknowledgement and address ? excellent receiver sensitivity ( ? 90 dbm at decoding 2 mbps, ? 98 dbm at 250 kbps) ? peripherals ? suitable for systems targeting compliance ? two-channel dma with access to all with worldwide radio frequency memory areas and peripherals regulations: etsi en 300 328 and en 300 ? general-purpose timers (one 16-bit, two 440 category 2 (europe), fcc cfr47 part 8-bit) 15 (us), and arib std-t66 (japan) ? radio timer, 40-bit ? accurate rssi function ? ir generation circuitry ? layout ? several oscillators: ? few external components ? 32mhz xosc ? pin out suitable for single layer pcb ? 16mhz rcosc applications ? 32khz rcosc ? reference designs available ? 32-khz sleep timer with capture ? 32-pin 5-mm 5-mm qfn (16 general i/o ? aes security coprocessor pins) package ? uart/spi/i 2 c serial interface ? low power ? 16 general-purpose i/o pins (3 20-ma ? active mode rx best performance: 21.2 ma drive strength, remaining pins have 4 ma ? active mode tx (0 dbm): 26 ma drive strength) ? power mode 1 (5 s wake-up): 235 a ? watchdog timer ? power mode 2 (sleep timer on): 0.9 a ? true random-number generator ? power mode 3 (external interrupts): 0.4 a ? adc and analog comparator ? wide supply voltage range (2v to 3.6v) ? full ram and register retention in all applications power modes ? proprietary 2.4-ghz systems ? human interface devices (keyboard, mouse) ? consumer electronics 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2012 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. description the cc2543 is an optimized system-on-chip (soc) solution with data rates up to 2mbps built with low bill-of- material cost. the cc2543 combines the excellent performance of a leading rf transceiver with a single-cycle 8051 compliant cpu, 32-kb in-system programmable flash memory, up to 1-kb ram, and many other powerful features. the cc2543 has efficient power modes with ram and register retention below 1 a, making it highly suited for low-duty-cycle systems where ultra-low power consumption is required. short transition times between operating modes further ensure low energy consumption. the cc2543 is compatible with the cc2541/cc2544/cc2545. it comes in a 5-mm 5-mm qfn32 package, with spi/uart/i2c interface. the cc2543 comes complete with reference designs from texas instruments. the device targets wireless consumer and hid applications. the cc2543 is tailored for peripheral devices such as wireless mice. for block diagram, see figure 7 . absolute maximum ratings (1) over operating free-air temperature range (unless otherwise noted) min max unit supply voltage vdd all supply pins must have the same voltage ? 0.3 3.9 v voltage on any digital pin ? 0.3 vdd + 0.3 3.9 v input rf level 10 dbm storage temperature range ? 40 125 c all pins, excluding 20 and 21, according to human-body model, 2.5 kv jedec std 22, method a114 (hbm) all pins, according to human-body model, jedec std 22, esd (2) 1.5 kv method a114 (hbm) according to charged-device model, jedec std 22, method 750 v c101 (cdm) (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) caution : esd sensitive device. precaution should be used when handing the device in order to prevent permanent damage. recommended operating conditions min max unit operating ambient temperature range, t a ? 40 85 c operating supply voltage vdd all supply pins must have same voltage 2 3.6 v 2 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 electrical characteristics measured on texas instruments cc2543em reference design with t a = 25 c and vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit 2 mbps, gfsk, 320-khz deviation rx mode, no peripherals active, low mcu activity 21.2 ma tx mode, 0-dbm output power, no peripherals active, low mcu activity 26 ma tx mode, 5-dbm output power, no peripherals active, low mcu activity 29.4 ma active mode, 16-mhz rcosc, low mcu activity 3 ma active mode, 32-mhz clock frequency, low mcu activity 6 ma power mode 0, cpu clock halted, all peripherals on, no clock division, 32-mhz 4.5 ma crystal selected i core ? core current power mode 0, cpu clock halted, all peripherals on, clock division at max (limits consumption 3.1 ma max speed in peripherals except radio), 32-mhz crystal selected power mode 1. digital regulator on; 16-mhz rcosc and 32-mhz crys tal oscillator off; 32.753-khz rcosc, por, bod, and sleep timer active; ram and register 235 a retention power mode 2. digital regulator off, 16 mhz rcosc and 32 mhz crystal oscillator 0.9 a off; 32.753 khz rcosc, por and sleep timer active; ram and register retention power mode 3. digital regulator off, no clocks, por active; ram and register 0.4 a retention timer 1 (16-bit). timer running, 32-mhz xosc used 90 a i peri ? peripheral current consumption radio timer(40 bit). timer running, 32-mhz xosc used 90 a (adds to core timer 3 (8-bit). timer running, 32-mhz xosc used 60 a current i core for each timer 4 (8-bit). timer running, 32-mhz xosc used 70 a peripheral unit activated) sleep timer. including 32.753-khz rcosc 0.6 a general characteristics measured on texas instruments cc2543em reference design with t a = 25 c and vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit wake-up and timing digital regulator on, 16-mhz rcosc and 32-mhz crystal oscillator off. power mode 1 active 5 s start-up of 16-mhz rcosc power mode 2 or 3 digital regulator off, 16 mhz rcosc and 32 mhz crystal oscillator off. 130 s active start-up of regulator and 16 mhz rcosc crystal esr = 16 . initially running on 16-mhz rcosc, with 32-mhz 500 s xosc off active tx or rx with 32-mhz xosc initially on 180 s rx/tx turnaround rcosc, with 32mhz xosc off 130 s radio part rf frequency range programmable in 1-mhz steps 2379 2496 mhz 2 mbps, gfsk 320-khz deviation 2-mbps, gfsk 500 khz deviation 1-mbps, gfsk 250 khz deviation data rates and modulation 1-mbps, gfsk 160 khz deviation formats 500 kbps, msk 250 kbps, gfsk 160 khz deviation 250 kbps, msk copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links : cc2543
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com rf receive section measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, and f c = 2440 mhz, unless otherwise noted. parameter test conditions min typ max unit 2 mbps, gfsk, 320-khz deviation, 0.1% ber receiver sensitivity ? 86 dbm saturation ? 8 dbm co-channel rejection wanted signal at ? 67 dbm ? 13 db 2-mhz offset, wanted signal at ? 67 dbm ? 1 in-band blocking rejection 4-mhz offset, wanted signal at ? 67 dbm 34 db > 6-mhz offset, wanted signal at ? 67 dbm 38 1-mhz resolution. wanted signal at ? 67 dbm, f < 2 ghz ? 32 two exception frequencies with poorer performance 1-mhz resolution. wanted signal at ? 67 dbm, 2 ghz > f < 3 ghz out-of-band blocking rejection ? 38 dbm two exception frequencies with poorer performance 1-mhz resolution. wanted signal at ? 67 dbm, f > 3ghz ? 12 two exception frequencies with poorer performance wanted signal at ? 64 dbm, 1 st interferer is cw, 2 nd interferer is gfsk- modulated signal. offsets of interferers are: intermodulation 6 and 12 mhz ? 43 dbm 8 and 16 mhz 10 and 20 mhz including both initial tolerance and drift. sensitivity better than ? 70 dbm. frequency error tolerance (1) ? 300 300 khz 250 byte payload. symbol rate error tolerance (2) sensitivity better than -70 dbm. 250 byte payload. ? 120 120 ppm 2 mbps, gfsk, 500 khz deviation, 0.1% ber receiver sensitivity ? 90 dbm saturation ? 3 dbm co-channel rejection wanted signal at ? 67 dbm ? 10 db 2 mhz offset, wanted signal at ? 67 dbm ? 3 db in-band blocking rejection 4 mhz offset, wanted signal at ? 67 dbm 36 db > 6 mhz offset, wanted signal at ? 67 dbm 44 db including both initial tolerance and drift. sensitivity better than ? 70 dbm. frequency error tolerance (1) ? 300 300 khz 250 byte payload. symbol rate error tolerance (2) sensitivity better than -70 dbm. 250 byte payload. ? 120 120 ppm 1 mbps, gfsk, 250 khz deviation, 0.1% ber receiver sensitivity ? 94 dbm saturation 6 dbm co-channel rejection wanted signal at ? 67 dbm ? 7 db 1 mhz offset, wanted signal ? 67 dbm 0 2 mhz offset, wanted signal ? 67 dbm 30 in-band blocking rejection db 3 mhz offset, wanted signal ? 67 dbm 34 > 5 mhz offset, wanted signal ? 67 dbm 38 including both initial tolerance and drift. sensitivity better than ? 70 dbm. frequency error tolerance ? 250 250 khz 250 byte payload. symbol rate error tolerance sensitivity better than ? 70 dbm. 250 byte payload. -80 80 ppm (1) difference between center frequency of the received rf signal and local oscillator frequency (2) difference between incoming symbol rate and the internally generated symbol rate 4 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 rf receive section (continued) measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, and f c = 2440 mhz, unless otherwise noted. parameter test conditions min typ max unit 1 mbps, gfsk, 160 khz deviation, 0.1% ber receiver sensitivity ? 91 dbm saturation 6 dbm co-channel rejection wanted signal at ? 67 dbm ? 8 db 1 mhz offset, wanted signal at ? 67 dbm 2 2 mhz offset, wanted signal at ? 67 dbm 28 in band blocking rejection db 3 mhz offset, wanted signal at ? 67 dbm 33 > 5 mhz offset, wanted signal at ? 67 dbm 36 frequency error tolerance including both initial tolerance and drift, sensitivity better than ? 67 dbm ? 250 250 khz symbol rate error tolerance maximum packet length ? 80 80 ppm 500 kbps, msk, 0.1% ber receiver sensitivity ? 98 dbm saturation 6 dbm co-channel rejection wanted signal at ? 67 dbm ? 5 db 1 mhz offset, wanted signal at ? 67 dbm 21 in band blocking rejection 2 mhz offset, wanted signal at ? 67 dbm 32 db > 2 mhz offset, wanted signal at ? 67 dbm 33 frequency error tolerance including both initial tolerance and drift, sensitivity better than ? 67dbm ? 150 150 khz symbol rate error tolerance maximum packet length ? 60 60 ppm 250 kbps, gfsk, 160 khz deviation , 0.1% ber receiver sensitivity ? 98 dbm saturation 6 dbm co-channel rejection wanted signal at ? 67 dbm ? 2 db 1 mhz offset, wanted signal at ? 67 dbm 22 in-band blocking rejection 2 mhz offset, wanted signal at ? 67 dbm 32 db > 2 mhz offset, wanted signal at ? 67 dbm 32 frequency error tolerance including both initial tolerance and drift, sensitivity better than ? 67 dbm ? 150 150 khz symbol rate error tolerance maximum packet length ? 60 60 ppm 250 kbps, msk, 0.1% ber receiver sensitivity ? 98 dbm saturation 6 dbm co-channel rejection wanted signal at ? 67 dbm ? 5 db 1 mhz offset, wanted signal at ? 67 dbm 21 in-band blocking rejection 2 mhz offset, wanted signal at ? 67 dbm 32 db > 2 mhz offset, wanted signal at ? 67 dbm 33 frequency error tolerance including both initial tolerance and drift, sensitivity better than ? 67 dbm ? 150 150 khz symbol rate error tolerance maximum packet length ? 60 60 ppm all rates/formats spurious emission in rx. f < 1 ghz ? 67 dbm conducted measurement spurious emission in rx. f > 1 ghz ? 60 dbm conducted measurement copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links : cc2543
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com rf transmit section measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, and f c = 2440 mhz, unless otherwise noted. parameter test conditions min typ max unit delivered to a single-ended 50- load through a balun using output power, maximum setting 5 dbm maximum recommended output power setting. delivered to a single-ended 50- load through a balun using output power, minimum setting ? 20 dbm minimum recommended output power setting. programmable output power range delivered to a single-ended 50- load through a balun. 25 db f < 1 ghz ? 46 dbm spurious emission in tx. f > 1 ghz ? 46 dbm conducted measurement suitable for systems targeting compliance with worldwide radio frequency regulations: etsi en 300 328 and en 300 440 class 2 (europe), fcc cfr47 part 15 (us), and arib std-t66 (japan) use a simple lc filter (1.6nh and 1.8pf in parallel to ground) to pass etsi conducted requirements below 1ghz in restricted bands. for radiated measurements low antenna gain for these frequencies (depending on antenna design) can achieve the same attenuation of these low frequency components (see em reference design). 32-mhz crystal oscillator measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit crystal frequency 32 mhz 250 kbps and 500 kbps data rates ? 30 30 crystal frequency accuracy 1 mbps data rate ? 40 40 ppm requirement 2 mbps data rate ? 60 60 equivalent series resistance 6 60 crystal shunt capacitance 1 7 pf crystal load capacitance 10 16 pf start-up time 0.25 ms the crystal oscillator must be in power down for a guard time before it is used again. this requirement is valid for all modes of power-down guard time 3 ms operation. the need for power-down guard time can vary with crystal type and load. 32-khz rc oscillator measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit calibrated frequency 32.753 khz frequency accuracy after calibration 0.2% temperature coefficient 0.4 %/ o c supply-voltage coefficient 3 %/v calibration time 2 ms 16-mhz rc oscillator measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit calibrated frequency 16 mhz uncalibrated frequency accuracy 18% frequency accuracy after calibration 0.6% start-up time 10 s initial calibration time 50 s 6 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 rssi characteristics measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. 2mbps, gfsk, 320-khz deviation, 0.1% ber and 2 mbps, gfsk, 500-khz deviation, 0.1% ber reduced gain by ac algorithm 64 rssi range (1) db high gain by agc algorithm 64 reduced gain by agc algorithm 79 rssi offset (1) dbm high gain by agc algorithm 99 absolute uncalibrated accuracy (1) 3 db step size (lsb value) 1 db all other rates/formats rssi range (1) 64 db rssi offset (1) 99 dbm absolute uncalibrated accuracy 3 db step size (lsb value) 1 db (1) assuming cc2543 em reference design. other rf designs give an offset from the reported value. frequency synthesizer characteristics measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. parameter test conditions min typ max unit at 1 mhz from carrier ? 112 phase noise, unmodulated carrier at 3 mhz from carrier ? 119 dbc/hz at 5 mhz from carrier ? 122 analog temperature sensor measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v unless otherwise noted parameter test conditions min typ max unit output 1480 12-bit temperature coefficient 4.5 / 1 o c voltage coeficcient 1 / 0.1v measured using integrated adc, internal band-gap voltage reference, and maximum resolution initial accuracy without calibration 10 o c accuracy using 1-point calibration 5 o c current consumption when enabled 0.5 ma comparator characteristics t a = 25 c, vdd = 3 v. all measurement results are obtained using the cc2543 reference designs, post-calibration. parameter test conditions min typ max unit common-mode maximum voltage vdd v common-mode minimum voltage ? 0.3 input offset voltage 1 mv offset vs temperature 16 v/ c offset vs operating voltage 4 mv/v supply current 230 na hysteresis 0.15 mv copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links : cc2543
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com adc characteristics t a = 25 c and vdd = 3 v parameter test conditions min typ max unit input voltage vdd is voltage from supply 0 vdd v external reference voltage vdd is voltage from supply 0 vdd v external reference voltage differential vdd is voltage from supply 0 vdd v input resistance, signal simulated using 4-mhz clock speed 197 k ? full-scale signal (1) peak-to-peak, defines 0 dbfs 2.97 v single-ended input, 7-bit setting 5.7 single-ended input, 9-bit setting 7.5 single-ended input, 10-bit setting 9.3 single-ended input, 12-bit setting 10.3 differential input, 7-bit setting 6.5 enob (1) effective number of bits bits differential input, 9-bit setting 8.3 differential input, 10-bit setting 10 differential input, 12-bit setting 11.5 10-bit setting, clocked by rcosc 9.7 12-bit setting, clocked by rcosc 10.9 useful power bandwidth 7-bit setting, both single and differential 0 ? 20 khz single ended input, 12-bit setting, ? 6 dbfs (1) ? 75.2 thd total harmonic distortion db differential input, 12-bit setting, ? 6 dbfs (1) ? 86.6 single-ended input, 12-bit setting (1) 70.2 differential input, 12-bit setting (1) 79.3 signal to nonharmonic ratio db single-ended input, 12-bit setting, ? 6 dbfs (1) 78.8 differential input, 12-bit setting, ? 6 dbfs (1) 88.9 differential input, 12-bit setting, 1-khz sine cmrr common-mode rejection ratio > 84 db (0 dbfs), limited by adc resolution single ended input, 12-bit setting, 1-khz sine crosstalk > 84 db (0 dbfs), limited by adc resolution offset midscale ? 3 mv gain error 0.68% 12-bit setting, mean (1) 0.05 dnl differential nonlinearity lsb 12-bit setting, maximum (1) 0.9 12-bit setting, mean (1) 4.6 12-bit setting, maximum (1) 13.3 inl integral nonlinearity lsb 12-bit setting, mean, clocked by rcosc 10 12-bit setting, max, clocked by rcosc 29 single ended input, 7-bit setting (1) 35.4 single ended input, 9-bit setting (1) 46.8 single ended input, 10-bit setting (1) 57.5 single ended input, 12-bit setting (1) 66.6 sinad signal-to-noise-and-distortion db ( ? thd+n) differential input, 7-bit setting (1) 40.7 differential input, 9-bit setting (1) 51.6 differential input, 10-bit setting (1) 61.8 differential input, 12-bit setting (1) 70.8 7-bit setting 20 9-bit setting 36 conversion time s 10-bit setting 68 12-bit setting 132 (1) measured with 300-hz sine-wave input and vdd as reference. 8 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 adc characteristics (continued) t a = 25 c and vdd = 3 v parameter test conditions min typ max unit power consumption 1.2 ma internal reference vdd coefficient 4 mv/v internal reference temperature 0.4 mv/10 c coefficient internal reference voltage 1.15 v dc characteristics measured on texas instruments cc2543em reference design with t a = 25 c, vdd = 3 v, unless otherwise noted. (1) parameter test conditions min typ max unit logic-0 input voltage 0.5 v logic-1 input voltage 2.5 v logic-0 input current ? 50 50 na logic-1 input current ? 50 50 na i/o pin pullup and pulldown resistors 20 k logic-0 output voltage 4-ma pins output load 4 ma 0.5 v logic-1 output voltage 4-ma pins output load 4 ma 2.4 v logic-0 output voltage 20-ma pins output load 20 ma 0.5 v logic-1 output voltage 20-ma pins output load 20 ma 2.4 v (1) note that only two of the three 20ma pins can drive in the same direction at the same time, and toggle at the same time. control input ac characteristics t a = ? 40 c to 85 c, vdd = 2 v to 3.6 v. parameter test conditions min typ max unit the undivided system clock is 32 mhz when crystal oscillator is used. system clock, f sysclk the undivided system clock is 16 mhz when calibrated 16-mhz rc 16 32 mhz t sysclk = 1/ f sysclk oscillator is used. see item 1, figure 1 . this is the shortest pulse that is recognized as a reset_n low duration complete reset pin request. note that shorter pulses may be recognized 1 s but do not lead to complete reset of all modules within the chip. see item 2, figure 1 .this is the shortest pulse that is recognized as an interrupt pulse duration 20 ns interrupt request. figure 1. control input ac characteristics copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links : cc2543 reset_n px.n t0299-01 1 2
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com spi ac characteristics t a = ? 40 c to 85 c, vdd = 2 v to 3.6 v parameter test conditions min typ max unit master, rx and tx 250 t 1 sck period ns slave, rx and tx 250 sck duty cycle master 50% master 63 t 2 ssn low to sck, figure 2 and figure 3 ns slave 63 master 63 t 3 sck to ssn high ns slave 63 t 4 mosi early out master, load = 10 pf 7 ns t 5 mosi late out master, load = 10 pf 10 ns t 6 miso setup master 90 ns t 7 miso hold master 10 ns sck duty cycle slave 50% ns t 10 mosi setup slave 35 ns t 11 mosi hold slave 10 ns t 8 miso early out slave, load = 10 pf 0 ns t 9 miso late out slave, load = 10 pf 95 ns master, tx only 8 master, rx and tx 4 operating frequency mhz slave, rx only 8 slave, rx and tx 4 figure 2. spi master ac characteristics 10 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543 sck ssn mosi miso d0 d1 x d0 x t 2 t 4 t 6 t 7 t 5 t 3 x t0478-01
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 figure 3. spi slave ac characteristics debug interface ac characteristics t a = ? 40 c to 85 c, vdd = 2 v to 3.6 v parameter test conditions min typ max unit f clk_dbg debug clock frequency (see figure 4 ) 12 mhz t 1 allowed high pulse on clock (see figure 4 ) 35 ns t 2 allowed low pulse on clock (see figure 4 ) 35 ns ext_reset_n low to first falling edge on debug t 3 167 ns clock (see figure 5 ) falling edge on clock to ext_reset_n high (see t 4 83 ns figure 5 ) ext_reset_n high to first debug command (see t 5 83 ns figure 5 ) t 6 debug data setup (see figure 6 ) 2 ns t 7 debug data hold (see figure 6 ) 4 ns t 8 clock-to-data delay (see figure 6 ) load = 10 pf 30 ns figure 4. debug clock ? basic timing copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links : cc2543 time debug_ clk p2_2 t 1 t 2 1/f clk_dbg t0436-01 t0479-01 sck ssn mosi miso d0 d1 x d0 x t 2 t 3 x t 8 t 10 t 11 t 9
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com figure 5. debug enable timing figure 6. data setup and hold timing timer inputs ac characteristics t a = ? 40 c to 85 c, vdd = 2 v to 3.6 v parameter test conditions min typ max unit synchronizers determine the shortest input pulse that can be input capture pulse duration recognized. the synchronizers operate at the current system clock rate 1.5 t sysclk (16 mhz or 32 mhz). 12 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543 reset_n time debug_ clk p2_2 t 3 t 4 t 5 t0437-01 time debug_ clk p2_2 debug_data (to cc2543) p2_1 debug_data (from cc2543) p2_1 t0438-03 t 6 t 8 t 7
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 device information pin descriptions note: the exposed ground pad must be connected to a solid ground plane; this is the main ground connection for the chip. table 1. pin description table name pin pin type description p1_3 1 digital i/o port 1.3 p2_1/dd 2 digital i/o / port 2.1 / debug data debug p2_0 3 digital i/o port 2.0 p0_7 4 digital i/o port 0.7 p0_6 5 digital i/o port 0.6 p0_5 6 digital i/o port 0.5 p0_4 7 digital i/o port 0.4 p0_3 8 digital i/o port 0.3 p0_2 9 digital i/o port 0.2 p0_1 10 digital i/o port 0.1 p0_0 11 digital i/o port 0.0 vdd 12 power (analog) 2-v-3.6v analog power-supply connection reset_n 13 digital input reset, active-low p2_2/dc 14 digital i/o / port 2.2 / debug clock debug vdd 15 power (analog) 2-v-3.6v analog power-supply connection xosc_q1 16 analog o 32-mhz crystal oscillator pin 1 xosc_q2 17 analog o 32-mhz crystal oscillator pin 2 vdd 18 power (analog) 2-v-3.6v analog power-supply connection vss 19 unused pin connect to ground rf_p 20 rf i/o positive rf input signal to lna during rx positive rf output signal from pa during tx copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links : cc2543 1 p1_3 2 p2_1/dd 3 p2_0 4 p0_7 5 p0_6 6 p0_5 7 p0_4 8 p0_3 vdd 24 vdd 23 vss 22 rf_n 21 rf_p 20 vss 19 vdd 18 xosc_q2 17 rbias 25 p1_2 26 p1_1 27 p1_0 28 vdd 29 dcpl1 30 vss 31 p1_4 32 16 xosc_q1 15 vdd 14 p2_2/dc 13 reset_n 12 vdd 11 p0_0 10 p0_1 9 p0_2 cc2543 rhb package (top view)
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com table 1. pin description table (continued) name pin pin type description rf_n 21 rf i/o negative rf input signal to lna during rx negative rf output signal from pa during tx vss 22 unused pin connect to ground vdd 23 power (analog) 2-v ? 3.6-v analog power-supply connection vdd 24 power (analog) 2-v ? 3.6-v analog power-supply connection rbias 25 analog i/o external precision bias resistor for reference current p1_2 26 digital i/o port 1.2, 20 ma p1_1 27 digital i/o port 1.1, 20 ma p1_0 28 digital i/o port 1.0, 20 ma vdd 29 power (analog) 2-v ? 3.6-v analog power-supply connection dcpl1 30 power (digital) 1.8-v digital power-supply decoupling. do not use for supplying external circuits. vss 31 unused pin connect to ground p1_4 32 digital i/o port 1.4 vss ground ground must be connected to solid ground as this is the main ground connection for the chip. see pad pinout diagram . 14 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 block diagram a block diagram of the cc2543 is shown in figure 7 . the modules can be roughly divided into one of three categories: cpu-related modules; modules related to power, test, and clock distribution; and radio-related modules. in the following subsections, a short description of each module is given. see cc2543/44/45 user's guide ( swru283 ) for more details. figure 7. cc2543 block diagram copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links : cc2543 reset watchdog timer irq ctrl flash ctrl debug interface clock mux and calibration dma 8051 cpu core 32mhz crystal osc high speed rcosc power management controller usart 0 i c 2 timer 1 (16-bit) timer 3 (8-bit)timer 4 (8-bit) timer 2 (radio timer) flash sram rom fifoctrl sram reset_n xosc_q2 xosc_q1 p0_7p0_6 p2_2p0_5 p1_2p0_2 p2_1p1_4 p0_4 p1_1p0_1 p2_0p1_3 p0_3 p1_0p0_0 modulator demodulator receive transmit frequency synthesizer synth rf_p rf_n b0301-12 radio registers sfr bus sfr bus adc audio/dc aes encryption and decryption flash ram unified sfr iram xram pdata sleep timer 32khz rcosc i/o controller digital analog mixed analog comparator sda scl radio arbiter link layer engine pseudo random number generator onchip voltage regulator power on reset brown out vdd (2 vC3.6 v) dcoupl memory arbitrator
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com block descriptions cpu and memory the 8051 cpu core is a single-cycle 8051-compatible core. it has three different memory access busses (sfr, data, and code/xdata), a debug interface, and an 15-input extended interrupt unit. the memory arbiter is at the heart of the system, as it connects the cpu and dma controller with the physical memories and all peripherals through the sfr bus. the memory arbiter has four memory-access points, access of which can map to one of three physical memories: an sram, flash memory, and xreg/sfr registers. it is responsible for performing arbitration and sequencing between simultaneous memory accesses to the same physical memory. the sfr bus is drawn conceptually in figure 7 as a common bus that connects all hardware peripherals to the memory arbiter. the sfr bus in the block diagram also provides access to the radio registers in the radio register bank, even though these are indeed mapped into xdata memory space. the 1-kb sram maps to the data memory space and to parts of the xdata memory spaces. the 18-kb/32-kb flash block provides in-circuit programmable non-volatile program memory for the device, and maps into the code and xdata memory spaces. peripherals writing to the flash block is performed through a flash controller that allows page-wise erasure and 4-bytewise programming. see user guide for details on the flash controller. a versatile two-channel dma controller is available in the system, accesses memory using the xdata memory space, and thus has access to all physical memories. each channel (trigger, priority, transfer mode, addressing mode, source and destination pointers, and transfer count) is configured with dma descriptors that can be located anywhere in memory. many of the hardware peripherals (aes core, flash controller, usart, timers, etc.) can be used with the dma controller for efficient operation by performing data transfers between a single sfr or xreg address and flash/sram. the interrupt controller services a total of 17 interrupt sources, divided into six interrupt groups, each of which is associated with one of four interrupt priorities. any interrupt service request is serviced also when the device is in idle mode by going back to active mode. some interrupts can also wake up the device from sleep mode (when in sleep mode, the device is in low-power mode pm1, pm2 or pm3). the debug interface implements a proprietary two-wire serial interface that is used for in-circuit debugging. through this debug interface, it is possible to perform an erasure of the entire flash memory, control which oscillators are enabled, stop and start execution of the user program, execute supplied instructions on the 8051 core, set code breakpoints, and single-step through instructions in the code. using these techniques, it is possible to perform in-circuit debugging and external flash programming elegantly. the i/o controller is responsible for all general-purpose i/o pins. the cpu can configure whether peripheral modules control certain pins or whether they are under software control, and if so, whether each pin is configured as an input or output and if a pullup or pulldown resistor in the pad is connected. each peripheral that connects to the i/o pins can choose between several different i/o pin locations to ensure flexibility in various applications. the sleep timer is an ultralow-power timer that uses an internal 32.753-khz rc oscillator. the sleep timer runs continuously in all operating modes. typical applications of this timer are as a real-time counter or as a wake-up timer to get out of power modes 1 or 2. a built-in watchdog timer allows the cc2543 to reset itself if the firmware hangs. when enabled by software, the watchdog timer must be cleared periodically; otherwise, it resets the device when it times out. timer 1 is a 16-bit timer with timer/counter/pwm functionality. it has a programmable prescaler, a 16-bit period value, and five individually programmable counter/capture channels, each with a 16-bit compare value. each of the counter/capture channels can be used as a pwm output or to capture the timing of edges on input signals. it can also be configured in ir generation mode, where it counts timer 3 periods and the output is anded with the output of timer 3 to generate modulated consumer ir signals with minimal cpu interaction. 16 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 timer 2 is a 40-bit timer used by the radio. it has a 16-bit counter with a configurable timer period and a 24-bit overflow counter that can be used to keep track of the number of periods that have transpired. a 40-bit capture register is also used to record the exact time at which a start-of-frame delimiter is received/transmitted or the exact time at which a packet ends. there are two 16-bit timer-compare registers and two 24-bit overflow- compare registers that can be used to give exact timing for start of rx or tx to the radio or general interrupts. timer 3 and timer 4 are 8-bit timers with timer/counter/pwm functionality. they have a programmable prescaler, an 8-bit period value, and one programmable counter channel with an 8-bit compare value. each of the counter channels can be used as pwm output. usart 0 is configurable as either an spi master/slave or a uart. it provides double buffering on both rx and tx and hardware flow control and is thus well suited to high-throughput full-duplex applications. the usart has its own high-precision baud-rate generator, thus leaving the ordinary timers free for other uses. when configured as spi slaves, the usart samples the input signal using sck directly instead of using some oversampling scheme, and are thus well-suited for high data rates. the i 2 c module provides a digital peripheral connection with two pins and supports both master and slave operation. the adc supports 7 bits (30 khz bandwidth) to 12 bits (4 khz bandwidth) of resolution. dc and audio conversions with up to eight input channels (port 0) are possible. the inputs can be selected as single-ended or differential. the reference voltage can be internal, avdd, or a single-ended or differential external signal. the adc also has a temperature-sensor input channel. the adc can automate the process of periodic sampling or conversion over a sequence of channels. the aes encryption/decryption core allows the user to encrypt and decrypt data using the aes algorithm with 128-bit keys. the aes core also supports ecb, cbc, cfb, ofb, ctr, and cbc-mac, as well as hardware support for ccm. the ultralow-power analog comparator enables applications to wake up from pm2 or pm3 based on an analog signal. both inputs are brought out to pins; the reference voltage must be provided externally. the comparator output is mapped into the digital i/o port and can be treated by the mcu as a regular digital input. copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 17 product folder links : cc2543
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com typical characteristics rx current tx current vs vs temperature temperature figure 8. figure 9. rx sensitivity tx power vs vs temperature temperature figure 10. figure 11. rx current tx current vs vs supply voltage supply voltage figure 12. figure 13. 18 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543 27 28 29 30 31 32 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage (v) current (ma) t a = 25c txpower setting = 0xe5 g006 ?90 ?88 ?86 ?84 ?82 ?80 ?40 ?20 0 20 40 60 80 temperature (c) sensitivity level (dbm) g003 3-v supplystandard gain setting 2 mbps, gfsk, 320 khz deviation 0 2 4 6 8 10 ?40 ?20 0 20 40 60 80 temperature (c) power level (dbm) 3-v supplytxpower setting = 0xe5 g004 19 20 21 22 23 24 ?40 ?20 0 20 40 60 80 temperature (c) current (ma) 3-v supplystandard gain setting ?70 dbm input g001 2 mbps, gfsk, 320 khz deviation 27 28 29 30 31 32 ?40 ?20 0 20 40 60 80 temperature (c) current (ma) 3-v supplytxpower setting = 0xe5 g002 19 20 21 22 23 24 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage (v) current (ma) g005 t a = 25c standard gain setting?70 dbm input 2 mbps, gfsk, 320 khz deviation
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 typical characteristics (continued) rx sensitivity tx power vs vs supply voltage supply voltage figure 14. figure 15. rx sensitivity tx power vs vs frequency frequency figure 16. figure 17. rx interferer rejection (selectivity) vs interferer frequency figure 18. copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 19 product folder links : cc2543 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 2400 2420 2440 2460 2480 frequency (mhz) rejection (dbm) 3-v supplyt a = 25c standard gain settingwanted signal at 2440 mhz with ?67 dbm level g010 ?90 ?88 ?86 ?84 ?82 ?80 2400 2420 2440 2460 2480 frequency (mhz) sensitivity level (dbm) g009 3-v supplyt a = 25c standard gain setting 2 mbps, gfsk, 320 khz deviation 0 2 4 6 8 10 2400 2420 2440 2460 2480 frequency (mhz) power level (dbm) 3-v supplyt a = 25c txpower setting = 0xe5 g011 ?90 ?88 ?86 ?84 ?82 ?80 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage (v) sensitivity level (dbm) t a = 25c standard gain setting g007 2 mbps, gfsk, 320 khz deviation 0 2 4 6 8 10 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 supply voltage (v) power level (dbm) t a = 25c txpower setting = 0xe5 g008
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com typical characteristics (continued) table 2. recommended output power settings (1) txpower register setting typical output power (dbm) 0xe5 5 0xd5 4 0xc5 3 0xb5 2 0xa5 0 0x95 ? 2 0x85 ? 3 0x75 ? 4 0x65 ? 6 0x55 ? 8 0x45 ? 11 0x35 ? 13 0x25 ? 15 0x15 ? 17 0x05 ? 20 (1) measured on texas instruments cc2543 em reference design with ta = 25 c, vdd = 3 v and fc = 2440 mhz. see swru283 for recommended register settings. 20 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543
cc2543 www.ti.com swrs107e ? april 2012 ? revised october 2013 application information few external components are required for the operation of the cc2543. a typical application circuit is shown in figure 19 . for suggestions of component values other than those listed in table 3 , see reference design cc2543em. the performance stated in this data sheet is only valid for the cc2543em reference design. to obtain similar performance, the reference design should be copied as closely as possible. figure 19. cc2543 application circuit table 3. overview of external components (excluding balun, crystal and supply decoupling capacitors) component description value c301 decoupling capacitor for the internal 1.8v digital voltage regulator 1 f r251 precision resistor 1%, used for internal biasing 56 k input/output matching when using an unbalanced antenna such as a monopole, a balun should be used to optimize performance. the balun can be implemented using low-cost discrete inductors and capacitors. see reference design, cc2543em, for recommended balun. copyright ? 2012 ? 2013, texas instruments incorporated submit documentation feedback 21 product folder links : cc2543 r251 c171c161 c301 cc2543 die attach pad antenna (50 ) w s0383-08 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1516 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 power supply decoupling capacitors are not shown digital i/o not connected vdd p1_3 p0_2 p1_4 vdd vss vss dcpl1 rf_n vdd rf_p p1_0 vss p1_1 vdd p1_2 xosc_q2 rbias p2_1/dd p0_1 p2_0 p0_0 p0_7 vdd p0_6 reset_n p0_5 p2_2/dc p0_4 vdd p0_3 xosc_q1 2-vC3.6-v power supply
cc2543 swrs107e ? april 2012 ? revised october 2013 www.ti.com crystal an external 32-mhz crystal with two loading capacitors is used for the 32-mhz crystal oscillator. the load capacitance seen by the 32-mhz crystal is given by: (1) a series resistor may be used to comply with esr requirement. on-chip 1.8-v voltage regulator decoupling the 1.8-v on-chip voltage regulator supplies the 1.8-v digital logic. this regulator requires a decoupling capacitor (c301) for stable operation. power-supply decoupling and filtering proper power-supply decoupling must be used for optimum performance. the placement and size of the decoupling capacitors and the power supply filtering are very important to achieve the best performance in an application. ti provides a compact reference design that should be followed very closely. spacer revision history changes from original (april 2012) to revision a page ? changed data sheet status from product preview to production data ................................................................................ 1 changes from revision a (april 2012) to revision b page ? added comparator characteristics specifications ................................................................................................................ 7 ? added adc characteristics specifications ........................................................................................................................... 8 changes from revision b (may 2012) to revision c page ? changed the temperature coefficient unit value from: mv/ c to: / 0.1 c ......................................................................... 7 changes from revision c (august 2012) to revision d page ? changed the pin package from: rhm to: rhb ................................................................................................................. 13 changes from revision d (november 2012) to revision e page ? changed the adc characteristics test conditions from: vdd is voltage on avdd5 pin to: vdd is voltage from supply ........................................................................................................................................................................... 8 22 submit documentation feedback copyright ? 2012 ? 2013, texas instruments incorporated product folder links : cc2543 = + + l parasitic 161 171 1 c c 1 1 c c
package option addendum www.ti.com 28-jun-2016 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples cc2543rhbr active vqfn rhb 32 3000 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 cc2543 CC2543RHBT active vqfn rhb 32 250 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 85 cc2543 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 28-jun-2016 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cc2543rhbr vqfn rhb 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 CC2543RHBT vqfn rhb 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 q2 package materials information www.ti.com 3-oct-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cc2543rhbr vqfn rhb 32 3000 338.1 338.1 20.6 CC2543RHBT vqfn rhb 32 250 210.0 185.0 35.0 package materials information www.ti.com 3-oct-2013 pack materials-page 2

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