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datasheet P9038 august 1, 2016 1 ?2016 integrated device technology, inc. 8w, qi-compliant, wireless power transmitter with integrated full bridge inverter P9038 features ? 4.5v to 6.9v input operating voltage range, supporting: ? usb or ac adapter ? usb dedicated charger port (dcp) detection ? wpc-1.2.2 compliant for a5 or a11-type coils ? integrated, high-efficiency power stage with low r ds(on) ? integrated foreign object detection & current sense ? excellent emi performance eliminates need for emi filter ? supports up to 8w power transfer to the receiver ? demodulates and decodes communication packets from wpc-compliant receivers ? i 2 c interface for eeprom access ? programmable input over-voltage protection ? programmable soft start ? current limit and over -temperature protection ? -40 to +85c temperature range ? 7 x 7 mm 56-vfqfpn package applications ? furniture ? pc peripherals ? rugged electronic gear ? small appliances ? battery-powered electronics description the P9038 is a wpc-compliant wireless power transmitter for a5 and a11 designs operating from 5v supplies conforming with wpc specificat ion 1.2.2. operating in the wpc-compliant mode, the integrated full-bridge inverter supports 8w power transfer utilizing the p902x receiver family, and ensures efficient switching with emi/rfi emissions that are better than the requirements of the wpc specification. to safeguard the device and the system under fault conditions, the P9038 offers resistor programmable foreign object detection, built-in over-current protection, and programmable over-voltage / over-temperature protection. this transmitter is extremely easy to use and provides a complete wpc-compliant solution with minimum external parts count, requiring significantly less board space and lower total solution cost th an competing products. the P9038 is available in a compact 7 x 7 mm vfqfpn package, and it is rated for -40 to +85c temperature range. typical application circuit ldo5v ldo2p5v adaptor dm dp wp P9038 l ctx vsns_avg in scl sda reg_in en reset ldo2p5v_in gnd reset c in c in ldo5v ldo2p5v gpio_0 - gpio_6 c ldo5v c out c ldo2p5v vo gpio_6 sw1 bst1 c bst1 bst2 c sw2 sw2 c sw1 c bst2 gate vbus_sns isnsp_in isnsn_in isns_avg inv5v_in dp dm c hpf c isns_1 isns hpf c isns_avg ovp_sel shield1 shield2 c vsns_avg gpio_1 z1 z2 eeprom r shld =10mo r gate c gate a0 a1 a2 vss vcc wp scl sda r sns r filt_p r filt_n c filt_n c filt_p c filt_cm en
P9038 datasheet ?2016 integrated device technology, inc. 2 P9038 august 1, 2016 absolute maximum ratings stresses above the ratings listed below ( ta b l e 1 and table 2 ) can cause permanent damage to the P9038. these ratings, which are standard values for idt commercially rated parts, are stress ratings only. functional operatio n of the device at these or a ny other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods can affect produc t reliability. electrical paramete rs are guaranteed only over t he recommended operating temperature range. table 1: absolute maximum ratings summary. (all voltages are referred to ground.) table 2: package thermal information 1,2,3 notes: 1. the maximum power dissipation is p d(max) = (t j(max ) - t a ) / ja where t j(max) is 125c. exceeding the maximum allowable power dissipation will result in excessive die temperature, and the device will enter thermal shutdown. 2. this thermal rating was calculated on jedec 51 standard 4-laye r board with dimensions 3" x 4.5" in still air conditions. 3. actual thermal resistance is affected by pcb size, solder joint quality, layer count, copper thickness, air flow, altitude, and other unlisted variables. table 3: esd information pins rating units vbus_sns -0.3 to 27 v en , in, reg_in, sw1, sw2, isnsn_in, isnsp_in -0.3 to 12.5 v gpio_6:0, scl, sda, reset, dp, dm, nc, nc1 , nc2, nc3, shield2, ldo5v, ldo2p5v_in, inv5v_in, vfod_sns, isns, hpf, ovp_sel, isns_v -0.3 to 5.5 v bst1, bst2 -0.3 to sw+6 v gate -0.3 to reg_in+6 v gnd, refgnd, pgnd1, pgnd2 + 0.3 v shield1 -0.3 to 8 v ldo2p5v -0.3 to 2.75 v symbol description rating (vfqfpn) units ja thermal resistance junction to ambient 25.5 ? c/w jc thermal resistance junction to case 8.6 ? c/w jb thermal resistance junction to board 2.4 ? c/w t j operating junction temperature -40 to +125 ? c t a ambient operating temperature -40 to +85 ? c t stg storage temperature -55 to +150 ? c t lead lead temperature (soldering, 10s) +300 ? c test model pins ratings units hbm all pins 2000 v cdm all pins 500 v
P9038 datasheet P9038 august 1, 2016 3 ?2016 integrated device technology, inc. electrical specifications table table 4: device characteristics v in = 5v, en = 0v, c in = 40 f, coil = a11, c s = 400nf, t a = -40 to +85c, unless otherwise no ted. typical values are at 25c. symbol description con ditions min typ max units input supplies & uvlo v bus input operating range vbus_min to ovp_max 4.5 6.9 v i in_regin 2 standby input current (no ping) after power-up sequence complete. no coil, no switching at sw1, sw2, ldo5v, ldo2p5v. reg_in = 6.9v 812ma standby input current (pinging) after power-up sequence complete. average including pinging. 15 ma sleep mode input current en = reg_in = 6.9v 600 ua i in_vbus_sns vbus_sns input current vbus_sns = 6.9v 1 ma v regin_uvlo regin under-voltage protection trip points rising 4.1 v falling 3.4 v hysteresis 150 mv full bridge pwm generators f sw switching frequency 110 205 khz f sw lsb switching frequency step size 12.5 ns duty 4 duty cycle v reg = 4.5v-6.9v 10 50 90 % full bridge inverter i hs_ocp_rng over-current protection trip point range v in = 5v, cycle-by-cycle protection, programmable range 315a i hs_ocp_acc over-current protection trip point accuracy v in = 5v, ocp setting = 5a -20 20 % input ovp, inrush control, and current limit v bus_ovp v bus over-voltage protection trip point v bus rising, ovp_sel pin grounded 6.7 7.15 v v bus rising, ovp_sel pin 220k 5% to gnd 5.8 6.3 v v bus rising, ovp_sel pin floating 7.3 7.85 v hysteresis 200 mv v reg_ovp reg_in over-voltage protection trip point v reg_in rising 9.3 9.8 v t gate_rise gate voltage rise time v bus = 5v, gate cap = 4nf v gate = 1v to v in +4v 3.6 ms d gate_fall delay from input ovp to gate voltage pull-down v gate pull down time, gate cap = 4nf v gate = v in +4v to v in 4 00 ns i gate_lkg gate leakage vbus_sns = 0v, reg_in = 5v, v gate = 10v -1 +1 a input average current sense
P9038 datasheet ?2016 integrated device technology, inc. 4 P9038 august 1, 2016 isen ir input range isnsp_in, isnsn_in regin -0.3v - regin +0.15v v isen acc current sense accuracy v regin = 4.5 to 7.2v, i sensr = 1.5a, note 1 +/- 3 % ldo2p5v 3 v in v in v in v in v in v in v in v out v out v out v out v out v out v out i out_max i out_max i out_max i out_max i out_max i out_max i out_max ldo5v 3 v in input voltage 4.5 6.9 v v out output voltage i load = 10ma, reg_in = 5.5 5 v i out_max maximum output current 10 ma thermal shutdown t sd thermal shutdown threshold rising 140 c threshold falling 110 c en v ih 1.1 v v il 0.3 v i en en input current v en = 6.9v 25 a general purpose inputs / outputs (gpio) 5 v ih input threshold high 3.5 v v il input threshold low 1.5 v i lkg input leakage -1 +1 a v oh output logic high i oh = -8ma 4 v v ol output logic low i ol = 8ma 0.5 v reset v ih input threshold high 3.5 v v il input threshold low 1.5 v i lkg input leakage -1 +1 a dp/dm charger detection v dp_src v dm_src dp and dm voltage source 0.6 v dp and dm voltage source output source current v dp or v dm between 0.5v and 0.7v 250 a dp and dm voltage source output sink current v dp or v dm at 2.2v 500 a idp_sink idm_sink current sink 25 100 175 a idp_src current source 7 13 a vdat_ref data detect voltage 0.25 0.4 v vdp/dm_lgchi logic high 2.0 v symbol description con ditions min typ max units
P9038 datasheet P9038 august 1, 2016 5 ?2016 integrated device technology, inc. notes: 1. 10m ?? 1% or better sense resistor is required to meet the fod specification 2. this current is the sum of the input currents for reg_in, in, isnsp_in, isnsn_in, and en_b. 3. 3.for internal use - do not externally load. 4. guaranteed by design. 5. any of the gpio pins is capable of sourcing 8ma. the gpio connected to the adc have a max operating input voltage of 2.4v to prevent saturation of the adc. vdp/dm_lgclo logic low 0.8 v rdp_dwn pull-down resistance 14.25 19.5 24.8 k ? ci input capacitance dm pin, switch open 4.5 5 pf dp pin, switch open 4.5 5 pf iilk input leakage dm pin, switch open v = 5.0 -1 +1 a dp pin, switch open v = 5.0 - 1+1 a scl, sda (i 2 c interface) f scl_mstr1 f scl_mstr1 f scl_mstr1 f scl_mstr1 f scl_mstr1 f scl_mstr1 f scl_mstr1 f scl_mstr2 f scl_mstr2 f scl_mstr2 f scl_mstr2 f scl_mstr2 f scl_mstr2 f scl_mstr2 f scl_slv clock frequency P9038 as slave 0 400 khz t hd,sta hold time (repeated) for start condition 0.6 s t hd:dat data hold time i 2 c-bus devices 10 ns t low clock low period 1.3 s t high clock high period 0.6 s t su:sta set-up time for repeated start condition 100 ns t buf bus free time between stop and start condition 1.3 s c b capacitive load for each bus line 100 pf c bin scl, sda input capacitance 5 5pf v il input threshold low 0.4 v v ih input threshold high 1.4 v i lkg input leakage current v = 0v & 5v -1.0 1.0 a v ol output logic low (sda) i = 2ma 0.25 v symbol description con ditions min typ max units
P9038 datasheet ?2016 integrated device technology, inc. 6 P9038 august 1, 2016 typical performance characteristics figure 1. system efficiency vs. load circuit v in = 5v, v out = 5.3v, spacer = 3.7mm, cs = 247nf, t a = 25c measured using the p9025ac-r-evk v1 .0 (receiver) and P9038-r-evk v1.0 (transmitter) reference boards. table 5: P9038 no load vs receiver i out = 1a, t a = 25c input voltage temp (c) no load temp (c) 1a load temp. change 4.5v 34.7 37.2 2.5 5.0v 34.9 37.4 2.5 5.5v 35.2 38.5 3.3
P9038 datasheet P9038 august 1, 2016 7 ?2016 integrated device technology, inc. pin configuration pin descriptions pin # name type function 1 gnd i signal ground connection. 2 nc ? do not connect. internally connected. 3 gpio6 i/o general purpose input/output. 4 gpio5 i/o general purpose input/output. 5 gpio4 i/o general purpose input/output. 6 gpio3 i/o general purpose input/output. 7 gpio2 i/o general purpose input/output. 8 gpio1 i/o general purpose input/output. 9 gpio0 i/o general purpose input/output. 10 scl i i 2 c clock. 11 sda i/o i 2 c data. 12 dp i/o usb data positive input. if not used, the pin can be floating. 13 dm i/o usb data negative input. if not used, the pin can be floating. 14 reset i active-high rese t pin. connect a 47k ? to gnd or tie directly to gnd if not used. 15 vbus_sns i vbus ovp sense point & provides bias for ovp circuitry. gpio6 nc gnd gnd sw1 bst1 pgnd1 en refgnd reg_in ldo2p5v_in ldo2p5v in in gpio5 gpio4 gpio3 gpio2 gpio1 gpio0 scl sda reset vsns_avg isns_avg pgnd1 pgnd1 dp dm ldo5v isnsp_in isnsn_in gate pgnd1 sw1 sw1 sw1 in in sw2 sw2 sw2 sw2 pgnd2 pgnd2 pgnd2 bst2 pgnd2 4 3 2 1 5 6 7 8 9 10 11 12 13 14 18 17 16 15 19 20 21 22 23 24 25 26 27 28 53 54 55 56 52 51 50 49 48 47 46 45 44 43 39 40 41 42 38 37 36 35 34 33 32 31 30 29 isns gnd hpf shield2 shield1 vbus_sns inv5v_in ovp_sel epad
P9038 datasheet ?2016 integrated device technology, inc. 8 P9038 august 1, 2016 16 en i active-low enable pin. connect a 47k ? to gnd or tie directly to gnd if chip is always enabled. 17 refgnd pwr signal ground connection. connect to agnd. 18 reg_in i input voltage for the internal 5v linear regul ator. connect a 1f capacitor from this pin to gnd. 19 ldo5v o 5v ldo output. connect a 1f capacitor from this pin to gnd. 20 lod2p5v o 2.5v ldo output. connect a 1f capacitor from this pin to gnd. 21 ldo2p5_in pwr input voltage for the internal 2.5v linear regulator. this pin must be connected to ldo5v (pin 19). 22 inv5v_in pwr input power to the internal driver circui try. connect a 1f capacitor from this pin to gnd. 23 ovp_sel i input over-voltage protecti on selection. when connected to gnd, the nominal ovp threshold is set to 7.15v. when floating, 7.85v. connecting the pin through a 220k ? resistor to g nd sets the ovp to 6.3v. 24 vsns_avg i input voltage sense averaging pin. conn ect a 6.8nf capacitor from this pin to agnd. 25 bst2 i bootstrap pin for sw2 bridge node. connect a 0.1uf capacitor from this pin to sw2 pin. 26,27,28,29 pgnd2 gnd power ground. 30,31,32,33 sw2 o h-bridge switch node 2. 34,35,36,37 in i power supply input vo ltage. connect two 22f capacitors from the pins to gnd. 38,39,40,41 sw1 o h-bridge switch node 1. 42,43,44,45 pgnd1 gnd power ground. 46 bst1 i bootstrap pin for sw1 bridge node. connect a 0.1uf capacitor from this pin to sw1 pin. 47 gate o output gate driver for the external fet. connect a 6.8nf capacitor in parallel with 10m ? from this pin to gnd to configure soft-start. 48 isns_avg i input current sense averaging pin. connect a 1nf capacitor from this pin to agnd. 49 isnsn_in i input current sens e amplifier inverting input. 50 isnsp_in i input current sense amplifier non-inverting input. 51 shield1 o shield output to guard dc voltage on hpf pin. connect a 10m ? resistor to gnd. 52 hpf i high pass filter input for demodulator. connect to an external high pass filter. 53 shield2 o shield output to guard dc volt age on hpf pin. leave this pin floating. 54 gnd i signal ground connection. 55 isns o coil current sense output, connec ted to external demodulation circuit. 56 gnd i signal ground connection. ep ep gnd exposed pad. connect to gnd. pin # name type function
P9038 datasheet P9038 august 1, 2016 9 ?2016 integrated device technology, inc. block diagram foreign object detection vbus_sns gate ovp_sel digital ldo2p5v reg_in ldo5v sw1 sw2 bst2 bst1 pgnd1 in pgnd2 scl sda reset epad refgnd hpf isns dp dm ram rom inv5v_in shield1 gpio[6:0] shield2 isnsp_in isnsn_in isns_avg vbus ovp & inrush control vsns_avg mcu adc & telemetry demodulator & communication bias & reference generators gpio usb dpdm i/o i 2 c i/o full bridge inverter en
P9038 datasheet ?2016 integrated device technology, inc. 10 P9038 august 1, 2016 description of the wireless power charging system a wireless charging system is comprised of a base station (transmitter) and a secondary coil (receiver) positioned against each other allowing power to be transferred magnetically. a wpc1 transmitter may be a free-positioning or magnetically-guided type. a free-positioning type of transmitter has an array of co ils that gives limited spatial freedom to the end-user, whereas a magnetically-guided type of transmitter helps the end-user align the receiver to the transmitter with a magnetic attraction. the amount of power transferred to the wireless charging device is controlled by the receiver. the receiver sends communication packets to the transmitter to increase power, decrease power, or maintain the power level. the communication is digital, and communication of 1's and 0's is achieved by the rx modulating the amount of load on the receiver coil. to conserve power, the transmitter places itself in a very-low-power sleep mode unless it detects the presence of a receiver. once a receiver is detected, the transmitter exits sleep mode and begins the power transfer per the wpc specification. input capacitors improper selection of the decoupling c apacitor will degrade the electrical performance of the P9038. the reg_in and in_a to in_d are the supply rails with nominal operating range of 4.5v to 6.9v powering the internal drivers and the full bridge inverter, respectively. at full load, the current through these pins are both high and fast switching. typically, three 10f and one 0.1f ceramic capacitor across the in_a to in_d pins are recommended. similarly, for reg_in, a 1f in parallel with 0. 1f capacitors are sufficient. prior to selecting the capacitor, always examine the capacitor's dc voltage coefficient characteristics as the value of the capacitors will decrease due to capacita nce-to-applied voltage characteristics of the commonly-used ceramic dielectrics. for example, a 22f x7r 6.3v capacitor's value can actually be 6f when operating at 5v, depending on the manufacturer. typically, 10v- or 16v-rated capacitors are required. it is typically best to select these capacitors with a voltage rating from two to tw o and half times the expected applied voltage. for optimum device performanc e, the decoupling capacitors must be mounted on the component side of the pcb, and also, located as physically close as possible to the related power pins and power ground (pgnd). ldo5v & ldo2p5v the ldo5v and ldo2p5v are 5v and 2.5v linear regulators designed to power the internal circuitry. they can support maximum of 10ma and 5ma of load current, respectively. to stabilize the regulators, a 1f capa citor from the output pin to gnd must be connected. the gate pin and associated mosfet shown in figure 2 below provide protection to the P9038 from input over-voltage events and control current inrush . both of these features are described in subsequent sections of this document. figure 2. input voltage support range (uvlo) full-bridge mosfet drive and mosfet current sense the P9038 incorporates an integrated full-bridge inverter. each half-bridge contains a high -side current sense block that is used for control and for peak current protection. for emi reduction purposes, th e switching rising and falling rates of the internal mosfets are controlled. input over-voltage protection and in-rush control the P9038 offers additional protection in the event of input voltage transients and the programmable soft start time to minimize the inrush currents. the P9038 is powered from a vbus input which may be subjecte d to voltages above 5.5v under normal operation. the P9038 is designed to support voltages as high as 27 v on this input. an external ovp mosfet is used to isolate pins that would be damaged by a 27 v transient on the v bus input. the ovp mosfet has a second function: limiting inrush current from the v bus line during startup. this is nece ssary due to the usb inrush specification and the large tota l effective capacitance (~40f) on the reg_in and in pins of the ic. P9038 reg_in c reg_in ldo5v c ldo5v gate vbus_sns adaptor 4.5 v min 25 m ? to inverter idc = 1.5 a 4.5 v - 25 m ? * 1.5 a = 4.46 v 5 ? to ic idc = 45 ma for demonstration purposes only not all connections shown not to scale 4.46 v ? 5 ? * 45 ma = 4.23 v ldo2p5v_in ldo2p5v ldo2p5v uvlo band gap ldo5v inverter & mcu
P9038 datasheet P9038 august 1, 2016 11 ?2016 integrated device technology, inc. the P9038 monitors the vbus_sns pin for over-voltage conditions and shuts off the ovp mosfet to implement over-voltage protection. this ovp threshold can be configured via a single pin as shown in ta b l e 6 . table 6: v bus ovp threshold selection a secondary over voltage protection with a 9.5v threshold is implemented on reg_in for cases where the ovp mosfet is not used. if the reg_in th reshold is exceeded, the P9038 is disabled until the reg_in voltage drops below 8v. demodulation power transfer from the P9038 to a wpc-compliant wireless power receiver, such as p902 5ac-r, is controlled by the receiver. communication packets are superimposed on the power link between the two devices, and are demodulated by the P9038. further information about the wpc communication protocol can be found at the wpc website. communication can be made more robust by running traces from shield1 and shield2 along both sides of the hpf trace. analog-to-digital converter [adc] the adc is the main functional block which the mcu uses for ic operation, including foreig n object detection. the adc also digitizes several internal and external voltages and currents for overall system control and improved demodulation functionality. usb dp/dm functionality the P9038 implements usb d+/d- detection derived from the bcs1.2 specification. this determines whether the usb power source is a standard port (such as from a computer) or a dedicated usb power supply charger port. when a charger port is detected, the P9038 will set its gpio-5 pin to a logic-high state to indicate power is from a charger port. this information may be used for any purpose, but has no direct effect on the actual operation of the P9038. operation of the P9038 follows the commonly accepted practice in wireless charging to draw as much power as the source will allow. a charger port will provide it s rated output, which is usually greater than the normal 500ma limit that could be typically expected from a standard port. foreign object dete ction and input over-current protection the P9038 makes precision measurements of the input voltage and input current, which are sampled by the internal adc and processed in firmware for wpc 1.2.2 foreign object detection [fod] compliance. tw o external pins, isns_avg and vsns_avg, are provided for filtering the input current sense and input voltage sense signals respectively. the input current sense signal is generated differentially from the isnsp_in and isnsn_in pins. this input current sense signal is filtered by an internal 50k ? output resistor combined with an external capacitor on the isns_avg pin. input voltage measurements are also filtered by an internal 33k ? output resistor on the vsns_avg pin combined with an external capacitor on the vsns _avg pin. it is recommended to follow approximately the filter time constants used on the vsns_avg and isns_avg signals as shown in the reference design to insure time alignment of the resulting measurements and accurate power calculation for fod and other purposes. external chip reset and en the P9038 can be ex ternally reset by pulling the reset pin to a logic high (above the v ih level). the reset pin is a dedicate d high-impedance active-high digital input, and its effect is similar to the automatic power-up reset function. because of the internal low voltage monitoring/ reset scheme, the use of the external reset pin is not mandatory. when reset is hi gh, the micro- controller's registers are set to the default configuration. when the reset pin is released to a low, the micro-controller starts loading and executing the firmware from the program memory. if the particular application requires the P9038 to be disabled, this can be accomplished with the en pin. when the en pin is pulled high, the device is shuts off and placed in a very low current condition.when en is connected to logic low, the device will become active, and the micro-controller starts loadi ng and executing the firmware from the program memory. the current into en is approximately equal to: or close to zero if v (en ) is less than 2v. ovp_sel pin connection ovp threshold 220k ? to ground 6.3v grounded 7.15v floating 7.85v i en v en 2 ? 300k ------------------- =
P9038 datasheet ?2016 integrated device technology, inc. 12 P9038 august 1, 2016 system overview for complete details of t he wpc wireless power systems, refer to the wpc specifications and other materials at http://www.wirelesspowerconsortium.com. the P9038 requires a minimum number of external components for proper operation. the provided reference design schematic and bill-of-mat erials component list enable a fully wpc "qi compliant" system . in addition to providing required led indications, this system also provides optional buzzer indications (that could be used with an external piezoelectric buzzer device), and an thermistor over-temperature limit function and optional buzzer indications that are available to drive an external piezeoelectric buzzer device. i 2 c communication the P9038 includes an i 2 c block which can support either i 2 c master or i 2 c slave operation. after power-on-reset (por), the P9038 will initially acts as an i 2 c master for the purpose of downloading firmware from an external memory device, such as an eeprom. the i 2 c master mode on the P9038 does not support multi-master mode, and it is important for system designers to avoid any bus master conflict until the P9038 has finished any firmware uploading and has released control of the bus as i 2 c master. after firmware downloaded from external memory is complete, and when the P9038 begins normal operation, the P9038 is configured by the standard firmware to be exclusively in i 2 c slave mode. for maximum flexibility, the p 9038 tries to co mmunicate with the first address on the eeprom at 300khz. if no acknowledge bit (ack) is received, communication is attempted at the other addre sses at 100khz. if no eeprom is present in the system, t he P9038 will attemp t to execute firmware from its internal rom memory. eeprom the P9038 evk supports an ex ternal eeprom memory chip, pre-programmed with a standard operating firmware that is automatically loaded when 5v power is applied. the P9038 uses i 2 c master address 0x52 to access the eeprom. the P9038 slave address is 0x39. if the standard firmware is not suitable for the application, custom eeprom or internal factory programmed rom configurations are possible. please contact idt sales for more information regarding non-standard solution options. overview of sta ndard gpio usage there are 7 gpio's on the P9038 transmitter ic. all gpios are configured as inputs during the power-on startup process. firmware will then reconf igure the gpio as follows: ? gpio-0: this pin is not used in the standard firmware and is configured as active-low output during normal operation. ? gpio-1: this pin is used to dynamically manage the optimum configuration of the external communication demodulation circuit. ? gpio-2: this pin is connected to an external thermistor circuit which is used by P9038 to determine an external over-temperature condition ? gpio-3: during power-on, this pin is sampled by the internal adc to determine the re sistor option setting for the led mode. in normal operation, this pin is configured as an output to drive the green led indication functions (see table 10). ? gpio-4: during power-on, this pin is sampled by the internal adc to determine the resistor option setting for adjusting the fod offset value. in normal operation, this pin is configured as an output to drive the optional external piezoelectric buzzer function. ? gpio-5: this pin is configured as an output to indicate the result of the usb d+/d- port type detection. if the usb port type is a charger port, t hen the output will be set to active-high. otherwise, the ou tput is set to active-low ? gpio-6: this pin is configured as an output to drive the red led functions (see ta b l e 7 ). ta b l e 7 lists how the red and green leds can be used to display information about the P9038's operating modes. this table also specifies how to co nfigure the gpio-3 optioning resistors to select the desired led mode.
P9038 datasheet P9038 august 1, 2016 13 ?2016 integrated device technology, inc. led functions depending upon the selected led mode, one or two leds indicate the various functional st ates of the system including possible fault conditions. bo th single-led and dual-led indications are fully compliant with wpc requirements. table 7 shows the various indications of all of the supported led modes. as shown in figure 3 one or two resistors configure the desired led option combinations in accordance with the values in table 7 . the dc voltage set in this way is measured one time during power-on to determine the led configuration. to avoid inaccuracy of the resistor setting caused by the led, the useful dc voltage range for all options except the highest value must be limited to not greater than 1vdc. figure 3. P9038 led resistor optioning table 7: P9038 led resistor optioning 1,2 idtP9038 to adc ra rb ldo2p5v_out gpio3 resistor to set options led mode resistor configuration standby transfer complete low-power fault led1- green on blink 1hz on blink 2hz off led2- red on off off off blink 4hz led1- green on on off blink 2hz off led2- red on off off off blink 4hz led1- green off blink 1hz on blink 2hz blink 4hz led2- n/a - - - - - led1- green off on off blink 2hz blink 4hz led2- n/a - - - - - led1- green off on off blink 2hz off led2- red off off off off blink 4hz led1- green off off on off off led2- red off on off blink 2hz blink 4hz led1- green led2- red led1- green led2- red led1- green led2- red led1- green off blink 1hz on blink 2hz off led2- red off off off off blink 4hz note 1 - voltage div ider on gpio3 should use 1% resistors w ith parallel impedance approx imately 20k-50k. "low pow er" is indicated in usb pow ered applications w hen usb does not prov ide sufficient dc pow er "low pow er" blink is approx imately 80% on-time note 2 - led select v oltage should be w ithin 3% of listed v alue. 9 pull up >=1.500v pull down <=0.080v 10 1 0.370v 0.510v 0.660v 0.220v dual led, standby - off red indicate, no-blink dual-led, standby - off blink dual-led, standby - on blink 3 4 5 2 7 6 8 single-led, standby off blink single-led, standby off no blink dual led, standby - off no-blink reserved reserved 1.000v 0.810v 1.100v 1.250v reserved led control option led select gpio3 voltage description led #/ color operational status dual led, standby - on no-blink
P9038 datasheet ?2016 integrated device technology, inc. 14 P9038 august 1, 2016 buzzer function an optional buzzer feature is supported on gpio4 which is able to drive directly a piezoe lectric type transducer without amplification. as shown on the reference schematic, a series current limiting resistor should be included if a buzzer device is included. the buzzer signal is approximately a 2khz square wave, and it is recommended to use a buzzer with a 2khz resonant frequency for best results. buzzer action: power transfer indication the P9038 supports audible notification when the device operation successfully reaches the power transfer state. the duration of the power transfer indication sound is approximately 200ms. buzzer action: charge complete indication the P9038 supports audible not ification when the receiver sends a "charge complete" during the power transfer state. if "charge complete" is sent as the very first packet before being in the power transfer state, there is no buzzer indication for this case. the duration of the ?charge complete? indication sound is approximately 200ms. wpc tx-a5 and a11 coils the P9038 sw output pins are connected to a series-resonance circuit comprised of a wpc type-a5 or a11 coil and a series resonant capacitor, as shown on the reference design schematic. the coil serves as the primary winding in a loosely-coupled transformer, the secondary of which is the coil connected to the power receiver the power transmitter coil is mounted on a ferrite shield per the wpc specifications. either a ground plane or grounded copper shielding can be added beneath the ferrite shield for a reduction in radiated electrical field emissions. the coil ground plane should be connected to the P9038 ground plane by a single trace. resonance capacitors the resonance capacitors must be c0g type dielectric and have a dc rating of at least 50v. the highest-efficiency combination is four 100nf in parallel to achieve the lowest esr. pcb layout considerations for optimum device performanc e and lowest output phase noise, idt recommends that cu stomers copy the reference layout used in the p90 38-r-evk reference kit. more information and layout files can be found at: http://www.idt.com/P9038-r-evk . additional layout guidelines can be found in application note, an-894 P9038 layout guidelines . users are encouraged to read this document prior to starting a board design. thermal overload protection the P9038 integrates thermal overload shutdown circuitry to prevent damage resulting from e xcessive thermal stress that may be encountered u nder fault conditions . this circuitry will shut down and reset the P9038 if the die temperature exceeds 140c. to enable the best perf ormance, it is important to ensure that the heat generated by the P9038 is dissipated into the pcb and then carried away into the environment. the package exposed pad must be soldered to the pcb, with multiple vias evenly distributed under the exposed pad and exiting the bottom side of the pc b. this improves heat flow away from the package and minimizes package thermal gradients. special notes 56-vfqfpn package assembly note 1 : unopened dry packaged parts have a one year shelf life. note 2 : the hic indicator card for newly opened dry packaged parts should be checked. if there is any moisture content, the parts must be bak ed for minimum of 8 hours at 125c within 24 hours of the assembly re-flow process.
P9038 datasheet P9038 august 1, 2016 15 ?2016 integrated device technology, inc. reference schematic (P9038-r-evk) the reference schematic bill-of-materials can be found in the P9038-r- evk reference bo ard manual. 5 5 4 4 3 3 2 2 1 1 d d c c b b a a leda ledb integrated device technology, inc. this document contains information proprietary to integrated device technology, inc. (idt). use or disclosure without the written permission of an officer of idt is expressly forbidden do not modify the voltage specification of capacitors: c13,c18,c17,c15,c19,c20,c29,c30 P9038-r-evk v1.1 optional fod tuning resistors tx coil scl wp sda isns ldo5v ldo2p5v gpio0 gpio5 gpio4 gpio2 gpio3 reset title size document number r e v date: sheet of 305-pd-15-0260 1 P9038-r-evk v1.1 b 22 wednesday, july 15, 2015 title size document number r e v date: sheet of 305-pd-15-0260 1 P9038-r-evk v1.1 b 22 wednesday, july 15, 2015 title size document number r e v date: sheet of 305-pd-15-0260 1 P9038-r-evk v1.1 b 22 wednesday, july 15, 2015 vin io6 r21 47k r9 10k r15 47k r5 33 r1 10m r7 47k 5% c25 6.8nf c11 6.8nf io5 c27 0.1uf r11 15k io4 c31 0.1uf c24 1uf 0402 u1 P9038 sw2_b 31 pgnd2_a 26 sw2_d 33 sw2_c 32 gpio4 5 in_a 34 in_b 35 gpio6 3 nc 2 gpio5 4 gpio1 8 gpio0 9 dp 12 pgnd2_d 29 sw2_a 30 pgnd2_b 27 scl 10 gpio3 6 sda 11 gpio2 7 pgnd2_c 28 pgnd1_a 42 bst2 25 in_c 36 in_d 37 sw1_a 38 sw1_b 39 sw1_c 40 dm 13 reset 14 vbus_sns 15 en 16 refgnd 17 reg_in 18 ldo5v 19 ldo2p5v 20 ldo2p5v_in 21 inv5v_in 22 ovp_sel 23 vsns_avg 24 bst1 46 pgnd1_d 45 pgnd1_c 44 sw1_d 41 pgnd1_b 43 gate 47 isns_avg 48 isnsn_in 49 gnd_a 1 isnsp_in 50 shield1 51 hpf 52 shield2 53 gnd_c 54 isns 55 gnd_b 56 epad 57 c26 1uf 0402 c4 6.8nf c12 3.3nf c1 6.8nf c10 0.1uf r18 np r27 0 c22 1uf r23 4.7k r4 22 c2 6.8nf r20 np c20 100nf 1206 50v gnd q6 fdc8878 1 2 3 6 5 4 r17 1.5k r8 33 gnd1 c30 100nf 1206 50v r26 0 ther 1 2 /en io3 u3 24aa64t-i/mny vss 4 a2 3 a0 1 a1 2 vcc 8 wp 7 scl 6 sda 5 epad 9 c5 0.1uf r24 4.7k wp c13 10uf io0 c14 22nf c18 0.1uf ldo5v d6 cdsu400b 0603 d3 green c29 100nf 1206 50v r22 47k c15 10uf r10 10k r12 4.7k c3 6.8nf l1 6.5uh r25 10k c28 22nf io2 c16 3.3nf c9 3.3nf r3 22 c6 1nf c23 0.1uf c17 10uf hpfc c8 1nf r2 0.01 c21 0.1uf r6 10m sld sld vcc d- d+ id gnd j4 usb_micro_ab 1 2 3 4 5 6 7 8 9 10 11 c19 100nf 1206 50v c7 22nf scl r13 47k d1 red sda r16 np r14 4.7k reset r19 10k
P9038 datasheet ?2016 integrated device technology, inc. 16 P9038 august 1, 2016 package outline and package dimensions (ndg56) ? use epad option p3
P9038 datasheet P9038 august 1, 2016 17 ?2016 integrated device technology, inc. package outline and package dimensions (ndg56), cont. u se epad 5.50mm sq.
disclaimer integrated device technology, inc. (idt) and its subsidiaries reserve the right to modify the products and/or specifications d escribed herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is subject to change without notice. performance spe cifications and the operating parameters of the described products are determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information co ntained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limi ted to, the suitab ility of idt?s products for any particular purpose, an implied war ranty of merchantability, or non-infringement of the intellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property rights of idt or any third pa rties. idt?s products are not intended for use in applications involvin g extreme environmental conditions or in life support systems o r similar devices where the failure or malfun ction of an idt product can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their o wn risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. product specification subject to change wi thout notice. other trademarks and service marks used herein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright ?2016 integrated device technology, inc.. all rights reserved. corporate headquarters 6024 silver creek valley road san jose, ca 95138 usa sales 1-800-345-7015 or 408-284-8200 fax: 408-284-2775 www.idt.com tech support technical support request form ordering information revision history part/order number marking package shipping packaging ambient temperature P9038-rndgi P9038-rndgi 7 x 7 mm 56-vfqfpn tray -40 to +85c P9038-rndgi8 P9038-rndgi 7 x 7 mm 56-vfqfpn tape and reel -40 to +85c date description of change august 1, 2016 updated compatibilit y from wpc-1.1.2 to wpc-1.2.2. august 19, 2015 initial release.

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