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the a1162 is a unipolar hall-effect switch with an externally enabled diagnostic function and user-programmable switchpoints. on-chip electromagnetic coils are used to implement self-test of the sensors entire magnetic and electrical signal chain. it is designed for systems where precise magnet switchpoints and safety, reliability, or both, are critical, such as those designed to meet the requirements of iso 26262. in normal operating mode, the a1162 functions as a standard unipolar hall-effect switch. the device output transistor turns on (output signal switches low) in the presence of sufficient magnetic field (>b op max). the output transistor of the a1162 switches off (output signal switches high) when the magnetic field is removed ( 2 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com absolute maximum ratings characteristic symbol notes rating unit forward supply voltage v cc 30 v reverse supply voltage v rcc C18 v forward diagnostic enable voltage v diag 6.5 v reverse diagnostic enable voltage v rdiag C0.5 v output off voltage v out 30 v continuous output current i out 25 ma reverse output current i outr 50 ma operating ambient temperature t a range l C40 to 150 c maximum junction temperature t j(max) 165 c storage temperature t stg C65 to 170 c rohs compliant specifications terminal list table pin # symbol description 1 nc/gnd connected to ground internally. may be left floating or connected to ground. 2 vout output from circuit 3 gnd ground 4 gnd ground 5 vcc connects power supply to chip 6 diag diagnostic enable 7 nc/gnd connected to ground internally. may be left floating or connected to ground. 8 nc/gnd connected to ground internally. may be left floating or connected to ground. nc/gnd vout gnd nc/gnd nc/gnd diag gnd vcc 1 2 3 4 5 6 7 8 package le, 8-pin etssop pinouts description (continued) with supply voltages of 3.8 to 24 v. it is temperature-stable and stress-resistant, making it especially suited for operation over temperature ranges up to 150oc (l temperature range). superior high-temperature performance is made possible through advanced dynamic offset cancellation techniques, which reduce the residual offset voltage normally caused by device overmolding, temperature dependencies, and thermal stress. the a1162 is a quality managed (qm) product that has been developed according to the automotive quality requirements of ts 16949 and contains features targeted for automotive safety applications. this product can be qualified for use in accordance with iso 26262 in compliant safety systems by ensuring a robust integration of the component into the system design. safety documentation will be provided to support and guide the integration process. selection guide part number packing package temperature range, t a (oc) output in south polarity field magnetic operate point, b op (g) A1162LLETR-00-T 4000 pieces / reel 8-pin tssop C40 to 150 low programmable programmable precision hall-effect switch with advanced diagnostics a1162
3 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. 1 max. unit electrical characteristics supply voltage v cc operating, t j < 165c 3.8 C 24 v output leakage current i outoff v out = 24 v, b < b rp C C 10 a output saturation voltage v out(sat) i out = 20 ma, b > b op C 185 400 mv output current limit i om b > b op 30 C 60 ma power-on time 2 t on v cc > 3.8 v, b < b rpmin C 10 g, b > b opmax + 10 g C C 25 s chopping frequency f c C 400 C khz output rise time 2,3 t r r load = 820 ?, c l = 20 pf C 0.2 2 s output fall time 2,3 t f r load = 820 ?, c l = 20 pf C 0.1 2 s supply current i cc(on) b > b op C C 5 ma i cc(off) b < b rp C C 5 ma i cc(diag) diag = 1, t j < t j(max) C 16 25 ma reverse-battery current i rcc v rcc = C18 v C C C10 ma supply zener clamp voltage v zsup i cc = 8 ma, t a = 25c 30 C C v output zener voltage v zout i out = 3 ma, t a = 25c 28 C C v diagnostic characteristics pwm carrier frequency f pwmout with diagnostic mode enabled C 3 C khz duty cycle (diagnostic mode) 4 dc fail diag = 1, device malfunction C 0 40 % dc fail diag = 1, device malfunction 60 100 C % dc pass diag = 1, device normal 40 50 60 % diag pin input resistance r diag diag pin pulled low C 1 C m diag pin input low voltage threshold v il device in normal mode C C 0.6 v diag pin input high voltage threshold v ih device in diagnostic mode 1.5 C 5 v diagnostic time t d the diagnostics feature should be enabled for at least t d in order to obtain an accurate pwm signal. 1 C C ms diagnostic disable time t dis time from when diag pin is released (high to low transition) to valid device output C C 25 s operating characteristics : valid over full operating voltage and ambient temperature ranges, unless otherwise specified continued on next page... 1 typical data is at t a = 25oc and v cc = 12 v and it is for design information only. 2 power-on time, rise time and fall time are guaranteed through device characterization and not final test. 3 c l = oscilloscope probe capacitance. 4 when the dut passes the diagnostic tests, the output will be a 50% duty cycle signal. any other output indicates the dut failed the test. please see the application notes for more information. programmable precision hall-effect switch with advanced diagnostics a1162
4 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristics symbol test conditions min. typ. 1 max. unit magnetic characteristics 5 magnetic step size b op programming step size C 5 C g operate point b op programmable b rpmin + b hys C 250 g release point b rp programmable C5 C b opmax C b hys g hysteresis (b op C b rp ) b hys00 b hys register = 00 5 C 30 g b hys01 b hys register = 01 7 C 40 g b hys10 b hys register = 10 10 C 60 g b hys11 b hys register = 11 15 C 65 g maximum external field in diagnostic mode 6 b ext(diag) 800 10,000 C g drift detection threshold operate point drift b op(drift) programmable 0.25 b op C 1.75 b op g release point drift b rp(drift) programmable 0.25 b rp C 1.75 b rp g operating characteristics (continued) : valid over full operating voltage and ambient temperature ranges, unless otherwise specified 1 typical data is at t a = 25oc and v cc = 12 and it is for design information only 5 magnetic flux density (b) is indicated as a negative value for north-polarity magnetic fields, and is a positive value for south-polarity magnetic fields. 6 800 g is the maximum test capability due to practical equipment limitations. design simulations show that a 10,000 g external field will not adversely affect the sensor in diagnostic mode. programmable precision hall-effect switch with advanced diagnostics a1162
5 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com thermal characteristics: may require derating at maximum conditions; see application information characteristic symbol test conditions* value unit package thermal resistance r ja on 4-layer pcb based on jedec standard jesd51-7 145 oc/w *additional thermal information available on the allegro website 20 40 60 80 100 120 140 160 180 te mperature,t (c) a power dissipation, p (mw) d 0 300 400 200 100 600 500 800 700 900 1000 powerd issipation versus ambient te mperature (r = 145 oc/w) ja maximum power dissipation vs. ambient temperature programmable precision hall-effect switch with advanced diagnostics a1162
6 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com characteristic performance 8 10 12 14 16 18 20 22 24 26 -50 0 50 100 150 supply current, i cc(diag) (ma) ambient temperature, t a (c) i cc(diag) vs. t a 3.8 v 12 v 24 v v cc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 0 50 100 150 supply current, i cc(off) (ma) ambient temperature, t a (c) i cc(off) vs. t a 3.8 v 12 v 24 v v cc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 supply current, i cc(off) (ma) supply voltage, v cc (v) i cc(off) vs. v cc -40oc 25oc 150oc t a 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 -50 0 50 100 150 supply current, i cc(on) (ma) ambient temperature, t a (c) i cc(on) vs. t a 3.8 v 12 v 24 v v cc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 supply current, i cc(on) (ma) supply voltage, v cc (v) i cc(on) vs. v cc -40oc 25oc 150oc t a 8 10 12 14 16 18 20 22 24 26 0 5 10 15 20 25 supply current, i cc(diag) (ma) supply voltage, v cc (v) i cc(diag) vs. v cc -40oc 25oc 150oc t a programmable precision hall-effect switch with advanced diagnostics a1162
7 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0 50 100 150 200 250 300 350 400 -50 0 50 100 150 output satura t on voltage, v out(sat) (mv) ambient temperature, t a (c) v out(sat) vs. t a 3.8 v 12 v 24 v v cc 0 50 100 150 200 250 300 350 400 0 5 10 15 20 25 output satura t on voltage, v out(sat) (mv) supply voltage, v cc (v) v out(sat) vs. v cc -40oc 25oc 150oc t a 40 42 44 46 48 50 52 54 56 58 60 0 5 10 15 20 25 duty cycle, dc pass (%) supply voltage, v cc (v) dc pass vs. v cc 25oc t a 40 42 44 46 48 50 52 54 56 58 60 -50 0 50 100 150 duty cycle, dc pass (%) ambient temperature, t a (c) dc pass vs. t a 3.8 v v cc 0 1 2 3 4 5 6 -50 0 50 100 150 pwm carrier frequency, f pwmout (khz) ambient temperature, t a (c) f pwmout vs. t a 3.8 v 12 v 24 v v cc 0 1 2 3 4 5 6 0 5 10 15 20 25 pwm carrier frequency, f pwmout (khz) supply voltage, v cc (v) f pwmout vs. v cc -40oc 25oc 150oc t a programmable precision hall-effect switch with advanced diagnostics a1162
8 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com -15 -10 -5 0 5 10 -50 0 50 100 150 magne t c operate point, b op(init) (g) ambient temperature, t a (c) b op(init) vs. t a 3.8 v 12 v 24 v v cc -15 -10 -5 0 5 10 0 5 10 15 20 25 magne t c operate point, b op(init) (g) supply voltage, v cc (v) b op(init) vs. v cc -40oc 25oc 150oc t a -25 -20 -15 -10 -5 0 -50 0 50 100 150 magne t c release point, b rp(init) (g) ambient temperature, t a (c) b rp(init) vs. t a 3.8 v 12 v 24 v v cc -25 -20 -15 -10 -5 0 0 5 10 15 20 25 magne t c release point, b rp(init) (g) supply voltage, v cc (v) b rp(init) vs. v cc -40oc 25oc 150oc t a 0 5 10 15 20 25 30 -50 0 50 100 150 magne t c hysteresis, b hys(init) (g) ambient temperature, t a (c) b hys(init) vs. t a 3.8 v 12 v 24 v v cc 0 5 10 15 20 25 30 0 5 10 15 20 25 magne t c release point, b hys(init) (g) supply voltage, v cc (v) b hys(init) vs. v cc -40oc 25oc 150oc t a programmable precision hall-effect switch with advanced diagnostics a1162
9 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com 0 1 2 3 4 5 6 7 8 9 10 -50 0 50 100 150 magne t c step size (g) ambient temperature, t a (c) b op programming step size vs. t a 5 15 25 35 45 55 65 -50 0 50 100 150 hysteresis, b hys (g) ambient temperature, t a (c) b hys vs. t a bhys00 bhys01 bhys10 bhys11 -20 0 20 40 60 80 100 120 140 160 180 0 4 8 12 16 20 24 28 32 36 magne t c operate point, b op(avg) (g) code b op(avg) vs. code bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 b op(init) 0 20 40 60 80 100 120 140 160 -50 0 50 100 150 magne t c operate point, b op (g) ambient temperature, t a (c) b op bit weight vs. t a bit0 bit1 bit2 bit3 bit4 bit5 programmable precision hall-effect switch with advanced diagnostics a1162
10 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com functional description operation the output of these devices switches low (turns on) when a mag- netic field perpendicular to the hall sensor exceeds the operate point threshold, b op (see figure 1). after turn-on, the output is capable of sinking 25 ma and the output voltage is v out(sat) . when the magnetic field is reduced below the release point (b rp ) the device output goes high (turns off). the difference in the magnetic operate and release points is the hysteresis (b hys ) of the device. this built-in hysteresis allows clean switching of the output, even in the presence of external mechanical vibration and electrical noise. powering-on the device in the hysteresis range, less than b op and higher than b rp , results in a high output state. the correct state is attained after the first excursion beyond b op or b rp . the output will not switch until there is a valid transition beyond b op or b rp . power-on sequence and timing the output states are only valid when the supply voltage is within the specified operating range (v cc(min) v cc v cc(max) ) and the power-on time has elapsed (t > t on ). refer to figure 2 for an illustration of the power-on sequence. once the supply voltage is within the operational range, the output will be in the low state (power-on state), irrespective of the magnetic field. the output will remain low until the sensor is fully powered on (t > t on ), at which point, the output will respond to the corresponding magnetic field presented to the sensor. v+ 0 0 b+ v cc v out(sat) b hys v out switch to low switch to high b rp b op figure 1: switching behavior of unipolar switches on the horizontal axis, the b+ direction indicates increasing south polarity magnetic field strength. output responds according to magnetic field input b > b op or b < b rp t > t on(max) v time time v v out(off) v cc(min) t on 0 0 v cc output undefined for v cc < v cc(min) v out(on) figure 2: power-on sequence and timing programmable precision hall-effect switch with advanced diagnostics a1162
11 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com diagnostic mode of operation the diagnostic mode is accessed by applying a voltage higher than v ih on the diagnostic enable pin. the diagnostic mode uses an internally generated magnetic signal to exercise the signal path. this signal is compared to two reference signals in the schmitt trigger block (refer to figure 3). if the diagnostic signal is between the two reference signals, the part is considered to be working within specifications and a 50% pwm signal is set at the output pin, as shown in figure 3. if the diagnostic signal is above the upper reference or below the lower reference, the output is set at a fixed value (high/low). the diagnostic mode of operation not only detects catastrophic failures but also drifts in the magnetic switchpoints. if b op or b rp drift to values below or above the values stated in the drift detection threshold table, the output is set at a fixed value when in the diagnostic mode of operation. diag diag v out device ok duty cycle = 50% device failure duty cycle 50% figure 3: diagnostic functional diagram when the device passes, there will be a 50% duty-cycle signal sent out. in the event of a failure, the output will typically be forced either high or low. diagnostic mode is only active when diag is pulled high. programmable precision hall-effect switch with advanced diagnostics a1162
12 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com v+ c l optional c bypass v cc gnd diag gnd r l output a1162 v out from controller 0.1 f figure 4: typical application circuit applications it is strongly recommended that an external capacitor be con- nected (in close proximity to the hall sensor) between the supply and ground of the device to reduce both external noise and noise generated by the chopper stabilization technique. as shown in figure 4, a 0.1 f capacitor is typical. note that pins 3 and 4 are the primary ground return for all sensor functions. these pins should be connected together close to the ic. pins 1, 7, and 8 are connected to ground internally, but these pins may be connected to ground or left floating. they must not be connected to vcc or any other signal. extensive applications information on magnets and hall-effect sensors is available in: ? hall-effect ic applications guide, an27701 ? soldering methods for allegros products C smt and through-hole, an26009 ? guideline for designing subassemblies using hall-effect devices, an27703.1 ? asek-02 allegro sensor evaluation kit technical guide all are provided on the allegro website: www.allegromicro.com programmable precision hall-effect switch with advanced diagnostics a1162
13 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com overview programming is accomplished by sending a series of input volt- age pulses serially through the vcc (supply) pin of the device. a unique combination of different voltage level pulses controls the internal programming logic of the device to select a desired programmable parameter and change its value. there are three voltage levels that must be taken into account when program- ming. these levels are referred to as high (v ph ), mid (v pm ), and low (v pl ). the a1162 features three programmable modes, try mode, blow mode, and read mode: ? in try mode, programmable parameter values are set and measured simultaneously. a parameter value is stored temporarily, and is reset after cycling the supply voltage. ? in blow mode, the value of a programmable parameter may be permanently set by blowing solid-state fuses internal to the device. device-locking is also accomplished in this mode. ? in read mode, each bit may be verified as blown or not blown. the programming sequence is designed to help prevent the device from being programmed accidentallyfor example, as a result of noise on the supply line. note that, for all programming modes, no parameter programming registers are accessible after the device- level lock bit is set. the only function that remains accessible is the overall fuse checking feature. although any programmable variable power supply can be used to generate the pulse waveforms, for design evaluations, allegro highly recommends using the asek-02 allegro sensor ic evalu - ation kit. the asek-02 kit provides a graphical user interface (gui) for programming various allegro field-programmable hall-effect devices. in addition, a low-voltage interface board (asek-02-wb-t) is requiredcontact your local fae regarding availability. the asek-02 kit is intended for use as a benchtop engineering tool, for learning about, evaluating, and characterizing allegro sensors, for programming/calibrating devices in small volumes, and for developing code and procedures for use in production. note that this kit is not recommended for production purposes. see the allegro sensor evaluation kit technical guide (asek-02) available at http://www.allegromicro.com/en/sample-and-buy/ demo-boards/asek-02-demo-board.aspx for more details. con- tact your local allegro fae regarding availability or purchase the kit from digi-key (part number 620-1625-nd). programming guidelines table 1: programming pulse requirements, protocol at t a = 25c characteristics symbol notes min. typ. max. unit programming voltage v pl measured at the vcc pin 4.5 5 5.5 v v pm 12.5 C 14 v v ph 21 C 27 v programming current i pp v cc = 5 26 v, c blow = 0.1 f (min); minimum supply current required to ensure proper fuse blowing. 175 C C ma pulse width t low duration of v pl separating pulses at v pm or v ph 20 C C s t active duration of pulses at v pm or v ph for key/code selection 20 C C s t blow duration of pulse at v ph for fuse blowing 90 100 C s pulse rise time t pr v pl to v pm or v pl to v ph 5 C 100 s pulse fall time t pf v pm to v pl or v ph to v pl 5 C 100 s blow pulse slew rate sr blow 0.375 C C v/s figure 5: programming pulse definitions (see table 1) supply voltage, v cc gnd (supply cycled) programming pulses blow pulse t active t low t low t blow t pr t pf v ph v pm v pl programmable precision hall-effect switch with advanced diagnostics a1162
14 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com definition of terms register the section of the programming logic that controls the choice of programmable modes and parameters. bit field the internal fuses unique to each register, represented as a binary number. changing the bit field settings of a particular register causes its programmable parameter to change, based on the internal programming logic. key a series of voltage pulses used to select a register or mode code the number used to identify the combination of fuses activated in a bit field, expressed as the decimal equivalent of the binary value. the lsb of a bit field is denoted as code 1, or bit 0. addressing increasing the bit field code of a selected register by serially applying a pulse train through the vcc pin of the device. each parameter can be measured during the addressing process, but the internal fuses must be blown before the program- ming code (and parameter value) becomes permanent. fuse blowing applying a high-voltage pulse of sufficient duration to permanently set an addressed bit by blowing a fuse internal to the device. once a bit (fuse) has been blown, it cannot be reset. blow pulse a high-voltage pulse of sufficient duration to blow the addressed fuse. cycling the supply powering-down, and then powering-up the supply voltage. cycling the supply is used to clear the program- ming settings in try mode. programming procedure programming involves selection of a register and mode, and then setting values for parameters in the register for evaluation or fuse blowing. figure 10 provides an overview state diagram. register selection each programmable parameter can be accessed through a specific register. to select a register, from the initial state, a sequence of voltage pulses consisting of one v ph pulse, one v pm pulse, and then a unique combination of v ph and v pm pulses, is applied serially to the vcc pin (with no v cc supply interruptions). this sequence of pulses is called the key, and uniquely identifies each register. an example register selection key is shown in figure 6. to simplify try mode, the a1162 provides a set of virtual reg- isters for each combination of: b op selection (bopsel), b hys selection, and a facility for transiting b op magnitude values in an increasing or decreasing sequence. these registers also allow wrapping back to the beginning of the register after transiting the register. mode selection the same physical registers are used for all programming modes. to distinguish blow mode and read mode, when selecting the registers, an additional pulse sequence consisting of eleven v pm pulses followed by one v ph pulse is added to the key. the com- bined register and mode keys are shown in table 3. try mode in try mode, the bit field addressing is accomplished by apply- ing a series of v pm pulses to the vcc pin of the device, as shown in figure 7. each pulse increases the total bit field value of the selected parameter, increasing by one on the falling edge of each additional v pm pulse. when addressing a bit field in try mode, the number of v pm pulses is represented by a decimal number called a code . addressing activates the corresponding fuse loca- tions in the given bit field by increasing the binary value of an internal dac, up to the maximum possible code. as the value of the bit field code increases, the value of the programmable parameter changes. measurements can be taken after each v pm pulse to determine if the desired result for the programmable parameter has been reached. cycling the supply voltage resets all the locations in the bit field that have un-blown fuses to their initial states. this should also be done before selection of a differ- ent register in try mode. when addressing a parameter in try mode, the bit field address (code) defaults to the value 1, on the falling edge of the final reg- ister selection key v ph pulse (see figure 5). a complete example is shown in figure 8. note that, in the four b op selection virtual registers, after the maximum code is entered, the next vpm pulse wraps back to the beginning of the register, and selects code 0. figure 6: example of try mode register selection pulses, for the b op negative trim, up-counting register. figure 7: try mode bit field addressing pulses. v ph v pm v pl gnd v cc v ph v pm v pl gnd v cc code 2 code 1 code 3 code 2 n ?2 code 2 n ?1 programmable precision hall-effect switch with advanced diagnostics a1162
15 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the b op selecting virtual register allows the programmer to adjust the b op parameter from low to high, or from high to low. figure 9 shows the relationship between the b op parameter and the different try mode registers. blow mode after the required code is determined for a given parameter, its value can be set permanently by blowing individual fuses in the appropriate register bit field. blowing is accomplished by select- ing the register and mode selection key, followed by the appro- priate bit field address, and ending the sequence with a blow pulse. the blow mode selection key is a sequence of eleven v pm pulses followed by one v ph pulse. the blow pulse consists of a v ph pulse of sufficient duration (t blow ) to permanently set an addressed bit by blowing a fuse internal to the device. the device power must be cycled after each individual fuse is blown. due to power requirements, a 0.1 f blowing capacitor (c blow ) must be mounted between the vcc pin and the gnd pin dur- ing programming, to ensure enough current is available to blow fuses. if programming in the application, c bypass (see figure 1) can serve the same purpose. the fuse for each bit in the bit field must be blown individually. the a1162 built-in circuitry allows only one fuse at a time to be blown. during blow mode, the bit field can be considered a one- hot shift register. table 2 illustrates how to relate the number of v pm pulses to the binary and decimal value for blow mode bit field addressing. it should be noted that the simple relationship between the number of v pm pulses and the required code is: 2 n = code, where n is the number of v pm pulses, and the bit field has an ini- tial state of decimal code 1 (binary 00000001). to correctly blow the required fuses, the code representing the required parameter value must be translated to a binary number. for example, as shown in figure 9, decimal code 5 is equivalent to the binary number 101. therefore bit 2 must be addressed and blown, the device power supply cycled, and then bit 0 must be addressed and blown. the order of blowing bits, however, is not impor- tant. blowing bit 0 first, and then bit 2 is acceptable. a complete example is shown in figure 10. table 2: blow mode bit field addressing quantity of v pm pulses binary register bit field decimal equivalent code 0 0000 0001 1 1 0000 0010 2 2 0000 0100 4 3 0000 1000 8 4 0001 0000 16 5 0010 0000 32 6 0100 0000 64 (decimal equivalent) code 5 bit field selection address code format code in binary fuse blowing target bits fuse blowing address code format (binary) 1 0 1 bit 2 bit 0 code 4 code 1 (decimal equivalents) figure 8: example of try mode programming pulses applied to the vcc pin in this example, b op trim, down-counting register is addressed to code 12 by the eleven v pm pulses (code 1 is selected automatically at the falling edge of the register-mode selection key). v ph v pm v pl gnd register (and mode) selection key bit field address codes 1 2 3 4 1 2 3 4 5 6 7 8 9 10 11 v cc code 7 code 8 code 9 code 10 code 11 code 12 code 4 code 5 code 6 code 1 code 2 code 3 figure 9: example of code 5 broken into its binary components programmable precision hall-effect switch with advanced diagnostics a1162
16 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com note: after blowing, the programming is not reversible, even after cycling the supply power. although a register bit field fuse cannot be reset after it is blown, additional bits within the same register can be blown at any time until the device is locked. for example, if bit 1 (binary 10) has been blown, it is still possible to blow bit 0. the end result would be binary 11 (decimal code 3). locking the device after the required code for each parameter is programmed, the device can be locked to prevent further programming of any parameters. to do so, perform the following steps: 1. ensure that the c blow capacitor is mounted. 2. select the output/lock bit register key . 3. select blow mode selection key . 4. address bit 4 (10000) by sending four v pm pulses. figure 10: example of blow mode programming pulses applied to the vcc pin in this example, the b op magnitude selection register (bopsel) is addressed to code 8 (bit 3, or 3 v pm pulses) and its value is permanently blown. v ph v pm v pl gnd register (and mode) selection key bit field (fuse) address codes 1 2 3 4 5 6 7 1 2 3 8 9 10 11 v cc bit 1 bit 2 bit 3 blow pulse t low code 8 5. send one blow pulse, at i pp and sr blow , and sustain it for t blow . 6. delay for a t low interval, then power-down. 7. optionally check all fuses. fuse checking incorporated in the a1162 is circuitry to simultaneously check the integrity of the fuse bits. the fuse-checking feature is enabled by using the fuse checking registers, and while in try mode, applying the codes shown in table 3. the register is only valid in try mode and is available before or after the programming lock bit is set. selecting the fuse threshold high register checks that all blown fuses are properly blown. selecting the fuse threshold low register checks all un-blown fuses are properly intact. the supply current (i cc ) increases by 250 a if a marginal fuse is detected. if all fuses are correctly blown or fully intact, there will be no change in supply current. programmable precision hall-effect switch with advanced diagnostics a1162
17 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com table 3: programming logic table register name (selection key) bit field address (code) notes binary (msb lsb) decimal equivalent try mode register selection: any vpm pulse after the register selection sequence will move the counter and change the selected register code b op trim up-counting [2 v ph ] 000000 111111 0 63 increases b op . code 1 automatically selected when register entered; wraps back to code 0. b op trim down-counting [2 v ph 4 v pm v ph] 111111 000000 63 0 decreases b op . code 63 automatically selected when register entered; wraps back to code 0. b op trim up-counting, bit wise [2 v ph 9 v pm v ph ] 000000 000001 000010 000100 001000 010000 100000 0 1 2 4 8 16 32 bit 1 automatically selected when register entered. b hys trim [v ph 3 v pm v ph ] 00 11 0 3 code 1 automatically selected when register entered. parity bit [v ph v pm v ph ] 0 0 code 1 automatically selected when register entered. fuse threshold low [v ph 3 v pm v ph 7 v pm ] checks un-blown fuses. fuse threshold high [v ph 3 v pm v ph 8 v pm ] checks blown fuses. blow mode register selection b op selection [2 v ph 11 v pm v ph (n) v pm v ph_blow ] 000000 111111 0 63 b op magnitude selection. code 0 = b op(min) (default C no fuse blowing required.) code 63 = b op(max) b hys selection [v ph 3 v pm v ph 11 v pm v ph (n) v pm v ph_blow ] 00 11 0 3 b hys magnitude selection. code 0 = b hys(min) (default C no fuse blowing required) code 3 = b hys(max) parity bit [v ph v pm v ph 11 v pm v ph v ph_blow ] 0 0 blow decision is made automatically. lock bit [v ph 3 v pm v ph 11 v pm v ph 4 v pm v ph_blow ] locks access to b op and b hys selection registers. programmable precision hall-effect switch with advanced diagnostics a1162
18 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com additional guidelines the additional guidelines in this section should be followed to ensure the proper behavior of these devices: ? the power supply used for programming must be capable of delivering at least v ph and 175 ma. ? be careful to observe the t low delay time before powering down the device after blowing each bit. ? set the lock bit (only after all other parameters have been programmed and validated) to prevent any further programming of the device. read mode the a1162 features a read mode that allows the status of each programmable fuse to be read back individually. the status, blown or not blown, of the addressed fuse is determined by moni- figure 11: read mode example pulse sequence for accessing the b op selection register (bopsel) and reading back the status of each of the eight bit fields. in this example, the code (blown fuses) is 2 0 + 2 3 + 2 4 + 2 6 = 89 (0101 1001). after each address pulse is sent, the voltage on the vout pin will be at gnd for blown fuses and at v cc (at v pl or v pm ) for un-blown fuses. v ph v pm v pl v ph v pm v pl gnd register (and mode) selection key bit field (fuse) address codes read-out on vout pin 1 2 3 4 5 6 7 1 2 3 4 5 6 7 8 9 10 11 bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 0 blown bit 1 un-blown bit 2 un-blown bit 3 blown bit 4 blown bit 5 un-blown bit 6 blown bit 7 un-blown gnd fuse intact fuse blown v out v cc don?t care toring the state of the vout pin. a complete example is shown in figure 11. read mode uses the same register selection keys as blow mode (see table 3), allowing direct addressing of the individual fuses in the bopsel register (do not inadvertently send a blow pulse while in read mode). after sending the register and mode selec- tion keys, that is, after the falling edge of the final v ph pulse in the key, the first bit (the lsb) is selected. each additional v pm pulse addresses the next bit in the selected register, up to the msb. read mode is available only before the lock bit has been set. after the final v ph key pulse, and after each v pm address pulse, if v out is low, the corresponding fuse can be considered blown. if the output state is high, the fuse can be considered un-blown. during read mode vout must be pulled high using a pull-up resistor (see r load in the typical application circuit diagram). programmable precision hall-effect switch with advanced diagnostics a1162
19 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com b op selection the a1162 allows accurate trimming of the magnetic operate point (b op ) within the application. this programmable feature reduces effects due to mechanical placement tolerances and improves performance when used in proximity or vane sensing applications. b op can be set to any value within the range allowed by the bopsel registers. however, switching is recommended only within the programmable b op range, specified in the operating characteristics table. trimming of b op is typically done in two stages. in the first stage, b op is adjusted temporarily using the try mode program- ming features, to find the fuse value that corresponds to the optimum b op . after a value is determined, then it can be perma- nently set using the blow mode features. as an aid to programming, the a1162 has two options available in try mode for adjusting the b op parameter. as shown in figure 12, this allows the b op parameter to either trim-up (i.e., start at the b op minimum value and increase to the maximum value) or trim-down (i.e., start at the b op maximum value and decrease to the minimum value). (a) b, trim up-counting register op (b) b, trim down-counting register op b (max) op b+ (south) b (max) op b+ (south) b (min) op b (min) op try mode, bit field code magnetic field intensity, b (g) 0 0 0 255 try mode, bit field code magnetic field intensity, b (g) 0 255 b setpoint op b setpoint op figure 12: b op profiles for each of the b op selection virtual registers available in try mode. programmable precision hall-effect switch with advanced diagnostics a1162
20 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com when using hall-effect technology, a limiting factor for switch point accuracy is the small signal voltage developed across the hall element. this voltage is disproportionally small relative to the offset that can be produced at the output of the hall sensor ic. this makes it difficult to process the signal while maintaining an accurate, reliable output over the specified operating temperature and voltage ranges. chopper stabilization is a proven approach used to minimize hall offset on the chip. the patented allegro technique, namely dynamic quadrature offset cancellation, removes key sources of the output drift induced by thermal and mechanical stresses. this offset reduction technique is based on a signal modulation-demodulation process. the undesired offset signal is separated from the magnetic field- induced signal in the frequency domain through modulation. the subsequent demodulation acts as a modulation process for the offset, causing the magnetic field-induced signal to recover its original spectrum at baseband, while the dc offset becomes a high-frequency signal. the magnetic signal then can pass through a low-pass filter, while the modulated dc offset is suppressed. the chopper stabilization technique uses a high frequency clock, generally at hundreds of kilohertz. a sample-and-hold technique is used for demodulation, where the sampling is performed at chopper stabilization technique amp. low-pass filter sample and hold regulator clock/logic hall element figure 13: model of chopper stabilization circuit twice the chopper frequency. this high-frequency operation allows a greater sampling rate, which results in higher accuracy and faster signal-processing capability. this approach desensi- tizes the chip to the effects of thermal and mechanical stresses, and produces devices that have extremely stable quiescent hall output voltages and precise recoverability after temperature cycling. this technique is made possible through the use of a bicmos process, which allows the use of low-offset, low-noise amplifiers in combination with high-density logic integration and sample-and-hold circuits. programmable precision hall-effect switch with advanced diagnostics a1162
21 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com the device must be operated below the maximum junction tem- perature of the device (t j(max) ). under certain combinations of peak conditions, reliable operation may require derating supplied power or improving the heat dissipation properties of the appli- cation. this section presents a procedure for correlating factors affecting operating t j . (thermal data is also available on the allegro microsystems website.) the package thermal resistance (r ja ) is a figure of merit sum- marizing the ability of the application and the device to dissipate heat from the junction (die), through all paths to the ambient air. its primary component is the effective thermal conductivity (k) of the printed circuit board, including adjacent devices and traces. radiation from the die through the device case (r jc ) is a relatively small component of r ja . ambient air temperature (t a ) and air motion are significant external factors, damped by overmolding. the effect of varying power levels (power dissipation, p d ), can be estimated. the following formulas represent the fundamental relationships used to estimate t j , at p d . p d = v in i in (1) t = p d r ja (2) t j = t a + t (3) for example, given common conditions such as: t a = 25c, v in = 12 v, i in = 5 ma, and r ja = 145c/w, then: p d = v in i in = 12 v 5 ma = 60 mw t = p d r ja = 60 mw 145c/w = 8.7c t j = t a + t = 25c + 8.7c = 33.7c for 5 v 5% systems, in diagnostic mode: r ja = 145c/w, t j(max) = 165oc, v cc = 5.25 v , and i cc(diag)max = 25 ma. calculate the maximum allowable power level with equation 1: p d(max) = v cc i cc(diag)max = 5.25 v 25 ma = 131.25 mw then determine the allowable increase to temperature with equa- tion 2: t max = p d(max) r ja = 131.25 mw 145c/w = 19c finally, inverting equation 3 results in the maximum ambient temperature: t a(max) = t j(max) + t max = 165c + 19c = 146c a worst-case estimate, p d(max) , represents the maximum allow- able power level, without exceeding t j(max) , at a selected r ja and t a . example : reliability for v cc at t a = 150c, package le, using a 4-layer pcb. observe the worst-case ratings for the device, specifically: r ja = 145c/w, t j(max) = 165c, v cc(max) = 24 v, and i cc(max) = 5 ma. calculate the maximum allowable power level (p d(max) ). first, invert equation 3: t max = t j(max) C t a = 165c C 150c = 15c this provides the allowable increase to t j resulting from internal power dissipation. then, invert equation 2: p d(max) = t max r ja = 15c 145c/w = 103 mw finally , invert equation 1 with respect to voltage: v cc(est) = p d(max) i cc(max) = 103 mw 5 ma = 20.6 v the result indicates that, at t a , the application and device can dissipate adequate amounts of heat at voltages v cc(est) . compare v cc(est) to v cc(max) . if v cc(est) v cc(max) , then reli- able operation between v cc(est) and v cc(max) requires enhanced r ja . if v cc(est) v cc(max) , then operation between v cc(est) and v cc(max) is reliable under these conditions. power derating programmable precision hall-effect switch with advanced diagnostics a1162
22 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com package outline drawing 1.70 b 12 8 pcb layout reference view for reference only ? not for tooling use (reference mo-153 aa) dimensions in millimeters - not to scale dimensions exclusive of mold ash, gate burrs, and dambar protrusions exact case and lead conguration at supplier discretion within limits shown 3.00 0.10 0.11 6.40 bsc 6.40 bsc 4.40 0.10 d b c c e e d d 12 8 branded face 8x 0.10 c 0.30 0.19 0.65 bsc 0.25 bsc 0.15 0.05 1.10 max seating plane c 8o 0o 0.02 0.09 0.60 1.00 ref +0.15 -0.10 seating plane gauge plane standard branding reference view 1 nnn yyww a a = last 3 digits of device part number = supplier emblem = last two digits of year of manufacture = week of manufacture n y w terminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x110-8m); all pads minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias can improve thermal dissipation (reference eia/jedec standard jesd51-5) branding scale and appearance at supplier discretion hall element, not to scale active area depth = 0.36 mm ref figure 14: package le, 8-pin etssop programmable precision hall-effect switch with advanced diagnostics a1162
23 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com for the latest version of this document, visit our website: www.allegromicro.com revision history revision revision date description of revision C january 27, 2016 initial release copyright ?2016, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. programmable precision hall-effect switch with advanced diagnostics a1162

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