cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 1/ 10 MTB1D5N03H8 cystek product specification n-channel enhancement mode power mosfet MTB1D5N03H8 bv dss 30v 156a (silicon limit) i d @v gs =10v, t c =25 c i d @v gs =10v, t c =25 c 84a (package limit) 23.5a i d @v gs =10v, t a =25 c r ds(on) @v gs =10v, i d =20a 1.3m (typ) features r ds(on) @v gs =4.5v, i d =20a ? low on resistance ? simple drive requirement ? low gate charge ? fast switching characteristic ? pb-free lead plating and halogen-free package symbol outline ordering information device package shipping MTB1D5N03H8-0-t6-g dfn 5 6 (pb-free lead plating and halogen-free package) 3000 pcs / tape & reel MTB1D5N03H8 dfn5 6 1.6m (typ) g gate d drain s source pin 1 d d environment friendly grade : s for rohs compliant products, g for rohs compliant and green compound products packing spec, t6 : 3000 pcs / tape & reel,13? reel product rank, zero for no rank products product name s s s g d d d d d d s s g s pin 1
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 2/ 10 MTB1D5N03H8 cystek product specification absolute maximum ratings (t c =25 c, unless otherwise noted) parameter symbol limits unit drain-source voltage (note 1) v ds 30 gate-source voltage v gs 20 v continuous drain current @t c =25 c, v gs =10v (silicon limit) (note 5) 156 continuous drain current @t c =100c, v gs =10v(silicon limit) (note 5) 110 continuous drain current @t c =25 c, v gs =10v (package limit) (note 1) i d 84 continuous drain current @t a =25 c, v gs =10v (note 2) 23.5 continuous drain current @t a =70 c, v gs =10v (note 2) i dsm 18.8 pulsed drain current @ v gs =10v (note 3) i dm 450 avalanche current @l=0.1mh (note 3) i as 80 a single pulse avalanche energy @ l=1mh, i d =50amps, v dd =15v (note 4) e as 1250 repetitive avalanche energy (note 3) e ar 12.5 mj t c =25 c (note 1) 125 t c =100c (note 1) p d 62.5 t a =25 c (note 2) 2.5 power dissipation t a =70 c (note 2) p dsm 1.6 w operating junction and storage temperature tj, tstg -55~+175 c *drain current limited by maximum junction temperature thermal data parameter symbol value unit thermal resistance, junction-to-case, max r jc 1.2 thermal resistance, junction-to-ambient, max (note 2) r ja 50 c/w note : 1.the power dissipation p d is based on t j(max) =175 c, using junction-to-case thermal resistance, and is more useful in setting the upper di ssipation limit for cases where additional heatsinking is used. 2. the value of r ja is measured with the device mounted on 1 in2 fr-4 board with 2 oz. copper, in a still air environment with t a =25 c. the value in any given application depends on the user?s specific board design. the power dissipation p dsm is based on r ja and the maximum allowed junction temperature of 150 c, and the maximum temperature of 175 c may be used if the pcb allows it. 3. pulse width limited by junction temperature t j(max) =175 c. 4. ratings are based on low frequency and low duty cycles to keep initial t j =25 c. 100% tested by conditions of v dd =15v, i d =20a, l=1mh, v gs =10v. 5. calculated continuous drain current based on maximum allowable junction temperature. 6. the static characteristics are obtained using <300 s pulses, duty cycle 0.5% maximum. 7. the r ja is the sum of thermal resistance from junction to case r jc and case to ambient. .
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 3/ 10 MTB1D5N03H8 cystek product specification characteristics (tj=25 c, unless otherwise specified) symbol min. typ. max. unit test conditions static bv dss 30 - - v v gs =0v, i d =250 a ? bv dss / ? tj - 0.024 - v/ c reference to 25c, i d =250 a v gs(th) 1 - 2.5 v v ds = v gs , i d =250 a *g fs - 51.9 - s v ds =10v, i d =20a i gss - - 100 na v gs = 20v - - 1 v ds =24v, v gs =0v i dss - - 5 a v ds =24v, v gs =0v, tj=55 c - 1.3 1.7 v gs =10v, i d =20a *r ds(on) - 1.6 2.2 m v gs =4.5v, i d =20a dynamic *qg(v gs =10v) - 144.8 - *qg(v gs =4.5v) - 75.3 - *qgs - 21 - *qgd - 35.4 - nc v ds =20v, i d =20a, v gs =10v *t d(on) - 32.4 - *tr - 28.8 - *t d(off) - 108.8 - *t f - 24 - ns v ds =15v, i d =20a, v gs =10v, r g =1 ciss - 6726 - coss - 1066 - crss - 506 - pf v gs =0v, v ds =20v, f=1mhz rg - 1.0 - f=1mhz source-drain diode *i s - - 84 *i sm - - 450 a *v sd - 0.71 1.1 v i s =5a, v gs =0v *trr - 40 - ns *qrr - 37.9 - nc v gs =0v, i f =5a, di f /dt=100a/ s *pulse test : pulse width 300 s, duty cycle 2%
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 4/ 10 MTB1D5N03H8 cystek product specification recommended soldering footprint & stencil design unit : mm
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 5/ 10 MTB1D5N03H8 cystek product specification typical characteristics typical output characteristics 0 50 100 150 200 250 300 012345 v ds , drain-source voltage(v) i d , drain current(a) 10v, 9v, 8v, 7v, 6v, 5v v gs =2.5v 3v 3.5v 4v brekdown voltage vs ambient temperature 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) bv dss , normalized drain-source breakdown voltage i d =250 a, v gs =0v static drain-source on-state resistance vs drain current 1 10 100 0.01 0.1 1 10 100 i d , drain current(a) r ds(on) , static drain-source on-state resistance(m) v gs =10v v gs =4.5v reverse drain current vs source-drain voltage 0.2 0.4 0.6 0.8 1 1.2 04812162 i dr , reverse drain current(a) v sd , source-drain voltage(v) static drain-source on-state resistance vs gate-source voltage 0 10 20 30 40 50 024681 0 0 tj=25c tj=150c drain-source on-state resistance vs junction tempearture 0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) r ds(on) , normalized static drain- source on-state resistance v gs =10v, i d =20a r ds( on) @tj=25c :1.3m typ. v gs , gate-source voltage(v) r ds(on) , static drain-source on- state resistance(m) i d =20a
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 6/ 10 MTB1D5N03H8 cystek product specification typical characteristics(cont.) capacitance vs drain-to-source voltage 100 1000 10000 0 5 10 15 20 25 30 v ds , drain-source voltage(v) capacitance---(pf) c oss ciss crss threshold voltage vs junction tempearture 0.2 0.4 0.6 0.8 1 1.2 1.4 -75 -50 -25 0 25 50 75 100 125 150 175 200 tj, junction temperature(c) v gs(th) , normalizedthreshold voltage i d =250 a i d =1ma forward transfer admittance vs drain current 0.01 0.1 1 10 100 0.001 0.01 0.1 1 10 100 i d , drain current(a) g fs , forward transfer admittance(s) v ds =10v pulsed ta=25c gate charge characteristics 0 2 4 6 8 10 0 20 40 60 80 100 120 140 160 total gate charge---qg(nc) v gs , gate-source voltage(v) i d =20a v ds =15v v ds =20v maximum safe operating area 0.1 1 10 100 1000 0.1 1 10 100 v ds , drain-source voltage(v) i d , drain current(a) dc 10ms 1ms 100 s r ds( on) limited t c =25c, tj=175c, v gs =10v, r jc =1.2c/w single pulse maximum drain current vs case temperature 0 20 40 60 80 100 120 140 160 180 25 50 75 100 125 150 175 200 t c , case temperature(c) i d , maximum drain current(a) v gs =10v, r jc =1.2c/w silicon limit package limit
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 7/ 10 MTB1D5N03H8 cystek product specification typical characteristics(cont.) typical transfer characteristics 0 50 100 150 200 250 300 012345 v gs , gate-source voltage(v) i d , drain current (a) v ds =10v single pulse maximum power dissipation 0 500 1000 1500 2000 2500 3000 0.0001 0.001 0.01 0.1 1 10 pulse width(s) power (w) t j(max) =175c t c =25c r jc =1.2c/w transient thermal response curves 0.01 0.1 1 1.e-04 1.e-03 1.e-02 1.e-01 1.e+00 1.e+01 t 1 , square wave pulse duration(s) r(t), normalized effective transient thermal resistance single pulse 0.02 0.05 0.1 0.2 d=0.5 1.r jc (t)=r(t)*r jc 2.duty factor, d=t 1 /t 2 3.t jm -t c =p dm *r jc (t) 4.r jc =1.2 c/w
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 8/ 10 MTB1D5N03H8 cystek product specification reel dimension carrier tape dimension pin #1
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 9/ 10 MTB1D5N03H8 cystek product specification recommended wave soldering condition soldering time product peak temperature pb-free devices 260 +0/-5 c 5 +1/-1 seconds recommended temperature profile for ir reflow profile feature sn-pb eutectic assembly pb-free assembly average ramp-up rate (tsmax to tp) 3 c/second max. 3c/second max. preheat ? temperature min(t s min) ? temperature max(t s max) ? time(ts min to ts max ) 100 c 150 c 60-120 seconds 150 c 200 c 60-180 seconds time maintained above: ? temperature (t l ) ? time (t l ) 183 c 60-150 seconds 217 c 60-150 seconds peak temperature(t p ) 240 +0/-5 c 260 +0/-5 c time within 5 c of actual peak 10-30 seconds 20-40 seconds temperature(tp) ramp down rate 6 c/second max. 6c/second max. time 25 c to peak temperature 6 minutes max. 8 minutes max. note : all temperatures refer to topside of the package, measured on the package body surface.
cystech electronics corp. spec. no. : c984h8 issued date : 2017.01.06 revised date : page no. : 10/ 10 MTB1D5N03H8 cystek product specification dfn5 6 dimension millimeters inches marking: b1d5 n03 device name date code 8-lead dfn5 6 plastic package cys package code : h8 millimeters inches dim min. max. min. max. dim min. max. min. max. a 1.00 1.20 0.039 0.047 e2 3.18 3.54 0.125 0.139 b 0.35 0.45 0.014 0.018 h 0.51 0.71 0.020 0.028 c 0.21 0.34 0.008 0.013 k 1.10 - 0.043 - d - 5.10 - 0.201 l 0.51 0.71 0.020 0.028 d1 4.80 5.00 0.189 0.197 l1 0.06 0.20 0.002 0.008 d2 3.82 4.11 0.150 0.162 l2 - 0.10 - 0.004 e 1.17 1.37 0.046 0.054 p 1.00 1.20 0.039 0.047 e 5.90 6.10 0.232 0.240 8 12 8 12 e1 5.70 5.80 0.224 0.228 notes: 1.controlling dimension: millimeters. 2.maximum lead thickness includes lead finish thickness, and minimum lead thickness is the minimum thickness of base material. 3.if there is any question with packing spec ification or packing method, please cont act your local cystek sales office. material: ? lead: pure tin plated. ? mold compound: epoxy resin family, flammability solid burning class: ul94v-0. important notice: ? all rights are reserved. reproduction in whole or in part is prohibited without the prior written approval of cystek. ? cystek reserves the right to make changes to its products without notice. ? cystek semiconductor products are not warranted to be suitab le for use in life-support applications, or systems. ? cystek assumes no liability for any consequence of customer pr oduct design, infringement of pat ents, or application assistance .
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