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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2001 mos integrated circuit pd16782 source driver for 300/288-output tft-lcd (navigation, automobile lcd-tv) data sheet document no. s15806ej1v0ds00 (1st edition) date published december 2002 ns cp (k) printed in japan description pd16782 is a source driver for tft liquid crystal panels. this ic consists of a multiplexer circuit supporting a variety of pixel arrays, a shift register that generates sampling timing, and two sample and hold circuits that sample analog voltages. because the two sample and hold circuits alternately execute sampling and holding, a high definition can be obtained. in addition, simultaneous sampling and successive sampling are automatically selected according to the pixel array of the lcd panel. it is ideal for a wide range of applications, including navigation systems and automobile lcd-tvs. features ? can be driven on 5 v (dynamic range: 4.3 v, v dd2 = 5.0 v) ? 300/288-output ? f clk = 15 mhz max. (v dd1 = 3.0 v) ? simultaneous/successive sampling selectable according to pixel array simultaneous sampling: vertical stripe successive sampling: delta array, mosaic array ? two sample and hold circuits ? low output deviation between pins ( 20 mv max.) ? stripe, delta, and mosaic pixel arrays supported by internal multiplexer circuit ? left and right shift selected by r,/l pin ? cog mounting possible remark /xxx indicates active low signal. ordering information part number package pd16782p chip remark purchasing the above chip entails the exchange of documents such as a separate memorandum or product quality, so please contact one of our sales representative.
data sheet s15806ej1v0ds 2 pd16782 1. block diagram 300-bit bidirectional shift register level shifter sample and hold sthr s 1 sthl r,/l cli1~cli3 v dd1 v ss1 c 1 c 2 c 3 mp/th v dd2 v ss2 s 2 s 3 s 300 inh multiplexer c1 c2 c3 mp/1.5 reset osel c 299 c 300 (monitor) rmon1, rmon2 2. sample and hold circuit and output circuit swb1 swa1 c h1 swb2 swa2 c h2 s n video line + +
data sheet s15806ej1v0ds 3 pd16782 3. pin configuration s 300 s 299 s 298 rmon2 s 1 s 2 v dd1 v ss1 v dd2 rmon2 cli3 test sthr osel reset inh cli1 cli2 sthl mp/th mp/1.5 r,/l v ss2 rmon1 rmon1 v dd2 v ss1 v dd1 c1 c2 c3 0 y(+) x(+) v ss2 alignment mark: (50 x 50 m ) output dummy pin input dummy pin connected resistance measurement pin alignment mark: (50 x 50 m ) 2 2 output dummy pin input dummy pin connected resistance measurement pin
data sheet s15806ej1v0ds 4 pd16782 table 3 1. pad layout (1/4) no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] 1dumm y 1 -464.0 8451.0 100:60 56 mp/th -464.0 378.6 100:60 2 rmon1 -464.0 8014.2 100:60 57 mp/1.5 -464.0 145.5 100:60 3 rmon1 -464.0 7842.0 100:60 58 mp/1.5 -464.0 65.5 100:60 4v dd2 -464.0 7538.6 100:60 59 mp/1.5 -464.0 -14.5 100:60 5v dd2 -464.0 7458.6 100:60 60 r , /l -464.0 -247.6 100:60 6v dd2 -464.0 7378.6 100:60 61 r , /l -464.0 -327.6 100:60 7v dd2 -464.0 7298.6 100:60 62 r , /l -464.0 -407.6 100:60 8v dd2 -464.0 7218.6 100:60 63 reset -464.0 -640.7 100:60 9v dd2 -464.0 7138.6 100:60 64 reset -464.0 -720.7 100:60 10 v dd2 -464.0 7058.6 100:60 65 reset -464.0 -800.7 100:60 11 v dd2 -464.0 6978.6 100:60 66 inh -464.0 -1033.8 100:60 12 v dd2 -464.0 6898.6 100:60 67 inh -464.0 -1113.8 100:60 13 v dd2 -464.0 6818.6 100:60 68 inh -464.0 -1193.8 100:60 14 v dd2 -464.0 6738.6 100:60 69 cli1 -464.0 -1427.0 100:60 15 v dd2 -464.0 6658.6 100:60 70 cli1 -464.0 -1507.0 100:60 16 v ss1 -464.0 6181.0 100:60 71 cli1 -464.0 -1587.0 100:60 17 v ss1 -464.0 6101.0 100:60 72 cli2 -464.0 -1820.1 100:60 18 v ss1 -464.0 6021.0 100:60 73 cli2 -464.0 -1900.1 100:60 19 v ss1 -464.0 5941.0 100:60 74 cli2 -464.0 -1980.1 100:60 20 v ss1 -464.0 5861.0 100:60 75 cli3 -464.0 -2213.2 100:60 21 v ss1 -464.0 5781.0 100:60 76 cli3 -464.0 -2293.2 100:60 22 v ss1 -464.0 5701.0 100:60 77 cli3 -464.0 -2373.2 100:60 23 v dd1 -464.0 5239.4 100:60 78 test -464.0 -2606.3 100:60 24 v dd1 -464.0 5159.4 100:60 79 test -464.0 -2686.3 100:60 25 v dd1 -464.0 5079.4 100:60 80 test -464.0 -2766.3 100:60 26 v dd1 -464.0 4999.4 100:60 81 sthr -464.0 -3227.0 100:60 27 v dd1 -464.0 4919.4 100:60 82 sthr -464.0 -3307.0 100:60 28 v dd1 -464.0 4839.4 100:60 83 sthr -464.0 -3387.0 100:60 29 v dd1 -464.0 4759.4 100:60 84 sthr -464.0 -3467.0 100:60 30 c1 -464.0 4335.2 100:60 85 sthr -464.0 -3547.0 100:60 31 c1 -464.0 4255.2 100:60 86 sthr -464.0 -3627.0 100:60 32 c1 -464.0 4175.2 100:60 87 osel -464.0 -4170.4 100:60 33 c1 -464.0 4095.2 100:60 88 osel -464.0 -4250.4 100:60 34 c1 -464.0 4015.2 100:60 89 osel -464.0 -4330.4 100:60 35 c1 -464.0 3935.2 100:60 90 v dd1 -464.0 -4759.4 100:60 36 c2 -464.0 3470.4 100:60 91 v dd1 -464.0 -4839.4 100:60 37 c2 -464.0 3390.4 100:60 92 v dd1 -464.0 -4919.4 100:60 38 c2 -464.0 3310.4 100:60 93 v dd1 -464.0 -4999.4 100:60 39 c2 -464.0 3230.4 100:60 94 v dd1 -464.0 -5079.4 100:60 40 c2 -464.0 3150.4 100:60 95 v dd1 -464.0 -5159.4 100:60 41 c2 -464.0 3070.4 100:60 96 v dd1 -464.0 -5239.4 100:60 42 c3 -464.0 2605.6 100:60 97 v ss1 -464.0 -5701.0 100:60 43 c3 -464.0 2525.6 100:60 98 v ss1 -464.0 -5781.0 100:60 44 c3 -464.0 2445.6 100:60 99 v ss1 -464.0 -5861.0 100:60 45 c3 -464.0 2365.6 100:60 100 v ss1 -464.0 -5941.0 100:60 46 c3 -464.0 2285.6 100:60 101 v ss1 -464.0 -6021.0 100:60 47 c3 -464.0 2205.6 100:60 102 v ss1 -464.0 -6101.0 100:60 48 sthl -464.0 1384.2 100:60 103 v ss1 -464.0 -6181.0 100:60 49 sthl -464.0 1304.2 100:60 104 v dd2 -464.0 -6658.6 100:60 50 sthl -464.0 1224.2 100:60 105 v dd2 -464.0 -6738.6 100:60 51 sthl -464.0 1144.2 100:60 106 v dd2 -464.0 -6818.6 100:60 52 sthl -464.0 1064.2 100:60 107 v dd2 -464.0 -6898.6 100:60 53 sthl -464.0 984.2 100:60 108 v dd2 -464.0 -6978.6 100:60 54 mp/th -464.0 538.6 100:60 109 v dd2 -464.0 -7058.6 100:60 55 mp/th -464.0 458.6 100:60 110 v dd2 -464.0 -7138.6 100:60
data sheet s15806ej1v0ds 5 pd16782 table 3 1. pad layout (2/4) no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] 111 v dd2 -464.0 -7218.6 100:60 166 s 37 402.0 -6533.5 80:37 112 v dd2 -464.0 -7298.6 100:60 167 s 38 402.0 -6476.5 80:37 113 v dd2 -464.0 -7378.6 100:60 168 s 39 402.0 -6419.5 80:37 114 v dd2 -464.0 -7458.6 100:60 169 s 40 402.0 -6362.5 80:37 115 v dd2 -464.0 -7538.6 100:60 170 s 41 402.0 -6305.5 80:37 116 rmon2 -464.0 -7842.0 100:60 171 s 42 402.0 -6248.5 80:37 117 rmon2 -464.0 -8014.2 100:60 172 s 43 402.0 -6191.5 80:37 118 dumm y 2 -464.0 -8451.0 100:60 173 s 44 402.0 -6134.5 80:37 119 v ss2 -399.8 -8769.0 60 100 174 s 45 402.0 -6077.5 80:37 120 v ss2 -319.8 -8769.0 60 100 175 s 46 402.0 -6020.5 80:37 121 v ss2 -239.8 -8769.0 60 100 176 s 47 402.0 -5963.5 80:37 122 v ss2 -159.8 -8769.0 60 100 177 s 48 402.0 -5906.5 80:37 123 v ss2 -79.8 -8769.0 60 100 178 s 49 402.0 -5849.5 80:37 124 v ss2 0.2 -8769.0 60 100 179 s 50 402.0 -5792.5 80:37 125 v ss2 80.2 -8769.0 60 100 180 s 51 402.0 -5735.5 80:37 126 v ss2 160.2 -8769.0 60 100 181 s 52 402.0 -5678.5 80:37 127 v ss2 240.2 -8769.0 60 100 182 s 53 402.0 -5621.5 80:37 128 v ss2 320.2 -8769.0 60 100 183 s 54 402.0 -5564.5 80:37 129 dumm y 3 402.0 -8642.5 80:37 184 s 55 402.0 -5507.5 80:37 130 s 1 402.0 -8585.5 80:37 185 s 56 402.0 -5450.5 80:37 131 s 2 402.0 -8528.5 80:37 186 s 57 402.0 -5393.5 80:37 132 s 3 402.0 -8471.5 80:37 187 s 58 402.0 -5336.5 80:37 133 s 4 402.0 -8414.5 80:37 188 s 59 402.0 -5279.5 80:37 134 s 5 402.0 -8357.5 80:37 189 s 60 402.0 -5222.5 80:37 135 s 6 402.0 -8300.5 80:37 190 s 61 402.0 -5165.5 80:37 136 s 7 402.0 -8243.5 80:37 191 s 62 402.0 -5108.5 80:37 137 s 8 402.0 -8186.5 80:37 192 s 63 402.0 -5051.5 80:37 138 s 9 402.0 -8129.5 80:37 193 s 64 402.0 -4994.5 80:37 139 s 10 402.0 -8072.5 80:37 194 s 65 402.0 -4937.5 80:37 140 s 11 402.0 -8015.5 80:37 195 s 66 402.0 -4880.5 80:37 141 s 12 402.0 -7958.5 80:37 196 s 67 402.0 -4823.5 80:37 142 s 13 402.0 -7901.5 80:37 197 s 68 402.0 -4766.5 80:37 143 s 14 402.0 -7844.5 80:37 198 s 69 402.0 -4709.5 80:37 144 s 15 402.0 -7787.5 80:37 199 s 70 402.0 -4652.5 80:37 145 s 16 402.0 -7730.5 80:37 200 s 71 402.0 -4595.5 80:37 146 s 17 402.0 -7673.5 80:37 201 s 72 402.0 -4538.5 80:37 147 s 18 402.0 -7616.5 80:37 202 s 73 402.0 -4481.5 80:37 148 s 19 402.0 -7559.5 80:37 203 s 74 402.0 -4424.5 80:37 149 s 20 402.0 -7502.5 80:37 204 s 75 402.0 -4367.5 80:37 150 s 21 402.0 -7445.5 80:37 205 s 76 402.0 -4310.5 80:37 151 s 22 402.0 -7388.5 80:37 206 s 77 402.0 -4253.5 80:37 152 s 23 402.0 -7331.5 80:37 207 s 78 402.0 -4196.5 80:37 153 s 24 402.0 -7274.5 80:37 208 s 79 402.0 -4139.5 80:37 154 s 25 402.0 -7217.5 80:37 209 s 80 402.0 -4082.5 80:37 155 s 26 402.0 -7160.5 80:37 210 s 81 402.0 -4025.5 80:37 156 s 27 402.0 -7103.5 80:37 211 s 82 402.0 -3968.5 80:37 157 s 28 402.0 -7046.5 80:37 212 s 83 402.0 -3911.5 80:37 158 s 29 402.0 -6989.5 80:37 213 s 84 402.0 -3854.5 80:37 159 s 30 402.0 -6932.5 80:37 214 s 85 402.0 -3797.5 80:37 160 s 31 402.0 -6875.5 80:37 215 s 86 402.0 -3740.5 80:37 161 s 32 402.0 -6818.5 80:37 216 s 87 402.0 -3683.5 80:37 162 s 33 402.0 -6761.5 80:37 217 s 88 402.0 -3626.5 80:37 163 s 34 402.0 -6704.5 80:37 218 s 89 402.0 -3569.5 80:37 164 s 35 402.0 -6647.5 80:37 219 s 90 402.0 -3512.5 80:37 165 s 36 402.0 -6590.5 80:37 220 s 91 402.0 -3455.5 80:37
data sheet s15806ej1v0ds 6 pd16782 table 3 1. pad layout (3/4) no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] 221 s 92 402.0 -3398.5 80:37 276 s 147 402.0 -263.5 80:37 222 s 93 402.0 -3341.5 80:37 277 s 148 402.0 -206.5 80:37 223 s 94 402.0 -3284.5 80:37 278 s 149 402.0 -149.5 80:37 224 s 95 402.0 -3227.5 80:37 279 s 150 402.0 -92.5 80:37 225 s 96 402.0 -3170.5 80:37 280 s 151 402.0 -35.5 80:37 226 s 97 402.0 -3113.5 80:37 281 s 152 402.0 21.5 80:37 227 s 98 402.0 -3056.5 80:37 282 s 153 402.0 78.5 80:37 228 s 99 402.0 -2999.5 80:37 283 s 154 402.0 135.5 80:37 229 s 100 402.0 -2942.5 80:37 284 s 155 402.0 192.5 80:37 230 s 101 402.0 -2885.5 80:37 285 s 156 402.0 249.5 80:37 231 s 102 402.0 -2828.5 80:37 286 s 157 402.0 306.5 80:37 232 s 103 402.0 -2771.5 80:37 287 s 158 402.0 363.5 80:37 233 s 104 402.0 -2714.5 80:37 288 s 159 402.0 420.5 80:37 234 s 105 402.0 -2657.5 80:37 289 s 160 402.0 477.5 80:37 235 s 106 402.0 -2600.5 80:37 290 s 161 402.0 534.5 80:37 236 s 107 402.0 -2543.5 80:37 291 s 162 402.0 591.5 80:37 237 s 108 402.0 -2486.5 80:37 292 s 163 402.0 648.5 80:37 238 s 109 402.0 -2429.5 80:37 293 s 164 402.0 705.5 80:37 239 s 110 402.0 -2372.5 80:37 294 s 165 402.0 762.5 80:37 240 s 111 402.0 -2315.5 80:37 295 s 166 402.0 819.5 80:37 241 s 112 402.0 -2285.5 80:37 296 s 167 402.0 876.5 80:37 242 s 113 402.0 -2201.5 80:37 297 s 168 402.0 933.5 80:37 243 s 114 402.0 -2144.5 80:37 298 s 169 402.0 990.5 80:37 244 s 115 402.0 -2087.5 80:37 299 s 170 402.0 1047.5 80:37 245 s 116 402.0 -2030.5 80:37 300 s 171 402.0 1104.5 80:37 246 s 117 402.0 -1973.5 80:37 301 s 172 402.0 1161.5 80:37 247 s 118 402.0 -1916.5 80:37 302 s 173 402.0 1218.5 80:37 248 s 119 402.0 -1859.5 80:37 303 s 174 402.0 1275.5 80:37 249 s 120 402.0 -1802.5 80:37 304 s 175 402.0 1332.5 80:37 250 s 121 402.0 -1745.5 80:37 305 s 176 402.0 1389.5 80:37 251 s 122 402.0 -1688.5 80:37 306 s 177 402.0 1446.5 80:37 252 s 123 402.0 -1631.5 80:37 307 s 178 402.0 1503.5 80:37 253 s 124 402.0 -1574.5 80:37 308 s 179 402.0 1560.5 80:37 254 s 125 402.0 -1517.5 80:37 309 s 180 402.0 1617.5 80:37 255 s 126 402.0 -1460.5 80:37 310 s 181 402.0 1674.5 80:37 256 s 127 402.0 -1403.5 80:37 311 s 182 402.0 1731.5 80:37 257 s 128 402.0 -1346.5 80:37 312 s 183 402.0 1788.5 80:37 258 s 129 402.0 -1289.5 80:37 313 s 184 402.0 1845.5 80:37 259 s 130 402.0 -1232.5 80:37 314 s 185 402.0 1902.5 80:37 260 s 131 402.0 -1175.5 80:37 315 s 186 402.0 1959.5 80:37 261 s 132 402.0 -1118.5 80:37 316 s 187 402.0 2016.5 80:37 262 s 133 402.0 -1061.5 80:37 317 s 188 402.0 2073.5 80:37 263 s 134 402.0 -1004.5 80:37 318 s 189 402.0 2130.5 80:37 264 s 135 402.0 -947.5 80:37 319 s 190 402.0 2187.5 80:37 265 s 136 402.0 -890.5 80:37 320 s 191 402.0 2244.5 80:37 266 s 137 402.0 -833.5 80:37 321 s 192 402.0 2301.5 80:37 267 s 138 402.0 -776.5 80:37 322 s 193 402.0 2358.5 80:37 268 s 139 402.0 -719.5 80:37 323 s 194 402.0 2415.5 80:37 269 s 140 402.0 -662.5 80:37 324 s 195 402.0 2472.5 80:37 270 s 141 402.0 -605.5 80:37 325 s 196 402.0 2529.5 80:37 271 s 142 402.0 -548.5 80:37 326 s 197 402.0 2586.5 80:37 272 s 143 402.0 -491.5 80:37 327 s 198 402.0 2643.5 80:37 273 s 144 402.0 -434.5 80:37 328 s 199 402.0 2700.5 80:37 274 s 145 402.0 -377.5 80:37 329 s 200 402.0 2757.5 80:37 275 s 146 402.0 -320.5 80:37 330 s 201 402.0 2814.5 80:37
data sheet s15806ej1v0ds 7 pd16782 table 3 1. pad layout (4/4) no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] no. pad name x [ m ] y [ m ] bum p size ( x:y ) [ m ] 331 s 202 402.0 2871.5 80:37 386 s 257 402.0 6006.5 80:37 332 s 203 402.0 2928.5 80:37 387 s 258 402.0 6063.5 80:37 333 s 204 402.0 2985.5 80:37 388 s 259 402.0 6120.5 80:37 334 s 205 402.0 3042.5 80:37 389 s 260 402.0 6177.5 80:37 335 s 206 402.0 3099.5 80:37 390 s 261 402.0 6234.5 80:37 336 s 207 402.0 3156.5 80:37 391 s 262 402.0 6291.5 80:37 337 s 208 402.0 3213.5 80:37 392 s 263 402.0 6348.5 80:37 338 s 209 402.0 3270.5 80:37 393 s 264 402.0 6405.5 80:37 339 s 210 402.0 3327.5 80:37 394 s 265 402.0 6462.5 80:37 340 s 211 402.0 3384.5 80:37 395 s 266 402.0 6519.5 80:37 341 s 212 402.0 3441.5 80:37 396 s 267 402.0 6576.5 80:37 342 s 213 402.0 3498.5 80:37 397 s 268 402.0 6633.5 80:37 343 s 214 402.0 3555.5 80:37 398 s 269 402.0 6690.5 80:37 344 s 215 402.0 3612.5 80:37 399 s 270 402.0 6747.5 80:37 345 s 216 402.0 3669.5 80:37 400 s 271 402.0 6804.5 80:37 346 s 217 402.0 3726.5 80:37 401 s 272 402.0 6861.5 80:37 347 s 218 402.0 3783.5 80:37 402 s 273 402.0 6918.5 80:37 348 s 219 402.0 3840.5 80:37 403 s 274 402.0 6975.5 80:37 349 s 220 402.0 3897.5 80:37 404 s 275 402.0 7032.5 80:37 350 s 221 402.0 3954.5 80:37 405 s 276 402.0 7089.5 80:37 351 s 222 402.0 4011.5 80:37 406 s 277 402.0 7146.5 80:37 352 s 223 402.0 4068.5 80:37 407 s 278 402.0 7203.5 80:37 353 s 224 402.0 4125.5 80:37 408 s 279 402.0 7260.5 80:37 354 s 225 402.0 4128.5 80:37 409 s 280 402.0 7317.5 80:37 355 s 226 402.0 4239.5 80:37 410 s 281 402.0 7374.5 80:37 356 s 227 402.0 4296.5 80:37 411 s 282 402.0 7431.5 80:37 357 s 228 402.0 4353.5 80:37 412 s 283 402.0 7488.5 80:37 358 s 229 402.0 4410.5 80:37 413 s 284 402.0 7545.5 80:37 359 s 230 402.0 4467.5 80:37 414 s 285 402.0 7602.5 80:37 360 s 231 402.0 4524.5 80:37 415 s 286 402.0 7659.5 80:37 361 s 232 402.0 4581.5 80:37 416 s 287 402.0 7716.5 80:37 362 s 233 402.0 4638.5 80:37 417 s 288 402.0 7773.5 80:37 363 s 234 402.0 4695.5 80:37 418 s 289 402.0 7830.5 80:37 364 s 235 402.0 4752.5 80:37 419 s 290 402.0 7887.5 80:37 365 s 236 402.0 4809.5 80:37 420 s 291 402.0 7944.5 80:37 366 s 237 402.0 4866.5 80:37 421 s 292 402.0 8001.5 80:37 367 s 238 402.0 4923.5 80:37 422 s 293 402.0 8058.5 80:37 368 s 239 402.0 4980.5 80:37 423 s 294 402.0 8115.5 80:37 369 s 240 402.0 5037.5 80:37 424 s 295 402.0 8172.5 80:37 370 s 241 402.0 5094.5 80:37 425 s 296 402.0 8229.5 80:37 371 s 242 402.0 5151.5 80:37 426 s 297 402.0 8286.5 80:37 372 s 243 402.0 5208.5 80:37 427 s 298 402.0 8343.5 80:37 373 s 244 402.0 5265.5 80:37 428 s 299 402.0 8400.5 80:37 374 s 245 402.0 5322.5 80:37 429 s 300 402.0 8457.5 80:37 375 s 246 402.0 5379.5 80:37 430 dumm y 4 402.0 8514.5 80:37 376 s 247 402.0 5436.5 80:37 431 v ss2 320.2 8769.0 60:100 377 s 248 402.0 5493.5 80:37 432 v ss2 240.2 8769.0 60:100 378 s 249 402.0 5550.5 80:37 433 v ss2 160.2 8769.0 60:100 379 s 250 402.0 5607.5 80:37 434 v ss2 80.2 8769.0 60:100 380 s 251 402.0 5664.5 80:37 435 v ss2 0.2 8769.0 60:100 381 s 252 402.0 5721.5 80:37 436 v ss2 -79.8 8769.0 60:100 382 s 253 402.0 5778.5 80:37 437 v ss2 -159.8 8769.0 60:100 383 s 254 402.0 5835.5 80:37 438 v ss2 -239.8 8769.0 60:100 384 s 255 402.0 5892.5 80:37 439 v ss2 -319.8 8769.0 60:100 385 s 256 402.0 5949.5 80:37 440 v ss2 -399.8 8769.0 60:100 441 ali g nment mark 1 429.2 8779.8 442 ali g nment mark 2 429.2 -8779.8
data sheet s15806ej1v0ds 8 pd16782 4. pin functions symbol pin name pad no. i/o description c1 to c3 video signal input 30 to 47 input input r, g, and b video signals. s 1 to s 300 video signal output 130 to 429 output video signal output pins. output sampled and held video signals during horizontal period. sthr, sthl cascade i/o 81 to 86, 48 to 53 i/o start pulse i/o pins of sample hold timing. sthr serves as an input pin and sthl, as an output pin, in the case of right shift. in the case of left shift, sthl serves as an input pin, and sthr, as an output pin. cli1 to cli3 shift clock input 69 to 77 input a start pulse is read at the rising edge of cli1. sampling pulse shpn is generated at the rising edge of cli1 through cli3 during successive sampling, and at the rising edge of cli1 during simultaneous sampling (for details, refer to the timing charts in 5. functional description ). inh inhibit input 66 to 68 input selects a multiplexer and one of the two sample and hold circuits at the falling edge. reset reset input 63 to 65 input resets the select counter of the multiplexer and the selector circuit of the two sample and hold circuits when it goes high. after reset, the multiplexer is turned off, so sure to input one pulse of the inh signal before inputting the video signal. if the video signal is input without the inh signal, sampling is not executed. four types of color filter arrays can be supported by combination of mp/th and mp/1.5. mode mp/th mp/1.5 mp/th multiplexer circuit select input (1) 54 to 56 input vertical stripe array l l single-side delta array l h mosaic array h l double-side delta array h h mp/1.5 multiplexer circuit select input (2) 57 to 59 input r,/l shift direction select input 60 to 62 input r,/l = h: right shift: sthr s 1 s 300 sthl r,/l = l: left shift: sthl s 300 s 1 sthr osel selection of number of outputs switching input 87 to 89 input selects number of outputs. o sel = l: 288 output mode o sel = h: 300 output mode output pins s 145 through s 156 are invalid in 288 output mode. the signal which is with s 157 to s 168 (r,/l = h) or s 133 to s 144 (r,/l = l) is output identically. rmon1, rmon2 monitor 2, 3, 116, 117 this pin can measure the connection resistance at the time of cog mounting. rmon1 and rmon2 are each short inside ic. it does not connect with other pins inside ic. dummy1 to dummy4 dummy 1, 118, 129, 430 no dummy pins are connected with other pins inside ic. v dd1 logic power supply 23 to 29, 90 to 96 3.0 to 5.5 v v dd2 driver power supply 4 to 15, 104 to 115 5.0 0.5 v v ss1 logic ground 16 to 22, 97 to 103 connect this pin to ground of system. v ss2 driver ground 119 to 128, 431 to 440 connect this pin to ground of system. test test 78 to 80 fix this pin to low level.
data sheet s15806ej1v0ds 9 pd16782 5. functional description 5.1 multiplexer circuit this circuit selects rgb video signals input to the c1 to c3 pins according to the pixel array of the liquid crystal panel, and outputs the signals to the s 1 through s 300 pins. vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the mp/th and mp/1.5 pins. 5.1.1 vertical stripe array mode (mp/th = l, mp/1.5 = l) in this mode, the relation between video signals c1 to c3, and output pins is as shown below. this mode is used to drive a panel of vertical stripe array. in this mode, the multiplexer circuit is in the through status. table 5 1. relation between video signals c1 to c3, and output pins (during right shift) line no. (number of inhs) reset inh s 1 to s 300 s 2 to s 299 s 3 to s 298 s 4 to s 297 ... s 299 to s 2 s 300 to s 1 0hl sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 1l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 1. pixel arrangement of vertical stripe array and multiplexer operation r r r r r b b b b b g g g g g r r r r r b b b b b g g g g g r r r r r s 7 s 6 s 5 s 4 s 3 s 2 s 1 c1 c2 c3 r b g pd16782 right shift (r,/l = "h"), mp/th = "l", mp/1.5 = "l"
data sheet s15806ej1v0ds 10 pd16782 figure 5 2. timing chart of vertical stripe array undifined undifined c1 (c3) reset inh s 1 (s 300 ) sampling input data output

s 2 (s 299 ) sampling input data s 3 (s 298 ) sampling inputdata s 299 (s 2 ) sampling input data s 300 (s 1 ) sampling input data output output output output c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c1 (c3) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) c3 (c1) undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15806ej1v0ds 11 pd16782 5.1.2 single-side delta array mode (mp/th = l, mp/1.5 = h) table 5 2. relation between video signals c1 to c3, and output pins line no. (number of inhs) reset inh s 1 to s 300 s 2 to s 299 s 3 to s 298 s 4 to s 297 ... s 299 to s 2 s 300 to s 1 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) ... output c3 (c3) output c1 (c2) 4l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 5l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) output c3 (c3) output c1 (c2) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 3. pixel arrangement of single-side delta array and multiplexer operation r r r b b b g g g r r r b b b g g g r r r r b g r b g r s 7 s 6 s 5 s 4 s 3 s 2 s 1 c1 c2 c3 r b g pd16782 right shift (r,/l = "h"), mp/th = "l", mp/1.5 = "h" bgrbg bg r bgrbg bg r bgrbg bg r
data sheet s15806ej1v0ds 12 pd16782 figure 5 4. timing chart of single-side delta array reset inh

s 1 (s 300 ) sampling input data output s 2 (s 299 ) sampling input data s 3 (s 298 ) sampling inputdata s 299 (s 2 ) sampling input data s 300 (s 1 ) sampling input data output output output output c1 (c3) c1 (c3) c2 (c1) c2 (c1) undifined undifined undifined undifined c1 (c3) c1 (c3) c2 (c1) c2 (c1) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c3) c3 (c3) c3 (c1) c3 (c1) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c1 (c2) c1 (c2) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15806ej1v0ds 13 pd16782 5.1.3 double-side delta array mode (mp/th = h, mp/1.5 = h) table 5 3. relation between video signals c1 to c3 and output pins line no. (number of inhs) reset inh s 1 to s 300 s 2 to s 299 s 3 to s 298 s 4 to s 297 ... s 299 to s 2 s 300 to s 1 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c2 (c3) sampling c3 (c2) sampling c1 (c1) sampling c2 (c3) ... sampling c3 (c2) sampling c1 (c1) 2l output c2 (c3) output c3 (c2) output c1 (c1) output c2 (c3) ... output c3 (c2) output c1 (c1) 3l output c1 (c1) output c2 (c3) output c3 (c2) output c1 (c1) ... output c2 (c3) output c3 (c2) 4l output c2 (c3) output c3 (c2) output c1 (c1) output c2 (c3) ... output c3 (c2) output c1 (c1) 5l output c1 (c1) output c2 (c3) output c3 (c2) output c1 (c1) ... output c2 (c3) output c3 (c2) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 5. pixel arrangement of double-side delta array and multiplexer operation r r r b b b g g g r r r b b b g g g r r r s 4 s 3 s 2 s 1 c1 c2 c3 r b g pd16782 right shift (r,/l = "h"), mp/th = "h", mp/1.5 = "h" s 297 s 298 s 299 s 300 c1 c2 c3 g r b pd16782 left shift (r,/l = "l"), mp/th = "h", mp/1.5 = "h" bgrbg bg r bgrbg bg r
data sheet s15806ej1v0ds 14 pd16782 figure 5 6. timing chart of both-sides delta array reset inh

s 1 (s 300 ) sampling input data output s 2 (s 299 ) sampling input data s 3 (s 298 ) sampling inputdata s 299 (s 2 ) sampling input data s 300 (s 1 ) sampling input data output output output output c2 (c3) c2 (c3) c1 (c1) c1 (c1) undifined undifined undifined undifined c2 (c3) c2 (c3) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c3(c2) c3 (c2) c2 (c3) c2 (c3) c1 (c1) c1(c1) c3 (c2) c3 (c2) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c3 (c2) c3 (c2) c2 (c3) c2 (c3) c1 (c1) c1 (c1) c3 (c2) c3 (c2) c1 (c1) c1 (c1) c3 (c2) c3 (c2) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15806ej1v0ds 15 pd16782 5.1.4 mosaic array mode (mp/th = h, mp/1.5 = l) table 5 4. relation between video signals c1 to c3, and output pins line no. (number of inhs) reset inh s 1 to s 300 s 2 to s 299 s 3 to s 298 s 4 to s 297 ... s 299 to s 2 s 300 to s 1 0 h l undefined undefined undefined undefined ... undefined undefined 1l sampling c1 (c3) sampling c2 (c2) sampling c3 (c1) sampling c1 (c3) ... sampling c2 (c2) sampling c3 (c1) 2l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) 3l output c3 (c2) output c1 (c1) output c2 (c3) output c3 (c2) ... output c1 (c1) output c2 (c3) 4l output c2 (c1) output c3 (c3) output c1 (c2) output c2 (c1) ... output c3 (c3) output c1 (c2) 5l output c1 (c3) output c2 (c2) output c3 (c1) output c1 (c3) ... output c2 (c2) output c3 (c1) : ::::::...:: remark ( ) indicates the case of left shift. figure 5 7. pixel arrangement of mosaic array and multiplexer operation r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b g r b s 7 s 6 s 5 s 4 s 3 s 2 s 1 c1 c2 c3 r g b pd16782 right shift (r,/l = "h"), mp/th = "h", mp/1.5 = "l"
data sheet s15806ej1v0ds 16 pd16782 figure 5 8. timing chart of mosaic array reset inh

s 1 (s 300 ) sampling input data output s 2 (s 299 ) sampling input data s 3 (s 298 ) sampling inputdata s 299 (s 2 ) sampling input data s 300 (s 1 ) sampling input data output output output output c1 (c3) c1 (c3) c3 (c2) c3 (c2) undifined undifined undifined undifined c2 (c1) c2 (c1) c1 (c3) c1 (c3) c2 (c2) c2 (c2) c1 (c1) c1 (c1) c3(c3) c3 (c3) c2 (c2) c2 (c2) c3 (c1) c3(c1) c2 (c3) c2 (c3) c1 (c2) c1 (c2) c3 (c1) c3 (c1) c2 (c2) c2 (c2) c1 (c1) c1 (c1) c3 (c3) c3 (c3) c2 (c2) c2 (c2) c3 (c1) c3 (c1) c2 (c3) c2 (c3) c1 (c2) c1 (c2) c3 (c1) c3 (c1) undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined undifined
data sheet s15806ej1v0ds 17 pd16782 5.1.5 relation between shift clock clin and internal sampling pulse shpn (1) simultaneous sampling ( ( ) indicates the case of left shift.) c1 sampling c2 sampling c3 sampling shp 1 (shp 300 ) sthr (sthl) cli1 shp 2 (shp 299 ) shp 3 (shp 298 ) shp 4 (shp 297 ) shp 5 (shp 296 ) shp 6 (shp 295 ) c1 sampling c2 sampling c3 sampling remark c1 through c3 are sampled while shpn is high level. (2) successive sampling ( ( ) indicates the case of left shift.) c1 sampling 3-phase clock c2 samling c3 sampling c1 sampling c2 sampling c3 sampling shp 1 (shp 300 ) sthr (sthl) cli3 cli2 cli1 shp 2 (shp 299 ) shp 3 (shp 298 ) shp 4 (shp 297 ) shp 5 (shp 296 ) shp 6 (shp 295 )
remarks 1. input a three-phase clock to shift clock pins cli1 through cli3. 2. the video signals (c1 to c3) are sampled while shpn is high level.
data sheet s15806ej1v0ds 18 pd16782 5.2 sample and hold circuit the sample and hold circuit samples and holds the video input signals c1 through c3 selected by the multiplexer circuit in the timing shown below. swa1 through swb2 are reset by the reset signal and change at the rising and falling edges of the inh signal (refer to 1. block diagram .). reset data swa1 swa2 swb1 swb2 inh undifined on on undifined 5.3 write operation timing the sampled video signals are written to the lcd panel by output currents i vol and i voh via output buffer. the dynamic range is 4.3 v min. (v dd2 = 5.0 v). while inh = h, do not stop shift clocks cli1 through cli3. the output operation of this ic is controlled by inh signals. inh = hi-z inh = connected with internal circuit (switch sample and hold circuit at the falling edge.) therefore, performing v com inversion while inh = l causes current flow to these ic output pins, which may result in malfunction. perform v com in version during inh = h (hi-z) and start output operation of the next line after the v com signal is stable enough to operate. make sure to evaluate this output operation sufficiently.
data sheet s15806ej1v0ds 19 pd16782 cautions 1. turn on power to v dd1 , logic input, v dd2 , and video signal input in that order to prevent destruction due to latch-up, and turn off power in the reverse sequence. observe this power sequence even during the transition period. 2. the pd16782 is designed to input successive signals such as chrome signals. the input band of the video signals is designed to be 9 mhz max. if video signals faster than that are input, display is not performed correctly. 3. insert a bypass capacitor of 0.1 f between v dd1 and v ss1 and between v dd2 and v ss2 . if the power supply is not reinforced, the sampling voltage may be abnormal if the supply voltage fluctuates. 4. display may not be correctly performed if noise is superimposed on the start pulse pin. therefore, be sure to input a reset signal during the vertical blanking period. 5. even if the start pulse width is extended by half a clock or more, sampling start timing shp 1 is not affected, and the sampling operation is performed normally. 6. when the multiplexer circuit is used in the vertical stripe mode, c1 to c3 are simultaneously sampled at the rising edge of shpn. internally, however, only cli1 is valid. therefore, input a shift clock to cli1 only. at this time, keep the cli2 and cli3 pins to "l". when using the multiplexer circuit in the delta array mode or mosaic array mode, c1 to c3 are sequentially sampled. input a three-phase clock to cli1 through cli3 (for the sampling timing, refer to 2. functional description.). 7. the recommended timing of t r-1 and pw res on starting is shown below (the following timing chart shows simultaneous sampling.). an inh pulse width of at least 5 clocks is required to reset the internal logic. unless the inh pulse is input after reset, sampling is not performed in the correct sequence. cli1 reset inh sthr (sthl) shp 1 to shp 3 shp 4 to shp 6 shp 7 to shp 9 12345 123 pw res t isetup t ihold t r?i pw inh : 5 clocks min. 3 clocks min.
data sheet s15806ej1v0ds 20 pd16782 6. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = 0 v) parameter symbol condition ratings unit logic supply voltage v dd1 0.5 to +6.0 v driver supply voltage v dd2 0.5 to +6.0 v logic input voltage v i 0.5 to v dd1 +0.5 v video input voltage v vi c1 to c3 0.5 to v dd2 +0.5 v logic output voltage v 01 0.5 to v dd1 +0.5 v driver output voltage v 02 0.5 to v dd2 +0.5 v driver output current i o2 10 ma operating ambient temperature t a 30 to +85 c storage temperature t stg 65 to +125 c caution product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating conditions (t a = ?40 to +85 c, v ss1 = v ss2 = 0 v ) parameter symbol condition min. typ. max. unit logic supply voltage v dd1 3.0 3.3 5.5 v driver supply voltage v dd2 4.5 5.0 5.5 v video input voltage v vi v ss2 + 0.35 v dd2 0.35 v driver output voltage v 02 v ss2 + 0.35 v dd2 0.35 v high level input voltage v ih 0.7 v dd1 v dd1 v low level input voltage v il 00.3 v dd1 v
data sheet s15806ej1v0ds 21 pd16782 electrical characteristics (t a = 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit maximum video signal output voltage v voh v dd 2 0.35 v minimum video signal output voltage v vol 0.35 v logic high level output voltage v loh sthl, sthr pins, i oh = 1.0 ma 0.9 v dd1 v logic low level output voltage v lol sthl, sthr pins i ol = 1.0 ma 0.1 v dd1 v video signal high level output current i voh inh = l, v of = v dd2 1.0 v v o = v dd2 0.5 v 0.20 0.08 ma video signal low level output current i vol inh = l, v of = 1.0 v, v o = 0.5 v 0.08 0.20 ma reference voltage 1 v ref1 v dd2 = 5.0 v, t a = 25 c, v vi = 0.5 v 0.49 v reference voltage 2 v ref2 v dd2 = 5.0 v, t a = 25 c, v vi = 2.0 v 1.99 v reference voltage 3 v ref3 v dd2 = 5.0 v, t a = 25 c, v vi = 3.5 v 3.49 v output voltage deviation 1 v vo1 v dd2 = 5.0 v, t a = 25 c, v vi = 0.5 v 30 mv output voltage deviation 2 v vo2 v dd2 = 5.0 v, t a = 25 c, v vi = 2.0 v 30 mv output voltage deviation 3 v vo3 v dd2 = 5.0 v, t a = 25 c, v vi = 3.5 v 30 mv logic input except osel 1.0 a logic input leakage current i ll osel, v i = v dd = 3.3 v 90 a video input leakage current i vl 10 a v dd1 = 3.3 0.3 v 3 ma logic dynamic current consumption i dd1 f cli = 14 mhz v vi = 2.0 v, no load, f inh = 15.4 khz, pw inh = 5.0 s v dd1 = 5.0 0.5 v 4.5 ma driver dynamic current consumption i dd2 f cli = 14 mhz v vi = 2.0 v, no load, f inh = 15.4 khz, pw inh = 5.0 s 12 ma remarks 1. v of : output applied voltage, v o : output voltage without load 2. the reference values are typical values only. the output deviation is only guaranteed within the chip.
data sheet s15806ej1v0ds 22 pd16782 switching characteristics (t a = 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit t phl c l = 20 pf 10 54 ns start pulse propagation delay time t plh c l = 20 pf 10 54 ns clock frequency 1 f clk 1 15 mhz clock frequency 2 f clk 2 with 3-phase clock input 8 mhz logic input capacitance c i1 other than sthl, sthr 15 pf sthl, sthr input capacitance c i2 sthl, sthr 20 pf video input capacitance c 3 c1 to c3, v vi = 2.0 v 50 pf timing requirements (t a = 30 to +85 c, v dd1 = 3.0 to 5.5 v, v dd2 = 5.0 v 0.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit clock pulse width pw cli duty = 50% 33 ns start pulse setup time t setup 8ns start pulse hold time t hold 8ns reset pulse width pw res 66 ns inh setup time t isetup 33 ns inh hold time t ihold 33 ns reset-inh time t r-i 81 ns inh pulse width pw inh 5clk remark keep the rise and fall times of the logic input signals to within t r = t f = 5 ns (10 to 90%). as an example, the switching characteristic wave of cli1 is defined on the next page.
data sheet s15806ej1v0ds 23 pd16782 switching characteristic waveform (simultaneous/successive sampling) start pulse input timing 1/f cli 1 pw cli 1pw cli 1 50% 50% 50% 50% t setup t hold cli1 sthr (sthl) shp 1 (shp 300 ) v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 start pulse output timing 50% 50% t plh 50% 50% t phl cli1 sthl (sthr) v dd1 v ss1 v oh v ol remark the input/output timing of the start pulse is the same for simultaneous/successive sampling.
data sheet s15806ej1v0ds 24 pd16782 reset inh pulse timing cli1 reset inh pw res t isetup t iihold pw inh t r-i 50% 50% 50% 50% 50%
data sheet s15806ej1v0ds 25 pd16782 notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function.
pd16782 reference documents nec semiconductor device reliability/quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of december, 2002. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such nec electronics products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact nec electronics sales representative in advance to determine nec electronics's willingness to support a given application. (note) (1) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. (2) "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). m8e 02. 11

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