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| this is information on a product in full production. may 2017 docid018780 rev 9 1/122 stm8l151c2/k2/g2/f2 stm8l151c3/k3/g3/f3 8-bit ultra-low-power mcu, up to 8 kb flash, up to 256 b data eeprom, rtc, timers, usart, i2c, spi, adc, comparators datasheet - production data features ? operating conditions ? operating power supply: 1.65 to 3.6 v (without bor), 1.8 to 3.6 v (with bor) ? temperature range: -40 to 85 or 125 c ? low power features ? 5 low-power modes: wait, low power run, low-power wait, active-halt with rtc, halt ? ultra-low leakage per i/0: 50 na ? fast wakeup from halt: 5 s ? advanced stm8 core ? harvard architecture and 3-stage pipeline ? max freq: 16 mhz, 16 cisc mips peak ? up to 40 external interrupt sources ? reset and supply management ? low-power, ultra safe bor reset with 5 selectable thresholds ? ultra-low power por/pdr ? programmable voltage detector (pvd) ? clock management ? 32 khz and 1-16 mhz crystal oscillators ? internal 16 mhz factory-trimmed rc ? internal 38 khz low consumption rc ? clock security system ? low power rtc ? bcd calendar with alarm interrupt ? digital calibration with +/- 0.5 ppm accuracy ? lse security system ? auto-wakeup from halt w/ periodic interrupt ? memories ? up to 8 kbyte of flash program memory plus 256 byte of data eeprom with ecc ? flexible write/read protection modes ? 1 kbyte of ram ? dma ? 4 channels supporting adc, spi, i 2 c, usart, timers ? 1 channel for memory-to-memory ? 12-bit adc up to 1 msps/28 channels ? temp. sensor and internal ref. voltage ? 2 ultra-low-power comparators ? 1 with fixed threshol d and 1 rail to rail ? wakeup capability ? timers ? two 16-bit timers with 2 channels (ic, oc, pwm), quadrature encoder (tim2, tim3) ? one 8-bit timer with 7-bit prescaler (tim4) ? 1 window and 1 independent watchdog ? beeper timer with 1, 2 or 4 khz frequencies ? communication interfaces ? one synchronous serial interface (spi) ?fast i 2 c 400 khz ? one usart ? up to 41 i/os, all mappab le on interrupt vectors ? up to 20 capacitive sensing channels supporting touchkey, pr oximity touch, linear touch, and rotary touch sensors ? development support ? fast on-chip programming and non- intrusive debugging with swim ? bootloader using usart ? 96-bit unique id lqfp48 (7x7 mm) ufqfpn32 (5x5 mm) ufqfpn28 (4x4 mm) ufqfpn20 (3x3 mm) tssop20 (6.4x4.4 mm) www.st.com
contents stm8l151x2, stm8l151x3 2/122 docid018780 rev 9 contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 ultra-low-power continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.1 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 central processing unit stm8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.1 advanced stm8 core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2.2 interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.1 power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.2 power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.4 clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.5 low power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.6 memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.7 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.8 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.9 ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 system configuration controller and routi ng interface . . . . . . . . . . . . . . . 21 3.11 touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.12.1 16-bit general purpose timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12.2 8-bit basic timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13.1 window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13.2 independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.14 beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.15 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.1 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 docid018780 rev 9 3/122 stm8l151x2, stm8l151x3 contents 4 3.15.2 i2c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.15.3 usart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.16 infrared (ir) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.17 development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4 pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 system configuration options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5 memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.1 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 5.2 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6 interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 7 option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 8 unique id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 9 electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1 parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.1 minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.2 typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.3 typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.4 loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 9.1.5 pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 9.3 operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3.1 general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.3.2 embedded reset and power control bloc k characteristics . . . . . . . . . . . 58 9.3.3 supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 9.3.4 clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 9.3.5 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 9.3.6 i/o current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.7 i/o port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 9.3.8 communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 9.3.9 embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 9.3.10 temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 contents stm8l151x2, stm8l151x3 4/122 docid018780 rev 9 9.3.11 comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 9.3.12 12-bit adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 9.3.13 emc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 10 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.1 ecopack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.2 lqfp48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 10.3 ufqfpn32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 10.4 ufqfpn28 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 10.5 ufqfpn20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 10.6 tssop20 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 10.7 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118 11 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 12 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 docid018780 rev 9 5/122 stm8l151x2, stm8l151x3 list of tables 6 list of tables table 1. low-density stm8l151x2/3 low power device features and peripheral counts . . . . . . . . . 12 table 2. timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 3. legend/abbreviation for table 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 4. low-density stm8l151x2/3 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 5. flash and ram boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 6. factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 7. i/o port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 8. general hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 table 9. cpu/swim/debug module/interrupt controller registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 10. interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 table 11. option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 12. option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 13. unique id registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 14. voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 table 15. current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 16. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 table 17. general operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table 18. embedded reset and power control block characterist ics. . . . . . . . . . . . . . . . . . . . . . . . . . 58 table 19. total current consumption in run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 table 20. total current consumption in wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 table 21. total current consumption and timing in low power run mode at vdd = 1.65 v to 3.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 table 22. total current consumption in low power wait mode at vdd = 1.65 v to 3.6 v . . . . . . . . . 67 table 23. total current consumption a nd timing in active-halt mode at vdd = 1.65 v to 3.6 v. . . . . 69 table 24. typical current consumption in active-hal t mode, rtc clocked by lse external crystal . . 69 table 25. total current consumption and timing in halt mode at vdd = 1.65 to 3.6 v . . . . . . . . . . . 70 table 26. peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 table 27. current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 28. hse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 29. lse external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 table 30. hse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 table 31. lse oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 table 32. hsi oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 33. lsi oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 table 34. ram and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 35. flash program and da ta eeprom memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 table 36. i/o current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 table 37. i/o static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 table 38. output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 39. output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 table 40. output driving current (pa0 wi th high sink led driver capability). . . . . . . . . . . . . . . . . . . . 83 table 41. nrst pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 42. spi1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 table 43. i2c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 44. reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 45. ts characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 46. comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 47. comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 list of tables stm8l151x2, stm8l151x3 6/122 docid018780 rev 9 table 48. adc1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 49. adc1 accuracy with vdda = 3.3 v to 2.5 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 50. adc1 accuracy with vdda = 2.4 v to 3.6 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 51. adc1 accuracy with vdda = vref+ = 1.8 v to 2.4 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 table 52. r ain max for f adc = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 53. ems data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 54. emi data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 55. esd absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2 table 56. electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 57. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 table 58. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 table 59. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 table 60. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 table 61. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 table 62. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 table 63. low-density stm8l151x2/3 ordering information sc heme. . . . . . . . . . . . . . . . . . . . . . . . 119 table 64. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 docid018780 rev 9 7/122 stm8l151x2, stm8l151x3 list of figures 8 list of figures figure 1. low-density stm8l151x2/3 device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 2. low-density stm8l151x2/3 clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 3. stm8l151cx lqfp48 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 4. stm8l151kx ufqfpn32 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 5. stm8l151gx ufqfpn28 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 6. stm8l151fx ufqfpn20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 7. stm8l151fx tssop20 package pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 8. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 9. pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10. pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 11. por/bor thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 12. typ. idd(run) vs. vdd, fcpu = 16 mhz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 13. typ. idd(wait) vs. vdd, fcpu = 16 mhz 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 14. typ. idd(lpr) vs. vdd (lsi cloc k source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 15. typ. idd(lpw) vs. vdd (lsi cloc k source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 16. hse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 figure 17. lse oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 figure 18. typical hsi frequency vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 figure 19. typical lsi frequency vs. vdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 figure 20. typical vil and vih vs vdd (high sink i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 21. typical vil and vih vs vdd (true open drain i/os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 22. typical pull-up resistance r pu vs v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 23. typical pull-up current i pu vs v dd with vin=vss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 24. typ. vol @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 25. typ. vol @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 26. typ. vol @ vdd = 3.0 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 27. typ. vol @ vdd = 1.8 v (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 28. typ. vdd - voh @ vdd = 3.0 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 29. typ. vdd - voh @ vdd = 1.8 v (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 30. typical nrst pull-up resistance r pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 31. typical nrst pull-up current i pu vs v dd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 32. recommended nrst pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 33. spi1 timing diagram - slave mode and cpha=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 34. spi1 timing diagram - slave mode and cpha=1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 35. spi1 timing diagram - master mode (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 figure 36. typical application with i2c bus and timing diagram 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 37. adc1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 38. typical connection diagram using the adc1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 39. power supply and reference decoupling (v ref+ not connected to v dda ). . . . . . . . . . . . . . 99 figure 40. power supply and reference decoupling (vref+ connected to vdda) . . . . . . . . . . . . . . . 99 figure 41. max. dynamic current consumption on v ref+ supply pin during adc conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 42. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 103 figure 43. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 44. lqfp48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 45. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 list of figures stm8l151x2, stm8l151x3 8/122 docid018780 rev 9 figure 46. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 47. ufqfpn32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 48. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 49. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 50. ufqfpn28 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 51. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 52. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 figure 53. ufqfpn20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 54. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 figure 55. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 figure 56. tssop20 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 docid018780 rev 9 9/122 stm8l151x2, stm8l151x3 introduction 49 1 introduction this document describes the features, pinout, mechanical data and ordering information for the low-density stm8l151x2/3 devices: stm8l1 51x2 and stm8l151x3 microcontrollers with a flash memory density of up to 8 kbyte. for further details on the stmicroelectronics ultra-low-power family please refer to section 2.2: ultra-low-power continuum on page 13 . for detailed information on device operation and registers, refer to the reference manual (rm0031). for information on to the flash program memory and data eeprom, refer to the programming manual (pm0054). for information on the debug module and swim (single wire interface module), refer to the stm8 swim communication protocol and debug module user manual (um0470). for information on the stm8 core, refer to the stm8 cpu programming manual (pm0044). low-density devices provide the following benefits: ? integrated system ? up to 8 kbyte of low-density embedded flash program memory ? 256 byte of data eeprom ? 1 kbyte of ram ? internal high-speed and low-power low speed rc. ? embedded reset ? ultra-low-power consumption ? 1 a in active-halt mode ? clock gated system and optimized power management ? capability to execute from ram for low power wait mode and low power run mode ? advanced features ? up to 16 mips at 16 mhz cpu clock frequency ? direct memory access (dma) for memory -to-memory or peripheral-to-memory access. ? short development cycles ? application scalability acro ss a common family prod uct architecture with compatible pinout, memory map and modular peripherals. ? wide choice of development tools introduction stm8l151x2, stm8l151x3 10/122 docid018780 rev 9 stm8l ultra-low-power microcontrollers can operate either from 1.8 to 3.6 v (down to 1.65 v at power-down) or from 1.65 to 3.6 v. they are available in the -40 to +85 c and -40 to +125 c temperature ranges. these features make the stm8l ultra-low-power microcontrolle r families suitable for a wide range of applications: ? medical and hand-held equipment ? application control and user interface ? pc peripherals, gaming, gps and sport equipment ? alarm systems, wired and wireless sensors ? metering the devices are offered in five different packages from 20 to 48 pins. different sets of peripherals are included depending on the device. refer to section 3 for an overview of the complete range of peripherals proposed in this family. all stm8l ultra-low-power products are bas ed on the same architecture with the same memory mapping and a coherent pinout. figure 1 shows the block diagram of the stm8l low-density family. docid018780 rev 9 11/122 stm8l151x2, stm8l151x3 description 49 2 description the low-density stm8l151x2/3 ultra-low-powe r devices feature an enhanced stm8 cpu core providing increased processing power (up to 16 mips at 16 mhz) while maintaining the advantages of a cisc architecture with improv ed code density, a 24-bit linear addressing space and an optimized architectu re for low power operations. the family includes an integrated debug modu le with a hardware in terface (swim) which allows non-intrusive in-application debugging and ultrafast flash programming. all low-density stm8l 151x2/3 microcontrollers feat ure embedded data eeprom and low- power low-voltage single-supply program flash memory. the devices incorporate an extensive range of enhanced i/os and peripherals, a 12-bit adc, two comparators, a real-time clock, two 16-bit timers, one 8-bit timer, as well as standard communication interfaces such as an spi, an i 2 c interface, and one usart. the modular design of the peripheral set allows the same peripherals to be found in different st microcontroller families including 32-bit families. this ma kes any transition to a different family very easy, and simplified even more by the use of a common set of development tools. description stm8l151x2, stm8l151x3 12/122 docid018780 rev 9 2.1 device overview table 1. low-density stm8l151x2/3 low pow er device features and peripheral counts features STM8L151F3 stm8l151g3 stm8l151k3/ stm8l151c3 stm8l151f2 stm8l151g2 stm8l151k2/ stm8l151c2 flash (kbyte) 8 4 data eeprom (byte) 256 ram (kbyte) 1 timers basic 1 (8-bit) general purpose 2 (16-bit) commun -ication interfaces spi 1 i2c 1 usart 1 gpios 18 (1) 26 (1) 30 (2) /41 (1)(2) 18 (1) 26 (1) 30 (2) /41 (1)(2) 12-bit synchronized adc (number of channels) 1 (10) 1 (18) 1 (23/28) (3) 1 (10) 1 (18) 1 (23/28) (3) comparators (comp1/comp2) 2 others rtc, window watchdog, independent watchdog, 16-mhz and 38-khz internal rc, 1- to 16-mhz and 32-khz external oscillator cpu frequency 16 mhz operating voltage 1.8 to 3.6 v (down to 1.65 v at power-down) with bor 1.65 to 3.6 v without bor operating temperature ? 40 to +85 c / ? 40 to +125 c packages tssop20 ufqfpn20 ufqfpn28 ufqfpn32 lqfp48 tssop20 ufqfpn20 ufqfpn28 ufqfpn32 lqfp48 1. the number of gpios given in this t able includes the nrst/pa1 pin but the app lication can use the nrst/pa1 pin as general purpose output only (pa1). 2. 26 gpios in the stm8l151k3 and 40 gpios in the stm8l151c3. 3. 22 channels in the stm8l151k3 and 28 channels in the stm8l151c3. docid018780 rev 9 13/122 stm8l151x2, stm8l151x3 description 49 2.2 ultra-low-power continuum the ultra-low-power low-density stm8l151x2/3 devices are fully pin-to-pin, software and feature compatib le. besides the full compatibility within the family, the devi ces are part of stmicroelectronics microcontrollers ultra- low-power strategy which also includes stm8l101xx and stm8l15xxx. the stm8l and stm32l fam ilies allow a continuum of performance, peripherals, system architecture, and features. they are all based on stmicroelectronics 0.13 m ultra-low leakage process. note: 1 the stm8l151xx and stm8l152xx are pin-to-pin compatible with stm8l101xx devices. performance all families incorpor ate highly energy-efficient cores with both harvard architecture and pipelined execution: advanced stm8 core for stm8l families and arm ? cortex ? -m3 core for stm32l family. in addition specific care for the design architecture has been taken to optimize the ma/dmips and ma/mhz ratios. this allows the ultra-low-power performance to range from 5 up to 33.3 dmips. shared peripherals stm8l151xx/152xx and stm8l15xxx share identical peripherals which ensure a very easy migration from one family to another: ? analog peripherals: adc1 and comparators comp1/comp2 ? digital peripherals: rtc and some communication interfaces common system strategy to offer flexibility and optim ize performance, the stm8l 151xx/152xx and stm8l15xxx devices use a common architecture: ? same power supply range from 1.8 to 3.6 v, down to 1.65 v at power down ? architecture optimized to reach ultra-low consumption both in low power modes and run mode ? fast startup strategy from low power modes ? flexible system clock ? ultra-safe reset: same reset strategy for both stm8l15x and stm32l15xxx including power-on reset, power-down reset, brownout reset and programmable voltage detector. features st ultra-low-power continuum al so lies in feature compatibility: ? more than 10 packages with pin count from 20 to 100 pins and size down to 3 x 3 mm ? memory density ranging from 4 to 128 kbyte functional overview stm8l151x2, stm8l151x3 14/122 docid018780 rev 9 3 functional overview figure 1. low-density stm8l1 51x2/3 device block diagram 1. legend : adc: analog-to-digital converter bor: brownout reset dma: direct memory access i2c: inter-integrated circuit multi master interface iwdg: independent watchdog por/pdr: power on reset / power down reset rtc: real-time clock spi: serial peripheral interface swim: single wire interface module usart: universal synchronous asyn chronous receiver transmitter wwdg: window watchdog 2. there is no tim1 on stm8l151x2, stm8l151x3 devices. - 3 6 # l o c k c o n t r o l l e r a n d # 3 3 # l o c k s ! d d r e s s c o n t r o l a n d d a t a b u s e s + b y t e + b y t e 2 ! - t o c o r e a n d p e r i p h e r a l s ) 7 $ ' k ( z c l o c k 0 o r t ! 0 o r t " 0 o r t # 0 o w e r 6 / , 4 2 % ' 7 7 $ ' b y t e 0 o r t $ 0 o r t % " e e p e r 2 4 # m e m o r y 0 r o g r a m $ a t a % % 0 2 / - 6 $ $ 6 $ $ 6 $ $ 6 6 3 3 3 7 ) - 3 # , 3 $ ! 3 0 ) ? - / 3 ) 3 0 ) ? - ) 3 / 3 0 ) ? 3 # + 3 0 ) ? . 3 3 5 3 ! 2 4 ? 2 8 5 3 ! 2 4 ? 4 8 5 3 ! 2 4 ? # + ! $ # ? ) . x # / - 0 ? ) . 0 # / - 0 # / - 0 # / - 0 ? ) . 0 6 $ $ ! 6 3 3 ! 3 - " 6 $ $ ! 6 3 3 ! 4 e m p s e n s o r b i t ! $ # 6 $ $ 2 % & 6 . 2 3 4 0 ! ; = 0 " ; = 0 # ; = 0 $ ; = 0 % ; = 0 & " % % 0 ! , ! 2 - # ! , ) " 0 / 2 0 $ 2 / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? ) . / 3 # ? / 5 4 t o " / 2 0 6 $ 0 6 $ ? ) . 2 % 3 % 4 $ - ! c h a n n e l s c h a n n e l s c h a n n e l s # / - 0 ? ) . - ) n t e r n a l r e f e r e n c e v o l t a g e 6 2 % & ) . 4 o u t ) 2 ? 4 ) - - ( z o s c i l l a t o r - ( z i n t e r n a l 2 # k ( z o s c i l l a t o r 3 4 - # o r e b i t 4 i m e r k ( z i n t e r n a l 2 # ) n t e r r u p t c o n t r o l l e r b i t 4 i m e r $ e b u g m o d u l e 3 7 ) - b i t 4 i m e r ) n f r a r e d i n t e r f a c e 3 0 ) ) # 5 3 ! 2 4 6 3 3 2 % & 0 o r t & u p t o docid018780 rev 9 15/122 stm8l151x2, stm8l151x3 functional overview 49 3.1 low-power modes the low-density stm8l151x2/3 devices support five low power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: ? wait mode : the cpu clock is stopped, but selected peripherals keep running. an internal or external interrupt or a reset can be used to exit the microcontroller from wait mode (wfe or wfi mode). wait consumption: refer to table 20 . ? low power run mode : the cpu and the selected peripherals are running. execution is done from ram with a low speed oscillator (lsi or lse). flash and data eeprom are stopped and the voltage regulator is configured in ultra-low-power mode. the microcontroller enters low power run mode by software and can exit from this mode by software or by a reset. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power run mode consumption: refer to table 21 . ? low power wait mode: this mode is entered when executing a wait for event in low power run mode. it is similar to low powe r run mode except that the cpu clock is stopped. the wakeup from this mode is triggered by a reset or by an internal or external event (peripheral event generate d by the timers, serial interfaces, dma controller (dma1), comparators and i/o ports). when the wakeup is triggered by an event, the system goes back to low power run mode. all interrupts must be masked. they cannot be used to exit the microcontroller from this mode. low power wait mode consumption: refer to table 22 . ? active-halt mode : cpu and peripheral clocks are stopped, except rtc. the wakeup can be triggered by rtc interrupts, external interrupts or reset. active-halt consumption: refer to table 23 and table 24 . ? halt mode : cpu and peripheral clocks are sto pped, the device remains powered on. the ram content is preserved. the wakeup is triggered by an external interrupt or reset. a few peripheral s have also a wakeup from halt capability. switching off the internal reference voltage reduces power co nsumption. through software configuration it is also possible to wake up the device without waiting for the internal reference voltage wakeup time to have a fast wakeup time of 5 s. halt consumption: refer to table 25 . 3.2 central proc essing unit stm8 3.2.1 advanced stm8 core the 8-bit stm8 core is designed for code efficiency and performance with an harvard architecture and a 3-stage pipeline. it contains 6 internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect an d relative addressing, and 80 instructions. functional overview stm8l151x2, stm8l151x3 16/122 docid018780 rev 9 architecture and registers ? harvard architecture ? 3-stage pipeline ? 32-bit wide program memory bus - single cycle fetching most instructions ? x and y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations ? 8-bit accumulator ? 24-bit program counter - 16 mbyte linear memory space ? 16-bit stack pointer - access to a 64 kbyte level stack ? 8-bit condition code register - 7 condition fl ags for the result of the last instruction addressing ? 20 addressing modes ? indexed indirect addressing mode for lookup tables located anywhere in the address space ? stack pointer relative addressing mode for local variables and parameter passing instruction set ? 80 instructions with 2-byte average instruction size ? standard data movement and logic/arithmetic functions ? 8-bit by 8-bit multiplication ? 16-bit by 8-bit and 16-bit by 16-bit division ? bit manipulation ? data transfer between stack and accumu lator (push/pop) with direct stack access ? data transfer using the x and y registers or direct memory-to-memory transfers 3.2.2 interrupt controller the low-density stm8l151x2/3 feature a nested vectored interrupt controller: ? nested interrupts with 3 software priority levels ? 32 interrupt vectors with hardware priority ? up to 40 external interrupt sources on 11 vectors ? trap and reset interrupts docid018780 rev 9 17/122 stm8l151x2, stm8l151x3 functional overview 49 3.3 reset and supply management 3.3.1 power supply scheme the device requires a 1.65 v to 3.6 v operating supply voltage (v dd ). the external power supply pins must be connected as follows: ? v ss1 ; v dd1 = 1.8 to 3.6 v, down to 1.65 v at power down: external power supply for i/os and for the internal regulator. provided externally through v dd1 pins, the corresponding ground pin is v ss1 . ? v ssa; v dda = 1.8 to 3.6 v, down to 1.65 v at power down: external power supplies for analog peripherals (minimum voltage to be applied to v dda is 1.8 v when the adc1 is used). v dda and v ssa must be connected to v dd1 and v ss1 , respectively. ? v ss2 ; v dd2 = 1.8 to 3.6 v, down to 1.65 v at power down: external power supplies for i/os. v dd2 and v ss2 must be connected to v dd1 and v ss1 , respectively. ? v ref+ ; v ref- (for adc1): external reference voltage for adc1. must be provided externally through v ref+ and v ref- pin. 3.3.2 power supply supervisor the device has an integrated zeropower power-on reset (por)/power-down reset (pdr), coupled with a brownout reset (bor) circ uitry. at power-on, bor is always active, and ensures proper operation starting from 1.8 v. after the 1.8 v bor threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable bor permanently (in which case, the v dd min value at power down is 1.65 v). five bor thresholds are available thro ugh option bytes, starting from 1.8 v to 3 v. to reduce the power consumption in halt mode, it is possible to automatically switch off the internal reference voltage (and consequently the bor) in halt mode. the device remains under reset when v dd is below a specified threshold, v por/pdr or v bor , without the need for any external reset circuit. the device features an embedded programmable voltage detector (pvd) that monitors the v dd /v dda power supply and compares it to the v pvd threshold. this pvd offers 7 different levels between 1.85 v and 3.05 v, chosen by software, with a step around 200 mv. an interrupt can be generated when v dd /v dda drops below the v pvd threshold and/or when v dd /v dda is higher than the v pvd threshold. the interrupt service routine can then generate a warning message and/or put the mcu into a safe state. the pvd is enabled by software. 3.3.3 voltage regulator the low-density stm8l151x2/3 embeds an intern al voltage regulator for generating the 1.8 v power supply for the core and peripherals. this regulator has two different modes: ? main voltage regulator mode (mvr) for run, wait for interrupt (wfi) and wait for event (wfe) modes. ? low power voltage regulator mode (lpvr) for halt, active-halt, low power run and low power wait modes. when entering halt or active -halt modes, the system automatic ally switches from the mvr to the lpvr in order to reduce current consumption. functional overview stm8l151x2, stm8l151x3 18/122 docid018780 rev 9 3.4 clock management the clock controller distributes the system cloc k (sysclk) coming from different oscillators to the core and the peripherals. it also manages clock gating for low power modes and ensures clock robustness. features ? clock prescaler: to get the best compromise between speed and current consumption the clock frequency to the cpu and peripherals can be adjusted by a programmable prescaler ? safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. ? clock management: to reduce power consumption, th e clock controller can stop the clock to the core, individual peripherals or memory. ? system clock sources: 4 different clock sources can be used to drive the system clock: ? 1-16 mhz high speed external crystal (hse) ? 16 mhz high speed internal rc oscillator (hsi) ? 32.768 khz low speed external crystal (lse) ? 38 khz low speed internal rc (lsi) ? rtc clock sources: the above four sources can be chosen to clock the rtc whatever the system clock. ? startup clock: after reset, the microcontroller rest arts by default with an internal 2 mhz clock (hsi/8). the prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. ? clock security system (css): this feature can be enabled by software. if a hse clock failure occurs, the system clock is automatically switched to hsi. ? configurable main clock output (cco): this outputs an external clock for use by the application. docid018780 rev 9 19/122 stm8l151x2, stm8l151x3 functional overview 49 figure 2. low-density stm8l1 51x2/3 clock tree diagram 3.5 low power real-time clock the real-time clock (rtc) is an independent binary coded decimal (bcd) timer/counter. six byte locations contain the second, minute, hour (12/24 hour), week day, date, month, year, in bcd (binary coded decimal) format. correction for 28, 29 (leap year), 30, and 31 day months are made automatically. it provides a programmable alarm and programmable periodic interrupts with wakeup from halt capability. ? periodic wakeup time using the 32.768 khz lse with the lowest resolution (of 61 s) is from min. 122 s to max. 3.9 s. with a di fferent resolution, the wakeup time can reach 36 hours ? periodic alarms based on the calendar can also be generated from every second to every year 2 6 & b 2 8 7 2 6 & b , 1 + 6 ( + 6 , / 6 , / 6 ( / 6 ( / 6 , + 6 ( 2 6 & 0 + ] + 6 , 5 & 0 + ] / 6 , 5 & n + ] / 6 ( 2 6 & n + ] 2 6 & b 2 8 7 2 6 & b , 1 & & 2 & r q i l j x u d e o h f o r f n r x w s x w s u h v f d o h u & & 2 + 6 ( + 6 , / 6 , / 6 ( s u h v f d o h u 6 < 6 & / . 6 < 6 & / . w r f r u h d q g p h p r u \ 3 & / . w r s h u l s k h u d o v 3 h u l s k h u d o & o r f n & / . % ( ( 3 6 ( / > @ , : ' * & / . % ( ( 3 & / . 5 7 & & / . h q d e o h e l w v 5 7 & 6 ( / > @ 5 7 & s u h v f d o h u w r % ( ( 3 w r , : ' * w r 5 7 & 0 6 9 6 : , 0 > @ & & 2 6 ( / > @ functional overview stm8l151x2, stm8l151x3 20/122 docid018780 rev 9 3.6 memories the low-density stm8l151x2/3 devices have the following main features: ? up to 1 kbyte of ram ? the non-volatile memory is divided into three arrays: ? up to 8 kbyte of low-density embedded flash program memory ? 256 byte of data eeprom ? option bytes. the eeprom embeds the error correction co de (ecc) feature. the option byte protects part of the flash program memory from write and readout piracy. 3.7 dma a 4-channel direct memory ac cess controller (dma1) offe rs a memory-to-memory and peripherals-from/to-memory tr ansfer capability. the 4 ch annels are shar ed between the following ips with dma capa bility: adc1, i2c1, spi1, usart1, the three timers. 3.8 analog-to-digital converter ? 12-bit analog-to-digital converter (adc1) wi th 25 channels (including 1 fast channel), temperature sensor and internal reference voltage ? conversion time down to 1 s with f sysclk = 16 mhz ? programmable resolution ? programmable sampling time ? single and continuous mode of conversion ? scan capability: automatic conversion perfo rmed on a selected gr oup of analog inputs ? analog watchdog ? triggered by timer note: adc1 can be served by dma1. 3.9 ultra-low-power comparators the low-density stm8l151x2/3 embed two comparators (comp1 and comp2) sharing the same current bias and voltage reference. the voltage reference can be internal or external (coming from an i/o). ? one comparator with fixed threshold (comp1). ? one comparator rail to rail with fast or sl ow mode (comp2). the threshold can be one of the following: ? external i/o ? internal reference voltage or internal reference voltage sub multiple (1/4, 1/2, 3/4) the two comparators can be used together to offer a window function. they can wake up from halt mode. docid018780 rev 9 21/122 stm8l151x2, stm8l151x3 functional overview 49 3.10 system configur ation controller an d routing interface the system configuration cont roller provides the capabilit y to remap some alternate functions on different i/o ports. tim4 and adc1 dma channels can also be remapped. the highly flexible routing inte rface controls the routing of in ternal analog signals to adc1, comp1, comp2, and the internal reference voltage v refint . it also provides a set of registers for efficiently managing the ch arge transfer acquisition sequence ( section 3.11: touch sensing ). 3.11 touch sensing low-density stm8l151x2/3 devices provide a si mple solution for adding capacitive sensing functionality to any a pplication. capacitive sensing technology is able to detect finger presence near an electrode which is protected from direct touch by a dielectric (example, glass, plastic). the capacitive variation introduc ed by a finger (or any conductive object) is measured using a proven implementation base d on a surface charge transfer acquisition principle. it consists of charging the electrode capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. in low-density stm8l15xxx devices, the acquisition sequence is managed either by software or by hardware and it involves analog i/o groups, the routing interface, and timers.relia ble touch sensing solutions can be quickly and easily implemented using the free stm8 touch sensing library. 3.12 timers low-density stm8l151x2/3devices contain two 16-bit general purpose timers (tim2 and tim3) and one 8-bit basic timer (tim4). all the timers can be served by dma1. table 2 compares the features of the advanced control, general-purpose and basic timers. table 2. timer feature comparison timer counter resolution counter type prescaler factor dma1 request generation capture/compare channels complementary outputs tim2 16-bit up/down any power of 2 from 1 to 128 yes 2 none tim3 tim4 8-bit up any power of 2 from 1 to 32768 0 functional overview stm8l151x2, stm8l151x3 22/122 docid018780 rev 9 3.12.1 16-bit general purpose timers ? 16-bit autoreload (ar) up/down-counter ? 7-bit prescaler adjustable to fixed power of 2 ratios (1?128) ? 2 individually configurable capture/compare channels ? pwm mode ? interrupt capability on various events (capt ure, compare, overfl ow, break, trigger) ? synchronization with other timers or external signals (external clock, reset, trigger and enable) 3.12.2 8-bit basic timer the 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable prescaler. it can be used for timebase gene ration with interrupt generation on timer overflow. 3.13 watchdog timers the watchdog system is based on two independent timers providing maximum security to the applications. 3.13.1 window watchdog timer the window watchdog (wwdg) is used to detect the occurrence of a software fault, usually generated by external interferences or by un expected logical conditions, which cause the application program to abandon its normal sequence. 3.13.2 independent watchdog timer the independent watchdog peripheral (iwdg) can be used to resolve processor malfunctions due to hardware or software failures. it is clocked by the internal lsi rc clock source, and thus stays active even in case of a cpu clock failure. 3.14 beeper the beeper function outputs a si gnal on the beep pin for sound generation. the signal is in the range of 1, 2 or 4 khz. docid018780 rev 9 23/122 stm8l151x2, stm8l151x3 functional overview 49 3.15 communication interfaces 3.15.1 spi the serial peripheral interface (spi1) provides half/ full duplex synchronous serial communication with external devices. ? maximum speed: 8 mbit/s (f sysclk /2) both for master and slave ? full duplex synchronous transfers ? simplex synchronous transfers on 2 lines with a possible bidirectional data line ? master or slave operation - selectable by hardware or software ? hardware crc calculation ? slave/master selection input pin note: spi1 can be served by the dma1 controller. 3.15.2 i2c the i 2 c bus interface ( i 2 c1 ) provides multi-mast er capability, and controls all i2c bus- specific sequencing, protocol, arbitration and timing. ? master, slave and mult i-master capability ? standard mode up to 100 khz and fast speed modes up to 400 khz. ? 7-bit and 10-bit addressing modes. ? smbus 2.0 and pmbus support ? hardware crc calculation note: i 2 c1 can be served by the dma1 controller. 3.15.3 usart the usart interface (usart1) allows full duplex, asynchronous communications with external devices requiring an industry standard nrz asynchronous serial data format. it offers a very wide range of baud rates. ? 1 mbit/s full duplex sci ? spi1 emulation ? high precision baud rate generator ? smartcard emulation ? irda sir encoder decoder ? single wire half duplex mode note: usart1 can be served by the dma1 controller. 3.16 infrared (ir) interface the low-density stm8l151x2/3 devices contai n an infrared interface which can be used with an ir led for remote control functions. two timer output compare channels are used to generate the infrared remote control signals. functional overview stm8l151x2, stm8l151x3 24/122 docid018780 rev 9 3.17 development support development tools development tools for the stm8 microcontrollers include: ? the stice emulation system offeri ng tracing and code profiling ? the stvd high-level language debugger including c compiler, assembler and integrated development environment ? the stvp flash programming software the stm8 also comes with starter kits, ev aluation boards and low-cost in-circuit debugging/programming tools. single wire data interface (swim) and debug module the debug module with its single wire data inte rface (swim) permits non-intrusive real-time in-circuit debugging and fast memory programming. the single-wire interface is used for direct access to the debugging module and memory programming. the interface can be acti vated in all device operation modes. the non-intrusive debugging module features a performance close to a full-featured emulator. beside memory and peripherals, cpu operation can also be monitored in real- time by means of shadow registers. bootloader the low-density stm8l151x2/3 ultra-low-power devices feature a built-in bootloader (see um0560: stm8 bootloader user manual ). the bootloader is used to download application software into the device memories, including ram, program and data memory, us ing standard serial interfaces. it is a complementary solution to programming via the swim debugging interface. docid018780 rev 9 25/122 stm8l151x2, stm8l151x3 pinout and pin description 49 4 pinout and pin description figure 3. stm8l151cx lqfp48 package pinout figure 4. stm8l151kx ufqfpn32 package pinout . 2 3 4 0 ! 0 ! 0 ! 0 ! 0 % 0 % 0 $ 0 $ 0 $ 0 % 0 $ 0 % 0 % 6 $ $ 6 $ $ ! 6 2 % & 0 % 0 " 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 % 0 % 0 " 0 " 0 " 0 " 0 " 0 & 0 $ 0 $ 0 $ 0 $ 0 ! 0 ! 0 ! 0 ! 6 3 3 ! 6 2 % & 6 3 3 0 " 6 3 3 ) / 6 $ $ ) / 0 " 2 e s - 3 6 0 ! 6 3 3 . 2 3 4 0 ! 0 ! 0 ! 0 ! 0 ! 6 $ $ 0 $ 0 " 0 " 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 $ 0 " 0 " 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 # 0 # 0 # 0 # 0 ! - 3 6 pinout and pin description stm8l151x2, stm8l151x3 26/122 docid018780 rev 9 figure 5. stm8l151gx ufqfpn28 package pinout figure 6. stm8l151fx ufqfpn20 package pinout figure 7. stm8l151fx tssop20 package pinout 3 ' 3 % 3 % 3 % 3 ' 3 ' 3 ' 3 $ 9 6 6 9 6 6 $ 9 5 ( ) 9 ' ' 9 ' ' $ 9 5 ( ) 1 5 6 7 3 $ 3 $ 3 $ 3 % 3 % 3 % 3 % 3 & 3 ' 3 % 3 & 3 & 3 & 3 & 3 $ 3 & 3 & 3 $ d l e 0 $ 6 $ $ 6 $ $ ! 6 2 % & 6 3 3 6 3 3 ! 6 2 % & 0 ! 0 ! 0 " . 2 3 4 0 ! 0 # 0 # 0 # 0 # 0 " 0 " 0 " 0 " 0 # 0 " 0 " 0 " 0 ! - 3 6 0 ! 0 ! 6 3 3 6 3 3 ! 6 2 % & . 2 3 4 0 ! 0 # 0 # 0 " 0 " 0 " 0 " 0 " 0 " 0 " 6 $ $ 6 $ $ ! 6 2 % & 0 # - 3 6 0 " 0 $ 0 ! 0 # 0 # docid018780 rev 9 27/122 stm8l151x2, stm8l151x3 pinout and pin description 49 table 3. legend/abbreviation for table 4 type i= input, o = output, s = power supply level output hs = high sink/source (20 ma) ft five-volt tolerant port and control configuration input float = floating, wpu = weak pull-up output t = true open drain, od = open drain, pp = push pull reset state bold x (pin state after reset release). unless otherwise specified, the pin state is the same during the reset phase (i.e. ?under reset?) and after internal reset release (i.e. at reset state). table 4. low-density st m8l151x2/3 pin description pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 ufqfpn32 ufqfpn28 ufqfpn20 tssop20 floating wpu ext. interrupt high sink/source od pp 21114nrst/pa1 (1) i/o x hs x reset pa1 32225 pa2/osc_in/ [usart_tx] (2) / [spi_miso] (2) i/o x xxhsxx port a2 hse oscillator input / [usart transmit] / [spi master in- slave out] / 43336 pa3/osc_out/ [usa rt_rx] (2) /[spi_mosi ] (2) i/o x xxhsxx port a3 hse oscillator output / [usart receive]/ [spi master out/slave in] / 544- - pa4/tim2_bkin/ [tim2_etr] (2) adc1_in2/ comp1_inp i/o x xxhsxx port a4 timer 2 - break input / [timer 2 - external trigger] /adc1 input 2/ comparator1 positive input 655- - pa5/tim3_bkin/ [tim3_etr] (2) / adc1_in1/ comp1_inp i/o x xxhsxx port a5 timer 3 - break input / [timer 3 - external trigger] /adc1input 1/ comparator1 positive input 76- - - pa6/adc1_trig/ adc1_in0/ comp1_inp i/o x xxhsxx port a6 adc1- trigger /adc1input 0/ comparator1 positive input 8----pa7 i/o x xxhsxx port a7 - 24 13 12 7 10 pb0 (3) /tim2_ch1/ adc1_in18/ comp1_inp i/o x xxhsxx port b0 timer 2 - channel 1 / adc1_in18/ comparator1 positive input pinout and pin description stm8l151x2, stm8l151x3 28/122 docid018780 rev 9 25 14 13 8 11 pb1/tim3_ch1/ adc1_in17/ comp1_inp i/o - x xxhsxx port b1 timer 3 - channel1/ adc1_in17/ comparator1 positive input 26 15 14 9 12 pb2/ tim2_ch2/ adc1_in16/ comp1_inp i/o - x xxhsxx port b2 timer 2 - channel2 adc1_in16/ comparator1 positive input 27 16 15 10 13 pb3/tim2_etr/ adc1_in15/rtc_al arm (4) / comp1_inp i/o - x xxhsxx port b3 timer 2 - external trigger / adc1_in15 / rtc_alarm (4) /comparator1 positive input 28 17 16 11 14 pb4 (3) /spi1_nss/ adc1_in14/ comp1_inp i/o - x xxhsxx port b4 spi master/slave select / adc1_in14/ comparator1 positive input 29 18 17 12 15 pb5/spi_sck/ /adc1_in13/ comp1_inp i/o - x xxhsxx port b5 [spi clock] / adc1_in13/ comparator 1 positive input 30 19 18 13 16 pb6/spi1_mosi/ adc1_in12/ comp1_inp i/o - x xxhsxx port b6 spi master out/ slave in / adc1_in12/ comparator1 positive input 31 20 19 14 17 pb7/spi1_miso/ adc1_in11/ comp1_inp i/o - x xxhsxx port b7 spi1 master in-slave out/ adc1_in11/ comparator1 positive input 37 25 21 15 18 pc0/i2c_sda i/o ft x xt (5) port c0 i2c data 38 26 22 16 19 pc1/i2c_scl i/o ft x xt (5) port c1 i2c clock 41 27 23 - - pc2/usart_rx/adc 1_in6/ comp1_inp i/o - x xxhsxx port c2 usart receive / adc1_in6/ comparator1 positive input 42 28 24 - - pc3/usart_tx/ adc1_in5/ comp1_inp/ comp2_inm i/o - x xxhsxx port c3 usart transmit / adc1_in5/ comparator1 positive input/comparator 2 negative input table 4. low-density stm8l151x2/3 pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 ufqfpn32 ufqfpn28 ufqfpn20 tssop20 floating wpu ext. interrupt high sink/source od pp docid018780 rev 9 29/122 stm8l151x2, stm8l151x3 pinout and pin description 49 43 29 25 17 20 pc4/usart_ck]/ i2c_smb/cco/ adc1_in4/ comp1_inp/ comp2_inm i/o - x xxhsxx port c4 usart synchronous clock / i2c1_smb / configurable clock output / adc1_in4/ comparator1 positive input/comparator 2 negative input 44 30 26 18 1 pc5/osc32_in / [spi1_nss] (2) / [usart_tx] (2) / tim2_ch1 (6) i/o - x xxhsxx port c5 lse oscillator input / [spi master/slave select] / [usart transmit]/ timer 2 -channel 1 (6) 45 31 27 19 2 pc6/osc32_out/ [spi_sck] (2) / [usart_rx] (2) / tim2_ch2 (6) i/o - x xxhsxx port c6 lse oscillator output / [spi clock] / [usart receive]/ timer 2 -channel 2 (6) 46---- pc7/adc1_in3/ comp1_inp/ comp2_inm i/o - x xxhsxx port c7 adc1_in3/ comparator1 positive input/comparator 2 negative input 209869 pd0/tim3_ch2/ [adc1_trig] (2) / adc1_in22/ comp1_inp/ comp2_inp i/o - x xxhsxx port d0 timer 3 - channel 2 / [adc1_trigger] / adc1_in22/ comparator1 positive input/comparator 2 positive input 21 10 9 - - pd1/tim3_etr/ adc1_in21/ comp1_inp/ comp2_inp i/o - x xxhsxx port d1 timer 3 - external trigger / adc1_in21/ comparator1 positive input/comparator 2 positive input 22 11 10 - - pd2/adc1_in20/ comp1_inp i/o - x xxhsxx port d2 adc1_in20/ comparator1 positive input 23 12 11 - - pd3/adc1_in19/ rtc_calib (7) / comp1_inp i/o - x xxhsxx port d3 adc1_in19/ rtc calibration (7) / comparator1 positive input 33 21 20 - - pd4/adc1_in10/ comp1_inp i/o - x xxhsxx port d4 adc1_in10/ comparator1 positive input table 4. low-density stm8l151x2/3 pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 ufqfpn32 ufqfpn28 ufqfpn20 tssop20 floating wpu ext. interrupt high sink/source od pp pinout and pin description stm8l151x2, stm8l151x3 30/122 docid018780 rev 9 34 22 - - - pd5/ adc1_in9/ comp1_inp i/o - x xxhsxx port d5 adc1_in9/ comparator1 positive input 35 23 - - - pd6/adc1_in8/ rtc_calib/ comp1_inp i/o - x xxhsxx port d6 adc1_in8 / rtc calibration/ comparator1 positive input 36 24 - - - pd7 /adc1_in7/ rtc_alarm/ comp1_inp i/o - x xxhsxx port d7 adc1_in7/rtc alarm/ comparator1 positive input 14----pe0 i/o- x xxhsxx port e0 - 15----pe1 i/o- x xxhsxx port e1 - 16----pe2 i/o- x xxhsxx port e2 - 17 - - - - pe3/adc1_in26 i/o - x xxhsxx port e3 adc1_in26 18 - - - - pe4/adc1_in27 i/o - x xxhsxx port e4 adc1_in27 19---- pe5/adc1_in23/ comp1_inp/ comp2_inp i/o - x xxhsxx port e5 adc1_in23/ comparator 1 positive input/comparator 2 positive input 47 - - - - pe6/pvd_in i/o - x xxhsxx port e6 pvd_in 48 - - - - pe7/adc1_in25 i/o - x xxhsxx port e7 adc1_in25 32 - - - - pf0/adc1_in24 i/o - x xxhsxx port f0 adc1_in24 10----v dd s - - - - - - - digital supply voltage - 8758v dd /v dda / v ref+ s- - - - - - - digital supply voltage / adc1 positive voltage reference 97647v ss / v ref- / v ssa s- - - - - - - ground voltage / adc1 negative voltage reference / analog ground voltage 11----v dda s - - - - - - - analog supply voltage 12----v ref+ s- - - - - - - adc1 positive voltage reference 13228203 pa0 (8) / [usart_ck] (2) / swim/beep/ir_tim (9) i/o x x x hs (9) xx port a0 [usart1 synchronous clock] (2) / swim input and output / beep output / infrared timer output table 4. low-density stm8l151x2/3 pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 ufqfpn32 ufqfpn28 ufqfpn20 tssop20 floating wpu ext. interrupt high sink/source od pp docid018780 rev 9 31/122 stm8l151x2, stm8l151x3 pinout and pin description 49 note: the slope control of all gpio pins, except true open drain pins, can be programmed. by default, the slope control is limited to 2 mhz. 4.1 system config uration options as shown in table 4: low-density stm8l151x2/3 pin description , some alternate functions can be remapped on different i/o ports by programming one of the two remapping registers described in the ?routing interface (ri) and sy stem configuration controller? section in the stm8l15xxx and stm8l16xxx reference manual (rm0031). 40----v ssio - - - - - - - - i/o ground voltage 39----v ddio - - - - - - - - i/o supply voltage 1. at power-up, the pa1/nrst pin is a reset input pin with pull-up. to be used as a general purpose pin (pa1), it can be configured only as output open-drain or push-pull, not as a general purpose input. refer to section configuring nrst/pa1 pin as general purpose output in the stm8l15xxx and stm8l1 6xxx reference manual (rm0031). 2. [ ] alternate function remapping option (if the same alternate f unction is shown twice, it indicates an exclusive choice not a duplication of the function). 3. a pull-up is applied to pb0 and pb4 during the reset phase. these two pins are input floating after reset release. 4. 20-pin and 28-pin packages only. 5. in the open-drain output column, ?t? defines a tr ue open-drain i/o (p-buffer and protection diode to v dd are not implemented). 6. 20-pin packages only. 7. 28-pin packages only 8. the pa0 pin is in input pull-up during the reset phase and after reset release. 9. high sink led driver ca pability available on pa0. table 4. low-density stm8l151x2/3 pin description (continued) pin number pin name type i/o level input output main function (after reset) default alternate function lqfp48 ufqfpn32 ufqfpn28 ufqfpn20 tssop20 floating wpu ext. interrupt high sink/source od pp memory and register map stm8l151x2, stm8l151x3 32/122 docid018780 rev 9 5 memory and register map 5.1 memory mapping the memory map is shown in figure 8 . figure 8. memory map 1. table 5 lists the boundary addresses for each memory si ze. the top of the stack is at the ram end address. 2. the vrefint_factory_conv byte represents the lsb of the v refint 12-bit adc1 conversion result. the ' 0 ) / a n d p e r i p h e r a l r e g i s t e r s x , o w d e n s i t y u p t o + b y t e s 2 e s e t a n d i n t e r r u p t v e c t o r s x & & 2 ! - x & & + b y t e b y t e s x $ a t a % % 0 2 / - x x & x x & & & x x & & & x x & & x % & & x x & & x & 2 e s e r v e d 2 e s e r v e d i n c l u d i n g 3 t a c k " y t e s / p t i o n b y t e s x & & & x x x 2 e s e r v e d x & & & " o o t 2 / - x x & & + b y t e s x 2 e s e r v e d # 0 5 3 7 ) - $ e b u g ) 4 # 2 e g i s t e r s & l a s h p r o g r a m m e m o r y x x x x x x x 6 2 % & ) . 4 ? & a c t o r y ? # / . 6 4 3 ? & a c t o r y ? # / . 6 ? 6 x 2 e s e r v e d 5 n i q u e ) $ 2 e s e r v e d - 3 6 6 q u p 2 e s e r v e d x x & & & 2 ) 2 e s e r v e d x x % x x x x $ x ! x ! x ! ! x ! x " x " x " x # x $ x $ x $ x % x % x & x & x x x x x x & x x " x x x x x % x % ! x & & x x x # x x x x x 2 e s e r v e d ' 0 ) / p o r t s & l a s h 2 e s e r v e d $ - ! 3 9 3 # & ' ) 4 # % 8 4 7 & % 2 3 4 0 7 2 # , + 7 7 $ ' ) 4 # % 8 4 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d ) 7 $ ' " % % 0 2 4 # 3 0 ) ) # 5 3 ! 2 4 4 ) - 4 ) - 2 e s e r v e d 2 e s e r v e d 2 e s e r v e d 4 ) - ) 2 4 ) - ! $ # # / - 0 # / - 0 2 ) docid018780 rev 9 33/122 stm8l151x2, stm8l151x3 memory and register map 49 msb have a fixed value: 0x6. 3. the ts_factory_conv_v90 byte represents the lsb of the v 90 12-bit adc1 conversion result. the msb have a fixed value: 0x3. 4. refer to table 8 for an overview of hardware register mapping, to table 7 for details on i/o port hardware registers, and to table 9 for information on cpu/swim/debug module controller registers. 5.2 register map table 5. flash and ram boundary addresses memory area size start address end address ram 1 kbyte 0x00 0000 0x00 03ff flash program memory 8 kbyte 0x00 8000 0x00 9fff 4 kbyte 0x00 8000 0x00 8fff table 6. factory conversion registers address block register label register name reset status 0x00 4910 - vrefint_factory_ conv value of the internal reference voltage measured during the factory phase 0xxx 0x00 4911 - ts_factory_conv_ v90 value of the temperature sensor output voltage measured during the factory phase 0xxx table 7. i/o port hardware register map address block register label register name reset status 0x00 5000 port a pa_odr port a data output latch register 0x00 0x00 5001 pa_idr port a input pin value register 0xxx 0x00 5002 pa_ddr port a data direction register 0x00 0x00 5003 pa_cr1 port a control register 1 0x01 0x00 5004 pa_cr2 port a control register 2 0x00 0x00 5005 port b pb_odr port b data output latch register 0x00 0x00 5006 pb_idr port b input pin value register 0xxx 0x00 5007 pb_ddr port b data direction register 0x00 0x00 5008 pb_cr1 port b control register 1 0x00 0x00 5009 pb_cr2 port b control register 2 0x00 memory and register map stm8l151x2, stm8l151x3 34/122 docid018780 rev 9 0x00 500a port c pc_odr port c data output latch register 0x00 0x00 500b pc_idr port c i nput pin value register 0xxx 0x00 500c pc_ddr port c data direction register 0x00 0x00 500d pc_cr1 port c control register 1 0x00 0x00 500e pc_cr2 port c control register 2 0x00 0x00 500f port d pd_odr port d data output latch register 0x00 0x00 5010 pd_idr port d input pin value register 0xxx 0x00 5011 pd_ddr port d data direction register 0x00 0x00 5012 pd_cr1 port d control register 1 0x00 0x00 5013 pd_cr2 port d control register 2 0x00 0x00 5014 port e pe_odr port e data output latch register 0x00 0x00 5015 pe_idr port e input pin value register 0xxx 0x00 5016 pe_ddr port e data direction register 0x00 0x00 5017 pe_cr1 port e control register 1 0x00 0x00 5018 pe_cr2 port e control register 2 0x00 0x00 5019 port f pf_odr port f data output latch register 0x00 0x00 501a pf_idr port f input pin value register 0xxx 0x00 501b pf_ddr port f data direction register 0x00 0x00 501c pf_cr1 port f control register 1 0x00 0x00 501d pf_cr2 port f control register 2 0x00 table 7. i/o port hardware register map (continued) address block register label register name reset status table 8. general hard ware register map address block register label register name reset status 0x00 502e to 0x00 5049 reserved area (44 byte) 0x00 5050 flash flash_cr1 flash control register 1 0x00 0x00 5051 flash_cr2 flash control register 2 0x00 0x00 5052 flash _pukr flash program memory unprotection key register 0x00 0x00 5053 flash _dukr flash data eeprom unprotection key register 0x00 0x00 5054 flash _iapsr flash in-application programming status register 0x00 docid018780 rev 9 35/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 5055 to 0x00 506f reserved area (27 byte) 0x00 5070 dma1 dma1_gcsr dma1 global configur ation & status register 0xfc 0x00 5071 dma1_gir1 dma1 globa l interrupt register 1 0x00 0x00 5072 to 0x00 5074 reserved area (3 byte) 0x00 5075 dma1_c0cr dma1 channel 0 configuration register 0x00 0x00 5076 dma1_c0spr dma1 channel 0 status & priority register 0x00 0x00 5077 dma1_c0ndtr dma1 number of data to transfer register (channel 0) 0x00 0x00 5078 dma1_c0parh dma1 peripheral address high register (channel 0) 0x52 0x00 5079 dma1_c0parl dma1 peripheral address low register (channel 0) 0x00 0x00 507a reserved area (1 byte) 0x00 507b dma1_c0m0arh dma1 memory 0 address high register (channel 0) 0x00 0x00 507c dma1_c0m0arl dma1 memory 0 address low register (channel 0) 0x00 0x00 507d to 0x00 507e reserved area (2 byte) 0x00 507f dma1_c1cr dma1 channel 1 configuration register 0x00 0x00 5080 dma1_c1spr dma1 channel 1 status & priority register 0x00 0x00 5081 dma1_c1ndtr dma1 number of data to transfer register (channel 1) 0x00 0x00 5082 dma1_c1parh dma1 peripheral address high register (channel 1) 0x52 0x00 5083 dma1_c1parl dma1 peripheral address low register (channel 1) 0x00 table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 36/122 docid018780 rev 9 0x00 5084 dma1 reserved area (1 byte) 0x00 5085 dma1_c1m0arh dma1 memory 0 address high register (channel 1) 0x00 0x00 5086 dma1_c1m0arl dma1 memory 0 address low register (channel 1) 0x00 0x00 5087 0x00 5088 reserved area (2 byte) 0x00 5089 dma1_c2cr dma1 channel 2 configuration register 0x00 0x00 508a dma1_c2spr dma1 channel 2 status & priority register 0x00 0x00 508b dma1_c2ndtr dma1 number of data to transfer register (channel 2) 0x00 0x00 508c dma1_c2parh dma1 peripheral address high register (channel 2) 0x52 0x00 508d dma1_c2parl dma1 peripheral address low register (channel 2) 0x00 0x00 508e reserved area (1 byte) 0x00 508f dma1_c2m0arh dma1 memory 0 address high register (channel 2) 0x00 0x00 5090 dma1_c2m0arl dma1 memory 0 address low register (channel 2) 0x00 0x00 5091 0x00 5092 reserved area (2 byte) 0x00 5093 dma1_c3cr dma1 channel 3 configuration register 0x00 0x00 5094 dma1_c3spr dma1 channel 3 status & priority register 0x00 0x00 5095 dma1_c3ndtr dma1 number of data to transfer register (channel 3) 0x00 0x00 5096 dma1_c3parh_ c3m1arh dma1 peripheral address high register (channel 3) 0x40 0x00 5097 dma1_c3parl_ c3m1arl dma1 peripheral address low register (channel 3) 0x00 0x00 5098 dma_c3m0ear dma channel 3 memory 0 extended address register 0x00 0x00 5099 dma1_c3m0arh dma1 memory 0 address high register (channel 3) 0x00 0x00 509a dma1_c3m0arl dma1 memory 0 address low register (channel 3) 0x00 0x00 509b to 0x00 509c reserved area (3 byte) table 8. general hardware register map (continued) address block register label register name reset status docid018780 rev 9 37/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 509d syscfg syscfg_rmpcr3 remapping register 3 0x00 0x00 509e syscfg_rmpcr1 remapping register 1 0x0c 0x2c (1) 0x00 509f syscfg_rmpcr2 rem apping register 2 0x00 0x00 50a0 itc - exti exti_cr1 external interrupt control register 1 0x00 0x00 50a1 exti_cr2 external interrupt control register 2 0x00 0x00 50a2 exti_cr3 external interrupt control register 3 0x00 0x00 50a3 exti_sr1 external interrupt status register 1 0x00 0x00 50a4 exti_sr2 external interrupt status register 2 0x00 0x00 50a5 exti_conf1 external interrupt port select register 1 0x00 0x00 50a6 wfe wfe_cr1 wfe contro l register 1 0x00 0x00 50a7 wfe_cr2 wfe control register 2 0x00 0x00 50a8 wfe_cr3 wfe control register 3 0x00 0x00 50a9 wfe_cr4 wfe control register 4 0x00 0x00 50aa itc - exti exti_cr4 external interrupt control register 4 0x00 0x00 50ab exti_conf2 external interrupt port select register 2 0x00 0x00 50a9 to 0x00 50af reserved area (7 byte) 0x00 50b0 rst rst_cr reset control register 0x00 0x00 50b1 rst_sr reset status register 0x01 0x00 50b2 pwr pwr_csr1 power control and status register 1 0x00 0x00 50b3 pwr_csr2 power control and status register 2 0x00 0x00 50b4 to 0x00 50bf reserved area (12 byte) table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 38/122 docid018780 rev 9 0x00 50c0 clk clk_ckdivr clk clock master divi der register 0x03 0x00 50c1 clk_crtcr clk clock rtc register 0x00 (2) 0x00 50c2 clk_ickcr clk internal clock control register 0x11 0x00 50c3 clk_pckenr1 clk peripheral clock gating register 1 0x00 0x00 50c4 clk_pckenr2 clk peripheral clock gating register 2 0x00 0x00 50c5 clk_ccor clk configurable clock control register 0x00 0x00 50c6 clk_eckcr clk external clock control register 0x00 0x00 50c7 clk_scsr clk system clock status register 0x01 0x00 50c8 clk_swr clk system cl ock switch register 0x01 0x00 50c9 clk_swcr clk clock switch control register 0xx0 0x00 50ca clk_cssr clk clock security system register 0x00 0x00 50cb clk_cbeepr clk clock beep register 0x00 0x00 50cc clk_hsicalr clk hsi calibration register 0xxx 0x00 50cd clk_hsitrimr clk hsi clock calibration trimming register 0x00 0x00 50ce clk_hsiunlckr clk hsi unlock register 0x00 0x00 50cf clk_regcsr clk main regulator control status register 0bxx11 100x 0x00 50d0 clk_pckenr3 clk peripheral clock gating register 3 0x00 0x00 50d1 to 0x00 50d2 reserved area (2 byte) 0x00 50d3 wwdg wwdg_cr wwdg control register 0x7f 0x00 50d4 wwdg_wr wwdr window register 0x7f 0x00 50d5 to 00 50df reserved area (11 byte) 0x00 50e0 iwdg iwdg_kr iwdg key register 0x01 0x00 50e1 iwdg_pr iwdg prescaler register 0x00 0x00 50e2 iwdg_rlr iwdg reload register 0xff 0x00 50e3 to 0x00 50ef reserved area (13 byte) 0x00 50f0 beep beep_csr1 beep control/status register 1 0x00 0x00 50f1 0x00 50f2 reserved area (2 byte) 0x00 50f3 beep_csr2 beep contro l/status register 2 0x1f 0x00 50f4 to 0x00 513f reserved area (76 byte) table 8. general hardware register map (continued) address block register label register name reset status docid018780 rev 9 39/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 5140 rtc rtc_tr1 rtc time register 1 0x00 0x00 5141 rtc_tr2 rtc time register 2 0x00 0x00 5142 rtc_tr3 rtc time register 3 0x00 0x00 5143 reserved area (1 byte) 0x00 5144 rtc_dr1 rtc date register 1 0x01 0x00 5145 rtc_dr2 rtc date register 2 0x21 0x00 5146 rtc_dr3 rtc date register 3 0x00 0x00 5147 reserved area (1 byte) 0x00 5148 rtc_cr1 rtc control register 1 0x00 (2) 0x00 5149 rtc_cr2 rtc control register 2 0x00 (2) 0x00 514a rtc_cr3 rtc control register 3 0x00 (2) 0x00 514b reserved area (1 byte) 0x00 514c rtc_isr1 rtc initialization and status register 1 0x01 0x00 514d rtc_isr2 rtc initialization and status register 2 0x00 0x00 514e 0x00 514f reserved area (2 byte) 0x00 5150 rtc_sprerh rtc synchronous prescaler register high 0x00 (2) 0x00 5151 rtc_sprerl rtc synchronous prescaler register low 0xff (2) 0x00 5152 rtc_aprer rtc asynchronous prescaler register 0x7f (2) 0x00 5153 reserved area (1 byte) 0x00 5154 rtc_wutrh rtc wakeup timer register high 0xff (2) 0x00 5155 rtc_wutrl rtc wakeup timer register low 0xff (2) 0x00 5156 reserved area (1 byte) 0x00 5157 rtc_ssrl rtc subsecond register low 0x00 0x00 5158 rtc_ssrh rtc subsecond register high 0x00 0x00 5159 rtc_wpr rtc write protection register 0x00 0x00 5158 rtc_ssrh rtc subsecond register high 0x00 0x00 5159 rtc_wpr rtc write protection register 0x00 0x00 515a rtc_shiftrh rtc shift register high 0x00 0x00 515b rtc_shiftrl rtc shift register low 0x00 0x00 515c rtc_alrmar1 rtc alarm a register 1 0x00 (2) 0x00 515d rtc_alrmar2 rtc alarm a register 2 0x00 (2) 0x00 515e rtc_alrmar3 rtc alarm a register 3 0x00 (2) 0x00 515f rtc_alrmar4 rtc alarm a register 4 0x00 (2) table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 40/122 docid018780 rev 9 0x00 5160 to 0x00 5163 rtc reserved area (4 byte) 0x00 5164 rtc_alrmassrh r tc alarm a subseco nd register high 0x00 (2) 0x00 5165 rtc_alrmassrl rtc alarm a subsecond register low 0x00 (2) 0x00 5166 rtc_alrmassms kr rtc alarm a masking register 0x00 (2) 0x00 5167 to 0x00 5169 reserved area (3 byte) 0x00 516a rtc_calrh rtc calibration register high 0x00 (2) 0x00 516b rtc_calrl rtc calibration register low 0x00 (2) 0x00 516c to 0x00 518f reserved area (36 byte) 0x00 5190 csslse_csr rtc css on lse control and status register 0x00 (2) 0x00 5191 to 0x00 51ff reserved area (111 byte) 0x00 5200 spi1 spi1_cr1 spi1 control register 1 0x00 0x00 5201 spi1_cr2 spi1 control register 2 0x00 0x00 5202 spi1_icr spi1 interrupt control register 0x00 0x00 5203 spi1_sr spi1 status register 0x02 0x00 5204 spi1_dr spi1 data register 0x00 0x00 5205 spi1_crcpr spi1 crc polynomial register 0x07 0x00 5206 spi1_rxcrcr spi1 rx crc register 0x00 0x00 5207 spi1_txcrcr spi1 tx crc register 0x00 0x00 5208 to 0x00 520f reserved area (8 byte) table 8. general hardware register map (continued) address block register label register name reset status docid018780 rev 9 41/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 5210 i2c1 i2c1_cr1 i2c1 control register 1 0x00 0x00 5211 i2c1_cr2 i2c1 control register 2 0x00 0x00 5212 i2c1_freqr i2c1 frequency register 0x00 0x00 5213 i2c1_oarl i2c1 own address register low 0x00 0x00 5214 i2c1_oarh i2c1 own address register high 0x00 0x00 5215 i2c1_oar2 i2c1 own address register for dual mode 0x00 0x00 5216 i2c1_dr i2c1 data register 0x00 0x00 5217 i2c1_sr1 i2c1 status register 1 0x00 0x00 5218 i2c1_sr2 i2c1 status register 2 0x00 0x00 5219 i2c1_sr3 i2c1 status register 3 0x0x 0x00 521a i2c1_itr i2c1 interrupt control register 0x00 0x00 521b i2c1_ccrl i2c1 clock control register low 0x00 0x00 521c i2c1_ccrh i2c1 clock control register high 0x00 0x00 521d i2c1_triser i2c1 trise register 0x02 0x00 521e i2c1_pecr i2c1 packet error checking register 0x00 0x00 521f to 0x00 522f reserved area (17 byte) 0x00 5230 usart1 usart1_sr usart1 status register 0xc0 0x00 5231 usart1_dr usart1 data register 0xxx 0x00 5232 usart1_brr1 usart1 baud rate register 1 0x00 0x00 5233 usart1_brr2 usart1 baud rate register 2 0x00 0x00 5234 usart1_cr1 usart1 control register 1 0x00 0x00 5235 usart1_cr2 usart1 control register 2 0x00 0x00 5236 usart1_cr3 usart1 control register 3 0x00 0x00 5237 usart1_cr4 usart1 control register 4 0x00 0x00 5238 usart1_cr5 usart1 control register 5 0x00 0x00 5239 usart1_gtr usart1 guard time register 0x00 0x00 523a usart1_pscr usart1 prescaler register 0x00 0x00 523b to 0x00 524f reserved area (21 byte) table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 42/122 docid018780 rev 9 0x00 5250 tim2 tim2_cr1 tim2 control register 1 0x00 0x00 5251 tim2_cr2 tim2 control register 2 0x00 0x00 5252 tim2_smcr tim2 slave mode control register 0x00 0x00 5253 tim2_etr tim2 external trigger register 0x00 0x00 5254 tim2_der tim2 dma1 request enable register 0x00 0x00 5255 tim2_ier tim2 interrupt enable register 0x00 0x00 5256 tim2_sr1 tim2 status register 1 0x00 0x00 5257 tim2_sr2 tim2 status register 2 0x00 0x00 5258 tim2_egr tim2 event generation register 0x00 0x00 5259 tim2_ccmr1 tim2 captur e/compare mode register 1 0x00 0x00 525a tim2_ccmr2 tim2 captur e/compare mode register 2 0x00 0x00 525b tim2_ccer1 tim2 capture/ compare enable register 1 0x00 0x00 525c tim2_cntrh tim2 counter high 0x00 0x00 525d tim2_cntrl tim2 counter low 0x00 0x00 525e tim2_pscr tim2 prescaler register 0x00 0x00 525f tim2_arrh tim2 au to-reload register high 0xff 0x00 5260 tim2_arrl tim2 auto-reload register low 0xff 0x00 5261 tim2_ccr1h tim2 captur e/compare register 1 high 0x00 0x00 5262 tim2_ccr1l tim2 capture/compare register 1 low 0x00 0x00 5263 tim2_ccr2h tim2 captur e/compare register 2 high 0x00 0x00 5264 tim2_ccr2l tim2 capture/compare register 2 low 0x00 0x00 5265 tim2_bkr tim2 break register 0x00 0x00 5266 tim2_oisr tim2 outpu t idle state register 0x00 0x00 5267 to 0x00 527f reserved area (25 byte) table 8. general hardware register map (continued) address block register label register name reset status docid018780 rev 9 43/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 5280 tim3 tim3_cr1 tim3 control register 1 0x00 0x00 5281 tim3_cr2 tim3 control register 2 0x00 0x00 5282 tim3_smcr tim3 slave mode control register 0x00 0x00 5283 tim3_etr tim3 external trigger register 0x00 0x00 5284 tim3_der tim3 dma1 request enable register 0x00 0x00 5285 tim3_ier tim3 interrupt enable register 0x00 0x00 5286 tim3_sr1 tim3 status register 1 0x00 0x00 5287 tim3_sr2 tim3 status register 2 0x00 0x00 5288 tim3_egr tim3 event generation register 0x00 0x00 5289 tim3_ccmr1 tim3 capture/compare mode register 1 0x00 0x00 528a tim3_ccmr2 tim3 capture/compare mode register 2 0x00 0x00 528b tim3_ccer1 tim3 capture/ compare enable register 1 0x00 0x00 528c tim3_cntrh tim3 counter high 0x00 0x00 528d tim3_cntrl tim3 counter low 0x00 0x00 528e tim3_pscr tim3 prescaler register 0x00 0x00 528f tim3_arrh tim3 auto-reload register high 0xff 0x00 5290 tim3_arrl tim3 auto-reload register low 0xff 0x00 5291 tim3_ccr1h tim3 captur e/compare register 1 high 0x00 0x00 5292 tim3_ccr1l tim3 captur e/compare register 1 low 0x00 0x00 5293 tim3_ccr2h tim3 captur e/compare register 2 high 0x00 0x00 5294 tim3_ccr2l tim3 captur e/compare register 2 low 0x00 0x00 5295 tim3_bkr tim3 break register 0x00 0x00 5296 tim3_oisr tim3 outpu t idle state register 0x00 0x00 5297 to 0x00 52df reserved area (72 byte) table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 44/122 docid018780 rev 9 0x00 52e0 tim4 tim4_cr1 tim4 control register 1 0x00 0x00 52e1 tim4_cr2 tim4 control register 2 0x00 0x00 52e2 tim4_smcr tim4 slave mode control register 0x00 0x00 52e3 tim4_der tim4 dma1 request enable register 0x00 0x00 52e4 tim4_ier tim4 interrupt enable register 0x00 0x00 52e5 tim4_sr1 tim4 status register 1 0x00 0x00 52e6 tim4_egr tim4 even t generation register 0x00 0x00 52e7 tim4_cntr tim4 counter 0x00 0x00 52e8 tim4_pscr tim4 prescaler register 0x00 0x00 52e9 tim4_arr tim4 au to-reload register 0x00 0x00 52ea to 0x00 52fe reserved area (21 byte) 0x00 52ff irtim ir_cr infrared control register 0x00 0x00 5317 to 0x00 533f reserved area (41 byte) 0x00 5340 adc1 adc1_cr1 adc1 configuration register 1 0x00 0x00 5341 adc1_cr2 adc1 configuration register 2 0x00 0x00 5342 adc1_cr3 adc1 configuration register 3 0x1f 0x00 5343 adc1_sr adc1 status register 0x00 0x00 5344 adc1_drh adc1 data register high 0x00 0x00 5345 adc1_drl adc1 data register low 0x00 0x00 5346 adc1_htrh adc1 high threshold register high 0x0f 0x00 5347 adc1_htrl adc1 high threshold register low 0xff 0x00 5348 adc1_ltrh adc1 low threshold register high 0x00 0x00 5349 adc1_ltrl adc1 low threshold register low 0x00 0x00 534a adc1_sqr1 adc1 channel sequence 1 register 0x00 0x00 534b adc1_sqr2 adc1 channel sequence 2 register 0x00 0x00 534c adc1_sqr3 adc1 channel sequence 3 register 0x00 0x00 534d adc1_sqr4 adc1 channel sequence 4 register 0x00 0x00 534e adc1_trigr1 adc1 trigger disable 1 0x00 0x00 534f adc1_trigr2 adc1 trigger disable 2 0x00 0x00 5350 adc1_trigr3 adc1 trigger disable 3 0x00 0x00 5351 adc1_trigr4 adc1 trigger disable 4 0x00 table 8. general hardware register map (continued) address block register label register name reset status docid018780 rev 9 45/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 53c8 to 0x00 542f reserved area (104 byte) 0x00 5430 ri reserved area (1 byte) 0x00 0x00 5431 ri_icr1 ri timer input capture routing register 1 0x00 0x00 5432 ri_icr2 ri timer input capture routing register 2 0x00 0x00 5433 ri_ioir1 ri i/o input register 1 0xxx 0x00 5434 ri_ioir2 ri i/o input register 2 0xxx 0x00 5435 ri_ioir3 ri i/o input register 3 0xxx 0x00 5436 ri_iocmr1 ri i/o control mode register 1 0x00 0x00 5437 ri_iocmr2 ri i/o control mode register 2 0x00 0x00 5438 ri_iocmr3 ri i/o control mode register 3 0x00 0x00 5439 ri_iosr1 ri i/o swit ch register 1 0x00 0x00 543a ri_iosr2 ri i/o swit ch register 2 0x00 0x00 543b ri_iosr3 ri i/o swit ch register 3 0x00 0x00 543c ri_iogcr ri i/o group control register 0xff 0x00 543d ri_ascr1 ri analog switch register 1 0x00 0x00 543e ri_ascr2 ri analog switch register 2 0x00 0x00 543f ri_rcr ri resistor control register 0x00 0x00 5440 comp1/ comp2 comp_csr1 comparator control and status register 1 0x00 0x00 5441 comp_csr2 comparator control and status register 2 0x00 0x00 5442 comp_csr3 comparator control and status register 3 0x00 0x00 5443 comp_csr4 comparator control and status register 4 0x00 0x00 5444 comp_csr5 comparator control and status register 5 0x00 0x00 5445 to 0x00 544f reserved area (11 byte) 0x00 5450 ri ri_cr ri i/o control register 0x00 0x00 5451 ri_maskr1 ri i/o mask register 1 0x00 0x00 5452 ri_maskr2 ri i/o mask register 2 0x00 0x00 5453 ri_maskr3 ri i/o mask register 3 0x00 0x00 5454 ri_maskr4 ri i/o mask register 4 0x00 0x00 5455 ri_ioir4 ri i/o input register 4 0xxx 0x00 5456 ri_iocmr4 ri i/o control mode register 4 0x00 0x00 5457 ri_iosr4 ri i/o switch register 4 0x00 1. for device in 20-pin packages 2. these registers are not impacted by a system reset. they are reset at power-on. table 8. general hardware register map (continued) address block register label register name reset status memory and register map stm8l151x2, stm8l151x3 46/122 docid018780 rev 9 table 9. cpu/swim/debug module/interrupt controller registers address block register label register name reset status 0x00 7f00 cpu (1) a accumulator 0x00 0x00 7f01 pce program counter extended 0x00 0x00 7f02 pch program counter high 0x00 0x00 7f03 pcl program counter low 0x00 0x00 7f04 xh x index register high 0x00 0x00 7f05 xl x index register low 0x00 0x00 7f06 yh y index register high 0x00 0x00 7f07 yl y index register low 0x00 0x00 7f08 sph stack pointer high 0x03 0x00 7f09 spl stack pointer low 0xff 0x00 7f0a ccr condition code register 0x28 0x00 7f0b to 0x00 7f5f cpu reserved area (85 byte) 0x00 7f60 cfg_gcr global configuration register 0x00 0x00 7f70 itc-spr itc_spr1 interrupt software priority register 1 0xff 0x00 7f71 itc_spr2 interrupt software priority register 2 0xff 0x00 7f72 itc_spr3 interrupt software priority register 3 0xff 0x00 7f73 itc_spr4 interrupt software priority register 4 0xff 0x00 7f74 itc_spr5 interrupt software priority register 5 0xff 0x00 7f75 itc_spr6 interrupt software priority register 6 0xff 0x00 7f76 itc_spr7 interrupt software priority register 7 0xff 0x00 7f77 itc_spr8 interrupt software priority register 8 0xff 0x00 7f78 to 0x00 7f79 reserved area (2 byte) 0x00 7f80 swim swim_csr swim control status register 0x00 0x00 7f81 to 0x00 7f8f reserved area (15 byte) docid018780 rev 9 47/122 stm8l151x2, stm8l151x3 memory and register map 49 0x00 7f90 dm dm_bk1re dm breakpoint 1 register extended byte 0xff 0x00 7f91 dm_bk1rh dm breakpoint 1 register high byte 0xff 0x00 7f92 dm_bk1rl dm breakpoint 1 register low byte 0xff 0x00 7f93 dm_bk2re dm breakpoint 2 register extended byte 0xff 0x00 7f94 dm_bk2rh dm breakpoint 2 register high byte 0xff 0x00 7f95 dm_bk2rl dm breakpoint 2 register low byte 0xff 0x00 7f96 dm_cr1 dm debug module control register 1 0x00 0x00 7f97 dm_cr2 dm debug module control register 2 0x00 0x00 7f98 dm_csr1 dm debug module control/status register 1 0x10 0x00 7f99 dm_csr2 dm debug module control/status register 2 0x00 0x00 7f9a dm_enfctr dm enable function register 0xff 0x00 7f9b to 0x00 7f9f reserved area (5 byte) 1. accessible by debug module only table 9. cpu/swim/debug module/interr upt controller registers (continued) address block register label register name reset status interrupt vector mapping stm8l151x2, stm8l151x3 48/122 docid018780 rev 9 6 interrupt vector mapping table 10. interrupt mapping irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address - reset reset yes yes yes yes 0x00 8000 - trap software interrupt - - - - 0x00 8004 0tli (2) external top level interrupt - - - - 0x00 8008 1 flash flash end of programing/ write attempted to protected page interrupt - - yes yes 0x00 800c 2 dma1 0/1 dma1 channels 0/1 half transaction/transaction complete interrupt - - yes yes 0x00 8010 3 dma1 2/3 dma1 channels 2/3 half transaction/transaction complete interrupt - - yes yes 0x00 8014 4rtc rtc alarm a/ wakeup/tamper 1/ tamper 2/tamper 3 yes yes yes yes 0x00 8018 5 extie/ pvd external interrupt port e pvd interrupt yes yes yes yes 0x00 801c 6 extib external interrupt port b yes yes yes yes 0x00 8020 7 extid external interrupt port d yes yes yes yes 0x00 8024 8 exti0 external interrupt 0 yes yes yes yes 0x00 8028 9 exti1 external interrupt 1 yes yes yes yes 0x00 802c 10 exti2 external interrupt 2 yes yes yes yes 0x00 8030 11 exti3 external interrupt 3 yes yes yes yes 0x00 8034 12 exti4 external interrupt 4 yes yes yes yes 0x00 8038 13 exti5 external interrupt 5 yes yes yes yes 0x00 803c 14 exti6 external interrupt 6 yes yes yes yes 0x00 8040 15 exti7 external interrupt 7 yes yes yes yes 0x00 8044 16 reserved 0x00 8048 17 clk clk system clock switch/ css interrupt - - yes yes 0x00 804c 18 comp1/ comp2/ adc1 comp1 interrupt comp2 interrupt acd1 end of conversion/ analog watchdog/ overrun interrupt yes yes yes yes 0x00 8050 docid018780 rev 9 49/122 stm8l151x2, stm8l151x3 interrupt vector mapping 49 19 tim2 tim2 update/overflow/ trigger/break interrupt - - yes yes 0x00 8054 20 tim2 tim2 capture/ compare interrupt - - yes yes 0x00 8058 21 tim3 tim3 update/overflow/ trigger/break interrupt - - yes yes 0x00 805c 22 tim3 tim3 capture/ compare interrupt - - yes yes 0x00 8060 23 ri ri trigger interrupt - - yes - 0x00 8064 24 reserved 0x00 8068 25 tim4 tim4 update/overflow/ trigger interrupt - - yes yes 0x00 806c 26 spi1 spi1 tx buffer empty/ rx buffer not empty/ error/wakeup interrupt yes yes yes yes 0x00 8070 27 usart1 usart1 transmit data register empty/ transmission complete interrupt - - yes yes 0x00 8074 28 usart1 usart1 received data ready/overrun error/ idle line detected/parity error/global error interrupt - - yes yes 0x00 8078 29 i 2 c1 i 2 c1 interrupt (3) yes yes yes yes 0x00 807c 1. the low power wait mode is entered when executing a wfe instruction in low power run mode. in wfe mode, the interrupt is served if it has been previously enabled. after processing the interrupt, the pr ocessor goes back to wfe mode. when the interrupt is configured as a wakeup event, the cpu wakes up and resumes processing. 2. the tli interrupt is the logic or between tim2 overflow interrupt, and tim4 overflow interrupts. 3. the device is woken up from halt or active-halt mode only when the address received matches the interface address. table 10. interrupt mapping (continued) irq no. source block description wakeup from halt mode wakeup from active-halt mode wakeup from wait (wfi mode) wakeup from wait (wfe mode) (1) vector address option bytes stm8l151x2, stm8l151x3 50/122 docid018780 rev 9 7 option bytes option bytes contain configurations for device hardware features as well as the memory protection of the device. they are stored in a dedicated memory block. all option bytes can be modified in icp mode (with swim) by accessing the eeprom address. see table 11 for details on option byte addresses. the option bytes can also be modified ?on the fl y? by the application in iap mode, except for the rop and ubc values which ca n only be taken into account when they are modified in icp mode (with the swim). refer to the stm8l15x flash programming manual (pm0054) and stm8 swim and debug manual (um0470) for information on swim programming procedures. table 11. option byte addresses addr. option name option byte no. option bits factory default setting 76543210 0x00 4800 read-out protection (rop) opt0 rop[7:0] 0xaa 0x00 4802 ubc (user boot code size) opt1 ubc[7:0] 0x00 0x00 4807 reserved 0x00 0x00 4808 independent watchdog option opt3 [3:0] reserved wwdg _halt wwdg _hw iwdg _halt iwdg _hw 0x00 0x00 4809 number of stabilization clock cycles for hse and lse oscillators opt4 reserved lsecnt[1 :0] hsecnt[1:0] 0x00 0x00 480a brownout reset (bor) opt5 [3:0] reserved bor_th bor_ on 0x01 0x00 480b bootloader option bytes (optbl) optbl [15:0] optbl[15:0] 0x00 0x00 480c 0x00 docid018780 rev 9 51/122 stm8l151x2, stm8l151x3 option bytes 52 table 12. option byte description option byte no. option description opt0 rop[7:0] memory readout protection (rop) 0xaa: disable readout protection (w rite access via swim protocol) refer to readout protection section in the st m8l15x and stm8l16x reference manual (rm0031). opt1 ubc[7:0] size of the user boot code area 0x00: ubc is not protected. 0x01: page 0 is write protected. 0x02: page 0 and 1 reserved for the ubc and write protected. it covers only the interrupt vectors. 0x03: page 0 to 2 reserved for ubc and write protected. 0x7f to 0xff - all 128 pages reserved for ubc and write protected. the protection of the memory area not protected by the ubc is enabled through the mass keys. refer to user boot code section in the stm8l1 5x and stm8l16x reference manual (rm0031). opt2 reserved opt3 iwdg_hw: independent watchdog 0: independent watchdog activated by software 1: independent watchdog activated by hardware iwdg_halt: independent window watchdog off on halt/active-halt 0: independent watchdog continues running in halt/active-halt mode 1: independent watchdog stopp ed in halt/active-halt mode wwdg_hw: window watchdog 0: window watchdog activated by software 1: window watchdog activated by hardware wwdg_halt: window window watchdog reset on halt/active-halt 0: window watchdog stopped in halt mode 1: window watchdog generates a reset when mcu enters halt mode opt4 hsecnt : number of hse oscillato r stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles lsecnt : number of lse oscillator stabilization clock cycles 0x00 - 1 clock cycle 0x01 - 16 clock cycles 0x10 - 512 clock cycles 0x11 - 4096 clock cycles refer to table 31: lse oscillator characteristics on page 74 . option bytes stm8l151x2, stm8l151x3 52/122 docid018780 rev 9 opt5 bor_on : 0: brownout reset off 1: brownout reset on bor_th[3:1] : brownout reset thresholds. refer to table 22 for details on the thresholds according to the value of bor_th bits. optbl optbl[15:0] : this option is checked by the boot rom code after reset. depending on content of addresses 00 480b, 00 480c and 0x8000 (reset vector) the cpu jumps to the bootloader or to the reset vector. refer to the um0560 bootloader user manual for more details. table 12. option byte description (continued) option byte no. option description docid018780 rev 9 53/122 stm8l151x2, stm8l151x3 unique id 53 8 unique id stm8 devices feature a 96-bit unique device id entifier which provides a reference number that is unique for any device and in any context. the 96 bits of the identifier can never be altered by the user. the unique device identifier can be read in single bytes and may then be concatenated using a custom algorithm. the unique device identifier is ideally suited: ? for use as serial numbers ? for use as security keys to increase the code security in the program memory while using and combining this unique id with software cryptograp hic primitives and protocols before programming the internal memory. ? to activate secure boot processes table 13. unique id registers (96 bits) address content description unique id bits 7654 3 2 1 0 0x4926 x co-ordinate on the wafer u_id[7:0] 0x4927 u_id[15:8] 0x4928 y co-ordinate on the wafer u_id[23:16] 0x4929 u_id[31:24] 0x492a wafer number u_id[39:32] 0x492b lot number u_id[47:40] 0x492c u_id[55:48] 0x492d u_id[63:56] 0x492e u_id[71:64] 0x492f u_id[79:72] 0x4930 u_id[87:80] 0x4931 u_id[95:88] electrical parameters stm8l151x2, stm8l151x3 54/122 docid018780 rev 9 9 electrical parameters 9.1 parameter conditions unless otherwise specified, all voltages are referred to v ss . 9.1.1 minimum and maximum values unless otherwise specified the minimum and ma ximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at t a = 25 c and t a = t a max (given by the selected temperature range). data based on characterization results, design simulation and/or technology characteristics is indicated in the table footnotes and are not tested in production. based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3 ). 9.1.2 typical values unless otherwise specified, typical data is based on t a = 25 c, v dd = 3 v. it is given only as design guidelines and is not tested. typical adc1 accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2 ) . 9.1.3 typical curves unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 9.1.4 loading capacitor the loading conditions used for pin parameter measurement are shown in figure 9 . figure 9. pin loading conditions 6 7 0 $ / 3 , 1 s ) 0 6 y 9 docid018780 rev 9 55/122 stm8l151x2, stm8l151x3 electrical parameters 102 9.1.5 pin input voltage the input voltage measurement on a pin of the device is described in figure 10 . figure 10. pin input voltage 9.2 absolute maximum ratings stresses above the absolute maximum ratings listed in table 14: voltage characteristics , table 15: current characteristics , and table 16: thermal characteristics may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these conditions is not implied. exposure to maximum rating conditions for extended periods may af fect device reliability. device mission profile (application condit ions) is compliant with jedec jesd47 qualification standard, extended miss ion profiles are available on demand. 6 7 0 6 3 , 1 0 6 y 9 9 , 1 table 14. voltage characteristics symbol ratings min max unit v dd - v ss external supply voltage (including v dd , v dda , and v ddio ) (1) 1. all power (v dd , v dda , v ddio ) and ground (v ss , v ssa , v ssio ) pins must always be connected to the external power supply. - 0.3 4.0 v v in (2) 2. v in maximum must always be respected. refer to table 15. for maximum allowed injected current values. input voltage on true open-drain pins (pc0 and pc1) v ss - 0.3 v dd + 4.0 v input voltage on any other pin v ss - 0.3 4.0 v esd electrostatic discharge voltage see absolute maximum ratings (electrical sensitivity) on page 102 - electrical parameters stm8l151x2, stm8l151x3 56/122 docid018780 rev 9 table 15. current characteristics symbol ratings max. unit i vdd total current into v dd power line (source) 80 ma i vss total current out of v ss ground line (sink) 80 i io output current sunk by ir_tim pin (with high sink led driver capability) 80 output current sunk by any other i/o and control pin 25 output current sourced by any i/os and control pin - 25 i inj(pin) injected current on true open-drain pins (pc0 and pc1) (1) - 5 / +0 ma injected current on 3.6 v tolerant pins (1) - 5 / +0 injected current on any other pin (1) 1. a positive injection is induced by v in >v dd while a negative injection is induced by v in electrical parameters stm8l151x2, stm8l151x3 58/122 docid018780 rev 9 9.3.2 embedded reset and power control block characteristics table 18. embedded reset and power control block characteristics symbol parameter conditions min typ max unit t vdd v dd rise time rate bor detector enabled 0 (1) - (1) s/v v dd fall time rate bor detector enabled 20 (1) - (1) t temp reset release delay v dd rising -3 (1) -ms v pdr power-down reset threshold falling edge 1.30 (2) 1.50 1.65 v v bor0 brown-out reset threshold 0 (bor_th[2:0]=000) falling edge 1.66 1.70 1.74 v rising edge 1.39 1.75 1.81 v bor1 brown-out reset threshold 1 (bor_th[2:0]=001) falling edge 1.89 1.93 1.97 rising edge 1.98 2.03 2.07 v bor2 brown-out reset threshold 2 (bor_th[2:0]=010) falling edge 2.25 2.30 2.35 rising edge 2.35 2.40 2.44 v bor3 brown-out reset threshold 3 (bor_th[2:0]=011) falling edge 2.50 2.55 2.60 rising edge 2.59 2.65 2.70 v bor4 brown-out reset threshold 4 (bor_th[2:0]=100) falling edge 2.74 2.79 2.85 rising edge 2.83 2.89 2.95 v pvd0 pvd threshold 0 falling edge 1.82 1.85 1.88 v rising edge 1.89 1.94 1.97 v pvd1 pvd threshold 1 falling edge 2.04 2.05 2.08 rising edge 2.12 2.14 2.17 v pvd2 pvd threshold 2 falling edge 2.21 2.24 2.28 rising edge 2.31 2.33 2.37 v pvd3 pvd threshold 3 falling edge 2.41 2.44 2.48 rising edge 2.51 2.53 2.57 v pvd4 pvd threshold 4 falling edge 2.61 2.64 2.69 rising edge 2.71 2.74 2.79 v pvd5 pvd threshold 5 falling edge 2.79 2.83 2.88 rising edge 2.90 2.94 2.99 v pvd6 pvd threshold 6 falling edge 3.01 3.04 3.09 rising edge 3.12 3.15 3.20 1. guaranteed by design. 2. guaranteed by characterization results. docid018780 rev 9 59/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 11. por/bor thresholds 9.3.3 supply current characteristics total current consumption the mcu is placed under the following conditions: l all i/o pins in input mode with a static value at v dd or v ss (no load) l all peripherals are disabled except if explicitly mentioned. in the following table, data is based on characterization results, unless otherwise specified. subject to general operating conditions for v dd and t a . 9 9 ' ' , q w h u q d o 1 5 6 7 9 % 2 5 % 2 5 w k u h v k r o g % 2 5 w k u h v k r o g b 3 ' 5 w k u h v k r o g z l w k % 2 5 z l w k r x w % 2 5 7 l p h z l w k % 2 5 6 d i h u h v h w 5 h v h w % 2 5 d f w l y d w h g e \ x v h u i r u s r z h u g r z q g h w h f w l r q 2 s h u d w l q j s r z h u v x s s o \ 9 z l w k r x w % 2 5 e d w w h u \ o l i h h [ w h q v l r q 9 3 ' 5 % 2 5 d o z d \ v d f w l y h d w s r z h u x s 6 d i h u h v h w u h o h d v h d l e 9 ' ' 9 ' ' electrical parameters stm8l151x2, stm8l151x3 60/122 docid018780 rev 9 table 19. total current consumption in run mode symbol para meter conditions (1) typ max unit 55 c 85 c 105c (2) 125 c (2) i dd(run) supply current in run mode (3) all peripherals off, code executed from ram, v dd from 1.65 v to 3.6 v hsi rc osc. (16 mhz) (4) f cpu = 125 khz 0.39 0.47 0.49 0.52 0.55 ma f cpu = 1 mhz 0.48 0.56 0.58 0.61 0.65 f cpu = 4 mhz 0.75 0.84 0.86 0.91 0.99 f cpu = 8 mhz 1.10 1.20 1.25 1.31 1.40 f cpu = 16 mhz 1.85 1.93 2.12 (6) 2.29 (6) 2.36 (6) hse external clock (f cpu =f hse ) (5) f cpu = 125 khz 0.05 0.06 0.09 0.11 0.12 f cpu = 1 mhz 0.18 0.19 0.20 0.22 0.23 f cpu = 4 mhz 0.55 0.62 0.64 0.71 0.77 f cpu = 8 mhz 0.99 1.20 1.21 1.22 1.24 f cpu = 16 mhz 1.90 2.22 2.23 (6) 2.24 (6) 2.28 (6) lsi rc osc. (typ. 38 khz) f cpu = f lsi 0.040 0.045 0.046 0.048 0.050 lse external clock (32.768 khz) f cpu = f lse 0.035 0.040 0.048 (6) 0.050 0.062 i dd(run) supply current in run mode all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi rc osc. (7) f cpu = 125 khz 0.43 0.55 0.56 0.58 0.62 ma f cpu = 1 mhz 0.60 0.77 0.80 0.82 0.87 f cpu = 4 mhz 1.11 1.34 1.37 1.39 1.43 f cpu = 8 mhz 1.90 2.20 2.23 2.31 2.40 f cpu = 16 mhz 3.8 4.60 4.75 4.87 4.88 hse external clock (f cpu =f hse ) (5) f cpu = 125 khz 0.30 0.36 0.39 0.44 0.47 f cpu = 1 mhz 0.40 0.50 0.52 0.55 0.56 f cpu = 4 mhz 1.15 1.31 1.40 1.45 1.48 f cpu = 8 mhz 2.17 2.33 2.44 2.56 2.77 f cpu = 16 mhz 4.0 4.46 4.52 4.59 4.77 lsi rc osc. f cpu = f lsi 0.110 0.123 0.130 0.140 0.150 lse ext. clock (32.768 khz) (8) f cpu = f lse 0.100 0.101 0.104 0.119 0.122 1. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc., f cpu =f sysclk 2. for devices with suffix 3 3. cpu executing typical data processing docid018780 rev 9 61/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 12. typ. i dd(run) vs. v dd , f cpu = 16 mhz 1. typical current consumption meas ured with code executed from ram 4. the run from ram consumption can be approximated with the linear formula: i dd (run_from_ram) = freq * 90 a/mhz + 380 a 5. oscillator bypassed (hsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 30 . 6. tested in production. 7. the run from flash consumption can be approximated with the linear formula: i dd (run_from_flash) = freq * 195 a/mhz + 440 a 8. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 31 . 9 ' ' > 9 @ ? & ? & ? & d l e , ' ' 5 8 1 + 6 , > p $ @ electrical parameters stm8l151x2, stm8l151x3 62/122 docid018780 rev 9 in the following table, data is based on characterization results, unless otherwise specified. table 20. total current consumption in wait mode symbol parameter conditions (1) typ max unit 55c 85 c 105 c (2) 125 c (2) i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from ram with flash in i ddq mode (3) , v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 0.33 0.39 0.41 0.43 0.45 ma f cpu = 1 mhz 0.35 0.41 0.44 0.45 0.48 f cpu = 4 mhz 0.42 0.51 0.52 0.54 0.58 f cpu = 8 mhz 0.52 0.57 0.58 0.59 0.62 f cpu = 16 mhz 0.68 0.76 0.79 0.82 (5) 0.85 (5) hse external clock (f cpu =f hse ) (4) f cpu = 125 khz 0.032 0.056 0.068 0.072 0.093 f cpu = 1 mhz 0.078 0.121 0.144 0.163 0.197 f cpu = 4 mhz 0.218 0.26 0.30 0.36 0.40 f cpu = 8 mhz 0.40 0.52 0.57 0.62 0.66 f cpu = 16 mhz 0.760 1.01 1.05 1.09 (5) 1.16 (5) lsi f cpu = f lsi 0.035 0.044 0.046 0.049 0.054 lse (6) external clock (32.768 khz) f cpu = f lse 0.032 0.036 0.038 0.044 0.051 docid018780 rev 9 63/122 stm8l151x2, stm8l151x3 electrical parameters 102 i dd(wait) supply current in wait mode cpu not clocked, all peripherals off, code executed from flash, v dd from 1.65 v to 3.6 v hsi f cpu = 125 khz 0.38 0.48 0.49 0.50 0.56 ma f cpu = 1 mhz 0.41 0.49 0.51 0.53 0.59 f cpu = 4 mhz 0.50 0.57 0.58 0.62 0.66 f cpu = 8 mhz 0.60 0.66 0.68 0.72 0.74 f cpu = 16 mhz 0.79 0.84 0.86 0.87 0.90 hse (4) external clock (f cpu =hse) f cpu = 125 khz 0.06 0.08 0.09 0.10 0.12 f cpu = 1 mhz 0.10 0.17 0.18 0.19 0.22 f cpu = 4 mhz 0.24 0.36 0.39 0.41 0.44 f cpu = 8 mhz 0.50 0.58 0.61 0.62 0.64 f cpu = 16 mhz 1.00 1.08 1.14 1.16 1.18 lsi f cpu = f lsi 0.055 0.058 0.065 0.073 0.080 lse (6) external clock (32.768 khz) f cpu = f lse 0.051 0.056 0.060 0.065 0.073 1. all peripherals off, v dd from 1.65 v to 3.6 v, hsi internal rc osc., f cpu = f sysclk 2. for temperature range 3. 3. flash is configured in i ddq mode in wait mode by setting the epm or waitm bit in the flash_cr1 register. 4. oscillator bypassed (hsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the hse consumption (i dd hse ) must be added. refer to table 30 . 5. tested in production. 6. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd hse ) must be added. refer to table 31 . table 20. total current consumption in wait mode (continued) symbol parameter conditions (1) typ max unit 55c 85 c 105 c (2) 125 c (2) electrical parameters stm8l151x2, stm8l151x3 64/122 docid018780 rev 9 figure 13. typ. i dd(wait) vs. v dd , f cpu = 16 mhz 1) 1. typical current consumption measured with code executed from flash memory. 9 ' ' > 9 @ , ' ' : $ , 7 + 6 , > ? $ @ ? & ? & ? & d l e docid018780 rev 9 65/122 stm8l151x2, stm8l151x3 electrical parameters 102 in the following table, data is based on characterization results, unless otherwise specified. table 21. total current consumption and timing in low power run mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1)(2) typ max unit i dd(lpr) supply current in low power run mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 5.1 5.4 a t a = 55 c 5.7 6 t a = 85 c 6.8 7.5 t a = 105 c 9.2 10.4 t a = 125 c 13.4 16.6 with tim2 active (3) t a = -40 c to 25 c 5.4 5.7 t a = 55 c 6.0 6.3 t a = 85 c 7.2 7.8 t a = 105 c 9.4 10.7 t a = 125 c 13.8 17 lse (4) external clock (32.768 khz) all peripherals off t a = -40 c to 25 c 5.25 5.6 t a = 55 c 5.67 6.1 t a = 85 c 5.85 6.3 t a = 105 c 7.11 7.6 t a = 125 c 9.84 12 with tim2 active (3) t a = -40 c to 25 c 5.59 6 t a = 55 c 6.10 6.4 t a = 85 c 6.30 7 t a = 105 c 7.55 8.4 t a = 125 c 10.1 15 1. no floating i/os 2. t a > 85 c is valid only for devices with suffix 3 temperature range. 3. timer 2 clock enabled and counter running 4. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 31 electrical parameters stm8l151x2, stm8l151x3 66/122 docid018780 rev 9 figure 14. typ. i dd(lpr) vs. v dd (lsi clock source) d l e , ' ' / 3 5 / 6 , > ? $ @ ? & ? & ? & 9 ' ' > 9 @ docid018780 rev 9 67/122 stm8l151x2, stm8l151x3 electrical parameters 102 in the following table, data is based on characterization results, unless otherwise specified. table 22. total current consumption in low power wait mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1)(2) typ max unit i dd(lpw) supply current in low power wait mode lsi rc osc. (at 38 khz) all peripherals off t a = -40 c to 25 c 33.3 a t a = 55 c 3.3 3.6 t a = 85 c 4.4 5 t a = 105 c 6.7 8 t a = 125 c 11 14 with tim2 active (3) t a = -40 c to 25 c 3.4 3.7 t a = 55 c 3.7 4 t a = 85 c 4.8 5.4 t a = 105 c 7 8.3 t a = 125 c 11.3 14.5 lse external clock (4) (32.768 khz) all peripherals off t a = -40 c to 25 c 2.35 2.7 t a = 55 c 2.42 2.82 t a = 85 c 3.10 3.71 t a = 105 c 4.36 5.7 t a = 125 c 7.20 11 with tim2 active (3) t a = -40 c to 25 c 2.46 2.75 t a = 55 c 2.50 2.81 t a = 85 c 3.16 3.82 t a = 105 c 4.51 5.9 t a = 125 c 7.28 11 1. no floating i/os. 2. t a > 85 c is valid only for devices with suffix 3 temperature range. 3. timer 2 clock enabled and counter is running. 4. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 31 . electrical parameters stm8l151x2, stm8l151x3 68/122 docid018780 rev 9 figure 15. typ. i dd(lpw) vs. v dd (lsi clock source) , ' ' / 3 : / 6 , > ? $ @ ? & ? & ? & 9 ' ' > 9 @ d l e docid018780 rev 9 69/122 stm8l151x2, stm8l151x3 electrical parameters 102 in the following table, data is based on characterization results, unless otherwise specified. table 23. total current consumption and timing in active-halt mode at v dd = 1.65 v to 3.6 v symbol parameter conditions (1)(2) typ max unit i dd(ah) supply current in active-halt mode lsi rc (at 38 khz) t a = -40 c to 25 c 0.9 2.1 a t a = 55 c 1.2 3 t a = 85 c 1.5 3.4 t a = 105 c 2.6 6.6 t a = 125 c 5.1 12 lse external clock (32.768 khz) (3) t a = -40 c to 25 c 0.5 1.2 t a = 55 c 0.62 1.4 t a = 85 c 0.88 2.1 t a = 105 c 2.1 4.85 t a = 125 c 4.8 11 i dd(wufah) supply current during wakeup time from active-halt mode (using hsi) --2.4-ma t wu_hsi(ah) (4)(5) wakeup time from active-halt mode to run mode (using hsi) --4.77 s t wu_lsi(ah) (4) (5) wakeup time from active-halt mode to run mode (using lsi) - - 150 - s 1. no floating i/o, unles s otherwise specified. 2. t a > 85 c is valid only for devices with suffix 3 temperature range. 3. oscillator bypassed (lsebyp = 1 in clk_eckcr). when c onfigured for external crystal, the lse consumption (i dd lse ) must be added. refer to table 31 4. wakeup time until start of interrupt vector fetch. the first word of interrupt routine is fetched 4 cpu cycles after t wu . 5. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. table 24. typical current consumption in active-halt mode, rtc clocked by lse external crystal symbol parameter condition (1) typ unit i dd(ah) (2) supply current in active-halt mode v dd = 1.8 v lse 1.15 a lse/32 (3) 1.05 v dd = 3 v lse 1.30 lse/32 (3) 1.20 v dd = 3.6 v lse 1.45 lse/32 (3) 1.35 1. no floating i/o, unless otherwise specified. 2. based on measurements on bench with 32.768 khz external crystal oscillator. 3. rtc clock is lse divided by 32. electrical parameters stm8l151x2, stm8l151x3 70/122 docid018780 rev 9 in the following table, data is based on characterization results, unless otherwise specified. table 25. total current consumption and timing in halt mode at v dd = 1.65 to 3.6 v symbol parameter condition (1)(2) typ max unit i dd(halt) supply current in halt mode (ultra-low-power ulp bit =1 in the pwr_csr2 register ) t a = -40 c to 25 c 350 1400 (3) na t a = 55 c 580 2000 t a = 85 c 1160 2800 (3) t a = 105 c 2560 6700 (3) t a = 125 c 4.4 13 (3) a i dd(wuhalt) supply current during wakeup time from halt mode (using hsi) -2.4-ma t wu_hsi(halt) (4)(5) wakeup time from halt to run mode (using hsi) -4.77s t wu_lsi(halt) (4)(5) wakeup time from halt mode to run mode (using lsi) -150-s 1. t a = -40 to 125 c, no floating i/o, unless otherwise specified. 2. t a > 85 c is valid only for devices with suffix 3 temperature range. 3. tested in production. 4. ulp=0 or ulp=1 and fwu=1 in the pwr_csr2 register. 5. wakeup time until start of interrupt vector fetch. the first word of interrupt routine is fetched 4 cpu cycles after t wu . docid018780 rev 9 71/122 stm8l151x2, stm8l151x3 electrical parameters 102 current consumption of on-chip peripherals table 26. peripheral current consumption symbol parameter typ. v dd = 3.0 v unit i dd(tim2) tim2 supply current (1) 8 a/mhz i dd(tim3) tim3 supply current (1) 8 i dd(tim4) tim4 timer supply current (1) 3 i dd(usart1) usart1 supply current (2) 6 i dd(spi1) spi1 supply current (2) 3 i dd(i2c1) i 2 c1 supply current (2) 5 i dd(dma1) dma1 supply current (2) 3 i dd(wwdg) wwdg supply current (2) 2 i dd(all) peripherals on (3) 38 a/mhz i dd(adc1) adc1 supply current (4) 1500 a i dd(comp1) comparator 1 supply current (5) 0.160 a i dd(comp2) comparator 2 supply current (5) slow mode 2 fast mode 5 i dd(pvd/bor) power voltage detector and brownout reset unit supply current (6) 2.6 i dd(bor) brownout reset unit supply current (6) 2.4 i dd(idwdg) independent watchdog supply current including lsi supply current 0.45 excluding lsi supply current 0.05 1. data based on a differential i dd measurement between all peripherals off and a timer counter running at 16 mhz. the cpu is in wait mode in both cases. no ic/oc program med, no i/o pins toggling. not tested in production. 2. data based on a differential i dd measurement between the on-chip peripheral in reset configuration and not clocked and the on-chip peripheral when clocked and not kept under reset. the cp u is in wait mode in both cases. no i/o pins toggling. not tested in production. 3. peripherals listed above the i dd(all) parameter on: tim2, tim3, tim4, usart1, spi1, i2c1, dma1, wwdg. 4. data based on a differential i dd measurement between adc1 in reset conf iguration and continuous adc1 conversion. 5. data based on a differential i dd measurement between comp1 or comp2 in reset configuration and comp1 or comp2 enabled with static inputs. supply current of internal reference voltage excluded. 6. including supply current of internal reference voltage. electrical parameters stm8l151x2, stm8l151x3 72/122 docid018780 rev 9 9.3.4 clock and ti ming characteristics hse external clock (hsebyp = 1 in clk_eckcr) subject to general operating conditions for v dd and t a . lse external clock (lsebyp=1 in clk_eckcr) subject to general operating conditions for v dd and t a . table 27. current consumption under external reset symbol parameter conditions typ unit i dd(rst) supply current under external reset (1) all pins are externally tied to v dd v dd = 1.8 v 48 a v dd = 3 v 76 v dd = 3.6 v 91 1. all pins except pa0, pb0 and pb4 are floating under reset. pa0, pb0 and pb4 are configured with pull-up under reset. table 28. hse external clock characteristics symbol parameter conditions min typ max unit f hse_ext external clock source frequency (1) 1. guaranteed by design. - 1-16mhz v hseh osc_in input pin high level voltage 0.7 x v dd -v dd v v hsel osc_in input pin low level voltage v ss - 0.3 x v dd c in(hse) osc_in input capacitance (1) - - 2.6 - pf i leak_hse osc_in input leakage current v ss < v in < v dd --1a table 29. lse external clock characteristics symbol parameter min typ max unit f lse_ext external clock source frequency (1) - 32.768 - khz v lseh (2) osc32_in input pin high level voltage 0.7 x v dd -v dd v v lsel (2) osc32_in input pin low level voltage v ss - 0.3 x v dd c in(lse) osc32_in input capacitance (1) -0.6-pf i leak_lse osc32_in input leakage current - - 1 a 1. guaranteed by design. 2. guaranteed by characterization results. docid018780 rev 9 73/122 stm8l151x2, stm8l151x3 electrical parameters 102 hse crystal/ceramic resonator oscillator the hse clock can be supplied with a 1 to 16 mh z crystal/ceramic resonator oscillator. all the information given in this paragraph is ba sed on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillato r pins in order to mini mize output distortion and startup stabilization time. re fer to the crystal resonator m anufacturer for more details (frequency, package , accuracy...). figure 16. hse oscilla tor circuit diagram table 30. hse oscillator characteristics symbol parameter conditions min typ max unit f hse high speed external oscillator frequency -1-16mhz r f feedback resistor - - 200 - k c (1) recommended load capacitance (2) --20-pf i dd(hse) hse oscillator power consumption c = 20 pf, f osc = 16 mhz -- 2.5 (startup) 0.7 (stabilized) (3) ma c = 10 pf, f osc =16 mhz -- 2.5 (startup) 0.46 (stabilized) (3) g m oscillator transconductance - 3.5 (3) --ma/v t su(hse) (4) startup time v dd is stabilized - 1 - ms 1. c= c l1 = c l2 is approximately equivalent to 2 x crystal c load . 2. the oscillator selection can be optimized in terms of supply current using a high qual ity resonator with small r m value. refer to crystal manufacturer for more details 3. guaranteed by design. 4. t su(hse) is the startup time measured from the moment it is enabled (by software) to a stabili zed 16 mhz oscillation. this value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. 0 6 9 2 6 & 2 8 7 2 6 & , 1 i + 6 ( w r f r u h & / 5 ) 6 7 0 5 h v r q d w r u & r q v x p s w l r q f r q w u r o j p 5 p & p / p 5 h v r q d w r u & / & 2 electrical parameters stm8l151x2, stm8l151x3 74/122 docid018780 rev 9 hse oscillator critical g m formula g mcrit 2 f hse () 2 r m 2co c + () 2 = r m : motional resistance (see crystal specification), l m : motional inductance (see crystal specification), c m : motional capacitance (see crystal specification), co: shunt capacit ance (see crystal specification), c l1 =c l2 =c: grounded external capacitance g m >> g mcrit lse crystal/ceramic resonator oscillator the lse clock can be supplied with a 32.768 kh z crystal/ceramic resonator oscillator. all the information given in this paragraph is ba sed on characterization results with specified typical external components. in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillato r pins in order to mini mize output distortion and startup stabilization time. re fer to the crystal resonator m anufacturer for more details (frequency, package , accuracy...). table 31. lse oscillator characteristics symbol parameter conditions min typ max unit f lse low speed external oscillator frequency - - 32.768 - khz r f feedback resistor v = 200 mv - 1.2 - m c (1) 1. c= c l1 = c l2 is approximately equivalent to 2 x crystal c load . recommended load capacitance (2) 2. the oscillator selection can be optimized in terms of supply current using a high quality resonator with a small r m value. refer to crystal manufacturer for more details. --8-p f i dd(lse) lse oscillator power consumption ---1.4 (3) 3. guaranteed by design. a v dd = 1.8 v - 450 - na v dd = 3 v - 600 - v dd = 3.6 v - 750 - g m oscillator transconductance - 3 (3) --a/v t su(lse) (4) 4. t su(lse) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 khz oscillation. this value is measured for a st andard crystal resonator and it can vary significantly with the crystal manufacturer. startup time v dd is stabilized - 1 - s docid018780 rev 9 75/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 17. lse oscilla tor circuit diagram internal clock sources subject to general operating conditions for v dd , and t a . high speed internal rc oscillator (hsi) in the following table, data is based on char acterization results, not tested in production, unless otherwise specified. 0 6 y 9 2 6 & 2 8 7 2 6 & , 1 i / 6 ( & / 5 ) 6 7 0 5 h v r q d w r u & r q v x p s w l r q f r q w u r o j p 5 p & p / p 5 h v r q d w r u & / & 2 table 32. hsi oscillator characteristics symbol parameter conditions (1)(2) min typ max unit f hsi frequency v dd = 3.0 v - 16 - mhz acc hsi accuracy of hsi oscillator (factory calibrated) v dd = 3.0 v, t a = 25 c -1 (3) -1 (3) % v dd = 3.0 v, 0 c t a 55 c -1.5 - 1.5 % v dd = 3.0 v, -10 c t a 70 c -2 - 2 % v dd = 3.0 v, -10 c t a 85 c -2.5 - 2 % v dd = 3.0 v, -10 c t a 125 c -4.5 - 2 % 1.65 v v dd 3.6 v, -40 c t a 125 c -4.5 - 3 % trim hsi user trimming step (4) trimming code multiple of 16 - 0.4 0.7 % trimming code = multiple of 16 - 1.5 % t su(hsi) hsi oscillator setup time (wakeup time) --3.76 (5) s i dd(hsi) hsi oscillator power consumption - - 100 140 (5) a 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. t a > 85 c is valid only for devices with suffix 3 temperature range. 3. tested in production. 4. the trimming step differs depending on the trimming code. it is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xe0). refer to the an3101 ?stm8l15x internal rc oscillator calibration? application note for more details. 5. guaranteed by design. electrical parameters stm8l151x2, stm8l151x3 76/122 docid018780 rev 9 figure 18. typical hsi frequency vs v dd low speed internal rc oscillator (lsi) in the following table, data is based on char acterization results, not tested in production. table 33. lsi oscilla tor characteristics symbol parameter (1) 1. v dd = 1.65 v to 3.6 v, t a = -40 to 125 c unless otherwise specified. conditions (1) min typ max unit f lsi frequency - 26 38 56 khz t su(lsi) lsi oscillator wakeup time - - - 200 (2) 2. guaranteed by design. s i dd(lsi) lsi oscillator frequency drift (3) 3. this is a deviation for an individual par t, once the initial frequency has been measured. 0 c t a 85 c -12 - 11 % ? & ? & ? & 9 ' ' > 9 @ + 6 , i u h t x h q f \ > 0 + ] @ d l f docid018780 rev 9 77/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 19. typical lsi frequency vs. v dd ? & ? & ? & d l e 9 ' ' > 9 @ / 6 , i u h t x h q f \ > n + ] @ electrical parameters stm8l151x2, stm8l151x3 78/122 docid018780 rev 9 9.3.5 memory characteristics t a = -40 to 125 c unless otherwise specified. flash memory table 34. ram and hardware registers symbol parameter conditions min typ max unit v rm data retention mode (1) 1. minimum supply voltage without losing data stored in ram (in halt mode or under reset) or in hardware registers (only in halt mode). g uaranteed by characterization results. halt mode (or reset) 1.65 - - v table 35. flash program and data eeprom memory symbol parameter conditions min typ max (1) unit v dd operating voltage (all modes, read/ write/erase) f sysclk = 16 mhz 1.65 - 3.6 v t prog programming time for 1 or 64 bytes (block) erase/write cycles (on programmed byte) --6-ms programming time for 1 to 64 bytes (block) write cycles (on erased byte) --3-ms i prog programming/ erasing consumption t a = +25 c, v dd = 3.0 v - 0.7 - ma t a = +25 c, v dd = 1.8 v - 0.7 - t ret (2) data retention (progr am memory) after 10000 erase/write cycles at t a = ?40 to +85 c (3 and 6 suffix) t ret = +85 c 30 (1) -- years data retention (progr am memory) after 10000 erase/write cycles at t a = ?40 to +125 c (3 suffix) t ret = +125 c 5 (1) -- data retention (data memory) after 300000 erase/write cycles at t a = ?40 to +85 c (3 and 6 suffix) t ret = +85 c 30 (1) -- data retention (data memory) after 300000 erase/write cycles at t a = ?40 to +125 c (3 suffix) t ret = +125 c 5 (1) -- n rw (3) erase/write cycles (program memory) t a = ?40 to +85 c (3 and 6 suffix), t a = ?40 to +105 c (3 suffix) or t a = ?40 to +125 c (3 suffix) 10 (1) -- kcycles erase/write cycles (data memory) 300 (1) (4) -- 1. guaranteed by characterization results. 2. conforming to jedec jesd22a117 3. the physical granularity of the memory is 4 bytes, so cy cling is performed on 4 bytes even when a write/erase operation addresses a single byte. 4. data based on characterization performed on the whole data memory. docid018780 rev 9 79/122 stm8l151x2, stm8l151x3 electrical parameters 102 9.3.6 i/o current inj ection characteristics as a general rule, current injection to the i/o pins, due to external voltage below v ss or above v dd (for standard pins) should be avoided during normal product operation. however, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection acci dentally happens, susceptibility tests are performed on a sample basis during device characterization. functional susceptibility to i/o current injection while a simple application is executed on the device, the device is stressed by injecting current into the i/o pins programmed in floating input mode . while current is injected into the i/o pin, one at a time, the device is checked for functional failures. the failure is indicated by an out of range parameter: adc1 error, out of spec current injection on adjacent pins or other functional failure (for example reset, oscillator frequency deviation, etc.). the test results are given in the following table. 9.3.7 i/o port pin characteristics general characteristics subject to general operating conditions for v dd and t a unless otherwise specified. all unused pins must be kept at a fixed voltage: using the output mode of the i/o for example or an external pull-up or pull-down resistor. table 36. i/o current injection susceptibility symbol description functional susceptibility unit negative injection positive injection i inj injected current on true open-drain pins (pc0 and pc1) -5 +0 ma injected current on all five-volt tolerant pins -5 +0 injected current on all 3.6 v tolerant pins -5 +0 injected current on any other pin -5 +5 electrical parameters stm8l151x2, stm8l151x3 80/122 docid018780 rev 9 table 37. i/o static characteristics symbol parameter conditions (1) min typ max unit v il input low level voltage (2) input voltage on true open-drain pins (pc0 and pc1) v ss -0.3 - 0.3 x v dd v input voltage on any other pin v ss -0.3 - 0.3 x v dd v ih input high level voltage (2) input voltage on true open-drain pins (pc0 and pc1) with v dd < 2 v 0.70 x v dd -5.2 v input voltage on true open-drain pins (pc0 and pc1) with v dd 2 v -5.5 input voltage on any other pin 0.70 x v dd - v dd +0.3 v hys schmitt trigger voltage hysteresis (3) i/os - 200 - mv true open drain i/os - 200 - i lkg input leakage current (4) v ss v in v dd high sink i/os - - 50 (5) na v ss v in v dd true open drain i/os - - 200 (5) v ss v in v dd pa0 with high sink led driver capability - - 200 (5) r pu weak pull-up equivalent resistor (2)(6) v in = v ss 30 45 60 k c io i/o pin capacitance - - 5 - pf 1. v dd = 3.0 v, t a = -40 to 125 c unless otherwise specified. 2. guaranteed by characterization results. 3. hysteresis voltage between schmitt trigger switching le vels. based on characterization results, not tested. 4. the max. value may be exceeded if negative current is injected on adjacent pins. 5. not tested in production. 6. r pu pull-up equivalent resistor based on a resistive transist or (corresponding i pu current characteristics described in figure 23 ). docid018780 rev 9 81/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 20. typical v il and v ih vs v dd (high sink i/os) figure 21. typical v il and v ih vs v dd (true open drain i/os) ? & ? & ? & d l f 9 , / d q g 9 , + > 9 @ 9 ' ' > 9 @ ? & ? & ? & d l e 9 , / d q g 9 , + > 9 @ 9 ' ' > 9 @ electrical parameters stm8l151x2, stm8l151x3 82/122 docid018780 rev 9 figure 22. typical pul l-up resistance r pu vs v dd with v in =v ss figure 23. typical pull-up current i pu vs v dd with v in =v ss ? & ? & ? & d l e 3 x o o x s u h v l v w d q f h > n ? @ 9 ' ' > 9 @ ? & ? & ? & d l e 3 x o o x s f x u u h q w > ? $ @ 9 ' ' > 9 @ docid018780 rev 9 83/122 stm8l151x2, stm8l151x3 electrical parameters 102 output driving current subject to general operating conditions for v dd and t a unless otherwise specified. table 38. output driving current (high sink ports) i/o type symbol parameter conditions min max unit high sink v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +2 ma, v dd = 3.0 v -0.45v i io = +2 ma, v dd = 1.8 v -0.45v i io = +10 ma, v dd = 3.0 v -0.7v v oh (2) 2. the i io current sourced must always respect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vdd . output high level vo ltage for an i/o pin i io = -2 ma, v dd = 3.0 v v dd -0.45 -v i io = -1 ma, v dd = 1.8 v v dd -0.45 -v i io = -10 ma, v dd = 3.0 v v dd -0.7 - v table 39. output driving current (true open drain ports) i/o type symbol parameter conditions min max unit open drain v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +3 ma, v dd = 3.0 v -0.45 v i io = +1 ma, v dd = 1.8 v -0.45 table 40. output driving current (pa0 with high sink led driver capability) i/o type symbol parameter conditions min max unit ir v ol (1) 1. the i io current sunk must always respect the absolute maximum rating specified in table 15 and the sum of i io (i/o ports and control pins) must not exceed i vss . output low level voltage for an i/o pin i io = +20 ma, v dd = 2.0 v -0.45v electrical parameters stm8l151x2, stm8l151x3 84/122 docid018780 rev 9 figure 24. typ. v ol @ v dd = 3.0 v (high sink ports) figure 25. typ. v ol @ v dd = 1.8 v (high sink ports) ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # a i ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # a i figure 26. typ. v ol @ v dd = 3.0 v (true open drain ports) figure 27. typ. v ol @ v dd = 1.8 v (true open drain ports) a i ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # ) / , ; m ! = 6 / , ; 6 = ? # ? # ? # ? # b j figure 28. typ. v dd - v oh @ v dd = 3.0 v (high sink ports) figure 29. typ. v dd - v oh @ v dd = 1.8 v (high sink ports) ) / ( ; m ! = 6 $ $ 6 / ( ; 6 = ? # ? # ? # ? # a i ) / ( ; m ! = 6 $ $ 6 / ( ; 6 = ? # ? # ? # ? # b j docid018780 rev 9 85/122 stm8l151x2, stm8l151x3 electrical parameters 102 nrst pin subject to general operating conditions for v dd and t a unless otherwise specified. figure 30. typical nrst pull-up resistance r pu vs v dd table 41. nrst pin characteristics symbol parameter conditions min typ max unit v il(nrst) nrst input low level voltage (1) - v ss -0.8 v v ih(nrst) nrst input high level voltage (1) -1.4- v dd v ol(nrst) nrst output low level voltage (1) i ol = 2 ma for 2.7 v v dd 3.6 v -- 0.4 i ol = 1.5 ma for v dd < 2.7 v -- v hyst nrst input hysteresis (3) - 10%v dd (2) --mv r pu(nrst) nrst pull-up equivalent resistor (1) -304560k v f(nrst) nrst input filtered pulse (3) ---50 ns v nf(nrst) nrst input not filtered pulse (3) - 300 - - 1. guaranteed by characterization results. 2. 200 mv min. 3. guaranteed by design. 9 ' ' > 9 @ ? & ? & ? & d l e 3 x o o x s u h v l v w d q f h > n ? @ electrical parameters stm8l151x2, stm8l151x3 86/122 docid018780 rev 9 figure 31. typical nrst pull-up current i pu vs v dd the reset network shown in figure 32 protects the device against parasitic resets. the user must ensure that the level on the nrst pin can go below the v il(nrst) max. level specified in table 41 . otherwise the reset is not taken into account internally. for power consumption sensitive applications , the external reset capacitor value can be reduced to limit the charge/discharge current. if the nrst signal is used to reset the external circuitry, attention must be paid to the charge/discharge time of the external capacitor to fulfill the external devices rese t timing conditions. the minimum recommended capacity is 10 nf. figure 32. recommended nrst pin configuration 3 x o o x s f x u u h q w > ? $ @ 9 ' ' > 9 @ ? & ? & ? & d l e 5 3 8 1 5 6 7 ( [ w h u q d o u h v h w f l u f x l w 2 s w l r q d o x ) ) l o w h u , q w h u q d o u h v h w 6 7 0 0 6 9 9 ' ' docid018780 rev 9 87/122 stm8l151x2, stm8l151x3 electrical parameters 102 9.3.8 communication interfaces spi1 - serial peripheral interface unless otherwise specified, the parameters given in table 42 are derived from tests performed under ambient temperature, f sysclk frequency and v dd supply voltage conditions summarized in section 9.3.1 . refer to i/o port characte ristics for more details on the input/output alternate function ch aracteristics (nss, sck, mosi, miso). table 42. spi1 characteristics symbol parameter conditions (1) min max unit f sck 1/t c(sck) spi1 clock frequency master mode 0 8 mhz slave mode 0 8 t r(sck) t f(sck) spi1 clock rise and fall time capacitive load: c = 30 pf - 30 ns t su(nss) (2) nss setup time slave mode 4 x 1/f sysclk - t h(nss) (2) nss hold time slave mode 80 - t w(sckh) (2) t w(sckl) (2) sck high and low time master mode, f master = 8 mhz, f sck = 4 mhz 105 145 t su(mi) (2) t su(si) (2) data input setup time master mode 30 - slave mode 3 - t h(mi) (2) t h(si) (2) data input hold time master mode 15 - slave mode 0 - t a(so) (2)(3) data output access time slave mode - 3x 1/f sysclk t dis(so) (2)(4) data output disable time slave mode 30 - t v(so) (2) data output valid time slave mode (after enable edge) - 60 t v(mo) (2) data output valid time master mode (after enable edge) -20 t h(so) (2) data output hold time slave mode (after enable edge) 15 - t h(mo) (2) master mode (after enable edge) 1- 1. parameters are given by selecting 10 mhz i/o output frequency. 2. values based on design simulation and/or characterization results. 3. min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. 4. min time is for the minimum time to invalidate the output and max time is for the maximum time to put the data in hi-z. electrical parameters stm8l151x2, stm8l151x3 88/122 docid018780 rev 9 figure 33. spi1 timing diagram - slave mode and cpha=0 figure 34. spi1 timing diagram - slave mode and cpha=1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . docid018780 rev 9 89/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 35. spi1 timing diagram - master mode (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . a i 6 3 # + / u t p u t # 0 ( ! - / 3 ) / 5 4 0 5 4 - ) 3 / ) . 0 5 4 # 0 ( ! - 3 " ) . - 3 " / 5 4 " ) 4 ) . , 3 " / 5 4 , 3 " ) . # 0 / , # 0 / , " ) 4 / 5 4 . 3 3 i n p u t t c 3 # + t w 3 # + ( t w 3 # + , t r 3 # + t f 3 # + t h - ) ( i g h 3 # + / u t p u t # 0 ( ! # 0 ( ! # 0 / , # 0 / , t s u - ) t v - / t h - / electrical parameters stm8l151x2, stm8l151x3 90/122 docid018780 rev 9 i 2 c - inter ic control interface subject to general operating conditions for v dd , f sysclk , and t a unless otherwise specified. the stm8l i 2 c interface (i2c1) meets the requirements of the standard i 2 c communication protocol described in the following table with the restriction mentioned below: refer to i/o port characteristics for more de tails on the input/output alternate function characteristics (sda and scl). note: for speeds around 200 khz, the achieved speed can have a 5% tolerance for other speed ranges, the achieved speed can have a 2% tolerance the above variations depend on the accuracy of the external components used. table 43. i2c characteristics symbol parameter standard mode i 2 c fast mode i 2 c (1) 1. f sysclk must be at least equal to 8 mhz to achieve max fast i 2 c speed (400 khz). unit min (2) 2. data based on standard i 2 c protocol requirement, not tested in production. max (2) min (2) max (2) t w(scll) scl clock low time 4.7 - 1.3 - s t w(sclh) scl clock high time 4.0 - 0.6 - t su(sda) sda setup time 250 - 100 - ns t h(sda) sda data hold time 0 - 0 900 t r(sda) t r(scl) sda and scl rise time - 1000 - 300 t f(sda) t f(scl) sda and scl fall time - 300 - 300 t h(sta) start condition hold time 4.0 - 0.6 - s t su(sta) repeated start condition setup time 4.7 - 0.6 - t su(sto) stop condition setup time 4.0 - 0.6 - s t w(sto:sta) stop to start condition time (bus free) 4.7 - 1.3 - s c b capacitive load for each bus line - 400 - 400 pf docid018780 rev 9 91/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 36. typical application with i 2 c bus and timing diagram 1) 1. measurement points are done at cmos levels: 0.3 x v dd and 0.7 x v dd 6 7 0 / 0 6 9 5 h s h d w h g v w d u w 6 w d u w 6 w r s , & % 8 6 6 ' $ 6 & / 9 ' ' 9 ' ' 6 ' $ 6 & / n ? n ? ? ? 6 w d u w w i 6 ' $ w u 6 ' $ w v x 6 ' $ w k 6 ' $ w v x 6 7 $ w z 6 7 2 6 7 $ w v x 6 7 2 w k 6 7 $ w z 6 & / + w z 6 & / / w u 6 & / w i 6 & / electrical parameters stm8l151x2, stm8l151x3 92/122 docid018780 rev 9 9.3.9 embedded reference voltage in the following table, data is based on char acterization results, not tested in production, unless otherwise specified. table 44. reference voltage characteristics symbol parameter conditions min typ max. unit i refint internal reference voltage consumption - - 1.4 - a t s_vrefint (1)(2) adc1 sampling time when reading the internal reference voltage --510s i buf (2) internal reference voltage buffer consumption (used for adc1) - - 13.5 25 a v refint out reference voltage output - 1.202 (3) 1.224 1.242 (3) v i lpbuf (2) internal reference voltage low power buffer consumption (used for comparators or output) - - 730 1200 na i refout (2) buffer output current (4) ---1a c refout reference voltage output load - - - 50 pf t vrefint internal reference voltage startup time --23ms t bufen (2) internal reference voltage buffer startup time once enabled (1) ---10s acc vrefint accuracy of v refint stored in the vrefint_factory_conv byte (5) --- 5mv stab vrefint stability of v refint over temperature -40 c t a 125 c - 20 50 ppm/c stability of v refint over temperature 0 c t a 50 c - - 20 ppm/c stab vrefint stability of v refint after 1000 hours - -- tbd ppm 1. defined when adc1 output reac hes its final value 1/2lsb 2. guaranteed by design. 3. tested in production at v dd = 3 v 10 mv. 4. to guaranty less than 1% v refout deviation. 5. measured at v dd = 3 v 10 mv. this value takes into account v dd accuracy and adc1 conversion accuracy. docid018780 rev 9 93/122 stm8l151x2, stm8l151x3 electrical parameters 102 9.3.10 temperature sensor in the following table, data is based on char acterization results, not tested in production, unless otherwise specified. 9.3.11 comparator characteristics in the following table, data is guaranteed by design, not tested in production, unless otherwise specified. table 45. ts characteristics symbol parameter min typ max. unit v 90 (1) 1. tested in production at v dd = 3 v 10 mv. the 8 lsb of the v 90 adc1 conversion result are stored in the ts_factory_conv_v90 byte. sensor reference voltage at 90c 5 c, 0.580 0.597 0.614 v t l v sensor linearity with temperature - 1 2 c avg_slope (2) average slope 1.59 1.62 1.65 mv/c i dd(temp) (2) consumption - 3.4 6 a t start (2)(3) 2. guaranteed by design. 3. defined for adc1 output reaching its final value 1/2lsb. temperature sensor startup time - - 10 s t s_temp (2) adc1 sampling time when reading the temperature sensor 10 - - s table 46. comparator 1 characteristics symbol parameter min typ max (1) 1. guaranteed by characterization results. unit v dda analog supply voltage 1.65 - 3.6 v t a temperature range -40 - 125 c r 400k r 400k value 300 400 500 k r 10k r 10k value 7.5 10 12.5 v in comparator 1 input voltage range 0.6 - v dda v v refint internal reference voltage (2) 2. tested in production at v dd = 3 v 10 mv. 1.202 1.224 1.242 t start comparator startup time - 7 10 s t d propagation delay (3) 3. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. -310 v offset comparator offset error - 3 10 mv i comp1 current consumption (4) 4. comparator consumption only. internal reference voltage not included. - 160 260 na electrical parameters stm8l151x2, stm8l151x3 94/122 docid018780 rev 9 in the following table, data is guarant eed by design, not tested in production. table 47. comparator 2 characteristics symbol parameter conditions min typ max (1) 1. guaranteed by characterization results. unit v dda analog supply voltage - 1.65 - 3.6 v t a temperature range - -40 - 125 c v in comparator 2 input voltage range - 0 - v dda v t start comparator startup time fast mode - 15 20 s slow mode - 20 25 t d slow propagation delay in slow mode (2) 2. the delay is characterized for 100 mv input step with 10 mv overdrive on the inverting input, the non- inverting input set to the reference. 1.65 v v dda 2.7 v - 1.8 3.5 2.7 v v dda 3.6 v - 2.5 6 t d fast propagation delay in fast mode (2) 1.65 v v dda 2.7 v - 0.8 2 2.7 v v dda 3.6 v - 1.2 4 v offset comparator offset error - - 4 20 mv i comp2 current consumption (3) 3. comparator consumption only. internal reference voltage not included. fast mode - 3.5 5 a slow mode - 0.5 2 docid018780 rev 9 95/122 stm8l151x2, stm8l151x3 electrical parameters 102 9.3.12 12-bit adc1 characteristics in the following table, data is guarant eed by design, not tested in production. table 48. adc1 characteristics symbol parameter cond itions min typ max unit v dda analog supply voltage - 1.8 - 3.6 v v ref+ reference supply voltage 2.4 v v dda 3.6 v 2.4 - v dda v 1.8 v v dda 2.4 v v dda v v ref- lower reference voltage - v ssa v i vdda current on the v dda input pin - - 1000 1450 a i vref+ current on the v ref+ input pin -- 400 700 (peak) (1) a -- 450 (average) (1) a v ain conversion voltage range - 0 (2) - v ref+ v t a temperature range - -40 - 125 c r ain external resistance on v ain on pf0 fast channel - - 50 (3) k on all other channels - - c adc1 internal sample and hold capacitor on pf0 fast channel - 16 - pf on all other channels - - f adc1 adc1 sampling clock frequency 2.4 v v dda 3.6 v without zooming 0.320 - 16 mhz 1.8 v v dda 2.4 v with zooming 0.320 - 8 mhz f conv 12-bit conversion rate v ain on pf0 fast channel -- 1 (4)(5) mhz v ain on all other channels -- 760 (4)(5) khz f trig external trigger frequency --- t conv 1/f adc1 t lat external trigger latency - - - 3.5 1/f sysclk electrical parameters stm8l151x2, stm8l151x3 96/122 docid018780 rev 9 t s sampling time v ain on pf0 fast channel v dda < 2.4 v 0.43 (4)(5) --s v ain on pf0 fast channel 2.4 v v dda 3.6 v 0.22 (4)(5) --s v ain on slow channels v dda < 2.4 v 0.86 (4)(5) --s v ain on slow channels 2.4 v v dda 3.6 v 0.41 (4)(5) --s t conv 12-bit conversion time - 12 + t s 1/f adc1 16 mhz 1 (4) s t wkup wakeup time from off state ---3s t idle (6) time before a new conversion t a = +25 c - - 1 (7) s t a = +70 c - - 20 (7) ms t a = +125 c - - 2 (7) ms t vrefint internal reference voltage startup time --- refer to table 44 ms 1. the current consumption through v ref is composed of two parameters: - one constant (max 300 a) - one variable (max 400 a), only during sa mpling time + 2 firs t conversion pulses. so, peak consumption is 300+400 = 700 a and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 a at 1msps 2. v ref- or v dda must be tied to ground. 3. guaranteed by design. 4. minimum sampling and conversion time is reached for maximum rext = 0.5 k . 5. value obtained for continuous conversion on fast channel. 6. the time between 2 conversions, or between adc1 on and the first conversion must be lower than t idle. 7. the t idle maximum value is on the ?z? revision code of the device. table 48. adc1 characteristics (continued) symbol parameter cond itions min typ max unit docid018780 rev 9 97/122 stm8l151x2, stm8l151x3 electrical parameters 102 in the following three tables, da ta is guaranteed by characte rization result, not tested in production. table 49. adc1 accuracy with v dda = 3.3 v to 2.5 v symbol parameter conditions typ max unit dnl differential non linearity f adc1 = 16 mhz 1 1.6 lsb f adc1 = 8 mhz 1 1.6 f adc1 = 4 mhz 1 1.5 inl integral non linearity f adc1 = 16 mhz 1.2 2 f adc1 = 8 mhz 1.2 1.8 f adc1 = 4 mhz 1.2 1.7 tue total unadjusted error f adc1 = 16 mhz 2.2 3.0 f adc1 = 8 mhz 1.8 2.5 f adc1 = 4 mhz 1.8 2.3 offset offset error f adc1 = 16 mhz 1.5 2 lsb f adc1 = 8 mhz 1 1.5 f adc1 = 4 mhz 0.7 1.2 gain gain error f adc1 = 16 mhz 11.5 f adc1 = 8 mhz f adc1 = 4 mhz table 50. adc1 accuracy with v dda = 2.4 v to 3.6 v symbol parameter typ max unit dnl differential non linearity 1 2 lsb inl integral non linearity 1.7 3 lsb tue total unadjusted error 24lsb offset offset error 1 2 lsb gain gain error 1.5 3 lsb table 51. adc1 accuracy with v dda = v ref + = 1.8 v to 2.4 v symbol parameter typ max unit dnl differential non linearity 1 2 lsb inl integral non linearity 23lsb tue total unadjusted error 35lsb offset offset error 2 3 lsb gain gain error 2 3 lsb electrical parameters stm8l151x2, stm8l151x3 98/122 docid018780 rev 9 figure 37. adc1 accura cy characteristics figure 38. typical connection diagram using the adc1 1. refer to table 48 for the values of r ain and c adc1 . 2. c parasitic represents the capacitance of the pcb (dependent on soldering and pcb layout quality) plus the pad capacitance (roughly 7 pf). a high c parasitic value will downgrade conversion accuracy. to remedy this, f adc1 should be reduced. general pcb desi gn guidelines power supply decoupling should be performed as shown in figure 39 or figure 40 , depending on whether v ref+ is connected to v dda or not. good quality ceramic 10 nf capacitors should be used. they should be placed as close as possible to the chip. e o e g 1lsb ideal (1) example of an actual transfer curve (2) the ideal transfer curve (3) end point correlation line e t =total unadjusted error: maximum deviation between the actual and the ideal transfer curves. e o =offset error: deviation between the first actual transition and the first ideal one. e g =gain error: deviation between the last ideal transition and the last actual one. e d =differential linearity error: maximum deviation between actual steps and the ideal one. e l =integral linearity error: maximum deviation between any actual transition and the end point correlation line. 4095 4094 4093 5 4 3 2 1 0 7 6 1234567 4093 4094 4095 4096 (1) (2) e t e d e l (3) v dda v ssa ai14395b v ref+ 4096 (or depending on package)] v dda 4096 [1lsb ideal = d l i 6 7 0 , / ? q $ e l w f r q y h u w h u 6 d p s o h d q g k r o g $ ' & f r q y h u w h u 9 $ , 1 5 $ , 1 $ , 1 [ 9 ' ' 9 7 9 9 7 9 & s d u d v l w l f 5 $ ' & & $ ' & docid018780 rev 9 99/122 stm8l151x2, stm8l151x3 electrical parameters 102 figure 39. power supply and reference decoupling (v ref+ not connected to v dda ) figure 40. power supply and reference decoupling (v ref+ connected to v dda ) 6 x s s o \ ( [ w h u q d o u h i h u h q f h 6 7 0 / 9 5 ( ) 9 ' ' $ 9 6 6 $ 9 5 ( ) ? ) q ) ? ) q ) d l f 6 7 0 / 6 x s s o \ d l f ? ) q ) 9 5 ( ) 9 ' ' $ 9 5 ( ) 9 ' ' $ electrical parameters stm8l151x2, stm8l151x3 100/122 docid018780 rev 9 figure 41. max. dynamic current consumption on v ref+ supply pin during adc conversion 9.3.13 emc characteristics susceptibility tests are perfor med on a sample basis during product characterization. functional ems (electromagnetic susceptibility) based on a simple running application on the product (toggling 2 leds through i/o ports), the product is stressed by two electromagnetic ev ents until a failure occurs (indicated by the leds). ? esd : electrostatic discharge (positive and negati ve) is applied on all pins of the device until a functional disturbance occurs. this test conforms with the iec 61000 standard. ? ftb : a burst of fast transient voltage (p ositive and negative) is applied to v dd and v ss through a 100 pf capacitor, until a function al disturbance occurs. this test conforms with the iec 61000 standard. 0 6 9 $ ' & f o r f n 6 d p s o l q j q f \ f o h v & r q y h u v l r q f \ f o h v , u h i ? $ ? $ table 52. r ain max for f adc = 16 mhz t s (cycles) t s (s) r ain max (kohm) slow channels fast channels 2.4 v < v dda < 3.6 v 1.8 v < v dda < 2.4 v 2.4 v < v dda < 3.3 v 1.8 v < v dda < 2.4 v 4 0.25 not allowed not allowed 0.7 not allowed 9 0.5625 0.8 not allowed 2.0 1.0 16 1 2.0 0.8 4.0 3.0 24 1.5 3.0 1.8 6.0 4.5 48 3 6.8 4.0 15.0 10.0 96 6 15.0 10.0 30.0 20.0 192 12 32.0 25.0 50.0 40.0 384 24 50.0 50.0 50.0 50.0 docid018780 rev 9 101/122 stm8l151x2, stm8l151x3 electrical parameters 102 a device reset allows normal operations to be resumed. the test results are given in the table below based on the ems levels and classes defined in application note an1709. designing hardened software to avoid noise problems emc characterization and optimization are per formed at component level with a typical application environment and simplified mcu soft ware. it should be noted that good emc performance is highly dependent on the user application and the software in particular. therefore it is recommended that the user applies emc software optimization and prequalification tests in re lation with the emc level requested for his application. prequalification trials most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forci ng a low state on the nrst pin or the oscillator pins for 1 second. to complete these trials, esd stress can be applie d directly on the device, over the range of specification values. when unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note an1015). electromagnetic interference (emi) based on a simple application running on the product (toggling 2 leds through the i/o ports), the product is monitored in terms of em ission. this emission te st is in line with the norm iec61967-2 which specifies the board and the loading of each pin. table 53. ems data symbol parameter conditions level/ class v fesd voltage limits to be applied on any i/o pin to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 2b v eftb fast transient voltage burst limits to be applied through 100 pf on v dd and v ss pins to induce a functional disturbance v dd = 3.3 v, t a = +25 c, f cpu = 16 mhz, conforms to iec 61000 using hsi 4a using hse 2b table 54. emi data (1) 1. not tested in production. symbol parameter conditions monitored frequency band max vs. unit 16 mhz s emi peak level v dd = 3.6 v, t a = +25 c, lqfp48 conforming to iec61967-2 0.1 mhz to 30 mhz -3 db v 30 mhz to 130 mhz 9 130 mhz to 1 ghz 4 sae emi level 2 - electrical parameters stm8l151x2, stm8l151x3 102/122 docid018780 rev 9 absolute maximum ratings (electrical sensitivity) based on two different tests (esd and lu) using specific measurement methods, the product is stressed in order to determine its performance in terms of electrical sensitivity. for more details, refer to the application note an1181. electrostatic discharge (esd) electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combinati on. the sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). two models can be simulated: human body model and charge device model. this test conforms to the jesd22-a114a/a115a standard. static latch-up ? lu : 3 complementary static tests are required on 6 parts to assess the latch-up performance. a supply overvoltage (applied to each power supply pin) and a current injection (applied to each input, output and configurable i/o pin) are performed on each sample. this test conforms to the eia/jesd 78 ic latch-up standard. for more details, refer to the application note an1181. table 55. esd absolute maximum ratings symbol ratings conditions maximum value (1) 1. guaranteed by characterization results. unit v esd(hbm) electrostatic discharge voltage (human body model) t a = +25 c 2000 v v esd(cdm) electrostatic discharge voltage (charge device model) 500 table 56. electrical sensitivities symbol parameter class lu static latch-up class ii docid018780 rev 9 103/122 stm8l151x2, stm8l151x3 package information 119 10 package information 10.1 ecopack in order to meet environmental requirements, st offers these devices in different grades of ecopack? packages, depending on their le vel of environmental compliance. ecopack? specifications, grade definitions a nd product status are available at: www.st.com . ecopack? is an st trademark. 10.2 lqfp48 package information figure 42. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package outline 1. drawing is not to scale. " ? - % ? 6 0 ) . ) $ % . 4 ) & ) # ! 4 ) / . c c c # # $ m m ' ! 5 ' % 0 , ! . % b ! ! ! c ! , , $ $ % % % e 3 % ! 4 ) . ' 0 , ! . % + package information stm8l151x2, stm8l151x3 104/122 docid018780 rev 9 table 57. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a - - 1.600 - - 0.0630 a1 0.050 - 0.150 0.0020 - 0.0059 a2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 d 8.800 9.000 9.200 0.3465 0.3543 0.3622 d1 6.800 7.000 7.200 0.2677 0.2756 0.2835 d3 - 5.500 - - 0.2165 - e 8.800 9.000 9.200 0.3465 0.3543 0.3622 e1 6.800 7.000 7.200 0.2677 0.2756 0.2835 e3 - 5.500 - - 0.2165 - e - 0.500 - - 0.0197 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - k 03.57 03.57 ccc - - 0.080 - - 0.0031 docid018780 rev 9 105/122 stm8l151x2, stm8l151x3 package information 119 figure 43. lqfp48 - 48-pin, 7 x 7 mm low-profile quad flat package recommended footprint 1. dimensions are expr essed in millimeters. device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 44. lqfp48 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet a i d 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 6 w d q g d u g 6 7 o r j r - $ 5 package information stm8l151x2, stm8l151x3 106/122 docid018780 rev 9 qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 10.3 ufqfpn32 package information figure 45. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline 1. drawing is not to scale. ! " ? - % ? 6 3 , 1 , g h q w l i l h u 6 ( $ 7 , 1 * 3 / $ 1 ( & & g g g $ $ $ h e ' e ( / h ( ( ' / ' docid018780 rev 9 107/122 stm8l151x2, stm8l151x3 package information 119 figure 46. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. table 58. ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.0060 - b 0.180 0.230 0.280 0.0071 0.0091 0.0110 d 4.900 5.000 5.100 0.1929 0.1969 0.2008 d1 3.400 3.500 3.600 0.1339 0.1378 0.1417 d2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e 4.900 5.000 5.100 0.1929 0.1969 0.2008 e1 3.400 3.500 3.600 0.1339 0.1378 0.1417 e2 3.400 3.500 3.600 0.1339 0.1378 0.1417 e - 0.500 - - 0.0197 - l 0.300 0.400 0.500 0.0118 0.0157 0.0197 ddd - - 0.080 - - 0.0031 $ % b ) 3 b 9 package information stm8l151x2, stm8l151x3 108/122 docid018780 rev 9 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 47. ufqfpn32 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q ' r w s l q 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 6 w d q g d u g 6 7 o r j r - , docid018780 rev 9 109/122 stm8l151x2, stm8l151x3 package information 119 10.4 ufqfpn28 package information figure 48. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 1. drawing is not to scale. table 59. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data (1) symbol millimeters inches min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 - 0.000 0.050 - 0.0000 0.0020 d 3.900 4.000 4.100 0.1535 0.1575 0.1614 d1 2.900 3.000 3.100 0.1142 0.1181 0.1220 e 3.900 4.000 4.100 0.1535 0.1575 0.1614 e1 2.900 3.000 3.100 0.1142 0.1181 0.1220 l 0.300 0.400 0.500 0.0118 0.0157 0.0197 l1 0.250 0.350 0.450 0.0098 0.0138 0.0177 t - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ! " ? - % ? 6 ' ( ' ( ' h w d l o = ' h w d l o < ' package information stm8l151x2, stm8l151x3 110/122 docid018780 rev 9 figure 49. ufqfpn28 - 28-lead, 7x7 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. 1. values in inches are converted from mm and rounded to 4 decimal digits. ! " ? & 0 ? 6 docid018780 rev 9 111/122 stm8l151x2, stm8l151x3 package information 119 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 50. ufqfpn28 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q ' r w s l q 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 ( package information stm8l151x2, stm8l151x3 112/122 docid018780 rev 9 10.5 ufqfpn20 package information figure 51. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline 1. drawing is not to scale. $ $ b 0 ( b 9 ' h e h ( $ $ g g g / / $ / ' ( 7 2 3 9 , ( : 6 , ' ( 9 , ( : % 2 7 7 2 0 9 , ( : 3 l q / ( ' docid018780 rev 9 113/122 stm8l151x2, stm8l151x3 package information 119 figure 52. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package recommended footprint 1. dimensions are expr essed in millimeters. table 60. ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data symbol millimeters inches (1) 1. values in inches are converted from mm and rounded to 4 decimal digits. min typ max min typ max a 0.500 0.550 0.600 0.0197 0.0217 0.0236 a1 0.000 0.020 0.050 0.0000 0.0008 0.0020 a3 - 0.152 - - 0.060 - d 2.900 3.000 3.100 0.1142 0.1181 0.1220 d1 - 2.000 - - 0.0790 - e 2.900 3.000 3.100 0.1142 0.1181 0.1220 e1 - 2.000 - - 0.0790 - l1 0.500 0.550 0.600 0.0197 0.0217 0.0236 l2 0.300 0.350 0.400 0.0118 0.0138 0.0157 l3 - 0.200 - - 0.0079 - l5 - 0.150 - - 0.0059 - b 0.180 0.250 0.300 0.0071 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.050 - - 0.0020 ! ! ? & 0 ? 6 package information stm8l151x2, stm8l151x3 114/122 docid018780 rev 9 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 53. ufqfpn20 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q ' r w s l q 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 - docid018780 rev 9 115/122 stm8l151x2, stm8l151x3 package information 119 10.6 tssop20 package information figure 54.tssop20 ? 20-lead thin shrink sma ll outline, 6.5 x 4.4 mm, 0.65 mm pitch, package outline 1. drawing is not to scale. table 61. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data symbol millimeters inches (1) min. typ. max. min. typ. max. a - - 1.200 - - 0.0472 a1 0.050 - 0.150 0.0020 - 0.0059 a2 0.800 1.000 1.050 0.0315 0.0394 0.0413 b 0.190 - 0.300 0.0075 - 0.0118 c 0.090 - 0.200 0.0035 - 0.0079 d 6.400 6.500 6.600 0.2520 0.2559 0.2598 e 6.200 6.400 6.600 0.2441 0.2520 0.2598 e1 4.300 4.400 4.500 0.1693 0.1732 0.1772 e - 0.650 - - 0.0256 - l 0.450 0.600 0.750 0.0177 0.0236 0.0295 l1 - 1.000 - - 0.0394 - z z d z s? ? > ? l > ^ d / e ' w > e ' h ' w > e x?? uu w / e / e d / & / d / k e package information stm8l151x2, stm8l151x3 116/122 docid018780 rev 9 figure 55. tssop20 ? 20-lead thin shrink smal l outline, 6.5 x 4.4 mm, 0.65 mm pitch, package footprint 1. dimensions are expr essed in millimeters. k 0 - 8 0 - 8 aaa - - 0.100 - - 0.0039 1. values in inches are converted fr om mm and rounded to four decimal digits. table 61. tssop20 ? 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data (continued) symbol millimeters inches (1) min. typ. max. min. typ. max. 9 ! ? & 0 ? 6 docid018780 rev 9 117/122 stm8l151x2, stm8l151x3 package information 119 device marking the following figure gives an example of topsid e marking orientation versus pin 1 identifier location. other optional marking or inse t/upset marks, which depend on supply chain operations, are not indicated below. figure 56. tssop20 marking example (package top view) 1. parts marked as ?es?, ?e? or accompanied by an engineering sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at st charge. in no event, st will be liable for any customer usage of these engineering samples in production. st quality has to be cont acted prior to any decisi on to use these engineering samples to run qualification activity. 0 6 9 3 u r g x f w l g h q w l i l f d w l r q 3 l q l g h q w l i l h u 5 h y l v l r q f r g h ' d w h f r g h : 8 8 3 6 w d q g d u g 6 7 o r j r - ' 1 package information stm8l151x2, stm8l151x3 118/122 docid018780 rev 9 10.7 thermal characteristics the maximum chip junction temperature (t jmax ) must never exceed the values given in table 17: general operating conditions on page 57 . the maximum chip-junction temperature, t jmax , in degree celsius, may be calculated using the following equation: t jmax = t amax + (p dmax x ja ) where: ? t amax is the maximum ambient temperature in c ? ja is the package junction-to-ambient thermal resistance in c/w ? p dmax is the sum of p intmax and p i/omax (p dmax = p intmax + p i/omax ) ? p intmax is the product of i dd and v dd , expressed in watts. this is the maximum chip internal power. ? p i/omax represents the maximum power dissipation on output pins where: p i/omax = (v ol *i ol ) + ((v dd -v oh )*i oh ), taking into account the actual v ol /i ol and v oh /i oh of the i/os at low and high level in the application. table 62. thermal characteristics (1) 1. thermal resistances are based on jedec jesd51- 2 with 4-layer pcb in a natural convection environment. symbol parameter value unit ja thermal resistance junction-ambient lqfp 48- 7 x 7 mm 65 c/w ja thermal resistance junction-ambient ufqfpn 32 - 5 x 5 mm 38 c/w ja thermal resistance junction-ambient ufqfpn28 - 4 x 4 mm 80 c/w ja thermal resistance junction-ambient ufqfpn20 - 3 x 3 mm 102 c/w ja thermal resistance junction-ambient tssop20 110 c/w docid018780 rev 9 119/122 stm8l151x2, stm8l151x3 part numbering 119 11 part numbering for a list of available options (memory, package, and so on) or for further information on any aspect of this device, please cont act your nearest st sales office. table 63. low-density stm8l151x2/3 ordering information scheme example :stm8l151k3u3 tr device family stm8 = 8-bit microcontroller product type l = low power sub-family 151 = ultra-low power pin count c = 48 pins k = 32 pins g = 28 pins f = 20 pins program memory size 3 = 8 kbyte of flash memory 2 = 4 kbyte of flash memory package u = ufqfpn t = lqfp p = tssop temperature range 3 = ?40 to 125 c 6 = ?40 to 85 c packing no character = tray or tube tr = tape and reel revision history stm8l151x2, stm8l151x3 120/122 docid018780 rev 9 12 revision history table 64. document revision history date revision changes 08-jun-2011 1 initial release 02-sep-2011 2 modified figure: memory map. modified opt1 description in table: option byte addresses. modified t prog in table: flash program and data eeprom memory. modified figure: recommended nrst pin configuration. modified l2 in f igure: ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline. replaced pm0051 with pm0054 and um0320 with um0470. 09-feb-2012 3 added part number stm8l151c2. updated the captions of figure 3 and figure 4 . table: low-density stm8l151x2/3 pin description : updated od column of nrst/pa1 pin. figure: ufqfpn32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat package outline: removed the line over a1. figure recommended ufqfpn28 footprint (dimensions in mm): updated title. t able: tssop20 - 20-pin thin shrink small outline package mechanical data: updated title. 06-jul-2012 4 added ?i/o level? in table: legend/abbreviation for table 4 and table: low-densit y stm8l151x2/3 pin description. updated figure: ufqfpn20 - 20-lead ultra thin fine pitch quad flat package outline (3x3). updated figure: spi1 timing diagram - master mode. updated table: voltage characteristics and table: i/o static characteristics. 11-apr-2014 5 updated table: ufqfpn20 - 20-lead ultra thin fine pitch quad flat package (3x3) package mechanical data, added notes on table: tssop20 - 20-pin thin shrink small outline package mechanical data. changed reset value of syscfg_rmpcr1 register on table: general hard ware register map. updated table: low-density stm8l151x2/3 pin description and table: embedded reset and power control block characteristics. docid018780 rev 9 121/122 stm8l151x2, stm8l151x3 revision history 121 18-dec-2014 6 updated section: ufqfpn20 package information. replaced ?ultralow power? occu rrences with ?ultra-low- power?, and ?low density? with ?low-density? where applicable. 08-apr-2015 7 added: ? figure 44: lqfp48 marking example (package top view) , ? figure 47: ufqfpn32 marking example (package top view) , ? figure 50: ufqfpn28 marking example (package top view) , ? figure 53: ufqfpn20 marking example (package top view) , ? figure 56: tssop20 marking example (package top view) . updated: ? table 63: low-density stm8l151x2/3 ordering information scheme . moved section 10.7: thermal characteristics to section 10: package information . 01-oct-2016 8 in table 4: low-density stm8l151x2/3 pin description row corresponding to pin names pd6/adc1_in8 / rtc_calib/comp1_inp, inserted pin number 35 in lqfp48 column. 12-may-2017 9 updated: ? figure 51: ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package outline ? table 60: ufqfpn20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat package mechanical data ? table 45: ts characteristics ? section 9.2: absolu te maximum ratings ? updated all document?s footnotes from ?data guaranteed by design, not tested in production? (or similar) to ?guaranteed by design? and ?data based on characterization results, not tested in production.? (or similar) to ?guaranteed by design.? ? section : device ma rking on page 105 ? section : device ma rking on page 108 ? section : device marking on page 111 ? section : device marking on page 114 ? section : device marking on page 117 table 64. document revision history (continued) date revision changes stm8l151x2, stm8l151x3 122/122 docid018780 rev 9 important notice ? please read carefully stmicroelectronics nv and its subsidiaries (?st?) reserve the right to make changes, corrections, enhancements, modifications, and improvements to st products and/or to this document at any time without notice. purchasers should obtain the latest relevant in formation on st products before placing orders. st products are sold pursuant to st?s terms and conditions of sale in place at the time of o rder acknowledgement. purchasers are solely responsible for the choice, selection, and use of st products and st assumes no liability for application assistance or the design of purchasers? products. no license, express or implied, to any intellectual property right is granted by st herein. resale of st products with provisions different from the information set forth herein shall void any warranty granted by st for such product. st and the st logo are trademarks of st. all other product or service names are the property of their respective owners. information in this document supersedes and replaces information previously supplied in any prior versions of this document. ? 2017 stmicroelectronics ? all rights reserved |
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