View CDCF2510_9061529.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 1 post office box 655303 ? dallas, texas 75265 designed to meet pc133 sdram registered dimm specification rev. 0.9 spread spectrum clock compatible operating frequency 25 mhz to 140 mhz static tphase error distribution at 66mhz to 133 mhz is 125 ps jitter (cyc cyc) at 66 mhz to 133 mhz is |70| ps available in plastic 24-pin tssop phase-lock loop clock distribution for synchronous dram applications distributes one clock input to one bank of ten outputs output enable pin to enable/disable all 10 outputs external feedback (fbin) terminal is used to synchronize the outputs to the clock input on-chip series damping resistors no external rc network required operates at 3.3 v description the CDCF2510 is a high-performance, low-skew, low-jitter, phase-lock loop (pll) clock driver. it uses a pll to precisely align, in both frequency and phase, the feedback (fbout) output to the clock (clk) input signal. it is specifically designed for use with synchronous drams. the CDCF2510 operates at 3.3 v v cc . it also provides integrated series-damping resistors that make it ideal for driving point-to-point loads. one bank of ten outputs provide ten low-skew, low-jitter copies of clk. output signal duty cycles are adjusted to 50%, independent of the duty cycle at clk. the outputs can be enabled/disabled with the control (g) input. when the g input is high, the outputs switch in phase and frequency with clk; when the g input is low, the outputs are disabled to the logic-low state. unlike many products containing plls, the CDCF2510 does not require external rc networks. the loop filter for the pll is included on-chip, minimizing component count, board space, and cost. because it is based on pll circuitry, the CDCF2510 requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. this stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at clk, and following any changes to the pll reference or feedback signals. the pll can be bypassed for test purposes by strapping av cc to ground. the CDCF2510 is characterized for operation from 0 c to 85 c. for application information refer to application reports high speed distribution design techniques for cdc509/516/2509/2510/2516 (literature number slma003) and using cdc2509a/2510a pll with spread spectrum clocking (ssc) (literature number scaa039). production data information is current as of publication date. products conform to specifications per the terms of texas instruments standard warranty. production processing does not necessarily include testing of all parameters. copyright ? 1999, texas instruments incorporated please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. clk av cc v cc 1y9 1y8 gnd gnd 1y7 1y6 1y5 v cc fbin 1 2 3 4 5 6 7 8 9 10 11 12 agnd v cc 1y0 1y1 1y2 gnd gnd 1y3 1y4 v cc g fbout 24 23 22 21 20 19 18 17 16 15 14 13 pw package (top view)
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 2 post office box 655303 ? dallas, texas 75265 function table inputs outputs g clk 1y (0:9) fbout x l l l l hl h h h h h functional block diagram 1y2 1y1 1y0 ??????? ??????? ??????? ??????? pll fbin av cc clk g 1y7 1y6 1y5 1y8 fbout 1y3 1y4 11 24 13 23 3 4 5 8 9 15 16 17 20 12 1y9 21 available options package t a small outline (pw) 0 c to 85 c CDCF2510pwr
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal type description name no. type description clk 24 i clock input. clk provides the clock signal to be distributed by the CDCF2510 clock driver. clk is used to provide the reference signal to the integrated pll that generates the clock output signals. clk must have a fixed frequency and fixed phase for the pll to obtain phase lock. once the circuit is powered up and a valid clk signal is applied, a stabilization time is required for the pll to phase lock the feedback signal to its reference signal. fbin 13 i feedback input. fbin provides the feedback signal to the internal pll. fbin must be hard-wired to fbout to complete the pll. the integrated pll synchronizes clk and fbin so that there is nominally zero phase error between clk and fbin. g 11 i output bank enable. g is the output enable for outputs 1y(0:9). when g is low, outputs 1y(0:9) are disabled to a logic-low state. when g is high, all outputs 1y(0:9) are enabled and switch at the same frequency as clk. fbout 12 o feedback output. fbout is dedicated for external feedback. it switches at the same frequency as clk. when externally wired to fbin, fbout completes the feedback loop of the pll. fbout has an integrated 25- w series-damping resistor. 1y (0:9) 3, 4, 5, 8, 9, 15, 16, 17, 20, 21 o clock outputs. these outputs provide low-skew copies of clk. output bank 1y(0:9) is enabled via the g input. these outputs can be disabled to a logic-low state by deasserting the g control input. each output has an integrated 25- w series-damping resistor. av cc 23 power analog power supply. av cc provides the power reference for the analog circuitry. in addition, av cc can be used to bypass the pll for test purposes. when av cc is strapped to ground, pll is bypassed and clk is buffered directly to the device outputs. agnd 1 ground analog ground. agnd provides the ground reference for the analog circuitry. v cc 2, 10, 14, 22 power power supply gnd 6, 7, 18, 19 ground ground
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) 2 supply voltage range, av cc (see note 1) av cc < v cc +0.7 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage range, v cc 0.5 v to 4.6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i (see note 2) 0.5 v to 6.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high or low state, v o (see notes 2 and 3) 0.5 v to v cc + 0.5 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v cc ) 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through each v cc or gnd 100 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . maximum power dissipation at t a = 55 c (in still air) (see note 4) 0.7 w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. av cc must not exceed v cc . 2. the input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. this value is limited to 4.6 v maximum. 4. the maximum package power dissipation is calculated using a junction temperature of 150 c and a board trace length of 750 mils. for more information, refer to the package thermal considerations application note in the abt advanced bicmos technology data book , literature number scbd002. recommended operating conditions (see note 5) min max unit v cc , av cc supply voltage 3 3.6 v v ih high-level input voltage 2 v v il low-level input voltage 0.8 v v i input voltage 0 v cc v i oh high-level output current 12 ma i ol low-level output current 12 ma t a operating free-air temperature 0 85 c note 5: unused inputs must be held high or low to prevent them from floating. timing requirements over recommended ranges of supply voltage and operating free-air temperature min max unit f clk clock frequency 25 140 mhz input clock duty cycle 40% 60% stabilization time 2 1 ms 2 time required for the integrated pll circuit to obtain phase lock of its feedback signal to its reference signal. for phase loc k to be obtained, a fixed-frequency, fixed-phase reference signal must be present at clk. until phase lock is obtained, the specifications for prop agation delay, skew, and jitter parameters given in the switching characteristics table are not applicable. this parameter does not apply for input modulation under ssc application.
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 5 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc , av cc min typ 3 max unit v ik input clamp voltage i i = 18 ma 3 v 1.2 v i oh = 100 m a min to max v cc 0.2 v oh high-level output voltage i oh = 12 ma 3 v 2.1 v i oh = 6 ma 3 v 2.4 i ol = 100 m a min to max 0.2 v ol low-level output voltage i ol = 12 ma 3 v 0.8 v i ol = 6 ma 3 v 0.55 v o = 1 v 3.135 v 32 i oh high-level output current v o = 1.65 v 3.3 v 36 v o = 3.135 v 3.465 v 12 v o = 1.95 v 3.135 v 34 i ol low-level output current v o = 1.65 v 3.3 v 40 v o = 0.4 v 3.465 v 14 i i input current v i = v cc or gnd 3.6 v 5 m a i cc supply current v i = v cc or gnd, outputs: low or high i o = 0, 3.6 v 10 m a d i cc change in supply current one input at v cc 0.6 v, other inputs at v cc or gnd 3.3 v to 3.6 v 500 m a c i input capacitance v i = v cc or gnd 3.3 v 4 pf c o output capacitance v o = v cc or gnd 3.3 v 6 pf 3 for conditions shown as min or max, use the appropriate value specified under recommended operating conditions. for i cc of av cc , and i cc vs frequency (see figures 8 and 9). switching characteristics over recommended ranges of supply voltage and operating free-air temperature, c l = 25 pf (see note 6 and figures 1 and 2) 3 parameter from (input)/condition to (output) v cc , av cc = 3.3 v 0.3 v unit (input)/condition (output) min typ max phase error time static (normalized) (see figures 3 6) clkin = 66 mhz to133 mhz fbin 125 125 ps t sk(o) output skew time any y or fbout any y or fbout 200 ps phase error time jitter (see note 7) clkin = 66 mhz to 133 mhz any y or fbout 50 50 p s jitter (cycle - cycle) clkin = 66 mh z to 133 mh z any y or fbout |70| ps (cycle cycle) (see figure 7) clkin = 100 mhz to 133 mhz any y or fbout |65| ps duty cycle f(clkin > 60 mhz) any y or fbout 45% 55% t r rise time (see notes 8 and 9) v o = 1.2 v to 1.8 v, ibis simulation any y or fbout 2.5 1 v/ns t f fall time (see notes 8 and 9) v o = 1.2 v to 1.8 v, ibis simulation any y or fbout 2.5 1 v/ns 3 these parameters are not production tested. the t sk(o) specification is only valid for equal loading of all outputs. notes: 6. the specifications for parameters in this table are applicable only after any appropriate stabilization time has elapse d. 7. calculated per pc dram spec (t phase error , static jitter (cycle-to-cycle) ). 8. this is equivalent to 0.8 ns/2.5 ns and 0.8 ns/2.7 ns into standard 500 w / 30 pf load for output swing of 04. v to 2 v. 9. 64 mb dimm configuration according to pc sdram registered dimm design support document, figure 20 and table 13. intel is a trademark of intel corporation. pc sdram register dimm design support document is published by intel corporation.
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 6 post office box 655303 ? dallas, texas 75265 parameter measurement information from output under test load circuit for outputs voltage waveforms propagation delay times t pd 50% v cc 3 v 0 v v oh v ol input 0.4 v 2 v t r t f 0.4 v 2 v output 500 50% v cc 25 pf notes: a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 133 mhz, z o = 50 w , t r 1.2 ns, t f 1.2 ns. c. the outputs are measured one at a time with one transition per measurement. figure 1. load circuit and voltage waveforms t sk(o) t sk(o) t phase error clkin fbin any y any y any y fbout figure 2. phase error and skew calculations
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 7 post office box 655303 ? dallas, texas 75265 typical characteristics 0 5 10 15 20 25 30 35 40 45 50 c (lf) lumped feedback capacitance at fbin pf 10 0 10 20 20 phase adjustment slope ps/pf 30 40 100 0 300 200 400 phase error ps phase error phase adjustment slope 100 200 v cc = 3.3 v f c = 133 mhz c (ly) = 25pf t a = 25 c see notes a and b phase adjustment slope and phase error vs load capacitance figure 3 notes: a. trace feedback length fbout to fbin = 5 mm, z o = 50 w phase error measured from clk to y b. clf = lumped feedback capacitance at fbin figure 4 phase error vs clock frequency phase error ps 50 60 70 80 90 100 110 120 f c clock frequency mhz 100 150 250 300 350 400 200 50 0 450 500 v cc = 3.3 v c (ly) = 25 pf c (lf) = 12 pf t a = 25 c see note a 130 140 figure 5 phase error vs supply voltage 100 150 250 300 350 400 200 phase error ps 3.1 3.2 3.3 3.4 3.5 50 0 450 500 v cc supply voltage v 3.6 3 f c = 133 mhz c (ly) = 25 pf c (lf) = 12 pf t a = 25 c see note a note a: trace feedback length fbout to fbin = 5 mm, z o = 50 w
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 8 post office box 655303 ? dallas, texas 75265 typical characteristics figure 6 static phase error vs clock frequency phase error ps 50 60 70 80 90 100 110 120 f c clock frequency mhz 100 150 250 300 350 400 200 50 0 450 500 v cc = 3.3 v c (ly) = 25 pf c (lf) = 12 pf t a = 25 c see note a 130 140 figure 7 300 250 200 0 jitter ps 50 60 70 80 90 100 110 120 130 140 150 100 50 cycle to cycle peak to peak f c clock frequency mhz v cc = 3.3 v c (ly) = 25 pf c (lf) = 12 pf t a = 25 c see notes a and b jitter vs clock frequency notes: a. trace feedback length fbout to fbin = 5 mm, z o = 50 w b. phase error measured from clk to fbin c. cly = lumped capacitive load at y d. clf = lumped feedback capacitance at fbin
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 9 post office box 655303 ? dallas, texas 75265 typical characteristics figure 8 analog supply current vs clock frequency 12 10 6 4 2 0 8 10 30 50 70 90 110 130 150 14 16 av cc = v cc = 3.465 v bias = 0/3 v c (ly) = 25 pf c (lf) = 0 t a = 25 c see notes a and b f c clock frequency mhz ai cc analog supply current ma figure 9 supply current vs clock frequency 250 150 100 50 0 200 10 30 50 70 90 110 130 150 i cc supply current ma f c clock frequency mhz 300 av cc = v cc = 3.465 v bias = 0/3 v c (ly) = 25 pf c (lf) = 0 t a = 25 c see notes a and b notes: a. c (ly) = lumped capacitive load at y b. c (lf) = lumped feedback capacitance at fbin
CDCF2510 3.3-v phase-lock loop clock driver scas628b april 1999 revised november 1999 10 post office box 655303 ? dallas, texas 75265 mechanical information pw (r-pdso-g**) plastic small-outline package 4040064 / e 08/96 14 pin shown seating plane 0,05 min 1,20 max 1 a 7 14 0,19 4,50 4,30 8 6,20 6,60 0,30 0,75 0,50 0,25 gage plane 0,15 nom 0,65 m 0,10 0 8 0,10 pins ** a min a max dim 2,90 3,10 8 4,90 5,10 14 6,60 6,40 4,90 5,10 16 7,70 20 7,90 24 9,60 9,80 28 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments and its subsidiaries (ti) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. ti warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with ti's standard warranty. testing and other quality control techniques are utilized to the extent ti deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. certain applications using semiconductor products may involve potential risks of death, personal injury, or severe property or environmental damage (acritical applicationso). ti semiconductor products are not designed, authorized, or warranted to be suitable for use in life-support devices or systems or other critical applications. inclusion of ti products in such applications is understood to be fully at the customer's risk. in order to minimize risks associated with the customer's applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. ti assumes no liability for applications assistance or customer product design. ti does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of ti covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. ti's publication of information regarding any third party's products or services does not constitute ti's approval, warranty or endorsement thereof. copyright ? 2000, texas instruments incorporated

▲Up To Search▲

Price & Availability of CDCF2510

	To Download CDCF2510 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .