1 ds9829-00 july 2011 www.richtek.com rt9829 dual push-button reset with push-button controlled output delay general description the rt9829 has two combined delayed reset inputs (sr0, sr1) with a user selectable delayed setup time (t src ) option of either 7.5s or 12.5s (typ.), selectable via the dual-state dsr input pin. when dsr is connected to ground, t src = 7.5s (typ.); when connected to v cc , t src = 12.5s (typ.). there are two reset outputs which become active simultaneously after both of the reset inputs are held active for the selected t src delay time. the outputs remain asserted until either or both inputs go to inactive logic level (for this device the output reset pulse duration is fully push-button controlled, meaning neither fixed nor minimum reset pulse width, nor power on reset pulse is implemented). the first reset output, rst1, is active low, open drain; the second reset output, rst2, is active high, push-pull. the device fully operates over a broad v cc range from 1.65v to 5.5v. below 1.575v (typ.), the inputs are ignored and the outputs are de-asserted. the de-asserted reset output levels are then valid down to 1v. the rt9829 is available in a tiny wdfn-8l 2x2 (col) package. pin configurations (top view) wdfn-8l 2x2 (col) applications z mobile phones, smartphones z e-books z mp3 players z games z portable navigation devices marking information ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. features z dual reset push-button inputs ` ` ` ` ` user selectable delay setup time : 7.5s and 12.5s (typ.) z push-button controlled reset pulse duration ` no fixed nor minimum pulse width guaranteed z no power on reset z dual reset outputs ` rst1 : active low, open-drain ` rst2 : active high, push-pull z fixed reset input logic voltage levels z broad operating voltage range : 1.65v to 5.5v ` inactive reset output levels valid down to 1v z 2 a low supply current z operating temperature : ? ? ? ? ? 40 c to 85 c z small thermally enhanced 8-lead wdfn package z rohs compliant and halogen free 56w 56 : product code w : date code rst2 rst1 vss vcc sr0 nc dsr sr1 7 6 5 1 2 3 4 8 rt9829 package type qw : wdfn-8l 2x2 (col) lead plating system g : green (halogen free and pb free)
2 ds9829-00 july 2011 www.richtek.com rt9829 typical application circuit typical operation : operation with regulator : vcc rt9829 dsr rst2 vss system asic mcu rst1 powerkey v bat c1 0.1f 8 5 2 7 3 4 1 sr1 sr0 reset power on sys_reset vcc rt9829 dsr rst2 vss system asic mcu rst1 powerkey v bat c1 0.1f 8 5 2 7 3 4 1 sr1 sr0 reset power on sys_reset regulator en
3 ds9829-00 july 2011 www.richtek.com rt9829 timing diagrams figure 1 . timing diagram figure 2 . under voltage condition rst2 sr0 sr1 rst1 v bat 1v 1.65v start timer n seconds t src end timer push-button controlled output 1.65v 1v glitch immunity t src time (s) v cc 5v 1.575v 0v 5v 0v 5v 0v 5v rst2 0v 5v 0v sr0 sr1 rst1
4 ds9829-00 july 2011 www.richtek.com rt9829 functional pin description pin no. pin name pin function 1 rst2 second reset output (active high, push-pull). 2 vss ground. 3 sr1 secondary push-button reset input (active low). 4 rst1 first reset output (active low, open-drain). 5 dsr dual-state reset input delay selection pin. when connected to ground, t src = 7.5s (typ.); when connected to vcc, t src = 12.5s (typ.). dsr is a dc-type input, intended to be either permanently grounded or permanently connected to vcc. 6 nc no internal connection. not bonded and should be connected to vss. 7 sr0 primary push-button reset input (active low). 8 vcc positive supply input. a 0.1 f decoupling ceramic capacitor is recommended to be connected between vcc and vss pins. function block diagram reset logic t src output logic t src selector two-state logic oscillator sr0 sr1 dsr rst1 rst2 vss vcc
5 ds9829-00 july 2011 www.richtek.com rt9829 electrical characteristics absolute maximum ratings (note 1) z supply input voltage, v cc to v ss ------------------------------------------------------------------------------------- ? 0.3v to 6v z other pins to v ss --------------------------------------------------------------------------------------------------------- ? 0.3v to 6v z power dissipation, p d @ t a = 25 c wdfn-8l 2x2 (col) ------------------------------------------------------------------------------------------------------ 0.606w z package thermal resistance (note 2) wdfn-8l 2x2 (col), ja ------------------------------------------------------------------------------------------------ 165 c/w z junction temperature ----------------------------------------------------------------------------------------------------- 150 c z lead temperature (soldering, 10 sec.) ------------------------------------------------------------------------------- 260 c z storage temperature range -------------------------------------------------------------------------------------------- ? 65 c to 150 c z esd susceptibility (note 3) hbm (human body mode) ---------------------------------------------------------------------------------------------- 2kv mm (ma chine mode) ------------------------------------------------------------------------------------------------------ 200v recommended operating conditions (note 4) z supply input voltage, v cc (note 5) --------------------------------------------------------------------------------- 1.65v to 5.5v z junction temperature range -------------------------------------------------------------------------------------------- ? 40 c to 125 c z ambient temperature range -------------------------------------------------------------------------------------------- ? 40 c to 85 c (v cc = 3.3v, t a = 25 c, unless otherwise specified) parameter symbol test conditions min typ max unit input power supply supply current i cc v cc = 5v -- 2 3 a v cc 4.5v, i sink = 3.2ma -- -- 0.3 v cc 3.3v, i sink = 2.5ma -- -- 0.3 reset output voltage low v ol v cc 1.65v, i sin k = 1ma -- -- 0.3 v v cc 4.5v, i source = 0.8ma 0.8 x v cc -- -- v cc 2.7v, i source = 0.5ma 0.8 x v cc -- -- reset output voltage high, rst2 v oh v cc 1.65v, i source = 0.25ma 0.8 x v cc -- -- v output leakage current, rst1 i lo open-drain, v rst1 = 5.5v ? 0.1 -- 0.1 a reset dsr = vss 6 7.5 9 reset delay t sr c dsr = vcc 10 12.5 15 s logic-low v il v ss ? 0.3 -- 0.3 sr0, sr1 input threshold voltage logic-high v ih 1.1 -- 5.5 v input leakage current (sr0, sr1, dsr pins) i li ? 1 -- 1 a
6 ds9829-00 july 2011 www.richtek.com rt9829 note 1. stresses listed as the above "absolute maximum ratings" may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. note 5. reset outputs are de-asserted below 1.575v (typ.) and remain de-asserted down to v cc = 1v.
7 ds9829-00 july 2011 www.richtek.com rt9829 typical operating characteristics time (2.5s/div) power on v cc (2v/div) sr0, sr1 (2v/div) rst1 (2v/div) rst2 (2v/div) v cc = 1.6v, sr0 = sr1 = gnd, dsr = vcc sr1 threshold voltage vs. input voltage 0.50 0.55 0.60 0.65 0.70 0.75 0.80 1.5 2 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) sr1 threshold voltage (v) high low sr0 threshold voltage vs. input voltage 0.50 0.55 0.60 0.65 0.70 0.75 0.80 1.5 2 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) sr0 threshold voltage (v) high low reset delay time vs. temperature 5 6 7 8 9 10 11 12 13 14 15 16 -50 -25 0 25 50 75 100 125 temperature (c) reset delay time (s) dsr = vcc v cc = 3.7v dsr = gnd supply current vs. input voltage 0 1 2 3 4 5 6 7 8 9 10 1.5 2 2.5 3 3.5 4 4.5 5 5.5 input voltage (v) supply current (a ) time (1s/div) power on v cc (2v/div) sr0, sr1 (2v/div) rst1 (2v/div) rst2 (2v/div) v cc = 1.6v, sr0 = sr1 = gnd, dsr = gnd
8 ds9829-00 july 2011 www.richtek.com rt9829 time (2.5s/div) reset delay v cc (5v/div) rst2 (5v/div) sr1 (5v/div) rst1 (5v/div) v cc = 3.7v, sr0 = gnd, dsr = gnd time (2.5s/div) reset delay v cc (5v/div) rst2 (5v/div) sr1 (5v/div) rst1 (5v/div) v cc = 3.7v, sr0 = gnd, dsr = vcc
9 ds9829-00 july 2011 www.richtek.com rt9829 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension w-type 8l dfn 2x2 (col) package dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.150 0.250 0.006 0.010 d 1.900 2.100 0.075 0.083 e 1.900 2.100 0.075 0.083 e 0.500 0.020 l 0.500 0.600 0.020 0.024
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