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1 datasheet radiation tolerant 5v 16-channel analog multiplexer ISL71830SEH the ISL71830SEH is a radiation tolerant, 16-channel multiplexer that is fabricated using intersil?s proprietary p6-soi process technology to provide excellent latch-up performance. it operates with a single supply range from 3v to 5.5v and has a 4-bit address line plus an enab le that can be driven with adjustable logic thresholds to conveniently select one of 16 available channels. an inactive channel is separated from the active channel by a high impedance, which inhibits any interaction between them. the ISL71830SEH?s low r ds(on) allows for improved signal integrity and reduced power losses. the ISL71830SEH is also designed for cold sparing, making it excellent for redundancy in high reliability applications. it is designed to provide a high impedance to the analog source in a powered off condition, making it easy to add additional backup devices without incurring extra power dissipation. the ISL71830SEH also has analog overvoltage protection on the input that disables the switch during an overvoltage event to protect upstream and downstream devices. the ISL71830SEH is available in a 28 ld cdfp and operates across the extended temperature range of -55c to +125c. a 32-channel version is also available offered in a 48 ld cqfp. refer to the isl71831seh datasheet for more information. for a list of differences, refer to table 1 on page 2 . related literature ? for a full list of related documents, visit our website - ISL71830SEH product page features ?dla smd# 5962-15247 ? fabricated using p6 soi process technology ? rail-to-rail operation ?no latch-up ?low r ds(on) . . . . . . . . . . . . . . . . . . . . . . . . . .<120 (maximum) ? single supply operation . . . . . . . . . . . . . . . . . . . . . . 3v to 5.5v - adjustable logic threshold control ? cold sparing capable . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 7v ? analog overvoltage range . . . . . . . . . . . . . . . . . . . . -0.4v to 7v ? switch input off leakage . . . . . . . . . . . . . . . . . . . . . . . . . 120na ? transition times (t ahl ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70ns ? internally grounded metal lid ? break-before-make switching ? esd protection 5kv (hbm) ? operating temperature range. . . . . . . . . . . .-55c to +125c ? radiation tolerance - low dose rate (0.01rad(si)/s) . . . . . . . . . . . . . . .75krad(si) - sel/seb let th (v + = 6.5v) . . . . . . . . . . . . . 60mev?cm 2 /mg ? all lots are assurance tested to 75krad (0.01rad(si)/s) wafer-by-wafer. applications ? telemetry signal processing ? harsh environments ? down-hole drilling figure 1. typical application figure 2. r ds(on) vs common-mode voltage (v + = 5v) in01 in02 in16 address 4 in03 . . . out adc ISL71830SEH en 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode voltage (v) r ds(on) () -55c +25c +125c november 18, 2016 fn8758.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas llc. 2015,2016. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
ISL71830SEH 2 fn8758.3 november 18, 2016 submit document feedback ordering information smd ordering number ( note 2 ) part number ( note 1 ) temp range (c) package (rohs compliant) pkg. dwg. # 5962l1524701vxc ISL71830SEHvf -55 to +125 28 ld cdfp k28.a n/a ISL71830SEHf/proto -55 to +125 28 ld cdfp k28.a 5962l1524701v9a ISL71830SEHvx -55 to +125 die n/a ISL71830SEHx/sample -55 to +125 die n/a ISL71830SEHev1z evaluation board notes: 1. these intersil pb-free hermetic packaged products employ 100% au plate - e4 termination finish, which is rohs compliant and c ompatible with both snpb and pb-free soldering operations. 2. specifications for rad hard qml devices are controlled by the defense logistics agency land and maritime (dla). the smd numbe rs listed in the ?ordering information? table must be used when ordering. table 1. key differences between family of parts part number number of chan nels output leakage package ISL71830SEH 16 60na 28 ld cdfp isl71831seh 32 120na 48 ld cqfp
ISL71830SEH 3 fn8758.3 november 18, 2016 submit document feedback pin configuration ISL71830SEH (28 ld cdfp) top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 v + nc nc in16 in15 in14 in13 in12 in11 in10 in9 gnd vref a3 out nc in8 in7 in6 in5 in4 in3 in2 in1 en a0 a1 a2 pin descriptions pin name esd circuit pin number description out 2 28 output for multiplexer. v + 1 1 positive power supply. nc - 2, 3, 27 not electrically connected. inx 1 4, 5, 6, 7, 8, 9, 10, 11, 19, 20, 21, 22, 23, 24, 25, 26 input for multiplexer. ax 1 14, 15, 16, 17 address lines for multiplexer. en 1 18 enable control for multiplexer (active low). vref 1 13 reference voltage used to set logic thresholds. gnd - 12 ground lid - - package lid is internally connected to gnd (pin 12). pin # circuit 2 vdd 9v clamp gnd 9v clamp gnd pin # 9v clamp circuit 1
ISL71830SEH 4 fn8758.3 november 18, 2016 submit document feedback absolute maximum ratings thermal information maximum supply voltage (v + to gnd). . . . . . . . . . . . . . . . . . . . . . . . . . . . 7v maximum supply voltage (v+ to gnd) ( note 5 ) . . . . . . . . . . . . . . . . . . .6.5v analog input voltage range (inx). . . . . . . . . . . . . . . . . . . . . . . . . -0.4v to 7v digital input voltage range (en , ax) . . . . . . . . . . . . . . . (gnd - 0.4v) to v ref vref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7v esd tolerance human device model (tested per mil- std-883 tm 3015) . . . . . . . . 5kv charged device model (tested per jesd22-c101d) . . . . . . . . . . . . 250v machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . . 250v thermal resistance (typical) ? ja (c/w) ? jc (c/w) 28 ld cdfp ( notes 3 , 4 ) . . . . . . . . . . . . . . . 55 8.5 storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c recommended operating conditions ambient operating temperature range . . . . . . . . . . . . . .-55c to +125c maximum operating junction temperature . . . . . . . . . . . . . . . . . .+150c supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.5v v ref to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3v to 5.5v caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 3. ? ja is measured with the component mounted on a high-effective thermal conductivity test board in free air. see tech brief tb379 for details. 4. for ? jc , the ?case temp? location is the center of the package underside. 5. tested in a heavy ion environment at let = 60mev ? cm 2 /mg at +125c. electrical specifications, v + = 5v gnd = 0v, v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the op erating temperature range, -55c to +125c; over a total ionizing dose of 75krad(si) with exposure at a low dose rate of <10mrad(si)/s. parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit analog input signal range v in 0v + v channel on-resistance r ds(on) v + = 4.5v, v in = 0v to v + i out = 1ma - 40 120 r ds(on) match between channels r ds(on) v + = 4.5v, v in = 0v, 2.25v, 4.5v i out = 1ma -- 5 on-resistance flatness r flat(on) v + = 4.5v, v in = 0v to v + -- 40 switch input off leakage i in(off) v + = 5.5v, v in = 5v, unused inputs and v out = 0.5v -30 - 30 na v + = 5.5v, v in = 0.5v, unused inputs and v out = 5v -30 - 30 na switch input off overvoltage leakage i in(off-ov) v + = 5.5v, v in = 7v, unused inputs and v out = 0v, t a = +25c, -55c -30 - 30 na t a = +125c -30 - 120 na post radiation, +25c -30 - 30 na switch input off leakage with supply voltage grounded i in(power-off) v in = 7v, v out = 0v v + = v en = v ref = 0v, t a = +25c, -55c -20 - 20 na t a = +125c -20 - 50 na post radiation, +25c -20 - 20 na switch input off leakage with supply voltage open i in(power-off) v in = 7v, v out = 0v v + = v en = v ref = open, t a = +25c, -55c -20 - 20 na t a = +125c -20 - 50 na post radiation, +25c -20 - 20 na switch on input leakage with overvoltage applied to the input i in(on-ov) v + = 5.5v, v in = 7v, v out = open 2.75 - 5.50 a
ISL71830SEH 5 fn8758.3 november 18, 2016 submit document feedback switch output off leakage i out(off) v + = 5.5v, v out = 5v, all inputs = 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 150 na post radiation, +25c -30 - 30 na v + = 5.5v, v out = 0.5v, all inputs = 5v, t a = +25c, -55c -30 - 30 na t a = +125c -60 0 na post radiation, +25c -30 - 30 na switch output leakage with switch enabled i out(on) v + = 5.5v, v in = v out = 5v all unused inputs at 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 150 na post radiation, +25c -30 - 30 na v + = 5.5v, v in = v out = 0.5v all unused inputs at 5v, t a = +25c, -55c -30 - 30 na t a = +125c -60 - 0 na post radiation, +25c -30 - 30 na logic input voltage high/low v ih/l v + = 5.5v, v ref = 3.3v 1.3 - 1.6 v input current with v ah, v enh i ah , i enh v + = 5.5v, v en = v a = v ref -0.1 - 0.1 a input current with v al, v enl i al , i enl v + = 5.5v, v en = v a = 0v -0.1 - 0.1 a quiescent supply current i supply v + = v ref = v en = 5.5v v a = 0v, t a = +25c, -55c --100na t a = +125c - - 300 na post radiation, +25c - - 300 na reference quiescent supply current i ref v + = v ref = v en = 5.5v v a = 0v -- 200 na dynamic addressing transition time t ahl v + = 4.5v; figure 3 10 - 70 ns break-before-make delay t bbm v + = 4.5v; figure 5 5 18 40 ns enable turn-on time t en(on) v + = 4.5v; figure 4 -- 40 ns enable turn-off time t en(off) v + = 4.5v; figure 4 -- 40 ns charge injection v cte c l = 100pf, v in = 0v, figure 6 -1.45 pc off isolation v iso v en = v ref , r l = open, f = 1khz 60 -- db crosstalk v ct v en = 0v, f = 1khz, v p-p = 1v, r l = open 73 -- db input capacitance c in(off) f = 1mhz - - 5 pf output capacitance c out(off) f = 1mhz - - 25 pf electrical specifications, v + = 5v gnd = 0v, v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the op erating temperature range, -55c to +125c; over a total ionizing dose of 75krad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter symbol test conditions min ( note 6 )typ max ( note 6 )unit
ISL71830SEH 6 fn8758.3 november 18, 2016 submit document feedback electrical specifications, v + = 3.3v v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c.; over a total ionizing dose of 75krad(si) with exposure at a low dose rate of <10mrad(si)/s. parameter symbol conditions min (note 6) typ max (note 6) unit analog input signal range v in 0-v + v channel on-resistance r ds(on) v + = 3v, v in = 0v to v + i out = 1ma 25 70 200 r ds(on) match between channels r ds(on) v + = 3v, v in = 0.5v, 2.5v i out = 1ma -- 5 on-resistance flatness r flat(on) v + = 3v v in = 0v to v + -- 50 switch input off leakage i in(off) v + = 3.6v v in = 3.1v, unused inputs and v out = 0.5v -30 - 30 na v + = 3.6v v in = 0.5v, unused inputs and v out = 3.1v -30 - 30 na switch input off overvoltage leakage i in(off-ov) v + = 3.6v v in = 7v, unused inputs and v out = 0v, t a = +25c, -55c -30 - 30 na t a = +125c -30 - 100 na post radiation, +25c -30 - 30 switch on input leakage with overvoltage applied to the input i in(on-ov) v + = 3.6v, v in = 7v, v out = open 1.8 - 3.6 a switch output off leakage i out(off) v + = 3.6v, v out = 3.1v, all inputs = 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 60 na post radiation, +25c -30 - 30 na v + = 3.6v, v out = 0.5v, all inputs = 3.1v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 30 na post radiation, +25c -30 - 30 na switch output leakage with switch enabled i out(on) v + = 3.6v, v in = v out = 3.1v all unused inputs at 0.5v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 30 na post radiation, +25c -30 - 30 na v + = 3.6v, v in = v out = 0.5v all unused inputs at 3.1v, t a = +25c, -55c -30 - 30 na t a = +125c 0 - 30 na post radiation, +25c -30 - 30 na quiescent supply current i supply v + = v ref = v en = 3.6v v a = 0v, t a = +25c, -55c --100na t a = +125c - - 300 na post radiation, +25c - - 300 na reference quiescent supply current i ref v + = v ref = v en = 3.6v, v a = 0v - - 200 na
ISL71830SEH 7 fn8758.3 november 18, 2016 submit document feedback dynamic addressing transition time t ahl v + = 3v; figure 3 10 - 100 ns break-before-make delay t bbm v + = 3v; figure 5 5 25 50 ns enable turn-on time t en(on) v + = 3v; figure 4 -- 50 ns enable turn-off time t en(off) v + = 3v; figure 4 -- 50 ns note: 6. compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design. electrical specifications, v + = 3.3v v ref = 3.3v, v ih = 3.3v, v il = 0v, t a = +25c, unless otherwise noted. boldface limits apply across the operating temperature range, -55c to +125c.; over a total ionizing dose of 75krad(si) with exposure at a low dose rate of <10mrad(si)/s. (continued) parameter symbol conditions min (note 6) typ max (note 6) unit table 2. truth a3 a2 a1 a0 en ?on? channel xxxx1none 000001 000102 001003 001104 010005 010106 011007 011108 100009 1001010 1010011 1011012 1100013 1101014 1110015 1111016 note: 7. x = don?t care, ?1? = logic high, ?0? = logic low.
ISL71830SEH 8 fn8758.3 november 18, 2016 submit document feedback timing diagrams figure 3. address time to output test circuit figure 4. address time to output diagram figure 5. time to enable/dis able output test circuit figure 6. time to enable /disable output diagram figure 7. break-before-make test circ uit figure 8. break-before-make diagram figure 9. charge injection test circuit figure 10. charge injection diagram ISL71830SEH a3 a2 a1 a0 en in01 in02-in15 in16 out 50 @ 0v 10k @ 50pf 0v, v + v + ,0v vout 0v vref w $+/ 287387 9 95() 9 9 3 3 w $+/ ISL71830SEH 50pf v + vout a3 a2 a1 a0 en in01 in02-in16 out 0v vref 50 1k t enable t disable 50% 90% 10% output 0v vref v + 0v 50% en ISL71830SEH a3 a2 a1 a0 en in01 in02-in15 in16 out 50 0v 50pf v + vout vref 0v 100 address 0v vref 50% t bbm out 0v v + ISL71830SEH a3 a2 a1 a0 en in01 in02-in15 in16 out 50 @ 0v 100pf 0v vout 0v vref address 0v vref vout out 0v q = 100pf * vout
ISL71830SEH 9 fn8758.3 november 18, 2016 submit document feedback typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. figure 11. r ds(on) vs common-mode voltage (v + = 4.5v) figure 12. r ds(on) vs common-mode voltage (v + = 5v) figure 13. r ds(on) vs common-mode voltage (v + = 5.5v) figure 14. r ds(on) vs common-mode voltage (v + = 3v) figure 15. r ds(on) vs common-mode voltage (v + = 3.3v) figure 16. r ds(on) vs common-mode voltage (v + = 3.6v) 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 common-mode voltage (v) r ds(on) () +125c +25c -55c 0 10 20 30 40 50 60 70 80 90 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 common-mode voltage (v) r ds(on) () -55c +25c +125c 0 10 20 30 40 50 60 70 80 012345 +125c +25c -55c r ds(on) () common-mode voltage (v) 0 20 40 60 80 100 120 140 0 0.5 1.0 1.5 2.0 2.5 3.0 r ds(on) () common-mode voltage (v) +25c +125c -55c 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 common-mode voltage (v) r ds(on) () -55c +25c +125c 0 20 40 60 80 100 120 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 +125c r ds(on) () +25c -55c common-mode voltage (v)
ISL71830SEH 10 fn8758.3 november 18, 2016 submit document feedback figure 17. address propagation delay (high to low) figure 18. address propagation delay (low to high) figure 19. address propagation delay figure 20. break-before-make delay figure 21. break-before-make delay figure 22. enable to output propagation delay typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0 10 20 30 40 50 60 70 80 3.0 3.5 4.0 4.5 5.0 5.5 address delay (ns) +125c -55c +25c supply voltage (v) 0 10 20 30 40 50 60 70 80 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) address delay (ns) -55c +125c +25c 200ns/div 1v/div 2v/div t adhl = 34.382ns t adlh = 44.087ns 0 5 10 15 20 25 30 35 40 3.0 3.5 4.0 4.5 5.0 5.5 supply voltage (v) t bmm delay (ns) +25c -55c +125c 200ns/div 1v/div 2v/div t bbm = 17.929ns 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 +25c -55c +125c supply voltage (v) t enable delay (ns)
ISL71830SEH 11 fn8758.3 november 18, 2016 submit document feedback figure 23. disable to output propagation delay figure 24. enable/disable propagation delay figure 25. off isolation (v + = 5v, +25c, r l = 511 ? ) figure 26. off isolation (v + = 5v, +25c, r l = open) figure 27. crosstalk (v + = 5v, +25c, r l = open) figure 28. charge injection typical performance curves v + = 5v, v ref = 3.3v, v in = 0v, r l = open, t a = +25c, unless otherwise specified. (continued) 0 10 20 30 40 50 60 3.0 3.5 4.0 4.5 5.0 5.5 t disable delay (ns) supply voltage (v) +25c +125c -55c 200ns/div 1v/div 2v/div t enable = 22.670ns t disable = 41.720ns 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m 100m frequency (hz) off isolation (db) 0 10 20 30 40 50 60 70 80 90 100 1k 10k 100k 1m 10m 100m frequency (hz) off isolation (db) 0 20 40 60 80 100 120 100 1k 10k 100k 1m 10m crosstalk (db) frequency (hz) 0 0.20 0.40 0.60 0.80 1.00 1.20 1.40 1.60 1.80 2.00 3.0 3.5 4.0 4.5 5.0 5.5 +125c +25c -55c supply voltage (v) charge injection (pc)
ISL71830SEH 12 fn8758.3 november 18, 2016 submit document feedback post low dose rate radiation characteristics (v + = 5v) unless otherwise specified, v + = 5v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. figure 29. r ds(on) (v + = 4.5v), biased figure 30. r ds(on) (v + = 4.5v), grounded figure 31. r ds(on) minimum (v + = 4.5v) figure 32. r ds(on) maximum (v + = 4.5v) figure 33. r ds(on) flatness (v + = 4.5v) figure 34. r ds(on) match (v + = 4.5v, v in = 0.5v) 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () v in = 0.5v v in = 2.25v v in = 4v 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) v in = 4v v in = 2.25v v in = 0.5v r ds(on) () 0 20 40 60 80 100 120 0 10 20 30 40 50 60 70 80 biased grounded r ds(on) () low dose rate radiation (krad(si)) 0 20 40 60 80 100 120 0 1020304050607080 biased grounded low dose rate radi ation (krad(si)) r ds(on) () 0 5 10 15 20 25 30 35 40 45 0 1020304050607080 r ds(on) () low dose rate radi ation (krad(si)) grounded biased 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () grounded biased
ISL71830SEH 13 fn8758.3 november 18, 2016 submit document feedback figure 35. r ds(on) match (v + = 4.5v, v in = 4v) figure 36. i s(off) (v + = 5.5v, v in = 5v) figure 37. i s(off) (v + = 5.5v, v s = 7v) figure 38. i s(on) (v + = 5.5v, v in = 5v) figure 39. i d(on) (v + = 5.5v, v in = 5v) figure 40. i d(off) (v + = 3.6v, v in = 3.1v) post low dose rate radiation characteristics (v + = 5v) unless otherwise specified, v + = 5v, v cm =0, v o = 0v, t a = +25c. this data is typical mean test data post radiation exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 r ds(on) () low dose rate radiation (krad(si)) grounded biased biased -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 grounded biased low dose rate radiation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radi ation (krad(si)) grounded biased 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1020304050607080 grounded leakage (na) low dose rate radiation (krad(si)) biased -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 grounded biased low dose rate radi ation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radiation (krad(si)) grounded biased
ISL71830SEH 14 fn8758.3 november 18, 2016 submit document feedback post low dose rate radiation characteristics (v + = 3.3v) unless otherwise specified, v + = 3.3v, v cm =0,v o = 0v, t a = +25c. this data is typical mean test data post radiat ion exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. figure 41. r ds(on) (v + = 3v), biased figure 42. r ds(on) (v + = 3v), grounded figure 43. r ds(on) minimum (v + = 3v) figure 44. r ds(on) maximum (v + = 3v) figure 45. r ds(on) flatness (v + = 3v) figure 46. r ds(on) match (v + = 3v, v in = 0.5v) 0 20 40 60 80 100 120 0 1020304050607080 r ds(on) () low dose rate radi ation (krad(si)) v in = 0.5v v in = 1.5v v in = 2.5v 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () v in = 1.5v v in = 0.5v v in = 2.5v 0 20 40 60 80 100 120 0 1020304050607080 grounded biased r ds(on) () low dose rate radiation (krad(si)) 0 20 40 60 80 100 120 0 1020304050607080 low dose rate radiation (krad(si)) r ds(on) () grounded biased 0 5 10 15 20 25 30 35 40 45 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () biased grounded 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 biased grounded low dose rate radiation (krad(si)) r ds(on) ()
ISL71830SEH 15 fn8758.3 november 18, 2016 submit document feedback figure 47. r ds(on) match (v + = 3v, v in = 2.5v) figure 48. i s(off) (v + = 3.6v, v in = 3.1v) figure 49. i s(off) (v + = 3.6v, v in = 7v) figure 50. i s(on) (v + = 3.6v, v in = 7v) figure 51. i d(on) (v + = 3.6v, v in = 3.1v) figure 52. i d(off) (v + = 3.6v, v in = 3.1v) post low dose rate radiation characteristics (v + = 3.3v) unless otherwise specified, v + = 3.3v, v cm =0,v o = 0v, t a = +25c. this data is typical mean test data post radiat ion exposure at a low dose rate of <10mrad(si)/s. this data is intended to show typical parameter shifts due to low do se rate radiation. these are not limits nor are they guaranteed. (continued) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0 1020304050607080 low dose rate radi ation (krad(si)) r ds(on) () biased grounded -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 biased grounded leakage (na) low dose rate radiation (krad(si)) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 low dose rate radi ation (krad(si)) leakage (na) biased grounded 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1020304050607080 grounded biased low dose rate radiation (krad(si)) leakage (na) -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 low dose rate radiation (krad(si)) leakage (na) biased grounded -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 1020304050607080 leakage (na) low dose rate radiation (krad(si)) biased grounded
ISL71830SEH 16 fn8758.3 november 18, 2016 submit document feedback applications information power-up considerations the circuit is designed to be insensitive to any given power-up sequence between v + and vref, however, it is recommended that all supplies power-up relatively close to each other. overvoltage protection the ISL71830SEH has overvoltage protection on both the input as well as the output. on the outp ut, the voltage is limited to a diode past the rails. each of the inputs has independent overvoltage protection that works regardless of the switch being selected. if a switch experiences an overvoltage condition, the switch is turned off. as soon as the voltage returns within the rails, the switch returns to normal operation. vref and logic functionality the vref pin sets the logic threshold for the ISL71830SEH. the range for vref is between 3v and 5.5v. the switching point is set to around 50% of the voltage presented to vref. this switching point allows for both 5v and 3.3v logic control. ISL71830SEH vs isl71831seh a 32-channel version of the ISL71830SEH is available in a 48 ld cqfp. in terms of performance sp ecs, the parts are very similar in behavior. apart from the apparent increase in channel density, the isl71831seh does have slightly higher output leakage compared to the ISL71830SEH due to having more channels connected to the output. the supply current for the isl71831seh is also a bit higher compared to the ISL71830SEH.
ISL71830SEH 17 fn8758.3 november 18, 2016 submit document feedback die characteristics die dimensions 2026m x 2240m (79.7638 mils x 88.1890 mils) thickness: 483m 25m (19 mils 1 mil) interface materials glassivation type: 12k ? silicon nitride on 3k ? oxide top metallization type: 300 ? tin on 2.8m alcu in bondpads, tin has been removed. backside finish silicon process p6soi assembly related information substrate potential floating additional information worst case current density 1.6 x 10 5 a/cm 2 transistor count 3875 weight of packaged device 2.091 grams lid characteristics finish: gold potential: grounded, ti ed to package pin 12 metalization mask layout in16 in15 in14 in13 in12 in11 in10 in9 gnd in8 in7 in6 in5 in4 in3 in2 in1 en bar vref a3 a2 a1 a0 out v+
ISL71830SEH 18 fn8758.3 november 18, 2016 submit document feedback intersil products are manufactured, assembled and tested utilizing iso9001 quality systems as noted in the quality certifications found at www.intersil.com/en/suppor t/qualandreliability.html intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com for additional products, see www.intersil.com/en/products.html table 3. ISL71830SEH die layout x-y coordinates pad number pad name packaging pin x (m) y (m) x (m) y (m) 1 in8 p26 110 110 1693.925 1939.8 5 out p28 110 110 1050.875 1915.8 6 v+ p1 110 110 844.875 1915.8 10 in16 p4 110 110 201.8 1939.8 11 in15 p5 110 110 201.8 1693.8 12 in14 p6 110 110 201.8 1477.8 13 in13 p7 110 110 201.8 1271.8 14 in12 p8 110 110 201.8 1065.8 15 in11 p9 110 110 201.8 859.8 16 in10 p10 110 110 201.8 653.8 17 in9 p11 110 110 201.8 442.8 18 gnd p12 110 110 206.225 201.8 19 vref p13 110 110 440.35 201.8 20 a3 p14 110 110 676.35 201.8 21 a2 p15 110 110 912.35 201.8 22 a1 p16 110 110 1148.35 201.8 23 a0 p17 110 110 1384.35 201.8 24 en p18 110 110 1620.35 201.8 25 in1 p19 110 110 1693.925 442.8 26 in2 p20 110 110 1693.925 653.8 27 in3 p21 110 110 1693.925 859.8 28 in4 p22 110 110 1693.925 1065.8 29 in5 p23 110 110 1693.925 1271.8 30 in6 p24 110 110 1693.925 1477.8 31 in7 p25 110 110 1693.925 1693.8 note: origin of coordinates is the center of the die.
ISL71830SEH 19 fn8758.3 november 18, 2016 submit document feedback about intersil intersil corporation is a leading provider of innovative power ma nagement and precision analog so lutions. the company's product s address some of the largest markets within the industrial and infrastr ucture, mobile computing and high-end consumer markets. for the most updated datasheet, application notes, related documentatio n and related parts, please see the respective product information page found at www.intersil.com . you may report errors or suggestions for improving this datasheet by visiting www.intersil.com/ask . reliability reports are also av ailable from our website at www.intersil.com/support . revision history the revision history provided is for in formational purposes only and is believ ed to be accurate, but not warranted. please go to the web to make sure that you have the latest revision. date revision change november 18, 2016 fn8758.3 added esd diagrams to the ?pin descriptions? on page 3. updated related literature section. march 4, 2016 fn8758.2 page 1 features, changed the following: from: sel/b immune to let 60mev?mg/cm 2 to: sel/b immune to let 60mev?cm 2 /mg december 10, 2015 fn8758.1 changed r on to r ds(on) throughout datasheet changed in features on page 1 last item under ?radiation tolerance? ?v + = 5v? to ?v + = 6.5v? changed in description and features on page 1 supply voltage from ?3.3v to 5v? to ?3v to 5.5v?. removed addr throughout datasheet from: pin configuration from pins 14 through 17 on page 3 ?pin descriptions? on page 3, ?absolute maximum ratings? on page 4 and table 3 on page 18. abs max section, page 4, changed: maximum supply voltage (v+ to gnd) (note 5) . . . . . . 7v to: maximum supply voltage (v+ to gnd) (note 5) . . . . . 6.5v electrical spec table: page 4 changed typ from 60 to 40 page 5 t bbm changed typ from 15 to 18 v cte changed typ from 2 to 1.4 swapped the "ven = " statements be tween off isolatio n and crosstalk. off isolation changed: from: 60db (typ) to: 60db (min) and crosstalk changed: from: 73db (typ) to: 73db (min) page 6 changed typ from 60 to 70 page 7 tbbm changed typ from 15 to 25 ?timing diagrams? on page 8 figures 5 and 7 changed 500 to 50 on page 7 added truth table. replaced die plot on page 17, changed vdd to v+. page 18 x-y coordinates table, changed vdd to v+ figure 7 changed 1000 on bottom right resistor to 100 . y-axis changes: figure 20: from address delay (ns) to: t bmm delay (ns) figure 22: from address delay (ns) to: t enable delay (ns) figure 23: from address delay (ns) to: t disable delay (ns) september 24, 2015 fn8758.0 initial release
ISL71830SEH 20 fn8758.3 november 18, 2016 submit document feedback ceramic metal seal flatpack packages (flatpack) notes: 1. index area: a notch or a pin one id entification mark shall be located adjacent to pin one and shall be located within the shaded area shown. the manufacturer?s identific ation shall not be used as a pin one identification mark. alternately, a tab (dimension k) may be used to identify pin one. 2. if a pin one identification mark is used in addition to a tab, the limits of dimension k do not apply. 3. this dimension allows for off-c enter lid, meniscus, and glass over- run. 4. dimensions b1 and c1 apply to lead base metal only. dimension m applies to lead plating and finish th ickness. the maximum limits of lead dimensions b and c or m s hall be measured at the centroid of the finished lead surfaces, when sol der dip or tin plate lead finish is applied. 5. n is the maximum number of terminal positions. 6. measure dimension s1 at all four corners. 7. for bottom-brazed lead packages, no organic or polymeric materi- als shall be molded to the bottom of the package to cover the leads. 8. dimension q shall be measured at the point of exit (beyond the me- niscus) of the lead from the bo dy. dimension q minimum shall be reduced by 0.0015 inch (0.038mm) maximum when solder dip lead finish is applied. 9. dimensioning and tolerancing per ansi y14.5m - 1982. 10. controlling dimension: inch. -d- -c- 0.004 h a - b m d s s -a- -b- 0.036 h a - b m d s s e e a q l d a e1 seating and l e2 e3 e3 base plane -h- b c s1 m c1 b1 (c) (b) section a-a base lead finish metal pin no. 1 id area a m k28.a mil-std-1835 cdfp3-f28 (f-11a, configuration b) 28 lead ceramic metal seal flatpack package symbol inches millimeters notes min max min max a 0.045 0.115 1.14 2.92 - b 0.015 0.022 0.38 0.56 - b1 0.015 0.019 0.38 0.48 - c 0.004 0.009 0.10 0.23 - c1 0.004 0.006 0.10 0.15 - d - 0.740 - 18.80 3 e 0.460 0.520 11.68 13.21 - e1 - 0.550 - 13.97 3 e2 0.180 - 4.57 - - e3 0.030 - 0.76 - 7 e 0.050 bsc 1.27 bsc - k 0.008 0.015 0.20 0.38 2 l 0.250 0.370 6.35 9.40 - q 0.026 0.045 0.66 1.14 8 s1 0.00 - 0.00 - 6 m - 0.0015 - 0.04 - n28 28- rev. 0 5/18/94 for the most recent package outline drawing, see k28.a .

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