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lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 lp38691-adj lp38693-adj 500ma low dropout cmos linear regulators with adjustable output stable with ceramic output capacitors check for samples: lp38691-adj , lp38693-adj 1 features description the lp38691/3-adj low dropout cmos linear 2 ? all wson options are available as aec-q100 regulators provide 2.0% precision reference voltage, grade 1 extremely low dropout voltage (250mv @ 500ma ? output voltage range of 1.25v - 9v load current, v out = 5v) and excellent ac ? 2.0% adjust pin voltage accuracy (25 c) performance utilizing ultra low esr ceramic output capacitors. ? low dropout voltage: 250mv @ 500ma (typ, 5v out) the low thermal resistance of the wson and sot- 223 packages allow the full operating current to be ? wide input voltage range (2.7v to 10v) used even in high ambient temperature ? precision (trimmed) bandgap reference environments. ? ensured specs for -40 c to +125 c the use of a pmos power transistor means that no ? 1 a off-state quiescent current dc base drive current is required to bias it allowing ? thermal overload protection ground pin current to remain below 100 a regardless of load current, input voltage, or operating ? foldback current limiting temperature. ? sot-223 and 6-lead wson packages dropout voltage: 250 mv (typ) @ 500ma (typ. 5v ? enable pin (lp38693-adj) out). applications ground pin current: 55 a (typ) at full load. ? hard disk drives adjust pin voltage: 2.0% (25 c) accuracy. ? notebook computers ? battery powered devices ? portable instrumentation typical application circuits v out = v adj x (1 + r1/r2) *minimum value required for stability. 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 all trademarks are the property of their respective owners. production data information is current as of publication date. copyright ? 2005 ? 2013, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. lp38693 -adj v in v out gnd 1 p f * 1 p f * v out v in r1 r2 v en v en adj lp38691 -adj v in v out gnd 1 p f * 1 p f * v out v in r1 r2 adj
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com connection diagrams figure 1. sot-223 (lp38693mp-adj) ? top view see package number ndc0005a figure 2. 6-lead wson (lp38691sd-adj) ? top figure 3. 6-lead wson (lp38693sd-adj) ? top view view see package number ngg0006a see package number ngg0006a pin descriptions pin description this is the input supply voltage to the regulator. for wson package devices, both v in pins must be tied v in together for full current operation (250ma maximum per pin). circuit ground for the regulator. for the sot-223 package this is thermally connected to the die and gnd functions as a heat sink when the soldered down to a large copper plane. v out regulated output voltage. v en the enable pin allows the part to be turned on and off by pulling this pin high or low. the adjust pin is used to set the regulated output voltage by connecting it to the external resistors r1 and adj r2 (see typical application circuits ). wson only - the dap (exposed pad) functions as a thermal connection when soldered to a copper plane. dap see wson mounting section in application hints for more information. these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj v in 2 3 4 5 6 1 gnd n/c adj v out v in exposed pad on bottom (dap) v in 2 3 4 5 6 1 gnd v en adj v out v in exposed pad on bottom (dap) adj v out gnd v en v in 12 4 3 5
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 absolute maximum ratings (1) (2) storage temperature range ? 65 c to +150 c lead temp. (soldering, 5 seconds) 260 c esd rating (3) 2 kv power dissipation (4) internally limited v(max) all pins (with respect to gnd) -0.3v to 12v i out (5) internally limited junction temperature ? 40 c to +150 c (1) absolute maximum ratings indicate limits beyond which damage to the component may occur. operating ratings indicate conditions for which the device is intended to be functional, but do not ensure specific performance limits. for ensured specifications, see electrical characteristics. specifications do not apply when operating the device outside of its rated operating conditions. (2) if military/aerospace specified devices are required, please contact the ti office/ distributors for availability and specifications. (3) esd is tested using the human body model which is a 100pf capacitor discharged through a 1.5k resistor into each pin. (4) at elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). the junction-to-ambient thermal resistance ( j-a ) for the sot-223 is approximately 125 c/w for a pc board mounting with the device soldered down to minimum copper area (less than 0.1 square inch). if one square inch of copper is used as a heat dissipator for the sot-223, the j-a drops to approximately 70 c/w. the j-a values for the wson package are also dependent on trace area, copper thickness, and the number of thermal vias used (refer to ti an-1187 application report and the wson mounting section in this datasheet). if power dissipation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown. (5) if used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground. operating ratings v in supply voltage 2.7v to 10v operating junction ? 40 c to +125 c temperature range electrical characteristics limits in standard typeface are for t j = 25 c, and limits in boldface type apply over the full operating temperature range. unless otherwise specified: v in = v out + 1v, c in = c out = 10 f, i load = 10ma. min/max limits are specified through testing, statistical correlation, or design. symbol parameter conditions min typ (1) max units v in = 2.7v 1.225 1.25 1.275 v adj adj pin voltage v 3.2v v in 10v 1.200 1.25 1.300 100 a < i l < 0.5a v o / v in output voltage line regulation (2) v o + 0.5v v in 10v 0.03 0.1 %/v i l = 25ma v o / i l output voltage load regulation (3) 1 ma < i l < 0.5a 1.8 5 %/a v in = v o + 1v (v o = 2.5v) 80 145 i l = 0.1a 430 725 i l = 0.5a (v o = 3.3v) 65 110 v in - v o dropout voltage (4) i l = 0.1a mv 330 550 i l = 0.5a (v o = 5v) 45 100 i l = 0.1a 250 450 i l = 0.5a i q quiescent current v in 10v, i l = 100 a - 0.5a 55 100 v en 0.4v, 0.001 1 a (lp38693-adj only) i l (min) minimum load current v in - v o 4v 100 (1) typical numbers represent the most likely parametric norm for 25 c operation. (2) output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage. (3) output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1ma to full load. (4) dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mv of nominal value. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 3 product folder links: lp38691-adj lp38693-adj
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com electrical characteristics (continued) limits in standard typeface are for t j = 25 c, and limits in boldface type apply over the full operating temperature range. unless otherwise specified: v in = v out + 1v, c in = c out = 10 f, i load = 10ma. min/max limits are specified through testing, statistical correlation, or design. symbol parameter conditions min typ (1) max units i fb foldback current limit v in - v o > 5v 350 ma v in - v o < 4v 850 psrr ripple rejection v in = v o + 2v(dc), with 1v(p-p) / 55 db 120hz ripple t sd thermal shutdown activation 160 (junction temp) c t sd (hyst) thermal shutdown hysteresis 10 (junction temp) i adj adj input leakage current v adj = 0 - 1.5v -100 0.01 100 na v in = 10v e n output noise bw = 10hz to 10khz 0.7 v/ hz v o = 3.3v v o (leak) output leakage current v o = v o (nom) + 1v @ v in = 10v 0.5 2 a v en enable voltage (lp38693-adj only) output = off 0.4 output = on, v in = 4v 1.8 v output = on, v in = 6v 3.0 output = on, v in = 10v 4.0 i en enable pin leakage (lp38693-adj v en = 0v or 10v, v in = 10v -1 0.001 1 a only) block diagrams figure 4. lp38691-adj functional diagram (wson) 4 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj enable logic - + mosfet driver foldback current limiting 1.25v reference thermal shutdown v in v out gnd p-fet p-fet n/c adj
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 figure 5. lp38693-adj functional diagram (sot-223, wson) copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 5 product folder links: lp38691-adj lp38693-adj enable logic - + mosfet driver foldback current limiting 1.25v reference thermal shutdown v in v out gnd p-fet p-fet v en adj
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com typical performance characteristics unless otherwise specified: t j = 25 c, c in = c out = 10 f, enable pin is tied to v in (lp38693-adj only), v o = 1.25v, v in = 2.7v, i l = 10ma. noise vs frequency noise vs frequency figure 6. figure 7. noise vs frequency ripple rejection figure 8. figure 9. ripple rejection ripple rejection figure 10. figure 11. 6 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj 10 100 1k 10k 100k frequency (hz) 0.0 0.5 1.0 1.5 noise ( p v/ hz) c out = 100 p f 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 10 p f 10 100 1k 10k 100k frequency (hz) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 noise/ ( p v hz) c out = 1 p f frequency (hz) 10 100 1k 10k 100k 0.0 0.2 0.4 0.6 0.8 1.0 noise ( p v/ hz) c out = 10 p f 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 1 p f 10 100 1k 10k 100k 0 10 20 30 40 50 60 70 frequency (hz) ripple rejection (db) v in (dc) = 3.25v v in (ac) = 1v(p-p) c out = 100 p f
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 typical performance characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, enable pin is tied to v in (lp38693-adj only), v o = 1.25v, v in = 2.7v, i l = 10ma. v ref vs temperature line transient response figure 12. figure 13. line transient response line transient response figure 14. figure 15. line transient response line transient response figure 16. figure 17. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 7 product folder links: lp38691-adj lp38693-adj 100 50 0 -50 -100 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v c out = 10 p f 100 p s/div 100 50 0 -50 -100 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v 40 p s/div c out = 1 p f 20 10 0 -10 -20 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v c out = 100 p f 200 p s/div 40 20 0 -20 -40 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v c out = 10 p f 200 p s/div -50 -25 0 25 50 75 100 125 temperature ( o c) -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 % deviation 20 10 0 -10 -20 ' v out (mv) 1 2 3 4 v in (v) v in v out v out = 1.25v c out = 100 p f 200 p s/div
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com typical performance characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, enable pin is tied to v in (lp38693-adj only), v o = 1.25v, v in = 2.7v, i l = 10ma. line transient response load transient response figure 18. figure 19. load transient response enable voltage vs temperature figure 20. figure 21. load regulation vs temperature line regulation vs temperature figure 22. figure 23. 8 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj ' v out / ' i out (%/a) -50 -25 0 25 50 75 100 125 temperature ( o c) -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 v en (v) v in = 10v v in = 6v v in = 4v 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 -50 -25 0 25 50 75 100 125 temperature ( o c) 400 200 0 -200 -400 ' v out (mv) 0.01 0.5 i load (a) i load v out c out = 1 p f 10 p s/div 200 100 0 -100 -200 ' v out (mv) 0.01 0.5 i load (a) i load v out c out = 10 p f 40 p s/div 100 50 0 -50 -100 ' v out (mv) 3 4 5 v in (v) v in v out v out = 3.3v 100 p s/div c out = 1 p f -50 -25 0 25 50 75 100 125 temperature ( o c) 0.02 0.022 0.024 0.026 0.028 0.03 0.032 0.034 ' v out / ' v in (%/v)
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 typical performance characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, enable pin is tied to v in (lp38693-adj only), v o = 1.25v, v in = 2.7v, i l = 10ma. v out vs v in , v out = 1.25v v out vs v in , v out = 1.80v figure 24. figure 25. v out vs v in , power-up v out vs v en , on (lp38693 only) figure 26. figure 27. v out vs v en , off (lp38693 only) min v in vs i out figure 28. figure 29. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 9 product folder links: lp38691-adj lp38693-adj 0 100 200 300 400 500 2 2.1 2.2 2.3 2.4 2.5 2.6 min v in (v) i out (ma) -40c 25c 125c
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com typical performance characteristics (continued) unless otherwise specified: t j = 25 c, c in = c out = 10 f, enable pin is tied to v in (lp38693-adj only), v o = 1.25v, v in = 2.7v, i l = 10ma. dropout voltage vs i out (v out = 1.8v) figure 30. 10 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj 0 100 200 300 400 500 i out (ma) 0 100 200 300 400 500 600 700 800 900 v dropout (mv) -40c 25c 125c
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 application hints external capacitors like any low-dropout regulator, external capacitors are required to assure stability. these capacitors must be correctly selected for proper performance. input capacitor: an input capacitor of at least 1 f is required (ceramic recommended). the capacitor must be located not more than one centimeter from the input pin and returned to a clean analog ground. output capacitor: an output capacitor is required for loop stability. it must be located less than 1 centimeter from the device and connected directly to the output and ground pins using traces which have no other currents flowing through them. the minimum amount of output capacitance that can be used for stable operation is 1 f. ceramic capacitors are recommended (the lp38691/3-adj was designed for use with ultra low esr capacitors). the lp38691/3-adj is stable with any output capacitor esr between zero and 100 ohms. setting the output voltage: the output voltage is set using the external resistors r1 and r2 (see typical application circuits ). the output voltage will be given by the equation: v out = v adj x (1 + ( r1 / r2 ) ) (1) because the part has a minimum load current requirement of 100 a, it is recommended that r2 always be 12k ohms or less to provide adequate loading. even if a minimum load is always provided by other means, it is not recommended that very high value resistors be used for r1 and r2 because it can make the adj node susceptible to noise pickup. a maximum ohmic value of 100k is recommended for r2 to prevent this from occurring. enable pin (lp38693-adj only): the lp38693 ? adj has an enable pin (en) which allows an external control signal to turn the regulator output on and off. the enable on/off threshold has no hysteresis. the voltage signal must rise and fall cleanly, and promptly, through the on and off voltage thresholds. the enable pin has no internal pull-up or pull-down to establish a default condition and, as a result, this pin must be terminated either actively or passively. if the enable pin is driven from a source that actively pulls high and low, the drive voltage should not be allowed to go below ground potential or higher than v in . if the application does not require the enable function, the pin should be connected directly to the v in pin. foldback current limiting: foldback current limiting is built into the lp38691/3-adj which reduces the amount of output current the part can deliver as the output voltage is reduced. the amount of load current is dependent on the differential voltage between v in and v out . typically, when this differential voltage exceeds 5v, the load current will limit at about 350 ma. when the v in -v out differential is reduced below 4v, load current is limited to about 850 ma. selecting a capacitor it is important to note that capacitance tolerance and variation with temperature must be taken into consideration when selecting a capacitor so that the minimum required amount of capacitance is provided over the full operating temperature range. capacitor characteristics ceramic for values of capacitance in the 10 to 100 f range, ceramics are usually larger and more costly than tantalums but give superior ac performance for bypassing high frequency noise because of very low esr (typically less than 10 m ? ). however, some dielectric types do not have good capacitance characteristics as a function of voltage and temperature. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 11 product folder links: lp38691-adj lp38693-adj
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com z5u and y5v dielectric ceramics have capacitance that drops severely with applied voltage. a typical z5u or y5v capacitor can lose 60% of its rated capacitance with half of the rated voltage applied to it. the z5u and y5v also exhibit a severe temperature effect, losing more than 50% of nominal capacitance at high and low limits of the temperature range. x7r and x5r dielectric ceramic capacitors are strongly recommended if ceramics are used, as they typically maintain a capacitance range within 20% of nominal over full operating ratings of temperature and voltage. of course, they are typically larger and more costly than z5u/y5u types for a given voltage and capacitance. tantalum solid tantalum capacitors have good temperature stability: a high quality tantalum will typically show a capacitance value that varies less than 10-15% across the full temperature range of -40 c to 125 c. esr will vary only about 2x going from the high to low temperature limits. the increasing esr at lower temperatures can cause oscillations when marginal quality capacitors are used (if the esr of the capacitor is near the upper limit of the stability range at room temperature). reverse voltage a reverse voltage condition will exist when the voltage at the output pin is higher than the voltage at the input pin. typically this will happen when v in is abruptly taken low and c out continues to hold a sufficient charge such that the input to output voltage becomes reversed. a less common condition is when an alternate voltage source is connected to the output. there are two possible paths for current to flow from the output pin back to the input during a reverse voltage condition. 1) while v in is high enough to keep the control circuity alive, and the enable pin (lp38693-adj only) is above the v en(on) threshold, the control circuitry will attempt to regulate the output voltage. if the input voltage is less than the programmed output voltage, the control circuit will drive the gate of the pass element to the full on condition. in this condition, reverse current will flow from the output pin to the input pin, limited only by the r ds(on) of the pass element and the output to input voltage differential. discharging an output capacitor up to 1000 f in this manner will not damage the device as the current will rapidly decay. however, continuous reverse current should be avoided. when the enable pin is low this condition will be prevented. 2) the internal pfet pass element has an inherent parasitic diode. during normal operation, the input voltage is higher than the output voltage and the parasitic diode is reverse biased. however, when v in is below the value where the control circuity is alive, or the enable pin is low (lp38693-adj only), and the output voltage is more than 500 mv (typical) above the input voltage the parasitic diode becomes forward biased and current flows from the output pin to the input pin through the diode. the current in the parasitic diode should be limited to less than 1a continuous and 5a peak. if used in a dual-supply system where the regulator output load is returned to a negative supply, the output pin must be diode clamped to ground to limit the negative voltage transition. a schottky diode is recommended for this protective clamp. pcb layout good pc layout practices must be used or instability can be induced because of ground loops and voltage drops. the input and output capacitors must be directly connected to the input, output, and ground pins of the regulator using traces which do not have other currents flowing in them (kelvin connect). the best way to do this is to lay out c in and c out near the device with short traces to the v in , v out , and ground pins. the regulator ground pin should be connected to the external circuit ground so that the regulator and its capacitors have a "single point ground". it should be noted that stability problems have been seen in applications where "vias" to an internal ground plane were used at the ground points of the ic and the input and output capacitors. this was caused by varying ground potentials at these nodes resulting from current flowing through the ground plane. using a single point ground technique for the regulator and it ? s capacitors fixed the problem. since high current flows through the traces going into v in and coming from v out , kelvin connect the capacitor leads to these pins so there is no voltage drop in series with the input and output capacitors. 12 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 wson mounting the ngg0006a (no pullback) 6-lead wson package requires specific mounting techniques which are detailed in the ti an-1187 application report . referring to the section pcb design recommendations (page 6), it should be noted that the pad style which should be used with the wson package is the nsmd (non-solder mask defined) type. additionally, it is recommended the pcb terminal pads to be 0.2 mm longer than the package pads to create a solder fillet to improve reliability and inspection. the thermal dissipation of the wson package is directly related to the printed circuit board construction and the amount of additional copper area connected to the dap. the dap (exposed pad) on the bottom of the wson package is connected to the die substrate with a conductive die attach adhesive. the dap has no direct electrical (wire) connection to any of the pins. there is a parasitic pn junction between the die substrate and the device ground. as such, it is strongly recommend that the dap be connected directly to the ground at device lead 2 (i.e. gnd). alternately, but not recommended, the dap may be left floating (i.e. no electrical connection). the dap must not be connected to any potential other than ground. for the lp38691sd-adj and lp38693sd-adj in the ngg0006a 6-lead wson package, the junction-to-case thermal rating, jc , is 10.4 c/w, where the case is the bottom of the package at the center of the dap. the junction-to-ambient thermal performance for the lp38691sd-adj and lp38693sd-adj in the ngg0006a 6- lead wson package, using the jedec jesd51 standards is summarized in the following table: board thermal jc ja type vias jedec 2-layer none 10.4 c/w 237 c/w jesd 51-3 1 10.4 c/w 74 c/w jedec 2 10.4 c/w 60 c/w 4-layer 4 10.4 c/w 49 c/w jesd 51-7 6 10.4 c/w 45 c/w rfi/emi susceptibility rfi (radio frequency interference) and emi (electromagnetic interference) can degrade any integrated circuit ? s performance because of the small dimensions of the geometries inside the device. in applications where circuit sources are present which generate signals with significant high frequency energy content ( > 1 mhz), care must be taken to ensure that this does not affect the ic regulator. if rfi/emi noise is present on the input side of the regulator (such as applications where the input source comes from the output of a switching regulator), good ceramic bypass capacitors must be used at the input pin of the ic. if a load is connected to the ic output which switches at high speed (such as a clock), the high-frequency current pulses required by the load must be supplied by the capacitors on the ic output. since the bandwidth of the regulator loop is less than 100 khz, the control circuitry cannot respond to load changes above that frequency. this means the effective output impedance of the ic at frequencies above 100 khz is determined only by the output capacitor(s). in applications where the load is switching at high speed, the output of the ic may need rf isolation from the load. it is recommended that some inductance be placed between the output capacitor and the load, and good rf bypass capacitors be placed directly across the load. pcb layout is also critical in high noise environments, since rfi/emi is easily radiated directly into pc traces. noisy circuitry should be isolated from "clean" circuits where possible, and grounded through a separate path. at mhz frequencies, ground planes begin to look inductive and rfi/ emi can cause ground bounce across the ground plane. in multi-layer pcb applications, care should be taken in layout so that noisy power and ground planes do not radiate directly into adjacent layers which carry analog power and ground. copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 13 product folder links: lp38691-adj lp38693-adj
lp38691-adj , lp38693-adj snvs324i ? january 2005 ? revised april 2013 www.ti.com output noise noise is specified in two ways- spot noise or output noise density is the rms sum of all noise sources, measured at the regulator output, at a specific frequency (measured with a 1hz bandwidth). this type of noise is usually plotted on a curve as a function of frequency. total output noise or broad-band noise is the rms sum of spot noise over a specified bandwidth, usually several decades of frequencies. attention should be paid to the units of measurement. spot noise is measured in units v/root-hz or nv/root-hz and total output noise is measured in v(rms) the primary source of noise in low-dropout regulators is the internal reference. noise can be reduced in two ways: by increasing the transistor area or by increasing the current drawn by the internal reference. increasing the area will decrease the chance of fitting the die into a smaller package. increasing the current drawn by the internal reference increases the total supply current (ground pin current). 14 submit documentation feedback copyright ? 2005 ? 2013, texas instruments incorporated product folder links: lp38691-adj lp38693-adj
lp38691-adj , lp38693-adj www.ti.com snvs324i ? january 2005 ? revised april 2013 revision history changes from revision h (april 2013) to revision i page ? changed layout of national data sheet to ti format .......................................................................................................... 14 copyright ? 2005 ? 2013, texas instruments incorporated submit documentation feedback 15 product folder links: lp38691-adj lp38693-adj
package option addendum www.ti.com 1-nov-2013 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples lp38691qsd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l251b lp38691qsdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l251b lp38691sd-adj nrnd wson ngg 6 1000 tbd call ti call ti -40 to 125 l117b lp38691sd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l117b lp38691sdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l117b lp38693mp-adj/nopb active sot-223 ndc 5 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 ljub lp38693mpx-adj/nopb active sot-223 ndc 5 2000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 ljub lp38693qsd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 llrb lp38693qsdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 llrb lp38693sd-adj/nopb active wson ngg 6 1000 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l127b lp38693sdx-adj/nopb active wson ngg 6 4500 green (rohs & no sb/br) cu sn level-1-260c-unlim -40 to 125 l127b (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above.
package option addendum www.ti.com 1-nov-2013 addendum-page 2 green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of lp38691-adj, lp38691-adj-q1, lp38693-adj, lp38693-adj-q1 : ? catalog: lp38691-adj , lp38693-adj ? automotive: lp38691-adj-q1 , lp38693-adj-q1 note: qualified version definitions: ? catalog - ti's standard catalog product ? automotive - q100 devices qualified for high-reliability automotive applications targeting zero defects
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant lp38691qsd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691qsdx-adj/nop b wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691sd-adj wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691sd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38691sdx-adj/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693mp-adj/nopb sot-223 ndc 5 1000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 q3 lp38693mpx-adj/nopb sot-223 ndc 5 2000 330.0 16.4 7.0 7.5 2.2 12.0 16.0 q3 lp38693qsd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693qsdx-adj/nop b wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693sd-adj/nopb wson ngg 6 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 lp38693sdx-adj/nopb wson ngg 6 4500 330.0 12.4 3.3 3.3 1.0 8.0 12.0 q1 package materials information www.ti.com 11-oct-2013 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) lp38691qsd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38691qsdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38691sd-adj wson ngg 6 1000 210.0 185.0 35.0 lp38691sd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38691sdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38693mp-adj/nopb sot-223 ndc 5 1000 367.0 367.0 35.0 lp38693mpx-adj/nopb sot-223 ndc 5 2000 367.0 367.0 35.0 lp38693qsd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38693qsdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 lp38693sd-adj/nopb wson ngg 6 1000 210.0 185.0 35.0 lp38693sdx-adj/nopb wson ngg 6 4500 367.0 367.0 35.0 package materials information www.ti.com 11-oct-2013 pack materials-page 2
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