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mb90350 series f 2 mc-16lx 16-bit microcontroller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-07872 rev. *a revised may 31, 2017 the mb90350-series with 1 channel full-can interface and flash rom is especially designed for automotive and industrial appli- cations. its main feature is the on-board ca n interface, which conforms to v2.0 part a and part b, while supporting a very flex ible message buffer scheme and so offering more functions than a normal full can approach. with the new 0.35 ? m cmos technology, cypress now offers on-chip flash-rom program memory up to 128 kbytes. the power supply (3 v) is supplied to the internal mcu core fr om an internal regulator circuit. this creates a major advantage in terms of emi and power consumption. the internal pll clock frequency multiplier provides an internal 42 ns instruction execution time from an external 4 mhz clock. also, the clock monitor function can monitor main clock and sub clock independently. as the peripheral resources, the unit feat ures a 4-channel output comp are unit, 6-channel input capt ure unit, 2 separate 16-bit freerun timers, 2-channel uart and 15-channel 8/10-bit a/d converter. features clock built-in pll clock frequency multiplication circuit selection of machine clocks (p ll clocks) is allowed among frequency division by two on oscillation clock, and multiplication of 1 to 6 times of oscillation cl ock (for 4 mhz oscillation clock, 4 mhz to 24 mhz). operation by sub clock (up to 50 khz : 100 khz oscillation clock divided by two) is allowed. (devices without s-suffix only) minimum execution time of instruction : 42 ns (when operating with 4-mhz oscillation clock, and 6-time multiplied pll clock). built-in clock modulation circuit 16 mbytes cpu memory space 24-bit internal addressing clock monitor function (mb90x356x and mb90x357x only) main clock or sub clock is monitored independently. internal cr oscillation clock (100 khz typical) can be used as sub clock. instruction system best suited to controller wide choice of data types (bit, byte, word, and long word) wide choice of addressing modes (23 types) enhanced multiply-divide instructions with sign and reti instructions enhanced high-precision computing with 32-bit accumulator instruction system compatible with high-level language (c language) and multitask employing system stack pointer enhanced various pointer indirect instructions barrel shift instructions increased processing speed 4-byte instruction queue powerful interrupt function powerful 8-level, 34-cond ition interrupt feature up to 8 channels external interrupts are supported. automatic data transfer function independent of cpu extended intelligent i/o service function (ei 2 os) : up to 16 channels dma: up to 16 channels low power consumption (standby) mode sleep mode (a mode that halts cpu operating clock) main timer mode (a timebase timer mode switched from the main clock mode) pll timer mode (a timebase timer mode switched from the pll clock mode) watch mode (a mode that operates sub clock and watch timer only) stop mode (a mode that stops oscillation clock and sub clock) cpu intermittent operation mode process cmos technology i/o port general-purpose input/out put port (cmos output) ? 49 ports (devices without s-su ffix : devices that correspond to sub clock) ? 51 ports (devices with s-suff ix : devices that do not corre- spond to sub clock)
document number: 002-07872 rev. *a page 2 of 83 mb90350 series sub clock pin (x0a, x1a) yes (using the external oscillation) : devices without s-suffix no (using the sub clock mode at internal cr oscillation) : devices with s-suffix timer timebase timer, watch timer, watchdog timer: 1 channel 8/16-bit ppg timer: 8-bit 10 channels or 16-bit 6 channels 16-bit reload timer: 4 channels 16- bit input/output timer ? 16-bit freerun timer : 2 channe ls (frt0: icu0/1, frt1: icu 4/5/6/7, o cu 4/5/6/7) ? 16- bit input capture: (icu): 6 channels ? 16-bit output compar e: (ocu): 4 channels full-can interface 1 channel compliant with ver2.0 part a a nd ver2.0 part b can specifica- tions flexible message buffering (mailbox and fifo buffering can be mixed) can wake-up function uart (lin/sci): 2 channels equipped with full-duplex double buffer clock-asynchronous or clock-synch ronous serial transmission is available. i 2 c interface: 1 channel up to 400 kbit/s transfer rate dtp/external interrupt: 8 channels, can wakeup: 1 channel module for activation of extended intelligent i/o service (ei 2 os), dma, and generation of ex ternal interrupt by external input. delay interrupt generator module generates interrupt requ est for task switching. 8/10-bit a/d converter: 15 channels resolution is selectable between 8-bit and 10-bit. activation by external trigger input is allowed. conversion time: 3 s (at 24-mhz machine clock, including sampling time) program patch function address matching detection for 6 address pointers. capable of changing input voltage level for port automotive/cmos-schmitt (initial level is automotive in single chip mode) ttl level (corresponds to external bus pins only, initial level of these pins is ttl in external bus mode) low voltage/cpu operation detection reset (devices with t-suffix) detects low voltage (4.0 v ? 0.3 v) and resets automatically resets automatically when program is runaway and counter is not cleared within interval time (approx. 262 ms : external 4 mhz) dual operation flash memo ry (only flash memory devices with a-suffix) erase/write and read can be exec uted in the different bank (upper bank/lower bank) at the same time. models that support ? 125 c devices without a-suffix (excluding evaluation device) : the maximum operating frequency is 16 mhz (at t a ? ? 125 c) . devices with a-suffix (excluding evaluation device) : the maximum operating frequency is 24 mhz (at t a ? ? 125 c) . flash security function protects the content of fl ash memory (mb90f352x and mb90f357x only) external bus interface 4 mbytes external memory space
document number: 002-07872 rev. *a page 3 of 83 mb90350 series contents product lineup 1 ............................................................. 4 product lineup 2 ............................................................. 6 product lineup 3 ............................................................. 8 product lineup 4 ........................................................... 10 packages and product correspondence ..................... 12 pin assignments ............................................................ 13 pin description ............................................................... 14 i/o circuit type ............................................................... 18 handling devices ............................................................ 22 preventing latch-up ................................................... 22 handling unused pins ................................................ 22 using external clock .................................................. 23 precautions for when not using a sub clock signal .... 23 notes on during operation of pll clock mode .......... 23 power supply pins (vcc/vss) ............ .............. ....... 23 pull-up/down resistors ......... ...................................... 23 crystal oscillator circuit ............................................ 23 turning-on sequence of power supply to a/d converter and analog inputs .............................. 24 connection of unused pins of a/d converter if a/d converter is not used ......................................... 24 notes on energization ............................................... 24 stabilization of power supply voltage ......... ........... .... 24 initialization ................................................................ 24 port 0 to port 3 output during power-on (external-bus mode) .............. .............. .............. ........ 24 notes on using can function ................................... 24 flash security function ............................................. 25 correspondence with ta ? ? 105 c or more ........... 25 low voltage/cpu operation re set circuit ................... 25 internal cr oscillation circuit ............ .............. ........... 26 block diagrams .............................................................. 27 memory map .................................................................... 31 i/o map ............................................................................ 32 can controllers .............................................................. 40 interrupt factors, interrupt vectors, interrupt control register .............................................. 46 electrical characteristics ............................................... 48 absolute maximum ratings ... .................................... 48 recommended operating conditions ....................... 50 dc characteristics .................................................... 51 ac characteristics ..................................................... 56 a/d converter ............................................................ 71 definition of a/d converter terms ........................... 74 flash memory program/erase characteristics .......... 76 ordering information ..................................................... 77 package dimensions ...................................................... 79 major changes ................................................................ 81 document history ........................................................... 82 sales, solutions, and legal information ...................... 83
document number: 002-07872 rev. *a page 4 of 83 mb90350 series 1. product lineup 1 (continued) part number parameter mb90f351, mb90f352 mb90f351s, mb90f352s mb90f351a, mb90f352a mb90f351ta, mb90f352ta mb90f351as, mb90f352as mb90f351tas, mb90f352tas cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier (1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom flash memory 64kbytes :mb90f351(s) 128kbytes :mb90f352(s) dual operation flash memory 64kbytes :mb90f351a(s), mb90f351ta(s) 128kbytes :mb90f352a(s), mb90f352ta(s) ram 4 kbytes emulator-specific power supply* ? sub clock pin (x0a, x1a) (max 100 khz) yes no yes no clock monitor function no low voltage/cpu operation detection reset no no yes no yes operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/ d converter/flash programming 4.5 v to 5.5 v : at using external bus operating temperature range ? 40 c to ? 105 c ( ? 125 c up to 16 mhz machine clock) ? 40 c to ? 125 c package lqfp-64 uart 2 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel a/d converter 15 channels 10-bit or 8-bit resolution conversion time : min 3 ? s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corre sponds to icu 4/5/ 6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match with output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock frequency) 16-bit output compare 4 channels signals an interrupt when 16-bit i/o timer matches with output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture 6 channels retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
document number: 002-07872 rev. *a page 5 of 83 mb90350 series (continued) * : it is setting of jumper switch (too l vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90f351, mb90f352 mb90f351s, mb90f352s mb90f351a, mb90f352a mb90f351ta, mb90f352ta mb90f351as, mb90f352as mb90f351tas, mb90f352tas 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler ? 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc ? 4 mhz (fsys ? machine clock frequency, fosc ? oscillation clock frequency) can interface 1 channel conforms to can specification version 2.0 part a and b. automatic re-transmissi on in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for external bus (only for external bus pin) flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycl es : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block. block protection with external programming voltage flash security feature for protecting t he content of the flash (mb90f352x only) corresponding eva name mb90v340a- 102 mb90v340a- 101 mb90v340a-102 mb90v340a-101
document number: 002-07872 rev. *a page 6 of 83 mb90350 series 2. product lineup 2 (continued) part number parameter mb90351a, mb90352a mb90351ta, mb90352ta mb90351as, mb90352as mb90351tas, mb90352tas mb90v340a- 101 mb90v340a- 102 cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier (1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom mask rom 64kbytes :mb90351a(s), mb90351ta(s) 128kbytes :mb90352a(s), mb90352ta(s) external ram 4 kbytes 30 kbytes emulator-specific power supply* ?yes sub clock pin (x0a, x1a) (max 100 khz) yes no no yes clock monitor function no low voltage/cpu operation detection reset no yes no yes no operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/d converter 4.5 v to 5.5 v : at using external bus 5 v ? 10% operating temperature range ? 40 c to ? 125 c ? package lqfp-64 pga-299 uart 2 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel 2 channels a/d converter 15 channels 24 channels 10-bit or 8-bit resolution conversion time : min 3 ? s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck 0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7. i/o timer 0 corresponds to icu 0/1/2/3, o cu 0/1/2/3. i/o timer 1 corresponds to icu 4/5/6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match with output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock frequency) 16-bit output compare 4 channels 8 channels signals an interrupt when 16-bit i/o timer matches output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture 6 channels 8 channels retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
document number: 002-07872 rev. *a page 7 of 83 mb90350 series (continued) * : it is setting of jumper switch (too l vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90351a, mb90352a mb90351ta, mb90352ta mb90351as, mb90352as mb90351tas, mb90352tas mb90v340a- 101 mb90v340a- 102 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 8 channels (16-bit)/ 16 channels (8-bit) 8-bit reload counters 16 8-bit reload registers for l pulse width 16 8-bit reload registers for h pulse width 16 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler ? 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc ? 4 mhz (fsys ? machine clock frequency, fosc ? oscillation clock frequency) can interface 1 channel 3 channels conforms to can specification version 2.0 part a and b. automatic re-transmissi on in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels 16 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? 2 channels i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for external bus (only for external bus pin) flash memory ? corresponding eva name mb90v340a-102 mb90v340a-101 ?
document number: 002-07872 rev. *a page 8 of 83 mb90350 series 3. product lineup 3 (continued) part number parameter mb90f356a, mb90f357a mb90f356ta, mb90f357ta mb90f356as, mb90f357as mb90f356tas, mb90f357tas cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier (1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom dual operation flash memory 64kbytes :mb90f356a(s), mb90f356ta(s) 128kbytes :mb90f357a(s), mb90f357ta(s) ram 4 kbytes emulator-specific power supply* ? sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) clock monitor function yes low voltage/cpu operation detection reset no yes no yes operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 3.5 v to 5.5 v : at using a/d converter/flash programming 3.5 v to 5.5 v : at using external bus operating temperature range ? 40 c to ? 125 c package lqfp-64 uart 2 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel a/d converter 15 channels 10-bit or 8-bit resolution conversion time : min 3 ? s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corre sponds to icu 4/5/ 6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match wit h output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock frequency) 16-bit output compare 4 channels signals an interrupt when 16-bit i/o timer matches with output compare registers. a pair of compare registers can be used to generate an output signal. 16-bit input capture 6 channels retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt.
document number: 002-07872 rev. *a page 9 of 83 mb90350 series (continued) * : it is setting of jumper switch (too l vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90f356a, mb90f357a mb90f356ta, mb90f357ta mb90f356as, mb90f357as mb90f356tas, mb90f357tas 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler ? 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc ? 4 mhz (fsys ? machine clock frequency, fosc ? oscillation clock frequency) can interface 1 channel conforms to can specification version 2.0 part a and b. automatic re-transmissi on in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral module signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for external bus (only for external bus pin) flash memory supports automatic programming, embedded algorithm write/erase/erase-suspend/resume commands a flag indicating completion of the algorithm number of erase cycl es : 10,000 times data retention time : 10 years boot block configuration erase can be performed on each block. block protection with external programming voltage flash security feature for protecting t he content of the flash (mb90f357x only) corresponding eva name mb90v340a-104 mb90v340a-103
document number: 002-07872 rev. *a page 10 of 83 mb90350 series 4. product lineup 4 (continued) part number parameter mb90356a, mb90357a mb90356ta, mb90357ta mb90356as, mb90357as mb90356tas, mb90357tas mb90v340a- 103 mb90v340a- 104 cpu f 2 mc-16lx cpu system clock on-chip pll clock multiplier (1, 2, 3, 4, 6, 1/2 when pll stops) minimum instruction execution time : 42 ns (oscillation clock 4 mhz, pll 6) rom mask rom 64kbytes :mb90356a(s), mb90356ta(s) 128kbytes :mb90357a(s), mb90357ta(s) external ram 4 kbytes 30 kbytes emulator-specific power supply* ?yes sub clock pin (x0a, x1a) yes no (internal cr oscillation can be used as sub clock) no (internal cr oscillation can be used as sub clock) yes clock monitor function yes low voltage/cpu operation detection reset no yes no yes no operating voltage range 3.5 v to 5.5 v : at normal operating (not using a/d converter) 4.0 v to 5.5 v : at using a/d converter 4.5 v to 5.5 v : at using external bus 5 v ? 10% operating temperature range ? 40 c to ? 125 c ? package lqfp-64 pga-299 uart 2 channels 5 channels wide range of baud rate settings using a dedicated reload timer special synchronous options for adapting to different synchronous serial protocols lin functionality working either as master or slave lin device i 2 c (400 kbps) 1 channel 2 channels a/d converter 15 channels 24 channels 10-bit or 8-bit resolution conversion time : min 3 ? s includes sample time (per one channel) 16-bit reload timer (4 channels) operation clock frequency : fsys/2 1 , fsys/2 3 , fsys/2 5 (fsys ? machine clock frequency) supports external event count function. 16-bit i/o timer (2 channels) i/o timer 0 (clock input frck 0) corresponds to icu 0/1. i/o timer 1 (clock input frck1) corresponds to icu 4/5/6/7, ocu 4/5/6/7. i/o timer 0 corresponds to icu 0/1/2/3, o cu 0/1/2/3. i/o timer 1 corresponds to icu 4/5/6/7, ocu 4/5/6/7. signals an interrupt when overflowing. supports timer clear when a match with output compare (channel 0, 4) . operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 , fsys/2 5 , fsys/2 6 , fsys/2 7 (fsys ? machine clock frequency) 16-bit output compare 4 channels 8 channels signals an interrupt when 16-bit i/o ti mer matches with output compare registers. a pair of compare registers can be used to generate an output signal.
document number: 002-07872 rev. *a page 11 of 83 mb90350 series (continued) * : it is setting of jumper switch (too l vcc) when emulator (mb2147-01) is used. please refer to the emulator hardware manual about details. part number parameter mb90356a, mb90357a mb90356ta, mb90357ta mb90356as, mb90357as mb90356tas, mb90357tas mb90v340a- 103 mb90v340a- 104 16-bit input capture 6 channels 8 channels retains freerun timer value by (rising edge, falling edge or rising & falling edge), signals an interrupt. 8/16-bit programmable pulse generator 6 channels (16-bit)/10 channels (8-bit) 8-bit reload counters 12 8-bit reload registers for l pulse width 12 8-bit reload registers for h pulse width 12 8 channels (16-bit)/16 channels (8-bit) 8-bit reload counters 16 8-bit reload registers for l pulse width 16 8-bit reload registers for h pulse width 16 supports 8-bit and 16-bit operation modes. a pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler ? 8-bit reload counter. operation clock frequency : fsys, fsys/2 1 , fsys/2 2 , fsys/2 3 , fsys/2 4 or 128 s@fosc ? 4 mhz (fsys ? machine clock frequency, fosc ? oscillation clock frequency) can interface 1 channel 3 channels conforms to can specification version 2.0 part a and b. automatic re-transmissi on in case of error automatic transmission responding to remote frame prioritized 16 message buffers for data and id supports multiple messages. flexible configuration of acceptance filtering : full bit compare/full bit mask/two partial bit masks supports up to 1 mbps. external interrupt 8 channels 16 channels can be used rising edge, falling edge, starting up by h/l level input, external interrupt, extended intelligent i/o services (ei 2 os) and dma. d/a converter ? 2 channels i/o ports virtually all external pins can be used as general purpose i/o port. all push-pull outputs bit-wise settable as input/output or peripheral module signal settable as cmos schmitt trigger/ automotive inputs ttl input level settable for external bus (only for external bus pin) flash memory ? corresponding eva name mb90v340a-104 mb90v340a-103 ?
document number: 002-07872 rev. *a page 12 of 83 mb90350 series 5. packages and product correspondence * : this device is under development. : yes, : no note : refer to ? package dimensions ? for detail of each package. package mb90v340a -101 -102 -103 -104 mb90f351 mb90f351s mb90f352 mb90f352s mb90f351a (s) , mb90f351ta (s) mb90f352a (s) , mb90f352ta (s) mb90f356a (s) , mb90f356ta (s) mb90f357a (s) , mb90f357ta (s) mb90351a (s) , mb90351ta (s) mb90352a (s) , mb90352ta (s) mb90356a (s) , mb90356ta (s) mb90357a (s) , mb90357ta (s) pga-299c-a01 fpt-64p-m23 (12 mm , 0.65 mm pitch) fpt-64p-m24 (10 mm , 0.50 mm pitch) *
document number: 002-07872 rev. *a page 13 of 83 mb90350 series 6. pin assignments mb90f351(s), mb90f352(s),mb90f351a(s), mb90 f351ta(s), mb90f352a(s), mb90f352ta(s), mb90f356a(s), mb90f356ta(s), mb90f357a(s), mb90f357ta(s),mb90351a(s), mb90351ta(s), mb90352a(s), mb90352ta(s),mb90356a(s), mb 90356ta(s), mb90357a(s), mb90357ta(s), (top view) (lqfp-64p) (fpt-64p-m23, fpt-64p-m24) * : devices without s-suffix : x0a, x1a devices with s-suffix : p40, p41 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 avcc p61/an1 p60/an0 p37/clk/out7 p36/rdy/out6 p35/hak /out5 p34/hrq/out4 p32/wrl /wr /int10r p31/rd /in5 p30/ale/in4 p45/scl0/frck1 p44/sda0/frck0 p25/a21/in1/adtg c vcc p33/wrh 10 11 12 13 14 15 16 1234567 9 8 p10/ad08/tin1 p07/ad07/int15 p06/ad06/int14 p05/ad05/int13 p04/ad04/int12 p03/ad03/int11 p02/ad02/int10 p01/ad01/int9 p00/ad00/int8 md0 md1 md2 p41/x1a* p40/x0a* vss p43/in7/tx1 vss x0 x1 rst p24/a20/in0 p23/a19/ppgf(e) p22/a18/ppgd(c) p21/a17/ppgb(a) p20/a16/ppg9(8) p17/ad15 p16/ad14 p15/ad13 p14/ad12/sck3 p13/ad11/sot3 p12/ad10/sin3/int11r p11/ad09/tot1 avss avrh p64/an4/ppg8(9) p65/an5/ppga(b) p66/an6/ppgc(d) p67/an7/ppge(f) p50/an8/sin2 p51/an9/sot2 p52/an10/sck2 p53/an11/tin3 p56/an14 p55/an13 p54/an12/tot3 p62/an2/ppg4(5) p63/an3/ppg6(7) p42/in6/rx1/int9r
document number: 002-07872 rev. *a page 14 of 83 mb90350 series 7. pin description (continued) pin no. pin name circuit type function lqfp64* 46 x1 a oscillation output pin 47 x0 oscillation input pin 45 rst e reset input pin 3 to 8 p62 to p67 i general purpose i/o ports an2 to an7 analog input pins for a/d converter ppg4 (5) , 6 (7) , 8 (9) , a (b) , c (d) , e (f) output pins for ppgs 9 p50 o general purpose i/o port an8 analog input pin for a/d converter sin2 serial data input pin for uart2 10 p51 i general purpose i/o port an9 analog input pin for a/d converter sot2 serial data output pin for uart2 11 p52 i general purpose i/o port an10 analog input pin for a/d converter sck2 serial clock i/o pin for uart2 12 p53 i general purpose i/o port an11 analog input pin for a/d converter tin3 event input pin for reload timer3 13 p54 i general purpose i/o port an12 analog input pin for a/d converter tot3 output pin for reload timer3 14, 15 p55, p56 i general purpose i/o ports an13, an14 analog input pins for a/d converter 16 p42 f general purpose i/o port in6 data sample input pin for input capture icu6 rx1 rx input pin for can1 int9r external interrupt request input pin for int9 17 p43 f general purpose i/o port in7 data sample input pin for input capture icu7 tx1 tx output pin for can1 19, 20 p40, p41 f general purpose i/o ports (devices with s-suffix and mb90v340a-101/103) x0a, x1a b x0a : oscillation input pins for sub clock x1a : oscillation output pins for sub clock (devices without s-suffix and mb90v340a-102/104) 24 to 31 p00 to p07 g general purpose i/o ports. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad00 to ad07 input/output pins of external address data bus lower 8 bits. this function is enabled when the external bus is enabled. int8 to int15 external interrupt requ est input pins for int8 to int15
document number: 002-07872 rev. *a page 15 of 83 mb90350 series (continued) pin no. pin name circuit type function lqfp64* 32 p10 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad08 input/output pin for external bus address data bus bit 8. this function is enabled when external bus is enabled. tin1 event input pin for reload timer1 33 p11 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad09 input/output pin for external bus address data bus bit 9. this function is enabled when external bus is enabled. tot1 output pin for reload timer1 34 p12 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad10 input/output pin for external bus address data bus bit 10. this function is enabled when external bus is enabled. sin3 serial data input pin for uart3 int11r external interrupt request input pin for int11 35 p13 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad11 input/output pin for external bus address data bus bit 11. this function is enabled when external bus is enabled. sot3 serial data output pin for uart3 36 p14 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad12 input/output pin for external bus address data bus bit 12. this function is enabled when external bus is enabled. sck3 clock input/output pin for uart3 37 p15 n general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad13 input/output pin for external bus address data bus bit 13. this function is enabled when external bus is enabled. 38 p16 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad14 input/output pin for external bus address data bus bit 14. this function is enabled when external bus is enabled. 39 p17 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ad15 input/output pin for external bus address data bus bit 15. this function is enabled when external bus is enabled. 40 to 43 p20 to p23 g general purpose i/o ports. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pins are enabled as a general purpose i/o port when the corresponding bit in the external address output control register (hacr) is 1. a16 to a19 output pins for a16 to a19 of the external address data bus. when the corresponding bit in the external addr ess output control register (hacr) is 0, the pins are enabled as high address output pins a16 to a19. ppg9 (8) , ppgb (a) , ppgd (c) , ppgf (e) output pins for ppgs
document number: 002-07872 rev. *a page 16 of 83 mb90350 series (continued) pin no. pin name circuit type function lqfp64* 44 p24 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pin is enabled as a general- purpose i/o port when the corresponding bi t in the external address output control register (hacr) is 1. a20 output pin for a20 of the external address data bus. when the corresponding bit in the external address output control regi ster (hacr) is 0, the pin is enabled as high address output pin a20. in0 data sample input pin for input capture icu0 51 p25 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. in external bus mode, the pin is enabled as a general- purpose i/o port when the corresponding bi t in the external address output control register (hacr) is 1. a21 output pin for a21 of the external address data bus. when the corresponding bit in the external address output control r egister (hacr) is 0, the pi n is enabled as high address output pin a21. in1 data sample input pin for input capture icu1 adtg trigger input pin for a/d converter 52 p44 h general purpose i/o port sda0 serial data i/o pin for i 2 c 0 frck0 input pin for the 16-bit i/o timer 0 53 p45 h general purpose i/o port scl0 serial clock i/o pin for i 2 c 0 frck1 input pin for the 16-bit i/o timer 1 54 p30 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. ale address latch enable output pi n. this function is enabled when external bus is enabled. in4 data sample input pin for input capture icu4 55 p31 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled in single-chip mode. rd read strobe output pin for data bus. this function is enabled when external bus is enabled. in5 data sample input pin for input capture icu5 56 p32 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the wr /wrl pin output disabled. wr /wrl write strobe output pin for the data bus. this function is enabled when both the external bus and the wr /wr l pin output are enabled. wrl is used to write-strobe 8 lower bits of the data bus in 16-bit access. wr is used to write-strobe 8 bi ts of the data bus in 8-bit access. int10r external interrupt request input pin for int10 57 p33 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode, in external bus 8-bit mode or with the wrh pin output disabled. wrh write strobe output pin for the 8 higher bits of the data bus. this function is enabled when the external bus is enabled, when the exter nal bus 16-bit mode is selected, and when the wrh output pin is enabled.
document number: 002-07872 rev. *a page 17 of 83 mb90350 series * : fpt-64p-m23, fpt-64p-m24 pin no. pin name circuit type function lqfp64* 58 p34 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hrq hold request input pin. this function is enab led when both the external bus and the hold function are enabled. out4 waveform output pin for output compare ocu4 59 p35 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the hold function disabled. hak hold acknowledge output pin. th is function is enabled when both the external bus and the hold function are enabled. out5 waveform output pin for output compare ocu5 60 p36 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the external ready function disabled. rdy ready input pin. this function is enabled when both the external bus and the external ready function are enabled. out6 waveform output pin for output compare ocu6 61 p37 g general purpose i/o port. the register can be set to select whether to use a pull-up resistor. this function is enabled either in single-chip mode or with the clk output disabled. clk clk output pin. this function is enabled w hen both the external bu s and clk output are enabled. out7 waveform output pin for output compare ocu7 62, 63 p60, p61 i general purpose i/o ports an0, an1 analog input pins for a/d converter 64 av cc kv cc power input pin for analog circuits 2avrhl reference voltage input for the a/d converter. this power supply must be turned on or off while a voltage higher than or equal to avrh is applied to av cc . 1av ss kv ss power input pin for analog circuits 22, 23 md1, md0 c input pins for specifying the operating mode 21 md2 d input pin for specifying the operating mode 49 v cc ? power (3.5 v to 5.5 v) input pin 18, 48 v ss ? power (0 v) input pins 50 c k this is the power supply stabi lization capacitor pin. it shou ld be connected to a higher than or equal to 0.1 f ceramic capacitor.
document number: 002-07872 rev. *a page 18 of 83 mb90350 series 8. i/o circuit type (continued) type circuit remarks a oscillation circuit ? high-speed oscillation feedback resistor = approx. 1 m ? b oscillation circuit ? low-speed oscillation feedback resistor = approx. 10 m ? c mask rom device: ? cmos hysteresis input pin flash memory device: ? cmos input pin d mask rom device: ? cmos hysteresis input pin ? pull-down resistor value: approx. 50 k ? flash memory device: ? cmos input pin ? no pull-down e cmos hysteresis input pin ? pull-up resistor value: approx. 50 k ? standby control signal x1 x0 xout standby control signal x1a x0a xout cmos hysteresis inputs r pull-down resistor cmos hysteresis inputs r pull-up resistor cmos hysteresis inputs r
document number: 002-07872 rev. *a page 19 of 83 mb90350 series (continued) type circuit remarks f ?cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) g ?cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos hysteresis inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the standby-time input shut- down function) ? programmable pull-up resistor: approx. 50 k ? h ?cmos level output (i ol = 3 ma, i oh ? ? 3 ma) ? cmos hysteresis inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) cmos hysteresis inputs automotive inputs standby control for input shutdown pout nout r p-ch n-ch pull-up control cmos hysteresis inputs automotive inputs ttl input standby control for input shutdown pull-up resistor pout nout r p-ch p-ch n-ch cmos hysteresis inputs automotive inputs standby control for input shutdown pout nout r p-ch n-ch
document number: 002-07872 rev. *a page 20 of 83 mb90350 series (continued) type circuit remarks i ? cmos level output (i ol = 4 ma, i oh = ? 4 ma) ? cmos hysteresis inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input k ? power supply input protection circuit l ? a/d converter reference voltage power supply input pin, with the protection circuit ? flash memory devices do not have a protection circuit against v cc for pin avrh. cmos hysteresis inputs automotive inputs standby control for input shutdown analog input pout nout r p-ch n-ch p-ch n-ch ane avr ane p-ch n-ch
document number: 002-07872 rev. *a page 21 of 83 mb90350 series (continued) type circuit remarks n ?cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? ttl input (with the st andby-time input shut- down function) ? programmable pull-up resistor: ? approx. 50 k ? o ?cmos level output (i ol = 4 ma, i oh ? ? 4 ma) ? cmos inputs (with the standby-time input shutdown function) ? automotive input (with the standby-time input shutdown function) ? a/d analog input pull-up control cmos inputs automotive inputs ttl input standby control for input shutdown pull-up resistor pout nout r cmos inputs automotive inputs standby control for input shutdown analog input p-ch n-ch pout nout r
document number: 002-07872 rev. *a page 22 of 83 mb90350 series 9. handling devices special care is required for the following when handling the device : preventing latch-up treatment of unused pins using external clock precautions for when not using a sub clock signal notes on during operation of pll clock mode power supply pins (v cc /v ss ) pull-up/down resistors crystal oscillator circuit turning-on sequence of power supply to a/d converter and analog inputs connection of unused pins of a/d converter notes on energization stabilization of power supply voltage initialization port0 to port3 output during power-on (external-bus mode) notes on using can function flash security function correspondence with t a ? ? 105 c or more low voltage/cpu operation detection reset circuit internal cr oscillation circuit 9.1 preventing latch-up cmos ic chips may suffer latch-up under the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc pin and v ss pin. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current dras tically, causing thermal damage to the device. in using the devices, take sufficient care to avoid exceeding maximum ratings. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avrh) exceed the digital power-supply voltage. 9.2 handling unused pins leaving unused input pins open may result in misbehavior or la tch up and possible permanent damage of the device. therefore the y must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused i/o pins should be set to the output state and can be le ft open, or the input state wit h the above described connection.
document number: 002-07872 rev. *a page 23 of 83 mb90350 series 9.3 using external clock to use external clock, drive the x0 pin and leave x1 pin open. 9.4 precautions for when not using a sub clock signal if you do not connect pins x0a and x1a to an oscillator, use pull-down handling on the x0a pin, and leave the x1a pin open. 9.5 notes on during operation of pll clock mode if the pll clock mode is selected, the micr ocontroller attempts to be working with the self-oscillating circuit even when there is no external oscillator or external clock input is stopped. pe rformance of this operation, however, cannot be guaranteed. 9.6 power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the st robe signal due to the rise of ground level, and observe the s tandard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the current supply source at a low impedance. as a measure against power supply nois e, connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss pins in the vicinity of v cc and v ss pins of the device. 9.7 pull-up/down resistors the mb90350 series does not support internal pull-up/down resistors (port 0 to port 3: built-in pull-up resistors). use externa l compo- nents where needed. 9.8 crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provid e bypass capacitors via shortest distance from x0, x1 pins, crystal oscill ator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, tha t lines of oscillation circuit do not cross the lines of other circuits. it is highly recommended to provide a printed circuit board artw ork surrounding x0 and x1 pins with a ground area for stabilizi ng the operation. please ask the crystal maker to evaluate the oscillat ional characteristics of the crystal and this device. x0 x1 mb90350 series open vcc vss vss vcc vss vcc mb90350 series vcc vss vcc vss
document number: 002-07872 rev. *a page 24 of 83 mb90350 series 9.9 turning-on sequence of power su pply to a/d converter and analog inputs make sure to turn on the a/d converter power supply (av cc , avrh) and analog inputs (an0 to an14) after turning-on the digital power supply (v cc ) . turn-off the digital power after turning off the a/d converter pow er supply and analog inputs. in this case, make sure that the voltage does not exceed avrh or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable). 9.10 connection of unused pins of a/d converter if a/d converter is not used connect unused pins of a/d converter to av cc ? v cc , av ss ? avrh ? v ss . 9.11 notes on energization to prevent the internal regulator circuit from malfunction ing, set the voltage rise time during energization at 50 s or more (0.2 v to 2.7 v) . 9.12 stabilization of power supply voltage a sudden change in the power supply voltage may cause the device to malfunction even within the specified v cc power supply voltage operating range. therefore, the v cc power supply voltage should be stabilized. for reference, the power supply volt age should be controlled so that v cc ripple variations (peak-to-peak value) at commercial frequencies (50 hz to 60 hz) fall below 10% of the standard v cc power supply voltage and the co efficient of fluc tuation does not exceed 0.1 v/ms at instantaneous power switching. 9.13 initialization in the device, there are internal registers which are initialized only by a power-on reset. to initialize these registers, tur n on the power again. 9.14 port 0 to port 3 output during power-on (external-bus mode) as shown below, when power is turned on in external-bus mode, there is a possibility that output signal of port 0 to port 3 might be unstable. 9.15 notes on using can function to use can function, please set ?1? to direct bit of can direct mode register (cdmr). if direct bit is set to ?0? (initial value), wait states will be performed when accessing can registers. note : please refer to section ?22.15 can direct mode register? in ha rdware manual of mb90350 series for detail of can direct mode register. port0 to port3 port0 to port3 outputs might be unstable. port0 to port3 outputs = hi-z v cc 1/2 v cc
document number: 002-07872 rev. *a page 25 of 83 mb90350 series 9.16 flash security function the security byte is located in the area of the flash memory. if protection code 01 h is written in the security by te, the flash memory is in the protected state by security. therefore please do not write 01 h in this address if you do not use the security function. please refer to following table for the address of the security byte. 9.17 correspondence with t a ? ? 105 c or more if used exceeding t a ? ? 105 c, please contact sales represent atives for reliability limitations. 9.18 low voltage/cpu operation reset circuit the low voltage detection reset circuit is a function that monito rs power supply voltage in order to detect when a voltage drop s below a given voltage level. when a low voltage condition is detected, an internal reset signal is generated. the cpu operation detection reset circuit is a 20-bit counter that uses oscillation as a count clock and generates an internal reset signal if not cleared within a given time after startup. 9.18.1 low voltage detection reset circuit when a low voltage condition is detected, the low voltage detecti on flag (lvrc: lvrf) is set to ?1? and an internal reset signa l is output. because the low voltage detection reset circuit continues to oper ate even in stop mode, detection of a low voltage condition ge nerates an internal reset and releases stop mode. during an internal ram write cycle, low voltage reset is g enerated after the completi on of writing. during the output of this i nternal reset, the reset output from the low volt age detection reset circuit is suppressed. 9.18.2 cpu operation detection reset circuit the cpu operation detection reset circuit is a counter that prevents progr am runaway. the counter starts automatically after a power-on reset, and must be continually cleared within a given ti me. if the given time interval elapses and the counter has not been cleared, a cause such as infinite program looping is assumed and an internal reset signal is generated. the internal reset gene rated from the cpu operation detection circ uit has a width of 5 machine cycles. * : this value assumes the interval time at an oscillation clock frequency of 4 mhz. during recovery from standby mode, the detec tion period is the maximum interval plus 20 s. this circuit does not operate in modes where cpu operation is stopped. the cpu operation detection reset circuit counter is cleared under any of the following conditions. ?0? writing to cl bit of lvrc register internal reset main oscillation clock stop transit to sleep mode transit to timebase timer mode and watch mode flash memory size address for security bit mb90f352(s) mb90f352a(s) mb90f352ta(s) mb90f357a(s) mb90f357ta(s) embedded 1 mbit flash memory fe0001 h detection voltage 4.0 v ? 0.3 v interval time 2 20 /f c (approx. 262 ms*)
document number: 002-07872 rev. *a page 26 of 83 mb90350 series 9.19 internal cr oscillation circuit parameter symbol value unit min typ max oscillation frequency f rc 50 100 200 khz oscillation stabilization wait time tstab ? ? 100 s
document number: 002-07872 rev. *a page 27 of 83 mb90350 series 10. block diagrams mb90v340a-101/102 av cc scl0,scl1 sda0,sda1 ppgf to ppg0 da00,da01 adtg avrh avrl an23 to an0 av ss sin4 to sin0 sck4 to sck0 sot4 to sot0 x0 x0a* frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin3 to tin0 tot3 to tot0 ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 int7 to int0 ckot (int11r to int9r) rst dmac 16lx cpu x1 x1a* clock controller ram 30 kbytes prescaler 5 channels uart 5 channels i/o timer 0 input capture 8 channels output compare 8 channels i/o timer 1 can controller 3 channels 16-bit reload timer 4 channels 10-bit a/d converter 24 channels 10-bit d/a converter 2 channels 8/16-bit ppg 16 channels i 2 c interface 2 channels external interrupt external bus interface f 2 mc-16 bus * : mb90v340a-102 only clock monitor
document number: 002-07872 rev. *a page 28 of 83 mb90350 series mb90v340a-103/104 av cc scl1, scl0 sda1, sda0 ppgf to ppg0 da01, da00 adtg avrh an23 to an0 av ss sin4 to sin0 sck4 to sck0 sot4 to sot0 x0 x0a * frck0 in7 to in0 out7 to out0 frck1 rx2 to rx0 tx2 to tx0 tin3 to tin0 tot3 to tot0 ad15 to ad00 a23 to a16 ale hrq rdy clk int15 to int8 (int15r to int8r) rst dma hak wrh wrl rd avrl ckot int7 to int0 x1 x1a* clock controller/monit or cr oscillation circuit uart 5 channels i/o timer 0 input capture 8 channels output compare 8 channels i/o timer 1 can controller 3 channels 16-bit reload timer 4 channels 8/10-bit a/d converter 24 channels 10-bit d/a converter 2 channels 8/16-bit ppg 16 channels i 2 c interface 2 channels dtp/external interrupt external bus interface internal data bus * : mb90v340a-104 only clock monitor ram 30 kbytes prescaler 5 channels f 2 mc-16lx core
document number: 002-07872 rev. *a page 29 of 83 mb90350 series mb90f352 (s) , mb90f351 (s) , mb90f352a (s) , mb90f352ta (s) , mb90f351a (s) , mb90f351ta (s) , mb90352a (s) , mb90352ta (s) , mb90351a (s) , mb90351ta (s) av cc scl0 sda0 ppg6, ppg4 ppgf to ppg8 adtg avrh an14 to an0 av ss sin3, sin2 sck3, sck2 sot3, sot2 frck0 in7 to in4, in1, in0 out7 to out4 frck1 rx1 tx1 tin3, tin1 tot3, tot1 ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 (int11r to int9r) dmac 16lx cpu x0 x0a * 1 rst x1 x1a* 1 clock controller low voltage/ cpu operation detection reset* 2 prescaler 2 channels uart 2 channels i/o timer 0 input capture 6 channels output compare 4 channels i/o timer 1 can controller 1 channel 16-bit reload timer 4 channels 8/10-bit a/d converter 15 channels 8/16-bit ppg 10/6 channels i 2 c interface 1 channel external interrupt external bus interface f 2 mc-16 bus *1 : only for devic es without ?s?-suffix *2 : only for devi ces with ?t?-suffix ram 4 kbytes rom/flash 128 k/64 kbytes
document number: 002-07872 rev. *a page 30 of 83 mb90350 series mb90f357a (s) , mb90f357ta (s) , mb90f356a (s) , mb90f356ta (s) , mb90357a (s) , mb90357ta (s) , mb90356a (s) , mb90356ta (s) av cc scl0 sda0 ppg6, ppg4 ppgf to ppg8 adtg avrh an14 to an0 av ss sin3, sin2 sck3, sck2 sot3, sot2 x0 x0a * 1 rst frck0 in7 to in4, in1, in0 out7 to out4 frck1 rx1 tx1 tin3, tin1 tot3, tot1 ad15 to ad00 a21 to a16 ale rd wrl wrh hrq hak rdy clk int15 to int8 (int11r to int9r) dmac 16lx cpu x1 x1a * 1 clock controller/ monitor cr oscillation circuit prescaler 2 channels uart 2 channels i/o timer 0 input capture 6 channels output compare 4 channels i/o timer 1 can controller 1 channel 16-bit reload timer 4 channels 8/10-bit a/d converter 15 channels 8/16-bit ppg 10/6 channels i 2 c interface 1 channel external interrupt external bus interface f 2 mc-16 bus *1 : only for device s without ?s?-suffix *2 : only for devices with ?t?-suffix ram 4 kbytes rom/flash 128 k/64 k bytes low voltage detector* 2 cpu operation detector* 2
document number: 002-07872 rev. *a page 31 of 83 mb90350 series 11. memory map note : the high-order portion of bank 00 gives the image of the ff bank rom to make the small model of the c compiler effective. since the low-order 16 bits are the same, t he table in rom can be referenced without us ing the far specification in the pointer declaration. for example, an attempt to access 00c000 h accesses the value at ffc000 h in rom. the rom area in bank ff exceeds 32 kbytes, a nd its entire image cannot be shown in bank 00. the image between ff8000 h and ffffff h is visible in bank 00, while the image between ff0000 h and ff7fff h is visible only in bank ff. ffffff h ff0000 h feffff h fe0000 h fdffff h c00100 h 00ffff h 008000 h 007fff h 007900 h 000100 h 0010ff h 001100 h 0000ef h 000000 h mb90351a (s) mb90351ta (s) mb90356a (s) mb90356ta (s) mb90f351a (s) mb90f351ta (s) mb90f356a (s) mb90f356ta (s) mb90f351 (s) mb90352a (s) mb90352ta (s) mb90357a (s) mb90357ta (s) mb90f352a (s) mb90f352ta (s) mb90f357a (s) mb90f357ta (s) mb90f352 (s) ffffff h ff0000 h fdffff h c00100 h 00ffff h 008000 h 007fff h 007900 h 000100 h 0010ff h 0000ef h 000000 h ffffff h mb90v340a-101 mb90v340a-102 mb90v340a-103 mb90v340a-104 feffff h ff0000 h fdffff h fe0000 h fcffff h fd0000 h fbffff h fc0000 h faffff h fb0000 h f9ffff h fa0000 h f8ffff h f90000 h 007fff h 008000 h 0078ff h 007900 h 000000 h 0000ef h f80000 h 00ffff h 000100 h rom (ff bank) rom (ff bank) rom (ff bank) rom (fb bank) rom (fc bank) peripheral rom (f8 bank) rom (image of ff bank) rom (fd bank) rom (fe bank) rom (fa bank) rom (f9 bank) ram 30 kbytes peripheral rom (fe bank) external access area rom (image of ff bank) peripheral ram 4 kbytes external access area peripheral external access area rom (image of ff bank) peripheral ram 4 kbytes external access area peripheral : no access
document number: 002-07872 rev. *a page 32 of 83 mb90350 series 12. i/o map (continued) address register abbreviation access resource name initial value 00 h port 0 data register pdr0 r/w port 0 xxxxxxxx b 01 h port 1 data register pdr1 r/w port 1 xxxxxxxx b 02 h port 2 data register pdr2 r/w port 2 xxxxxxxx b 03 h port 3 data register pdr3 r/w port 3 xxxxxxxx b 04 h port 4 data register pdr4 r/w port 4 xxxxxxxx b 05 h port 5 data register pdr5 r/w port 5 xxxxxxxx b 06 h port 6 data register pdr6 r/w port 6 xxxxxxxx b 07 h to 0a h reserved 0b h port 5 analog input enable register ader5 r/w port 5, a/d 11111111 b 0c h port 6 analog input enable register ader6 r/w port 6, a/d 11111111 b 0d h reserved 0e h input level select register 0 ilsr0 r/w ports 00000000 b 0f h input level select register 1 ilsr1 r/w ports 00000000 b 10 h port 0 direction register ddr0 r/w port 0 00000000 b 11 h port 1 direction register ddr1 r/w port 1 00000000 b 12 h port 2 direction register ddr2 r/w port 2 xx000000 b 13 h port 3 direction register ddr3 r/w port 3 00000000 b 14 h port 4 direction register ddr4 r/w port 4 xx000000 b 15 h port 5 direction register ddr5 r/w port 5 x0000000 b 16 h port 6 direction register ddr6 r/w port 6 00000000 b 17 h to 19 h reserved 1a h sin input level setting regi ster ddra w uart2, uart3 x00xxxxx b 1b h reserved 1c h port 0 pull-up control register pucr0 r/w port 0 00000000 b 1d h port 1 pull-up control register pucr1 r/w port 1 00000000 b 1e h port 2 pull-up control register pucr2 r/w port 2 00000000 b 1f h port 3 pull-up control register pucr3 r/w port 3 00000000 b 20 h to 37 h reserved 38 h ppg 4 operation mode control register ppgc4 w, r/w 16-bit programmable pulse generator 4/5 0x000xx1 b 39 h ppg 5 operation mode control register ppgc5 w, r/w 0x000001 b 3a h ppg 4/5 count clock select register ppg45 r/w 000000x0 b 3b h address detect control register 1 pacsr1 r/w address match detection 1 00000000 b 3c h ppg 6 operation mode control register ppgc6 w, r/w 16-bit programmable pulse generator 6/7 0x000xx1 b 3d h ppg 7 operation mode control register ppgc7 w, r/w 0x000001 b 3e h ppg 6/7 count clock select register ppg67 r/w 000000x0 b 3f h reserved 40 h ppg 8 operation mode control register ppgc8 w, r/w 16-bit programmable pulse generator 8/9 0x000xx1 b 41 h ppg 9 operation mode control register ppgc9 w, r/w 0x000001 b 42 h ppg 8/9 count clock select register ppg89 r/w 000000x0 b 43 h reserved
document number: 002-07872 rev. *a page 33 of 83 mb90350 series (continued) address register abbreviation access resource name initial value 44 h ppg a operation mode control register ppgca w, r/w 16-bit programmable pulse generator a/b 0x000xx1 b 45 h ppg b operation mode control register ppgcb w, r/w 0x000001 b 46 h ppg a/b count clock select register ppgab r/w 000000x0 b 47 h reserved 48 h ppg c operation mode control register ppgcc w,r/w 16-bit programmable pulse generator c/d 0x000xx1 b 49 h ppg d operation mode control register ppgcd w,r/w 0x000001 b 4a h ppg c/d count clock select register ppgcd r/w 000000x0 b 4b h reserved 4c h ppg e operation mode control register ppgce w,r/w 16-bit programmable pulse generator e/f 0x000xx1 b 4d h ppg f operation mode control register ppgcf w,r/w 0x000001 b 4e h ppg e/f count clock select register ppgef r/w 000000x0 b 4f h reserved 50 h input capture control stat us register 0/1 ics01 r/w input capture 0/1 00000000 b 51 h input capture edge regist er 0/1 ice01 r/w, r xxx0x0xx b 52 h , 53 h reserved 54 h input capture control stat us register 4/5 ics45 r/w input capture 4/5 00000000 b 55 h input capture edge register 4/5 ice45 r xxxxxxxx b 56 h input capture control stat us register 6/7 ics67 r/w input capture 6/7 00000000 b 57 h input capture edge regist er 6/7 ice67 r/w, r xxx000xx b 58 h to 5b h reserved 5c h output compare control status register 4 ocs4 r/w output compare 4/5 0000xx00 b 5d h output compare control status register 5 ocs5 r/w 0xx00000 b 5e h output compare control status register 6 ocs6 r/w output compare 6/7 0000xx00 b 5f h output compare control status register 7 ocs7 r/w 0xx00000 b 60 h timer control status register 0 tmcsr0 r/w 16-bit reload timer 0 00000000 b 61 h timer control status register 0 tmcsr0 r/w xxxx0000 b 62 h timer control status register 1 tmcsr1 r/w 16-bit reload timer 1 00000000 b 63 h timer control status register 1 tmcsr1 r/w xxxx0000 b 64 h timer control status register 2 tmcsr2 r/w 16-bit reload timer 2 00000000 b 65 h timer control status register 2 tmcsr2 r/w xxxx0000 b 66 h timer control status register 3 tmcsr3 r/w 16-bit reload timer 3 00000000 b 67 h timer control status register 3 tmcsr3 r/w xxxx0000 b 68 h a/d control status register 0 adcs0 r/w a/d converter 000xxxx0 b 69 h a/d control status register 1 adcs1 r/w 0000000x b 6a h a/d data register 0 adcr0 r 00000000 b 6b h a/d data register 1 adcr1 r xxxxxx00 b 6c h adc setting register 0 adsr0 r/w 00000000 b 6d h adc setting register 1 adsr1 r/w 00000000 b 6e h low voltage/cpu operation detection reset control register lvrc r/w, w low voltage/cpu operation detection reset 00111000 b
document number: 002-07872 rev. *a page 34 of 83 mb90350 series (continued) address register abbrevia- tion access resource name initial value 6f h rom mirror function select r egister romm w rom mirror xxxxxxx1 b 70 h to 7f h reserved 80 h to 8f h reserved for can interface 1. refer to ? can controllers ? 90 h to 9a h reserved 9b h dma descriptor channel specification register dcsr r/w dma 00000000 b 9c h dma status register l dsrl r/w 00000000 b 9d h dma status register h dsrh r/w 00000000 b 9e h address detect control register 0 pacsr0 r/w address match detection 0 00000000 b 9f h delayed interrupt/release regist er dirr r/w delayed interrupt xxxxxxx0 b a0 h low-power consumption mode control register lpmcr w,r/w low power consumption control circuit 00011000 b a1 h clock selection re gister ckscr r,r/w low power consumption control circuit 11111100 b a2 h , a3 h reserved a4 h dma stop status register dssr r/w dma 00000000 b a5 h automatic ready function selection register arsr w external memory access 0011xx00 b a6 h external address output control register hacr w 00000000 b a7 h bus control signal selection register ecsr w 0000000x b a8 h watchdog control register wd tc r,w watchdog timer xxxxx111 b a9 h timebase timer control register tbtc w,r/w timebase timer 1xx00100 b aa h watch timer control register wtc r,r/w watch timer 1x001000 b ab h reserved ac h dma enable register l derl r/w dma 00000000 b ad h dma enable register h derh r/w 00000000 b ae h flash control status register (flash devices only. otherwise reserved) fmcs r,r/w flash memory 000x0000 b af h reserved
document number: 002-07872 rev. *a page 35 of 83 mb90350 series (continued) address register abbreviation access resource name initial value b0 h interrupt control register 00 icr00 w,r/w interrupt control 00000111 b b1 h interrupt control register 01 icr01 w,r/w 00000111 b b2 h interrupt control register 02 icr02 w,r/w 00000111 b b3 h interrupt control register 03 icr03 w,r/w 00000111 b b4 h interrupt control register 04 icr04 w,r/w 00000111 b b5 h interrupt control register 05 icr05 w,r/w 00000111 b b6 h interrupt control register 06 icr06 w,r/w 00000111 b b7 h interrupt control register 07 icr07 w,r/w 00000111 b b8 h interrupt control register 08 icr08 w,r/w 00000111 b b9 h interrupt control register 09 icr09 w,r/w 00000111 b ba h interrupt control register 10 icr10 w,r/w 00000111 b bb h interrupt control register 11 icr11 w,r/w 00000111 b bc h interrupt control register 12 icr12 w,r/w 00000111 b bd h interrupt control register 13 icr13 w,r/w 00000111 b be h interrupt control register 14 icr14 w,r/w 00000111 b bf h interrupt control register 15 icr15 w,r/w 00000111 b c0 h to c9 h reserved ca h external interrupt enable register 1 enir1 r/w external interrupt 1 00000000 b cb h external interrupt source register 1 eirr1 r/w xxxxxxxx b cc h external interrupt level register 1 elvr1 r/w 00000000 b cd h external interrupt level register 1 elvr1 r/w 00000000 b ce h external interrupt source se lect register eissr r/w 00000000 b cf h pll/sub clock control register psccr w pll xxxx0000 b d0 h dma buffer address pointer l bapl r/w dma xxxxxxxx b d1 h dma buffer address pointer m bapm r/w xxxxxxxx b d2 h dma buffer address pointer h baph r/w xxxxxxxx b d3 h dma control register dmacs r/w xxxxxxxx b d4 h i/o register address pointer l ioal r/w xxxxxxxx b d5 h i/o register address pointer h ioah r/w xxxxxxxx b d6 h data counter l dctl r/w xxxxxxxx b d7 h data counter h dcth r/w xxxxxxxx b d8 h serial mode register 2 smr2 w,r/w uart2 00000000 b d9 h serial control register 2 scr2 w,r/w 00000000 b da h reception/transmission data register 2 rdr2/tdr2 r/w 00000000 b db h serial status register 2 ssr2 r,r/w 00001000 b dc h extended communication control register 2 eccr2 r,w, r/w 000000xx b dd h extended status/control register 2 escr2 r/w 00000100 b de h baud rate generator register 20 bgr20 r/w 00000000 b df h baud rate generator register 21 bgr21 r/w 00000000 b e0 h to ef h reserved
document number: 002-07872 rev. *a page 36 of 83 mb90350 series (continued) address register abbreviation access resource name initial value f0 h to ff h external area 7900 h to 7907 h reserved 7908 h reload register l4 prll4 r/w 16-bit programmable pulse generator 4/5 xxxxxxxx b 7909 h reload register h4 prlh4 r/w xxxxxxxx b 790a h reload register l5 prll5 r/w xxxxxxxx b 790b h reload register h5 prlh5 r/w xxxxxxxx b 790c h reload register l6 prll6 r/w 16-bit programmable pulse generator 6/7 xxxxxxxx b 790d h reload register h6 prlh6 r/w xxxxxxxx b 790e h reload register l7 prll7 r/w xxxxxxxx b 790f h reload register h7 prlh7 r/w xxxxxxxx b 7910 h reload register l8 prll8 r/w 16-bit programmable pulse generator 8/9 xxxxxxxx b 7911 h reload register h8 prlh8 r/w xxxxxxxx b 7912 h reload register l9 prll9 r/w xxxxxxxx b 7913 h reload register h9 prlh9 r/w xxxxxxxx b 7914 h reload register la prlla r/w 16-bit programmable pulse generator a/b xxxxxxxx b 7915 h reload register ha prlha r/w xxxxxxxx b 7916 h reload register lb prllb r/w xxxxxxxx b 7917 h reload register hb prlhb r/w xxxxxxxx b 7918 h reload register lc prllc r/w 16-bit programmable pulse generator c/d xxxxxxxx b 7919 h reload register hc prlhc r/w xxxxxxxx b 791a h reload register ld prlld r/w xxxxxxxx b 791b h reload register hd prlhd r/w xxxxxxxx b 791c h reload register le prlle r/w 16-bit programmable pulse generator e/f xxxxxxxx b 791d h reload register he prlhe r/w xxxxxxxx b 791e h reload register lf prllf r/w xxxxxxxx b 791f h reload register hf prlhf r/w xxxxxxxx b 7920 h input capture register 0 ipcp0 r input capture 0/1 xxxxxxxx b 7921 h input capture register 0 ipcp0 r xxxxxxxx b 7922 h input capture register 1 ipcp1 r xxxxxxxx b 7923 h input capture register 1 ipcp1 r xxxxxxxx b 7924 h to 7927 h reserved 7928 h input capture register 4 ipcp4 r input capture 4/5 xxxxxxxx b 7929 h input capture register 4 ipcp4 r xxxxxxxx b 792a h input capture register 5 ipcp5 r xxxxxxxx b 792b h input capture register 5 ipcp5 r xxxxxxxx b
document number: 002-07872 rev. *a page 37 of 83 mb90350 series (continued) address register abbreviation access resource name initial value 792c h input capture register 6 ipcp6 r input capture 6/7 xxxxxxxx b 792d h input capture register 6 ipcp6 r xxxxxxxx b 792e h input capture register 7 ipcp7 r xxxxxxxx b 792f h input capture register 7 ipcp7 r xxxxxxxx b 7930 h to 7937 h reserved 7938 h output compare register 4 occp4 r/w output compare 4/5 xxxxxxxx b 7939 h output compare register 4 occp4 r/w xxxxxxxx b 793a h output compare register 5 occp5 r/w xxxxxxxx b 793b h output compare register 5 occp5 r/w xxxxxxxx b 793c h output compare register 6 occp6 r/w output compare 6/7 xxxxxxxx b 793d h output compare register 6 occp6 r/w xxxxxxxx b 793e h output compare register 7 occp7 r/w xxxxxxxx b 793f h output compare register 7 occp7 r/w xxxxxxxx b 7940 h timer data register 0 tcdt0 r/w i/o timer 0 00000000 b 7941 h timer data register 0 tcdt0 r/w 00000000 b 7942 h timer control status register 0 tccsl0 r/w 00000000 b 7943 h timer control status register 0 tccsh0 r/w 0xxxxxxx b 7944 h timer data register 1 tcdt1 r/w i/o timer 1 00000000 b 7945 h timer data register 1 tcdt1 r/w 00000000 b 7946 h timer control status register 1 tccsl1 r/w 00000000 b 7947 h timer control status register 1 tccsh1 r/w 0xxxxxxx b 7948 h timer register 0/reload register 0 tmr0/tmrl r0 r/w 16-bit reload timer 0 xxxxxxxx b 7949 h r/w xxxxxxxx b 794a h timer register 1/reload register 1 tmr1/tmrl r1 r/w 16-bit reload timer 1 xxxxxxxx b 794b h r/w xxxxxxxx b 794c h timer register 2/reload register 2 tmr2/tmrl r2 r/w 16-bit reload timer 2 xxxxxxxx b 794d h r/w xxxxxxxx b 794e h timer register 3/reload register 3 tmr3/tmrl r3 r/w 16-bit reload timer 3 xxxxxxxx b 794f h r/w xxxxxxxx b 7950 h serial mode register 3 smr3 w, r/w uart3 00000000 b 7951 h serial control register 3 scr3 w, r/w 00000000 b 7952 h reception/transmission data register 3 rdr3/tdr3 r/w 00000000 b 7953 h serial status register 3 ssr3 r,r/w 00001000 b 7954 h extended communication control register 3 eccr3 r,w, r/w 000000xx b 7955 h extended status/control register 3 escr3 r/w 00000100 b 7956 h baud rate generator register 30 bgr30 r/w 00000000 b 7957 h baud rate generator register 31 bgr31 r/w 00000000 b 7958 h , 7959 h reserved
document number: 002-07872 rev. *a page 38 of 83 mb90350 series (continued) address register abbreviation access resource name initial value 7960 h clock monitor function control register csvcr r, r/w clock monitor 00011100 b 7961 h to 796d h reserved 796e h can direct mode register cdmr r/w can clock sync xxxxxxx0 b 796f h reserved 7970 h i 2 c bus status register 0 ibsr0 r i 2 c interface 0 00000000 b 7971 h i 2 c bus control register 0 ibcr0 w,r/w 00000000 b 7972 h i 2 c 10-bit slave address register 0 itbal0 r/w 00000000 b 7973 h itbah0 r/w 00000000 b 7974 h i 2 c 10-bit slave address mask register 0 itmkl0 r/w 11111111 b 7975 h itmkh0 r/w 00111111 b 7976 h i 2 c 7-bit slave address register 0 isba0 r/w 00000000 b 7977 h i 2 c 7-bit slave address mask register 0 ismk0 r/w 01111111 b 7978 h i 2 c data register 0 idar0 r/w 00000000 b 7979 h , 797a h reserved 797b h i 2 c clock control register 0 iccr0 r/w i 2 c interface 0 00011111 b 797c h to 79a1 h reserved 79a2 h flash write control register 0 fwr0 r/w dual operation flash 00000000 b 79a3 h flash write control register 1 fwr1 r/w 00000000 b 79a4 h sector change setting register ssr0 r/w 00xxxxx0 b 79a5 h to 79c1 h reserved 79c2 h setting prohibited 79c3 h to 79df h reserved 79e0 h detect address setting register 0 padr0 r/w address match detection 0 xxxxxxxx b 79e1 h detect address setting register 0 padr0 r/w xxxxxxxx b 79e2 h detect address setting register 0 padr0 r/w xxxxxxxx b 79e3 h detect address setting register 1 padr1 r/w xxxxxxxx b 79e4 h detect address setting register 1 padr1 r/w xxxxxxxx b 79e5 h detect address setting register 1 padr1 r/w xxxxxxxx b 79e6 h detect address setting register 2 padr2 r/w xxxxxxxx b 79e7 h detect address setting register 2 padr2 r/w xxxxxxxx b 79e8 h detect address setting register 2 padr2 r/w xxxxxxxx b 79e9 h to 79ef h reserved
document number: 002-07872 rev. *a page 39 of 83 mb90350 series (continued) note s : initial value of ?x? represents unknown value. any write access to reserved addresses in i/o map should not be performed. a read access to reserved addresses results reading ?x?. address register abbreviation access resource name initial value 79f0 h detect address setting register 3 padr3 r/w address match detection 1 xxxxxxxx b 79f1 h detect address setting register 3 padr3 r/w xxxxxxxx b 79f2 h detect address setting register 3 padr3 r/w xxxxxxxx b 79f3 h detect address setting register 4 padr4 r/w xxxxxxxx b 79f4 h detect address setting register 4 padr4 r/w xxxxxxxx b 79f5 h detect address setting register 4 padr4 r/w xxxxxxxx b 79f6 h detect address setting register 5 padr5 r/w xxxxxxxx b 79f7 h detect address setting register 5 padr5 r/w xxxxxxxx b 79f8 h detect address setting register 5 padr5 r/w xxxxxxxx b 79f9 h to 7bff h reserved 7c00 h to 7cff h reserved for can interface 1. refer to ? can controllers ? 7d00 h to 7dff h reserved for can interface 1. refer to ? can controllers ? 7e00 h to 7fff h reserved
document number: 002-07872 rev. *a page 40 of 83 mb90350 series 13. can controllers the can controller has the following features : conforms to can specification version 2.0 part a and b ? supports transmission/reception in st andard frame and extended frame formats supports transmitting of data frames by receiving remote frames 16 transmitting/receiving message buffers ? 29-bit id and 8-byte data ? multi-level message buffer configuration provides full-bit comparison, full-bit mask , acceptance register 0/acc eptance register 1 for each message buffer as id acceptan ce mask ? two acceptance mask registers in either st andard frame format or extended frame formats bit rate programmable from 10 kbps to 2 mbps (when input clock is at 16 mhz) list of control registers (continued) address register abbreviation access initial value can1 000080 h message buffer enable register bvalr r/w 00000000 b 00000000 b 000081 h 000082 h transmit request register treqr r/w 00000000 b 00000000 b 000083 h 000084 h transmit cancel register tcanr w 00000000 b 00000000 b 000085 h 000086 h transmission complete register tcr r/w 00000000 b 00000000 b 000087 h 000088 h receive complete register rcr r/w 00000000 b 00000000 b 000089 h 00008a h remote request receiving register rrtrr r/w 00000000 b 00000000 b 00008b h 00008c h receive overrun register rovrr r/w 00000000 b 00000000 b 00008d h 00008e h reception interrupt enable register rier r/w 00000000 b 00000000 b 00008f h 007d00 h control status register csr r/w, w r/w, r 0xxxx0x1 b 00xxx000 b 007d01 h 007d02 h last event indicator register leir r/w 000x0000 b xxxxxxxx b 007d03 h 007d04 h receive/transmit error counter rtec r 00000000 b 00000000 b 007d05 h 007d06 h bit timing register btr r/w 11111111 b x1111111 b 007d07 h 007d08 h ide register ider r/w xxxxxxxx b xxxxxxxx b 007d09 h 007d0a h transmit rtr register trtrr r/w 00000000 b 00000000 b 007d0b h
document number: 002-07872 rev. *a page 41 of 83 mb90350 series (continued) address register abbreviation access initial value can1 007d0c h remote frame receive waiting register rfwtr r/w xxxxxxxx b xxxxxxxx b 007d0d h 007d0e h transmit interrupt enable register tier r/w 00000000 b 00000000 b 007d0f h 007d10 h acceptance mask select register amsr r/w xxxxxxxx b xxxxxxxx b 007d11 h 007d12 h xxxxxxxx b xxxxxxxx b 007d13 h 007d14 h acceptance mask register 0 amr0 r/w xxxxxxxx b xxxxxxxx b 007d15 h 007d16 h xxxxxxxx b xxxxxxxx b 007d17 h 007d18 h acceptance mask register 1 amr1 r/w xxxxxxxx b xxxxxxxx b 007d19 h 007d1a h xxxxxxxx b xxxxxxxx b 007d1b h
document number: 002-07872 rev. *a page 42 of 83 mb90350 series list of message buffers (id registers) (continued) address register abbreviation access initial value can1 007c00 h to 007c1f h general-purpose ram ? r/w xxxxxxxx b to xxxxxxxx b 007c20 h id register 0 idr0 r/w xxxxxxxx b xxxxxxxx b 007c21 h 007c22 h xxxxxxxx b xxxxxxxx b 007c23 h 007c24 h id register 1 idr1 r/w xxxxxxxx b xxxxxxxx b 007c25 h 007c26 h xxxxxxxx b xxxxxxxx b 007c27 h 007c28 h id register 2 idr2 r/w xxxxxxxx b xxxxxxxx b 007c29 h 007c2a h xxxxxxxx b xxxxxxxx b 007c2b h 007c2c h id register 3 idr3 r/w xxxxxxxx b xxxxxxxx b 007c2d h 007c2e h xxxxxxxx b xxxxxxxx b 007c2f h 007c30 h id register 4 idr4 r/w xxxxxxxx b xxxxxxxx b 007c31 h 007c32 h xxxxxxxx b xxxxxxxx b 007c33 h 007c34 h id register 5 idr5 r/w xxxxxxxx b xxxxxxxx b 007c35 h 007c36 h xxxxxxxx b xxxxxxxx b 007c37 h 007c38 h id register 6 idr6 r/w xxxxxxxx b xxxxxxxx b 007c39 h 007c3a h xxxxxxxx b xxxxxxxx b 007c3b h 007c3c h id register 7 idr7 r/w xxxxxxxx b xxxxxxxx b 007c3d h 007c3e h xxxxxxxx b xxxxxxxx b 007c3f h 007c40 h id register 8 idr8 r/w xxxxxxxx b xxxxxxxx b 007c41 h 007c42 h xxxxxxxx b xxxxxxxx b 007c43 h
document number: 002-07872 rev. *a page 43 of 83 mb90350 series (continued) address register abbreviation access initial value can1 007c44 h id register 9 idr9 r/w xxxxxxxx b xxxxxxxx b 007c45 h 007c46 h xxxxxxxx b xxxxxxxx b 007c47 h 007c48 h id register 10 idr10 r/w xxxxxxxx b xxxxxxxx b 007c49 h 007c4a h xxxxxxxx b xxxxxxxx b 007c4b h 007c4c h id register 11 idr11 r/w xxxxxxxx b xxxxxxxx b 007c4d h 007c4e h xxxxxxxx b xxxxxxxx b 007c4f h 007c50 h id register 12 idr12 r/w xxxxxxxx b xxxxxxxx b 007c51 h 007c52 h xxxxxxxx b xxxxxxxx b 007c53 h 007c54 h id register 13 idr13 r/w xxxxxxxx b xxxxxxxx b 007c55 h 007c56 h xxxxxxxx b xxxxxxxx b 007c57 h 007c58 h id register 14 idr14 r/w xxxxxxxx b xxxxxxxx b 007c59 h 007c5a h xxxxxxxx b xxxxxxxx b 007c5b h 007c5c h id register 15 idr15 r/w xxxxxxxx b xxxxxxxx b 007c5d h 007c5e h xxxxxxxx b xxxxxxxx b 007c5f h
document number: 002-07872 rev. *a page 44 of 83 mb90350 series list of message buffers (dlc registers and data registers) (continued) address register abbreviation access initial value can1 007c60 h dlc register 0 dlcr0 r/w xxxxxxxx b 007c61 h 007c62 h dlc register 1 dlcr1 r/w xxxxxxxx b 007c63 h 007c64 h dlc register 2 dlcr2 r/w xxxxxxxx b 007c65 h 007c66 h dlc register 3 dlcr3 r/w xxxxxxxx b 007c67 h 007c68 h dlc register 4 dlcr4 r/w xxxxxxxx b 007c69 h 007c6a h dlc register 5 dlcr5 r/w xxxxxxxx b 007c6b h 007c6c h dlc register 6 dlcr6 r/w xxxxxxxx b 007c6d h 007c6e h dlc register 7 dlcr7 r/w xxxxxxxx b 007c6f h 007c70 h dlc register 8 dlcr8 r/w xxxxxxxx b 007c71 h 007c72 h dlc register 9 dlcr9 r/w xxxxxxxx b 007c73 h 007c74 h dlc register 10 dlcr10 r/w xxxxxxxx b 007c75 h 007c76 h dlc register 11 dlcr11 r/w xxxxxxxx b 007c77 h 007c78 h dlc register 12 dlcr12 r/w xxxxxxxx b 007c79 h 007c7a h dlc register 13 dlcr13 r/w xxxxxxxx b 007c7b h 007c7c h dlc register 14 dlcr14 r/w xxxxxxxx b 007c7d h 007c7e h dlc register 15 dlcr15 r/w xxxxxxxx b 007c7f h 007c80 h to 007c87 h data register 0 (8 bytes) dtr0 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-07872 rev. *a page 45 of 83 mb90350 series address register abbreviation access initial value can1 007c88 h to 007c8f h data register 1 (8 bytes) dtr1 r/w xxxxxxxx b to xxxxxxxx b 007c90 h to 007c97 h data register 2 (8 bytes) dtr2 r/w xxxxxxxx b to xxxxxxxx b 007c98 h to 007c9f h data register 3 (8 bytes) dtr3 r/w xxxxxxxx b to xxxxxxxx b 007ca0 h to 007ca7 h data register 4 (8 bytes) dtr4 r/w xxxxxxxx b to xxxxxxxx b 007ca8 h to 007caf h data register 5 (8 bytes) dtr5 r/w xxxxxxxx b to xxxxxxxx b 007cb0 h to 007cb7 h data register 6 (8 bytes) dtr6 r/w xxxxxxxx b to xxxxxxxx b 007cb8 h to 007cbf h data register 7 (8 bytes) dtr7 r/w xxxxxxxx b to xxxxxxxx b 007cc0 h to 007cc7 h data register 8 (8 bytes) dtr8 r/w xxxxxxxx b to xxxxxxxx b 007cc8 h to 007ccf h data register 9 (8 bytes) dtr9 r/w xxxxxxxx b to xxxxxxxx b 007cd0 h to 007cd7 h data register 10 (8 bytes) dtr10 r/w xxxxxxxx b to xxxxxxxx b 007cd8 h to 007cdf h data register 11 (8 bytes) dtr11 r/w xxxxxxxx b to xxxxxxxx b 007ce0 h to 007ce7 h data register 12 (8 bytes) dtr12 r/w xxxxxxxx b to xxxxxxxx b 007ce8 h to 007cef h data register 13 (8 bytes) dtr13 r/w xxxxxxxx b to xxxxxxxx b 007cf0 h to 007cf7 h data register 14 (8 bytes) dtr14 r/w xxxxxxxx b to xxxxxxxx b 007cf8 h to 007cff h data register 15 (8 bytes) dtr15 r/w xxxxxxxx b to xxxxxxxx b
document number: 002-07872 rev. *a page 46 of 83 mb90350 series 14. interrupt factors, interrupt vectors, in terrupt control register y1 : usable y2 : usable, with ei 2 os stop function n : unusable interrupt cause ei 2 os corre- sponding dma ch number interrupt vector interrupt control register number address number address reset n ? #08 ffffdc h ?? int9 instruction n ? #09 ffffd8 h ?? exception n ? #10 ffffd4 h ?? reserved n ? #11 ffffd0 h icr00 0000b0 h reserved n ? #12 ffffcc h can 1 rx / input capture 6 y1 ? #13 ffffc8 h icr01 0000b1 h can 1 tx/ns / input capture 7 y1 ? #14 ffffc4 h i 2 c n ? #15 ffffc0 h icr02 0000b2 h reserved n ? #16 ffffbc h 16-bit reload timer 0 y1 0 #17 ffffb8 h icr03 0000b3 h 16-bit reload timer 1 y1 1 #18 ffffb4 h 16-bit reload timer 2 y1 2 #19 ffffb0 h icr04 0000b4 h 16-bit reload timer 3 y1 ? #20 ffffac h ppg 4/5 n ? #21 ffffa8 h icr05 0000b5 h ppg 6/7 n ? #22 ffffa4 h ppg 8/9/c/d n ? #23 ffffa0 h icr06 0000b6 h ppg a/b/e/f n ? #24 ffff9c h timebase timer n ? #25 ffff98 h icr07 0000b7 h external interrupt 8 to 11 y1 3 #26 ffff94 h watch timer n ? #27 ffff90 h icr08 0000b8 h external interrupt 12 to 15 y1 4 #28 ffff8c h a/d converter y1 5 #29 ffff88 h icr09 0000b9 h i/o timer 0 / i/o timer 1 n ? #30 ffff84 h input capture 4/5 y1 6 #31 ffff80 h icr10 0000ba h output compare 4/5 y1 7 #32 ffff7c h input capture 0/1 y1 8 #33 ffff78 h icr11 0000bb h output compare 6/7 y1 9 #34 ffff74 h reserved n 10 #35 ffff70 h icr12 0000bc h reserved n 11 #36 ffff6c h uart 3 rx y2 12 #37 ffff68 h icr13 0000bd h uart 3 tx y1 13 #38 ffff64 h uart 2 rx y2 14 #39 ffff60 h icr14 0000be h uart 2 tx y1 15 #40 ffff5c h flash memory n ? #41 ffff58 h icr15 0000bf h delayed interrupt n ? #42 ffff54 h
document number: 002-07872 rev. *a page 47 of 83 mb90350 series note s : the peripheral resources sharing the icr register have the same interrupt level. when two peripheral resources share the icr register, only one can use ei 2 osat a time. when either of the two peripheral resour ces sharing the icr register specifies ei 2 os, the other one cannot use interrupts.
document number: 002-07872 rev. *a page 48 of 83 mb90350 series 15. electrical characteristics 15.1 absolute maximum ratings (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss ? 6.0 v av cc v ss ? 0.3 v ss ? 6.0 v v cc ? av cc * 2 avrh v ss ? 0.3 v ss ? 6.0 v av cc avrh* 2 input voltage* 1 v i v ss ? 0.3 v ss ? 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss ? 6.0 v *3 maximum clamp current i clamp ? 4.0 ? 4.0 ma *5 total maximum clamp current ? |i clamp |? 40 ma*5 ?l? level maximum output current i ol ?15ma*4 ?l? level average output current i olav ?4ma*4 ?l? level maximum overall output current ? i ol ?100ma*4 ?l? level average overall output current ? i olav ?50ma*4 ?h? level maximum output current i oh ? ? 15 ma *4 ?h? level average output current i ohav ? ? 4ma*4 ?h? level maximum overall output current ? i oh ? ? 100 ma *4 ?h? level average overall output current ? i ohav ? ? 50 ma *4 power consumption p d ?240mw mb90f351(s), mb90f352(s) ? 105 c < t a ? 125 c, normal operation : maximum frequency 16 mhz ?320mw mb90f351(s), mb90f352(s) ? 40 c < t a ? 105 c, normal operation : maximum frequency 24 mhz ? 320 mw device other than above operating temperature t a ? 40 ? 105 c ? 40 ? 125 c *6 storage temperature t stg ? 55 ? 150 c
document number: 002-07872 rev. *a page 49 of 83 mb90350 series (continued) *1: this parameter is based on v ss ? av ss ? 0 v *2: set av cc and v cc to the same voltage. make sure that av cc does not exceed v cc and that the voltage at the analog inputs does not exceed av cc when the power is switched on. *3: v i and v o should not exceed v cc ? 0.3 v. v i should not exceed the specified ratings. however if the maxi mum current to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4: applicable to pins: p00 to p07, p10 to p17, p20 to p 25, p30 to p37, p40 to p45, p50 to p56, p60 to p67 *5: ? applicable to pins: p00 to p07, p10 to p17, p20 to p25, p30 to p37, p40 to p45, p50 to p56 (for evaluation device : p50 to p55) , p60 to p67 ? use within recommended operating conditions. ? use at dc voltage (current) ?the ? b signal should always be applied a limiting resistance placed between the ? b signal and the microcontroller. ? the value of the limiting resistan ce should be set so that when the ? b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the ? b input potential may pass through the protective diode and increase the potential at the v cc pin, and this may affect other devices. ? note that if a ? b signal is input when the microcontroller power supply is off (not fixed at 0 v) , the power supply is provided from the pins, so that incomplete operation may result. ? note that if the ? b input is applied during power-on, the power supply is provided from the pins and the resulting power supply voltage may not be sufficient to operate the power-on reset. ? care must be take n not to leave the ? b input pin open. ? sample recommended circuits: *6 : if used exceeding t a ? ? 105 c, be sure to contact sales for reliability limitations. warning: semiconductor devices can be permanently damaged by application of stress (v oltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. p-ch n-ch v cc r input/output equivalent circuits ? b input (0 v to 16 v) limiting resistance protective diode
document number: 002-07872 rev. *a page 50 of 83 mb90350 series 15.2 recommended operating conditions (v ss ? av ss ? 0 v) * : if used exceeding t a ? ? 105 c, be sure to contact sales for reliability limitations. warning: the recommended operating conditi ons are required in order to ensure th e normal operation of the semiconductor device. all of the device's electrical characteristics ar e warranted when the device is operated within these ranges. always use semiconductor devi ces within their recommended operating condition ranges. operation outside these ranges may adversely affe ct reliability and could result in device failure. no warranty is made with respect to uses, operating conditi ons, or combinations not re presented on the data sheet. users considering application outside the listed conditions are advised to contact thei r representatives beforehand. parameter symbol value unit remarks min typ max power supply voltage v cc , av cc 4.0 5.0 5.5 v under normal operation 3.5 5.0 5.5 v under normal operation, when not using the a/d converter and not flash programming. 4.5 5.0 5.5 v when external bus is used. 3.0 ? 5.5 v maintains ram data in stop mode smooth capacitor c s 0.1 ? 1.0 f use a ceramic capacitor or capacitor of better ac characteristics. bypass capacitor at the v cc pin should be greater th an this capacitor. operating temperature t a ? 40 ? ? 105 c mb90f352(s) f cp 24mhz ? 40 ? ? 125 c *, mb90f352(s) f cp 16mhz, devices with a-suffix c c s c pin connection diagram 24 16 ? 40 +105 +125 operation guaranteed range operation temperature t a ( c) internal clock f cp (mhz) mb90f351(s), mb90f352(s) device other than above
document number: 002-07872 rev. *a page 51 of 83 mb90350 series 15.3 dc characteristics (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symbol pin condition value unit remarks min typ max input h voltage (at v cc ? 5 v ? 10%) v ihs ? ? 0.8 v cc ?v cc ? 0.3 v pin inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v iha ? ? 0.8 v cc ?v cc ? 0.3 v pin inputs if automotive input levels are selected v iht ??2.0?v cc ? 0.3 v pin inputs if ttl input levels are selected v ihs ? ? 0.7 v cc ?v cc ? 0.3 v p12, p15, p50 inputs if cmos input levels are selected v ihi ? ? 0.7 v cc ?v cc ? 0.3 v p44, p45 inputs if cmos hysteresis input levels are selected v ihr ? ? 0.8 v cc ?v cc ? 0.3 v rst input pin (cmos hysteresis) v ihm ??v cc ? 0.3 ? v cc ? 0.3 v md input pin input l voltage (at v cc ? 5 v ? 10%) v ils ??v ss ? 0.3 ? 0.2 v cc v pin inputs if cmos hysteresis input levels are selected (except p12, p15, p44, p45, p50) v ila ??v ss ? 0.3 ? 0.5 v cc v pin inputs if automotive input levels are selected v ilt ??v ss ? 0.3 ? 0.8 v pin inputs if ttl input levels are selected v ils ??v ss ? 0.3 ? 0.3 v cc v p12, p15, p50 inputs if cmos input levels are selected v ili ??v ss ? 0.3 ? 0.3 v cc v p44, p45 inputs if cmos hysteresis input levels are selected v ilr ??v ss ? 0.3 ? 0.2 v cc v rst input pin (cmos hysteresis) v ilm ??v ss ? 0.3 ? v ss ? 0.3 v md input pin output h voltage v oh normal outputs v cc ? 4.5 v, i oh ? ? 4.0 ma v cc ? 0.5 ? ? v output h voltage v ohi i 2 c current outputs v cc ? 4.5 v, i oh ? ? 3.0 ma v cc ? 0.5 ? ? v
document number: 002-07872 rev. *a page 52 of 83 mb90350 series (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symbol pin condition value unit remarks min typ max output l voltage v ol normal outputs v cc ? 4.5 v, i ol ? 4.0 ma ??0.4v output l voltage v oli i 2 c current outputs v cc ? 4.5 v, i ol ? 3.0 ma ??0.4v input leak current i il ? v cc ? 5.5 v, v ss document number: 002-07872 rev. *a page 53 of 83 mb90350 series (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symbol pin condition value unit remarks min typ max power supply current i ccl v cc v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at sub clock operation t a = ? 25 ? c ? 100 200 a mb90f356a mb90f357a mb90356a mb90357a v cc = 5.0 v, internal cr oscillation/ 4 division, at sub clock operation t a = ? 25 ? c ? 100 200 a mb90f356as mb90f357as mb90356as mb90357as v cc = 5.0 v, internal frequency: 8 khz, during stopping clock monitor function, at sub clock operation t a = ? 25 ? c ? 120 240 a mb90f351ta mb90f352ta mb90f356ta mb90f357ta mb90351ta mb90352ta mb90356ta mb90357ta v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at sub clock operation t a = ? 25 ? c ? 150 300 a mb90f356ta mb90f357ta mb90356ta mb90357ta v cc = 5.0 v, internal cr oscillation/ 4 division, at sub clock operation t a = ? 25 ? c ? 150 300 a mb90f356tas mb90f357tas mb90356tas mb90357tas i ccls v cc = 5.0 v, internal frequency: 8 khz, during stopping clock monitor function, at sub sleep t a = ? 25 ? c ?2050 a mb90f351 mb90f352 mb90f351a mb90f352a mb90f356a mb90f357a mb90351a mb90352a mb90356a mb90357a
document number: 002-07872 rev. *a page 54 of 83 mb90350 series (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symbol pin condition value unit remarks min typ max power supply current i ccls v cc v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at sub sleep t a = ? 25 ? c ? 60 200 a mb90f356a mb90f357a mb90356a mb90357a v cc = 5.0 v, internal cr oscillation/ 4 division, at sub sleep t a = ? 25 ? c ? 60 200 a mb90f356as mb90f357as mb90356as mb90357as v cc = 5.0 v, internal frequency: 8 khz, during stopping clock monitor function, at sub sleep t a = ? 25 ? c ? 70 150 a mb90f351ta mb90f352ta mb90f356ta mb90f357ta mb90351ta mb90352ta mb90356ta mb90357ta v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at sub sleep t a = ? 25 ? c ? 110 300 a mb90f356ta mb90f357ta mb90356ta mb90357ta v cc = 5.0 v, internal cr oscillation/ 4 division, at sub sleep t a = ? 25 ? c ? 110 300 a mb90f356tas mb90f357tas mb90356tas mb90357tas i cct v cc = 5.0 v, internal frequency: 8 khz, during stopping clock monitor function, at watch mode t a = ? 25 ? c ?1035 a mb90f351 mb90f352 mb90f351a mb90f352a mb90f356a mb90f357a mb90351a mb90352a mb90356a mb90357a
document number: 002-07872 rev. *a page 55 of 83 mb90350 series (continued) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) parameter symbol pin condition value unit remarks min typ max power supply current i cct v cc v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at watch mode t a = ? 25 ? c ? 25 150 a mb90f356a mb90f357a mb90356a mb90357a v cc = 5.0 v, internal cr oscillation/ 4 division, at watch mode t a = ? 25 ? c ? 25 150 a mb90f356as mb90f357as mb90356as mb90357as v cc = 5.0 v, internal frequency: 8 khz, during stopping clock monitor function, at watch mode t a = ? 25 ? c ? 60 140 a mb90f351ta mb90f352ta mb90f356ta mb90f357ta mb90351ta mb90352ta mb90356ta mb90357ta v cc = 5.0 v, internal frequency: 8 khz, during operating clock monitor function, at watch mode t a = ? 25 ? c ? 80 250 a mb90f356ta mb90f357ta mb90356ta mb90357ta v cc = 5.0 v, internal cr oscillation/ 4 division, at watch mode t a = ? 25 ? c ? 80 250 a mb90f356tas mb90f357tas mb90356tas mb90357tas i cch v cc ? 5.0 v, at stop mode, t a ? ? 25 ? c ?725 a devices without ?t?-suffix ? 60 130 a devices with ?t?-suffix input capacity c in other than c, av cc , av ss , avrh, v cc , v ss , ??515pf
document number: 002-07872 rev. *a page 56 of 83 mb90350 series 15.4 ac characteristics 15.4.1 clock timing (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (continued) parameter symbol pin value unit remarks min typ max clock frequency f c x0, x1 3?16mhz 1/2 (at pll stop) when using an oscillation circuit 4?16mhz 1 multiplied pll when using an oscillation circuit 4?12mhz 2 multiplied pll when using an oscillation circuit 4?8mhz 3 multiplied pll when using an oscillation circuit 4?6mhz 4 multiplied pll when using an oscillation circuit ?? 4mhz 6 multiplied pll when using an oscillation circuit x0 3?24mhz 1/2 (at pll stop), when using an external clock 4?24mhz 1 multiplied pll when using an external clock 4?12mhz 2 multiplied pll when using an external clock 4?8mhz 3 multiplied pll when using an external clock 4?6mhz 4 multiplied pll when using an external clock ?? 4mhz 6 multiplied pll when using an external clock f cl x0a, x1a ? 32.768 100 khz clock cycle time t cyl x0, x1 62.5 ? 333 ns when using an oscillation circuit x0 41.67 ? 333 ns when using an external clock t cyll x0a, x1a 10 30.5 ? ? s input clock pulse width p wh , p wl x0 10 ? ? ns duty ratio is about 30% to 70%. p whl , p wll x0a 5 15.2 ? ? s input clock ri se and fall time t cr , t cf x0 ? ? 5 ns when using an external clock
document number: 002-07872 rev. *a page 57 of 83 mb90350 series (continued) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) parameter symbol pin value unit remarks min typ max internal operating clock frequency (machine clock) f cp ? 1.5 ? 24 mhz mb90f352/(s), mb90f351/(s) when using main clock (t a ? 105 c) 16 mb90f352/(s), mb90f351/(s) when using main clock (t a ? 125 c) 1.5 ? 24 mhz device other than above, when using main clock f cpl ? ? 8.192 50 khz when using sub clock internal operating clock cycle time (machine clock) t cp ? 41.67 ? 666 ns mb90f352/(s), mb90f351/(s) when using main clock (t a ? 105 c) 62.5 mb90f352/(s), mb90f351/(s) when using main clock (t a ? 125 c) 41.67 ? 666 ns device other than above, when using main clock t cpl ? 20 122.1 ? ? s when using sub clock x0 t cyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl x0a t cyll t cf t cr 0.8 v cc 0.2 v cc p whl p wll clock timing
document number: 002-07872 rev. *a page 58 of 83 mb90350 series pll guaranteed operation range guaranteed operation range of mb90350 series *1 : guaranteed 1 multiplied pll operation range is 4.0 mhz to 20 mhz. *2 : when using crystal oscillator or ceramic o scillator, the maximum clock frequency is 16 mhz. external clock frequency and internal operation clock frequency 5.5 3.5 4 1.5 24 4.5 8 20 guaranteed a/d converter operation range guaranteed pll operation range (cs2=0) guaranteed pll operation range (cs2=1) guaranteed operation range power supply voltage v cc (v) internal clock f cp (mhz) 20 16 12 8 4.0 1.5 34 8 24 12 20 1/2 (pll off) 16 guaranteed oscillation frequency range 4 multiplied (cs=11) 3 multiplied (cs=10) 2 multiplied (cs=01) 1 multiplied (cs=00) internal clock f cp (mhz) external clock f c (mhz) * 1 cs2(bit0 of psccr register) = 0 24 16 12 8 4.0 1.5 34 8 24 12 16 1/2 (pll off) guaranteed oscillation frequency range 6 multiplied (cs=10) 4 multiplied (cs=01) 2 multiplied (cs=00) internal clock f cp (mhz) external clock f c (mhz) * 2 cs2(bit0 of psccr register) = 1
document number: 002-07872 rev. *a page 59 of 83 mb90350 series 15.4.2 reset standby input (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) * : oscillation time of o scillator is the time that the amplitude reaches 90%. in the crystal oscillator, the oscillation ti me is between several ms to tens of ms. in far / ceramic oscillators, the oscillat ion time is between hundreds of s to several ms. with an external cl ock, the oscillation time is 0 ms. parameter symbol pin value unit remarks min max reset input time t rstl rst 500 ? ns under normal operation oscillation time of oscillator* ? 100 s ? s in stop mode, sub clock mode, sub sleep mode and watch mode 100 ? s in main timer mode and pll timer mode t rstl 0.2 v cc 0.2 v cc rst x0 90% of amplitude instruction execution oscillation stabilization waiting time oscillation time of oscillator internal operation clock internal reset 100 s 0.2 v cc rst t rstl 0.2 v cc under normal operation: in stop mode, sub clock mode, sub sleep mode, watch mode:
document number: 002-07872 rev. *a page 60 of 83 mb90350 series 15.4.3 power on reset (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) 15.4.4 clock output timing (t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, v ss ? 0.0 v, f cp 24 mhz) parameter symbol pin condition value unit remarks min max power on rise time t r v cc ? 0.05 30 ms power off time t off v cc 1 ? ms due to repetitive operation parameter symbol pin condition value unit remarks min max cycle time t cyc clk ? 62.5 ? ns f cp ? 16 mhz 41.67 ? ns f cp ? 24 mhz clk clk t chcl clk ? 20 ? ns f cp ? 16 mhz 13 ? ns f cp ? 24 mhz v cc v cc v ss 3 v t r t off 2.7 v 0.2 v 0.2 v 0.2 v holds ram data if you change the power supply voltage too rapidly, a power on reset may occur. we recommend that you start up smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. perform while not using the pll clock. however, if voltage drops are within 1 v/s, you can operate while using the pll clock. we recommend the slope for a rise of 50 mv/ms maximum. clk 2.4 v t cyc 2.4 v 0.8 v t chcl
document number: 002-07872 rev. *a page 61 of 83 mb90350 series 15.4.5 bus timing (read) (t a = ?40 ? c to +105 ? c, v cc = 5.0 v ? 10 %, v ss = 0.0 v, f cp 24 mhz) * : n: number of ready cycles parameter symbol pin condition value unit remarks min max ale pulse width t lhll ale ? t cp /2 ? 10 ? ns valid address ale ? time t avll ale, a21 to a16, ad15 to ad00 t cp /2 ? 20 ? ns ale ? address valid time t llax ale, ad15 to ad00 t cp /2 ? 15 ? ns valid address rd ? time t avrl a21 toa16, ad15 to ad00, rd t cp ? 15 ? ns valid address valid data input t avdv a21 to a16, ad15 to ad00 ?5 t cp /2 ? 60 ns rd pulse width t rlrh rd (n*+3/2) t cp ? 20 ? ns rd ? valid data input t rldv rd , ad15 to ad00 ?(n*+3/2) t cp ? 50 ns rd ? data hold time t rhdx rd , ad15 to ad00 0?ns rd ? ale ? time t rhlh rd , ale t cp /2 ? 15 ? ns rd ? address valid time t rhax rd , a21 to a16 t cp /2 ? 10 ? ns valid address clk ? time t avch a21 to a16, ad15 to ad00, clk t cp /2 ? 16 ? ns rd ? clk ? time t rlch rd , clk t cp /2 ? 15 ? ns ale ? rd ? time t llrl ale, rd t cp /2 ? 15 ? ns
document number: 002-07872 rev. *a page 62 of 83 mb90350 series a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t rhax ad15 to ad00 0.8 v 2.4 v 2.4 v 0.8 v address v il v ih v ih v il read data t rhdx t rldv t avdv clk t avch 2.4 v t rlch 2.4 v ale 2.4 v t lhll 2.4 v t rhlh 0.8 v t llax 2.4 v t avll rd t llrl t rlrh 0.8 v 2.4 v t avrl for 1 cycle of auto-ready
document number: 002-07872 rev. *a page 63 of 83 mb90350 series 15.4.6 bus timing (write) (t a = ?40 ? c to +105 ? c, v cc = 5.0 v ? 10 %, v ss = 0.0 v, f cp 24 mhz) * : n: number of ready cycles parameter symbol pin condition value unit remarks min max valid address wr ? time t avwl a21 to a16, ad15 to ad00, wr ? t cp ? 15 ? ns wr pulse width t wlwh wr (n*+3/2)t cp ? 20 ? ns valid data output wr ? time t dvwh ad15 to ad00, wr (n*+3/2)t cp ? 20 ? ns wr ? data hold time t whdx ad15 to ad00, wr 15 ? ns wr ? address valid time t whax a21 to a16, wr t cp /2 ? 10 ? ns wr ? ale ? time t whlh wr , ale t cp /2 ? 15 ? ns wr ? clk ? time t wlch wr , clk t cp /2 ? 15 ? ns clk t wlch 2.4 v ale t whlh 2.4 v wr (wrl , wrh ) t wlwh 0.8 v 2.4 v t avwl a21 to a16 0.8 v 2.4 v 2.4 v 0.8 v t whax ad15 to ad00 2.4 v 0.8 v address 0.8 v 2.4 v write data t dvwh 0.8 v 2.4 v t whdx for 1 cycle of auto-ready
document number: 002-07872 rev. *a page 64 of 83 mb90350 series 15.4.7 ready input timing (t a = ?40 ? c to +105 ? c, v cc = 5.0 v ? 10 %, v ss = 0.0 v, f cp 24 mhz) note : if the rdy set-up time is insufficient, use the auto-ready function. parameter symbol pin condition value units remarks min max rdy set-up time t ryhs rdy ? 45 ? ns f cp ? 16 mhz 32 ? ns f cp ? 24 mhz rdy hold time t ryhh rdy 0 ? ns clk 2.4 v ale rd /wr rdy (when wait is not used.) v ih v ih t ryhh rdy (when wait is used.) t ryhs v il
document number: 002-07872 rev. *a page 65 of 83 mb90350 series 15.4.8 hold timing (t a = ?40 ? c to +105 ? c, v cc = 5.0 v ? 10 %, v ss = 0.0 v, f cp 24 mhz) note : there is more than 1 machine cycle fr om when hrq pin reads in until the hak is changed. parameter symbol pin condition value units remarks min max pin floating hak ? time t xhal hak ? 30 t cp ns hak ? time pin valid time t hahv hak t cp 2 t cp ns hak each pin hi-z t hahv t xhal 2.4 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v
document number: 002-07872 rev. *a page 66 of 83 mb90350 series 15.4.9 uart 2/3 (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) * : refer to ? (1) clo ck timing? rating for t cp (internal operating clock cycle time). note s : ac characteristic in clk synchronized mode. c l is load capacity value of pins when testing. parameter symbol pin condition value unit remarks min max serial clock cycle time t scyc sck2, sck3 internal shift clock mode output pins are c l ? 80 pf ? 1 ttl 8 t cp *? ns sck sot delay time t slov sck2, sck3, sot2, sot3 ? 80 ? 80 ns valid sin sck t ivsh sck2, sck3, sin2, sin3 100 ? ns sck valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns serial clock ?h? pulse width t shsl sck2, sck3 external shift clock mode output pins are c l ? 80 pf ? 1 ttl 4 t cp ?ns serial clock ?l? pulse width t slsh sck2, sck3 4 t cp ?ns sck sot delay time t slov sck2, sck3, sot2, sot3 ? 150 ns valid sin sck t ivsh sck2, sck3, sin2, sin3 60 ? ns sck valid sin hold time t shix sck2, sck3, sin2, sin3 60 ? ns internal shift clock mode sck 2.4 v t scyc 0.8 v sot 0.8 v 2.4 v 0.8 v t slov sin v il v ih t ivsh v il v ih t shix
document number: 002-07872 rev. *a page 67 of 83 mb90350 series 15.4.10 trigger input timing (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) parameter symbol pin condition value unit remarks min max input pulse width t trgh t trgl int8 to int15, int9r to int11r, adtg ?5 t cp ?ns external shift clock mode sck v ih t slsh v il sot 0.8 v 2.4 v t slov sin v il v ih t ivsh v il v ih t shix v ih v il t shsl v il v ih t trgh v il v ih t trgl int8 to int15, int9r to int11r, adtg
document number: 002-07872 rev. *a page 68 of 83 mb90350 series 15.4.11 timer related resource input timing (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) 15.4.12 timer related resource output timing (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) parameter symbol pin condition value unit remarks min max input pulse width t tiwh tin1, tin3, in0, in1, in4 to in7 ?4 t cp ?ns t tiwl parameter symbol pin condition value unit remarks min max clk ? t out change time t to tot1, tot3, ppg4, ppg6, ppg8 to ppgf ?30?ns v il v ih t tiwh v il v ih t tiwl tin1, tin3, in0, in1, in4 to in7 clk 2.4 v 0.8 v 2.4 v t to tot1, tot3, ppg4, ppg6 ppg8 to ppgf
document number: 002-07872 rev. *a page 69 of 83 mb90350 series 15.4.13 i 2 c timing (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, v cc ? av cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, v cc ? av cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) (device other than above: t a ? ? 40 c to ? 125 c, v cc ? av cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) *1 : r,c : pull-up resistor and load capacitor of the scl and sda lines. *2 : the maximum t hddat has only to be met if the device does not stretch the ?l? width (t low ) of the scl signal. *3 : a fast-mode i 2 c -bus device can be used in a standard-mode i 2 c-bus system, but the requirement t sudat 250 ns must then be met. *4 : for use at over 100 khz, set the machine clock to at least 6 mhz. *5 : refer to ?note of sda, scl set-up time?. parameter symbol condition standard-mode fast-mode* 4 unit min max min max scl clock frequency f scl r ? 1.7 k ? , c ? 50 pf* 1 0 100 0 400 khz hold time for (repeated) start condition sda scl t hdsta 4.0 ? 0.6 ? s ?l? width of the scl clock t low 4.7 ? 1.3 ? s ?h? width of the scl clock t high 4.0 ? 0.6 ? s set-up time for a repeated start condition scl sda t susta 4.7 ? 0.6 ? s data hold time scl sda t hddat 0 3.45* 2 00.9* 3 s data set-up time sda scl t sudat 250* 5 ?100* 5 ?ns set-up time for stop condition scl sda t susto 4.0 ? 0.6 ? s bus free time between stop condition and start condition t bus 4.7 ? 1.3 ? s sda scl 6 tcp note of sda, scl set-up time input data set-up time
document number: 002-07872 rev. *a page 70 of 83 mb90350 series note : the rating of the input data set-up time in the device c onnected to the bus cannot be satisfied depending on the load capaci tance or pull-up resistor. be sure to adjust the pull-up resistor of sda and scl if the rating of the input data set-up time cannot be satisfied. sda scl t buf t low f scl t hddat t high t sudat t hdsta t susta t hdsta t susto timing definition
document number: 002-07872 rev. *a page 71 of 83 mb90350 series 15.5 a/d converter (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 105 c, 3.0 v avrh, v cc ? av cc ? 5.0 v ? 10%, f cp 24 mhz, v ss ? av ss ? 0 v) (mb90f352(s)/mb90f351(s): t a ? ? 40 c to ? 125 c, 3.0 v avrh, v cc ? av cc ? 5.0 v ? 10%, f cp 16 mhz, v ss ? av ss ? 0 v) ( device other than above: t a ? ? 40 c to ? 125 c , 3.0 v avrh, v cc ? av cc ? 5.0 v ? 10% , f cp 24 mhz, v ss ? av ss ? 0 v ) * : if a/d converter is not operating, a cu rrent when cpu is stopped is applicable (v cc ? av cc ? avrh ? 5.0 v) . parameter symbol pin value unit remarks min typ max resolution ? ? ? ? 10 bit total error ? ? ? ? ? 3.0 lsb nonlinearity error ? ? ? ? ? 2.5 lsb differential nonlinearity error ?? ? ? ? 1.9 lsb zero reading voltage v ot an0 to an14 av ss ? 1.5 lsb av ss ? 0.5 lsb av ss ? 2.5 lsb v full scale reading voltage v fst an0 to an14 avrh ? 3.5 lsb avrh ? 1.5 lsb avrh ? 0.5 lsb v compare time ? ? 1.0 ? 16,500 ? s 4.5 v av cc 5.5 v 2.0 4.0 v av cc < 4.5 v sampling time ? ? 0.5 ? ? s 4.5 v av cc 5.5 v 1.2 4.0 v av cc < 4.5 v analog port input current i ain an0 to an14 ? 0.3 ? +0.3 ? a analog input voltage range v ain an0 to an14 av ss ?avrhv reference voltage range ?avrhav ss ? 2.7 ? av cc v power supply current i a av cc ?3.57.5ma i ah av cc ?? 5 a* reference voltage supply current i r avrh ? 600 900 a i rh avrh ? ? 5 a* offset between input channels ? an0 to an14 ? ? 4 lsb
document number: 002-07872 rev. *a page 72 of 83 mb90350 series notes on a/d converter section about the external impedance of t he analog input and its sampling time a/d converter with sample and hold circuit. if the external im pedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore to sati sfy the a/d conversion precision standard , consider the relationship between the ext ernal impedance and minimum sampling time and either adjust the regi ster value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. also if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. analog input equivalence circuit on at sampling note : the value is reference value. r c c r analog input comparator mb90f352(s), mb90f351a(s), mb90f352a(s), mb90f351ta(s), mb90f352ta(s), mb90f356a(s), mb90f357a(s), mb90f356ta(s), mb90f357ta(s), 4.5 v av cc 5.5 v 2.0 k (max) 16.0 pf (max) 4.0 v av cc 4.5 v 8.2 k (max) 16.0 pf (max) c r mb90v340a-101/102/103/104, mb90351a(s), mb90352a(s), mb90351ta(s), mb90352ta(s), mb90356a(s), mb90357a(s), mb90356ta(s), mb90357ta(s), 4.5 v av cc 5.5 v 2.0 k (max) 14.4 pf (max) 4.0 v av cc 4.5 v 8.2 k (max) 14.4 pf (max)
document number: 002-07872 rev. *a page 73 of 83 mb90350 series flash memory device mask rom device about the error values of relative errors grow larger, as |avrh ? av ss | becomes smaller. relation between external impedance and minimum sampling time 4.5 v av cc 5.5 v [external impedance = 0 k to 100 k ] minimum sampling time [ s] external impedance [k ] 0 5 101520253035 10 20 30 40 50 60 70 80 90 100 4.0 v av cc 4.5 v 4.5 v av cc 5.5 v [external impedance = 0 k to 20 k ] minimum sampling time [ s] external impedance [k ] 0 12345678 2 4 6 8 10 12 14 16 18 20 4.0 v av cc 4.5 v (mb90f352(s), mb90f351a(s), mb90f352a(s), mb90f351ta(s), mb90f352ta(s), mb90f356a(s), mb90f357a(s), mb90f356ta(s), mb90f357ta(s)) 00 relation between external impedance and minimum sampling time 4.5 v av cc 5.5 v [external impedance = 0 k to 100 k ] minimum sampling time [ s] external impedance [k ] 0 5 101520253035 10 20 30 40 50 60 70 80 90 100 4.0 v av cc 4.5 v 4.5 v av cc 5.5 v [external impedance = 0 k to 20k ] minimum sampling time [ s] external impedance [k ] 0 12345678 2 4 6 8 10 12 14 16 18 20 4.0 v av cc 4.5 v (mb90v340a-101/102/103/104, mb90351a(s), mb90352a(s), mb90351ta(s), mb90352ta(s), mb90356a(s), mb90357a(s), mb90356ta(s), mb90357ta(s)) 00
document number: 002-07872 rev. *a page 74 of 83 mb90350 series 15.6 definition of a/d converter terms (continued) resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line ( ?00 0000 0000? ?00 0000 0001? ) and full-scale transition line ( ?11 1111 1110? ?11 1111 1111? ) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required fo r changing output code by 1 lsb, from an ideal value. to t a l e r r o r : difference between an actual value and a theoretical value. a total error includes zero transition error, full-scale transition error, and linear error. 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh v nt 1.5 lsb 0.5 lsb {1 lsb (n ? 1) + 0.5 lsb} actual conversion characteristics (actual measurement value) actual conversion characteristics ideal characteristics digital output analog input total error total error of digital output ?n? ? v nt ? {1 lsb (n ? 1) ? 0.5 lsb} 1 lsb [lsb] 1 lsb ? (ideal value) avrh ? av ss 1024 [v] v ot (ideal value) ? av ss ? 0.5 lsb [v] v fst (ideal value) ? avrh ? 1.5 lsb [v] v nt : a voltage at which digita l output transits from (n ? 1) to n. n : a/d converter digital output value
document number: 002-07872 rev. *a page 75 of 83 mb90350 series (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avrh av ss avrh n + 1 n n ? 1 n ? 2 v ot ( actual measurement value ) {1 lsb (n ? 1) + v ot } actual conversion characteristics v fst (actual measurement value) v nt (actual measurement value) actual conversion characteristics ideal characteristics actual conversion characteristics actual conversion characteristics ideal characteristics digital output digital output analog input analog input v nt (actual measurement value) v (n + 1) t (actual measurement value) non linearity error diffe rential linearity error non linearity error of digital output n ? v nt ? {1 lsb (n ? 1) ? v ot } 1 lsb [lsb] differential linearity erro r of digital output n ? v ( n+1 ) t ? v nt 1 lsb ? 1 lsb [lsb] v fst ? v ot 1022 [v] 1 lsb ? n : a/d converter di gital output value v ot : voltage at which digital output transits from ?000 h ? to ?001 h .? v fst : voltage at which digital output transits from ?3fe h ? to ?3ff h .?
document number: 002-07872 rev. *a page 76 of 83 mb90350 series 15.7 flash memory program/erase characteristics flash memory * : this value comes from the technology qualification. (using arrhenius equation to translate high temp erature measurements into normalized value at ? 85 c) dual operation flash memory * : this value comes from the technology qualification. (using arrhenius equation to translate high temp erature measurements into normalized value at ? 85 c) parameter conditions value unit remarks min typ max sector erase time t a ? ? 25 c v cc ? 5.0 v ?115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16-bit width) programming time ?163,600 s except for the overhead time of the system level program/erase cycle ? 10,000 ? ? cycle flash memory data retention time average t a ? ? 85 c 20 ? ? year * parameter conditions value unit remarks min typ max sector erase time (4 kbytes sector) t a ? ? 25 c v cc ? 5.0 v ?0.20.5s excludes programming prior to erasure sector erase time (16 kbytes sector) ?0.57.5s excludes programming prior to erasure chip erase time ? 4.6 ? s excludes programming prior to erasure word (16-bit width) programming time ? 64 3,600 s except for the overhead time of the system level program/erase cycle ? 10,000 ? ? cycle flash memory data retention time average t a ? ? 85 c 20 ? ? year *
document number: 002-07872 rev. *a page 77 of 83 mb90350 series 16. ordering information (continued) part number package remarks mb90f351pmc 64-pin plastic lqfp fpt-64p-m23 12mm, 0.65mm pitch flash memory products (64 kbytes) mb90f351spmc mb90f352pmc flash memory products (128 kbytes) mb90f352spmc mb90f351apmc 64-pin plastic lqfp fpt-64p-m23 12mm, 0.65mm pitch dual operation flash memory products (64 kbytes) mb90f351aspmc mb90f351tapmc mb90f351taspmc mb90f356apmc mb90f356aspmc mb90f356tapmc mb90f356taspmc mb90f352apmc 64-pin plastic lqfp fpt-64p-m23 12mm, 0.65mm pitch dual operation flash memory products (128 kbytes) mb90f352aspmc mb90f352tapmc mb90f352taspmc mb90f357apmc mb90f357aspmc mb90f357tapmc mb90f357taspmc MB90351APMC 64-pin plastic lqfp fpt-64p-m23 12mm, 0.65mm pitch mask rom products (64 kbytes) mb90351aspmc mb90351tapmc mb90351taspmc mb90356apmc mb90356aspmc mb90356tapmc mb90356taspmc mb90352apmc 64-pin plastic lqfp fpt-64p-m23 12mm, 0.65mm pitch mask rom products (128 kbytes) mb90352aspmc mb90352tapmc mb90352taspmc mb90357apmc mb90357aspmc mb90357tapmc mb90357taspmc
document number: 002-07872 rev. *a page 78 of 83 mb90350 series (continued) * : these devices are under development. part number package remarks mb90f351apmc1 64-pin plastic lqfp fpt-64p-m24 10 mm , 0.50 mm pitch dual operation flash memory products* (64 kbytes) mb90f351aspmc1 mb90f351tapmc1 mb90f351taspmc1 mb90f356apmc1 mb90f356aspmc1 mb90f356tapmc1 mb90f356taspmc1 mb90f352apmc1 64-pin plastic lqfp fpt-64p-m24 10 mm , 0.50 mm pitch dual operation flash memory products* (128 kbytes) mb90f352aspmc1 mb90f352tapmc1 mb90f352taspmc1 mb90f357apmc1 mb90f357aspmc1 mb90f357tapmc1 mb90f357taspmc1 MB90351APMC1 64-pin plastic lqfp fpt-64p-m24 10 mm , 0.50 mm pitch mask rom products* (64 kbytes) mb90351aspmc1 mb90351tapmc1 mb90351taspmc1 mb90356apmc1 mb90356aspmc1 mb90356tapmc1 mb90356taspmc1 mb90352apmc1 64-pin plastic lqfp fpt-64p-m24 10 mm , 0.50 mm pitch mask rom products* (128 kbytes) mb90352aspmc1 mb90352tapmc1 mb90352taspmc1 mb90357apmc1 mb90357aspmc1 mb90357tapmc1 mb90357taspmc1 mb90v340a-101 299-pin ceramic pga pga-299c-a01 device for evaluation mb90v340a-102 mb90v340a-103 mb90v340a-104
document number: 002-07872 rev. *a page 79 of 83 mb90350 series 17. package dimensions (continued) 64-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 12.0 12.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm max weight 0.47 g code (reference) p-lqfp64-12 12-0.65 64-pin pl as tic lqfp (fpt-64p-m2 3 ) (fpt-64p-m2 3 ) c 200 3 -2010 fujit s u s emiconductor limited f640 3 4 s -c-1-4 0.65(.026) 0.10(.004) 1 16 17 3 2 49 64 33 4 8 * 12.00 0.10(.472 .004) s q 14.00 0.20(.551 .00 8 ) s q index 0. 3 2 0.05 (.01 3 .002) m 0.1 3 (.005) 0.145 0.055 (.006 .002) "a" .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 0~ 8 0.25(.010) (mo u nting height) 0.50 0.20 (.020 .00 8 ) 0.60 0.15 (.024 .006) 0.10 0.10 (.004 .004) det a il s of "a" p a rt ( s t a nd off) dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
document number: 002-07872 rev. *a page 80 of 83 mb90350 series (continued) 64-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 10.0 mm 10.0 mm le a d s h a pe g u llwing s e a ling method pl as tic mold code (reference) p-lfqfp64-10 10-0.50 64-pin pl as tic lqfp (fpt-64p-m24) (fpt-64p-m24) lead no. "b" 0.0 8 (.00 3 ) (.006 .002) 0.145 0.055 0.0 8 (.00 3 ) m (.00 8 .002) 0.20 0.05 0.50(.020) 12.00 0.20(.472 .00 8 ) s q * 10.00 0.10(. 3 94 .004) s q index 49 64 33 4 8 17 3 2 16 1 2006-2010 fujit s u s emiconductor limited f640 3 6 s -1c(d)-1- 3 c "a" nom. 11.00(.4 33 ) 0.15(.006) max max 0.40(.016) det a il s of "a" p a rt ( s t a nd off) det a il s of "b" p a rt (.004 .004) 0.10 0.10 (.024 .006) 0.60 0.15 (.020 .00 8 ) 0.50 0.20 (mo u nting height) 0.25(.010) .059 ? .004 +.00 8 ? 0.10 +0.20 1.50 0~ 8 dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder.
document number: 002-07872 rev. *a page 81 of 83 mb90350 series 18. major changes spansion publication number: ds07-13737-6e note: please see ?document history? about later revised information. page section change results ?? deleted the following package. fpt-64p-m09 13 5. packages and product correspon- dence changed the correspondence package for mb90f351, mb90f351s, mb90f352 and mb90f352s. fpt-64p-m09 fpt-64p-m23 26 9. handling devices corrected a typo in number 10. ?is used? ?is not used? 64 15. electrical characteristics 15.4. ac characteristics 15.4.4. clock output timing changed the minimum value of cycle time. 41.76 41.67 75 15.5. a/d converter changed the notation of ?zero reading voltage? and ?full scale reading voltage?. 81 16. ordering information changed the part numbers and the package. mb90f351pfm mb90f351pmc mb90f351spfm mb90f351spmc mb90f352pfm mb90f352pmc mb90f352spfm mb90f352spmc fpt-64p-m09 fpt-64p-m23
document number: 002-07872 rev. *a page 82 of 83 mb90350 series document history document title: mb90350 series f 2 mc-16lx 16-bit microcontroller document number: 002-07872 revision ecn orig. of change submission date description of change ** ? akfu 09/29/2003 migrated to cypress and assigned document number 002-07872. no change to document contents or format. *a 5755299 akfu 05/31/2017 updated to cypress format.
document number: 002-07872 rev. *a revised may 31, 2017 page 83 of 83 ? cypress semiconductor corporation, 2003-2017. this document is the property of cypress semiconductor corporation and its subs idiaries, including spansion llc (?cypress?). this document, including any software or firmware included or referenced in this document (?software?), is owned by cypress under the intellec tual property laws and treaties of the united states and other countries worldwide. cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragr aph, grant any license under its patents, copyrights, trademarks, or other intellectual property rights. if the software is not accompanied by a license agreement and you do not otherwise have a written agreement with cypress governing the use of the software, then cypress hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the software (a) for software provided in source code form, to modify and reproduce the software solely for use with cypress hard ware products, only internally within your organization, and (b) to distribute the software in binary code form externally to end users (either directly or indirectly through resellers and distributors), solely for use on cypress hardware product units, and (2) u nder those claims of cypress's patents that are infringed by the software (as provided by cypress, unmodified) to make, use, distribute, and import the software solely for use with cypress hardware product s. any other use, reproduction, modification, translation, or compilation of the software is prohibited. to the extent permitted by applicable law, cypress makes no warranty of any kind, express or implied, with regard to this docum ent or any software or accompanying hardware, including, but not limited to, the im plied warranties of merchantability and fitness for a particular purpose. to the extent permitted by applicable law, cypress reserves the right to make changes to this document without further notice. cypress does n ot assume any liability arising out of the application or use of any product or circuit described in this document. any information pr ovided in this document, includ ing any sample design informati on or programming code, is provided only for reference purposes. it is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any appli cation made of this information and any resulting product. cypress products are not designed, intended, or authorized fo r use as critical components in systems de signed or intended for the operation of w eapons, weapons systems, nuclear in stallations, life-support devices or systems, other medical devices or systems (inc luding resuscitation equipment and surgical implants), pollution control or hazar dous substances management, or other uses where the failure of the device or system could cause personal injury , death, or property damage (?unintended uses?). a critical component is any compon ent of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affe ct its safety or effectiveness. cypress is not liable, in whol e or in part, and you shall and hereby do release cypress from any claim, damage, or other liability arising from or related to all unintended uses of cypress products. you shall indemnify and hold cyp ress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal inju ry or death, arising from or related to any unintended uses of cypress products. cypress, the cypress logo, spansion, the spansion logo, and combinations thereof, wiced, psoc, capsense, ez-usb, f-ram, and tra veo are trademarks or registered trademarks of cypress in the united states and other countries. for a more complete list of cypress trademarks, visit cypress.com. other names and brand s may be claimed as property of their respective owners. mb90350 series sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution cent ers, manufacturer?s representativ es, and distributors. to find t he office closest to you, visit us at cypress locations . products arm ? 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