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rm48l952 spns177d ? september 2011 ? revised june 2015 rm48l952 16- and 32-bit risc flash microcontroller 1 device overview 1.1 features 1 ? high-performance microcontroller for safety- ? multiple communication interfaces critical applications ? 10/100 mbps ethernet mac (emac) ? dual cpus running in lockstep ? ieee 802.3 compliant (3.3-v i/o only) ? ecc on flash and ram interfaces ? supports mii , rmii, and mdio ? built-in self-test (bist) for cpu and on-chip ? usb rams ? 2-port usb host controller ? error signaling module with error pin ? one full-speed usb device port ? voltage and clock monitoring ? three can controllers (dcans) ? arm ? cortex ? -r4f 32-bit risc cpu ? 64 mailboxes, each with parity protection ? efficient 1.66 dmips/mhz with 8-stage pipeline ? compliant to can protocol version 2.0b ? fpu with single- and double-precision ? standard serial communication interface (sci) ? 12-region memory protection unit (mpu) ? local interconnect network (lin) interface ? open architecture with third-party support controller ? operating conditions ? compliant to lin protocol version 2.1 ? system clock up to 220 mhz ? can be configured as a second sci ? core supply voltage (vcc): 1.2 v nominal ? inter-integrated circuit (i 2 c) ? i/o supply voltage (vccio): 3.3 v nominal ? three multibuffered serial peripheral interfaces ? adc supply voltage (v ccad ): 3.0 to 5.25 v (mibspis) ? integrated memory ? 128 words with parity protection each ? 3mb of program flash with ecc ? two standard serial peripheral interfaces (spis) ? 256kb of ram with ecc ? two next generation high-end timer (n2het) ? 64kb of flash with ecc for emulated modules eeprom ? n2het1: 32 programmable channels ? 16-bit external memory interface ? n2het2: 18 programmable channels ? common platform architecture ? 160-word instruction ram each with parity ? consistent memory map across family protection ? real-time interrupt (rti) timer os timer ? each n2het includes hardware angle ? 96-channel vectored interrupt module (vim) generator ? 2-channel cyclic redundancy checker (crc) ? dedicated high-end transfer unit (htu) with ? direct memory access (dma) controller mpu for each n2het ? 16 channels and 32 peripheral requests ? two 12-bit multibuffered adc modules ? parity protection for control packet ram ? adc1: 24 channels ? dma accesses protected by dedicated mpu ? adc2: 16 channels shared with adc1 ? frequency-modulated phase-locked loop ? 64 result buffers with parity protection each (fmpll) with built-in slip detector ? general-purpose input/output (gpio) pins ? separate nonmodulating pll capable of generating interrupts ? trace and calibration capabilities ? 16 pins on the zwt package ? embedded trace macrocell (etm-r4) ? 10 pins on the pge package ? data modification module (dmm) ? ieee 1149.1 jtag, boundary scan and arm ? ram trace port (rtp) coresight ? components ? parameter overlay module (pom) ? jtag security module ? package s ? 144-pin quad flatpack (pge) [green] ? 337-ball grid array (zwt) [green] 1 an important notice at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. production data. productfolder sample &buy technical documents tools & software support &community
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 1.2 applications ? industrial safety applications ? medical applications ? industrial automation ? ventilators ? safe programmable logic controllers (plcs) ? defibrillators ? power generation and distribution ? infusion and insulin pumps ? turbines and windmills ? radiation therapy ? elevators and escalators ? robotic surgery 2 device overview copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 1.3 description the rm48l952 device is a high-performance microcontroller family for safety systems. the safety architecture includes dual cpus in lockstep, cpu and memory bist logic, ecc on both the flash and the data sram, parity on peripheral memories, and loopback capability on peripheral i/os. the rm48l952 device integrates the arm cortex-r4f floating-point cpu. the cpu offers an efficient 1.66 dmips/mhz, and has configurations that can run up to 220 mhz, providing up to 365 dmips. the device supports the little-endian [le] format. the rm48l952 device has 3mb of integrated flash and 256kb of data ram. both the flash and ram have single-bit error correction and double-bit error detection. the flash memory on this device is a nonvolatile, electrically erasable, and programmable memory implemented with a 64-bit-wide data bus interface. the flash operates on a 3.3-v supply input (same level as i/o supply) for all read, program, and erase operations. when in pipeline mode, the flash operates with a system clock frequency of up to 220 mhz. the sram supports single-cycle read and write accesses in byte, halfword, word, and double-word modes. the rm48l952 device features peripherals for real-time control-based applications, including two next generation high-end timer (n2het) timing coprocessors and two 12-bit analog-to-digital converters (adcs) supporting up to 24 inputs. the n2het is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. the timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached i/o port. the n2het can be used for pulse-width-modulated outputs, capture or compare inputs, or gpio. the n2het is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. a high-end timer transfer unit (htu) can perform dma-type transactions to transfer n2het data to or from main memory. a memory protection unit (mpu) is built into the htu. the device has two 12-bit-resolution mibadcs with 24 channels and 64 words of parity-protected buffer ram each. the mibadc channels can be converted individually or can be grouped by software for sequential conversion sequences. sixteen channels are shared between the two mibadcs. there are three separate groupings. each sequence can be converted once when triggered or configured for continuous conversion mode. the mibadc has a 10-bit mode for use when compatibility with older devices or faster conversion time is desired. the device has multiple communication interfaces: three mibspis, two spis, one lin, one sci, three dcans, one i2c module , one ethernet, and one usb module. the spis provide a convenient method of serial high-speed communication between similar shift-register type devices. the lin supports the local interconnect standard 2.0 and can be used as a uart in full-duplex mode using the standard non- return-to-zero (nrz) format. the dcan supports the can 2.0 (a and b) protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 mbps. the dcan is ideal for systems operating in noisy and harsh environments (for example, automotive vehicle networking and industrial fieldbus) that require reliable serial communication or multiplexed wiring. the ethernet module supports mii, rmii, and mdio interfaces. the usb module includes a 2-port usb host controller. it is revision 2.0-compatible, based on the ohci specification for usb, release 1.0. the usb module also includes a usb device controller compatible with the usb specification revision 2.0 and usb specification revision 1.1. the i2c module is a multimaster communication module providing an interface between the microcontroller and an i 2 c-compatible device through the i 2 c serial bus. the i 2 c supports speeds of 100 and 400 kbps. copyright ? 2011 ? 2015, texas instruments incorporated device overview 3 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com the frequency-modulated phase-locked loop (fmpll) clock module is used to multiply the external frequency reference to a higher frequency for internal use. there are two fmpll modules on this device. these modules, when enabled, provide two of the seven possible clock source inputs to the global clock module (gcm). the gcm manages the mapping between the available clock sources and the device clock domains. the device also has an external clock prescaler (ecp) module that when enabled, outputs a continuous external clock on the eclk pin (or ball). the eclk frequency is a user-programmable ratio of the peripheral interface clock (vclk) frequency. this low-frequency output can be monitored externally as an indicator of the device operating frequency. the dma controller has 16 channels, 32 peripheral requests, and parity protection on its memory. an mpu is built into the dma to limit the dma to prescribed areas of memory and to protect the rest of the memory system from any malfunction of the dma. the error signaling module (esm) monitors all device errors and determines whether an interrupt is generated or the external error pin is toggled when a fault is detected. the error pin can be monitored externally as an indicator of a fault condition in the microcontroller. the external memory interface (emif) provides off-chip expansion capability with the ability to interface to synchronous dram (sdram) devices, asynchronous memories, peripherals, or fpga devices. several interfaces are implemented to enhance the debugging capabilities of application code. in addition to the built-in arm cortex-r4f coresight debug features, an external trace macrocell (etm) provides instruction and data trace of program execution. for instrumentation purposes, a ram trace port (rtp) module is implemented to support high-speed tracing of ram and peripheral accesses by the cpu or any other master. a data modification module (dmm) gives the ability to write external data into the device memory. both the rtp and dmm have no or only minimum impact on the program execution time of the application code. a parameter overlay module (pom) can reroute flash accesses to internal memory or to the emif. this rerouting allows the dynamic calibration against production code of parameters and tables without rebuilding the code to explicitly access ram or halting the processor to reprogram the data flash. with integrated safety features and a wide choice of communication and control peripherals, the rm48l952 device is an ideal solution for high-performance real-time control applications with safety- critical requirements. device information (1) part number package body size rm48l952zwt nfbga (337) 16.0 mm 16.0 mm rm48l952pge lqfp (144) 20.0 mm 20.0 mm (1) for more information, see section 9 , mechanical packaging and orderable information . 4 device overview copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 1.4 functional block diagram figure 1-1. functional block diagram copyright ? 2011 ? 2015, texas instruments incorporated device overview 5 submit documentation feedback dma pom dmm htu1 htu2 emac switched central resource main cross bar: arbitration and prioritization control crc switched central resource peripheral central resource bridge dual cortex-r4f cpus in lockstep emac slaves switched central resource mibadc1 mibadc2 i2c n2het1 gio n2het2 64kb flash for eeprom emulation with ecc mdio mii iomm pmm vim rti dcc1 dcc2 3mb flash with ecc etm-r4 rtp 64k64k 64k 64k rtpclk rtpnena rtpsync rtpdata[15:0] traceclkin traceclk tracectl etmdata[31:0] dmmclk dmmnena dmmsync dmmdata[15:0] 256kb ram with ecc mdclk mdio mii_rxd[3:0] mii_rxer mii_txd[3:0] mii_txen mii_txclk mii_rxclk mii_crs mii_rxdv mii_col emif emif_clk emif_cke emif_ncs[4:2] emif_ncs[0] emif_addr[21:0] emif_ba[1:0] emif_data[15:0] emif_ndqm[1:0] emif_noe emif_nwe emif_nrasemif_ncas emif_nwait vssad vccad i2c_scl i2c_sda giob[7:0] gioa[7:0] vccad vssad adrefhi adreflo ad1evt ad1in[7:0] ad1in[23:8] ad2in[15:0] ad2evt adrefhi adreflo switched central resource device host usb1.overcurrentusb1.rcv usb1.vm usb1.vp usb1.portpower usb1.speed usb1.suspend usb1.txdat usb1.txen usb1.txse0 usb2.overcurrent usb2.rcv usb2.vm usb2.vp usb2.portpower usb2.speed usb2.suspend usb2.txdat usb2.txen usb2.txse0 usb_func.gzo usb_func.pueno usb_func.puenon usb_func.rxdi usb_func.rxdmi usb_func.rxdpi usb_func.se0o usb_func.suspendo usb_func.txdo usb_func.vbusi usb slaves usb host # 2# 3 # 4 # 1 # 2 # 1 always on core/ram ram core # 5 # 3 color legend for power domains dcan1dcan2 dcan3 lin sci spi4 mibspi1 can1_rx can1_tx can2_rx can2_tx can3_rx can3_tx mibspi1_clk mibspi1_simo[1:0] mibspi1_somi[1:0] mibspi1_ncs[5:0] mibspi1_nena spi2 spi2_clk spi2_simo spi2_somi spi2_ncs[1:0] spi2_nena mibspi3 mibspi3_clk mibspi3_simo mibspi3_somi mibspi3_ncs[5:0] mibspi3_nena spi4_clkspi4_simo spi4_somi spi4_ncs0 spi4_nena mibspi5 mibspi5_simo[3:0]mibspi5_somi[3:0] mibspi5_ncs[3:0] mibspi5_nena lin_rx lin_tx sci_rx sci_tx sys nporrst nrst eclk esm nerror giob[7:0] gioa[7:0] n2het2[18,16] n2het2[15:0] n2het1[31:0] n2het1_pin_ndis n2het2_pin_ndis
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table of contents 1 device overview ......................................... 1 6.12 parity protection for peripheral rams .............. 85 1.1 features .............................................. 1 6.13 on-chip sram initialization and testing ........... 87 1.2 applications ........................................... 2 6.14 external memory interface (emif) .................. 89 1.3 description ............................................ 3 6.15 vectored interrupt manager ......................... 96 1.4 functional block diagram ............................ 5 6.16 dma controller ...................................... 99 2 revision history ......................................... 7 6.17 real time interrupt module ........................ 102 3 device comparison ..................................... 8 6.18 error signaling module ............................. 104 4 terminal configuration and functions ........... 10 6.19 reset / abort / error sources ...................... 108 4.1 pge qfp package pinout (144-pin) ............... 10 6.20 digital windowed watchdog ....................... 110 4.2 zwt bga package ball-map (337-ball grid array) 11 6.21 debug subsystem ................................. 111 4.3 terminal functions ................................. 12 7 peripheral information and electrical specifications ......................................... 122 5 specifications .......................................... 45 7.1 peripheral legend ................................. 122 5.1 absolute maximum ratings ........................ 45 7.2 multibuffered 12-bit analog-to-digital converter .. 122 5.2 esd ratings ........................................ 45 7.3 general-purpose input/output ..................... 133 5.3 power-on hours (poh) ............................. 45 7.4 enhanced next generation high-end timer 5.4 recommended operating conditions ............... 46 (n2het) ............................................ 134 5.5 switching characteristics for clock domains ....... 47 7.5 controller area network (dcan) .................. 139 5.6 wait states required ............................... 47 7.6 local interconnect network interface (lin) ........ 140 5.7 power consumption ................................. 48 7.7 serial communication interface (sci) ............. 141 5.8 input/output electrical characteristics .............. 49 7.8 inter-integrated circuit (i2c) ....................... 142 5.9 thermal resistance characteristics ................ 50 7.9 multibuffered / standard serial peripheral 5.10 output buffer drive strengths ...................... 51 interface ............................................ 145 5.11 input timings ........................................ 52 7.10 ethernet media access controller ................. 157 5.12 output timings ...................................... 52 7.11 universal serial bus (usb) host and device controllers ......................................... 161 5.13 low-emi output buffers ............................ 54 8 device and documentation support .............. 163 6 system information and electrical specifications ........................................... 56 8.1 device support ..................................... 163 6.1 device power domains ............................. 56 8.2 documentation support ............................ 165 6.2 voltage monitor characteristics ..................... 57 8.3 community resources ............................. 165 6.3 power sequencing and power on reset ........... 58 8.4 trademarks ........................................ 165 6.4 warm reset (nrst) ................................. 60 8.5 electrostatic discharge caution ................... 165 6.5 arm cortex-r4f cpu information ................. 61 8.6 glossary ............................................ 165 6.6 clocks ............................................... 65 8.7 device identification code register ............... 165 6.7 clock monitoring .................................... 73 8.8 die identification registers ....................... 167 6.8 glitch filters ......................................... 75 8.9 module certifications ............................... 168 6.9 device memory map ................................ 76 9 mechanical packaging and orderable information ............................................. 173 6.10 flash memory ....................................... 82 9.1 packaging information ............................. 173 6.11 tightly coupled ram (tcram) interface module .. 85 6 table of contents copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 2 revision history this data manual revision history highlights the technical changes made to the spns177c device-specific data manual to make it an spns177d revision. scope: applicable updates to the hercules ? rm mcu device family, specifically relating to the rm48l952 devices, which are now in the production data (pd) stage of development have been incorporated. changes from april 30, 2015 to june 30, 2015 (from c revision (april 2015) to d revision) page ? section 1.3 (description): corrected dma description, 32 peripheral requests, not 32 control packets ................... 4 ? section 6.5.1 : added quantity of breakpoints and watchpoints ............................................................. 61 ? section 7.9.1 corrected size of spi baud rate generator, 11 bit, not 5 bit ................................................ 145 ? figure 8-1 (rm48x device numbering conventions): updated/changed figure to show the die revision letter ...... 164 copyright ? 2011 ? 2015, texas instruments incorporated revision history 7 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 3 device comparison table 3-1 lists the features of the rm48l952 devices. table 3-1. rm48l952 device comparison (1) (2) features devices generic part rm57l843zwt (3) rm48l952zwt (3) rm48l952pge rm48l950zwt rm48l750zwt rm48l550zwt rm46l852zwt (3) rm44l922zwt number package 337 bga 337 bga 144 qfp 337 bga 337 bga 337 bga 337 bga 337 bga cpu arm cortex-r5f arm cortex-r4f arm cortex-r4f arm cortex-r4f arm cortex-r4f arm cortex-r4f arm cortex-r4f arm cortex-r4f frequency (mhz) 333 220 220 200 200 200 220 220 32 i cache (kb) ? ? ? ? ? ? ? 32 d flash (kb) 4096 3072 3072 3072 2048 2048 1280 1024 ram (kb) 512 256 256 256 256 192 192 128 data flash 128 64 64 64 64 64 64 64 [eeprom] (kb) usb ohci + device ? 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 2+0 or 1+1 ? emac 10/100 10/100 10/100 10/100 10/100 10/100 10/100 ? can 4 3 3 3 3 3 3 3 mibadc 2 (41ch) 2 (24ch) 2 (24ch) 2 (41ch) 2 (41ch) 2 (41ch) 2 (24ch) 2 (24ch) 12-bit (ch) n2het (ch) 2 (64) 2 (44) 2 (40) 2 (44) 2 (44) 2 (44) 2 (44) 2 (44) epwm channels 14 ? ? ? ? ? 14 14 ecap channels 6 ? ? ? ? ? 6 6 eqep channels 2 ? ? ? ? ? 2 2 mibspi (cs) 5 (4 x 6 + 2) 3 (6 + 6 + 4) 3 (5 + 6 + 1) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (6 + 6 + 4) 3 (6 + 6 + 4) spi (cs) ? 2 (2 + 1) 1 (1) 2 (2 + 1) 2 (2 + 1) 2 (2 + 1) 2 (2 + 1) 2 (2 + 1) sci (lin) 4 (2 with lin) 2 (1 with lin) 2 (1 with lin) 2 (1 with lin) 2 (1 with lin) 2 (1 with lin) 2 (1 with lin) 2 (1 with lin) 2 1 1 1 1 1 1 1 i 2 c 168 (with 16 interrupt 144 (with 16 interrupt 64 (with 4 interrupt 144 (with 16 interrupt 144 (with 16 interrupt 144 (with 16 interrupt 101 (with 16 interrupt 101 (with 16 interrupt gpio (int) (4) capable) capable) capable) capable) capable) capable) capable) capable) emif 16-bit data 16-bit data ? 16-bit data 16-bit data 16-bit data 16-bit data ? etm [trace] (data) (32) (32) ? 32-bit 32-bit 32-bit ? ? rtp/dmm (data) (16/16) (16/16) ? 16/16 16/16 16/16 ? ? operating ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c ? 40 o c to 105 o c temperature (1) for additional device variants, see www.ti.com/rm (2) this table reflects the maximum configuration for each peripheral. some functions are multiplexed and not all pins are available at the same time. (3) superset device (4) total number of pins that can be used as general-purpose input or output when not used as part of a peripheral 8 device comparison copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 3-1. rm48l952 device comparison (1) (2) (continued) features devices core supply (v) 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v 1.14 v ? 1.32 v i/o supply (v) 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v 3.0 v ? 3.6 v copyright ? 2011 ? 2015, texas instruments incorporated device comparison 9 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4 terminal configuration and functions 4.1 pge qfp package pinout (144-pin) a. pins can have multiplexed functions. only the default function is depicted in the figure. figure 4-1. pge qfp package pinout (144-pin) (a) 10 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 1 108 23 4 5 gioa[1] ntrst 109144 110 111 112 113 114 115 116 117 118 119 120 121 ad1in[10] / ad2in[10] 122123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 7271 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 67 8 9 10 11 1213 14 15 16 17 18 19 20 21 22 2323 24 25 26 2727 28 29 30 31 32 33 34 35 36 107 106 105 104 103 102 101 100 9998 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 giob[3] gioa[0] mibspi3ncs[3]mibspi3ncs[2] n2het1[11] fltp1 fltp2 gioa[2] vccio vss can3rx can3tx gioa[5] n2het1[22] gioa[6] vcc oscin kelvin_gnd oscout vss gioa[7] n2het1[01] n2het1[03] n2het1[0] vccio vssvss vcc n2het1[02] n2het1[05] mibspi5ncs[0] n2het1[07] test n2het1[09] n2het1[4] mibspi3ncs[1] n2het1[06] n2het1[13] mibspi1ncs[2] n2het1[15] vccio vss vss vcc nporrst vss vcc vcc vss mibspi3somi mibspi3simo mibspi3clk mibspi3nena mibspi3ncs[0] vss vcc ad1in[16] / ad2in[0] ad1in[17] / ad2in[01] ad1in[0] ad1in[07] ad1in[18] / ad2in[02] ad1in[19] / ad2in[03] ad1in[20] / ad2in[04] ad1in[21] / ad2in[05] adrefhi adreflo vssad vccad ad1in[09] / ad2in[09] ad1in[01] ad1in[02] ad1in[03] ad1in[11] / ad2in[11] ad1in[04] ad1in[12] / ad2in[12] ad1in[05] ad1in[13] / ad2in[13] ad1in[06] ad1in[22] / ad2in[06] ad1in[14] / ad2in[14] ad1in[08] / ad2in[08] ad1in[23] / ad2in[07] ad1in[15] / ad2in[15] ad1evt vcc vss can1tx can1rx n2het1[24] n2het1[26] mibspi1simo mibspi1somi mibspi1clk mibspi1nena mibspi5nena mibspi5somi[0] mibspi5simo[0] mibspi5clk vcc vss vss vccio n2het1[08] n2het1[28] tms tdi tdo tck rtck vcc vss nrst nerror n2het1[10] eclk vccio vss vss vcc n2het1[12] n2het1[14] giob[0] n2het1[30] can2tx can2rx mibspi1ncs[1] linrx lintx giob[1] vccp vss vccio vcc vss n2het1[16]n2het1[18] n2het1[20] giob[2] vcc vss mibspi1ncs[0]
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.2 zwt bga package ball-map (337-ball grid array) a. balls can have multiplexed functions. only the default function, except for the emif signals that are multiplexed with etm signals, is depicted in the figure. figure 4-2. zwt package pinout. top view (a) note: balls can have multiplexed functions. only the default function is depicted in figure 4-2 , except for the emif signals that are multiplexed with etm signals. copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 11 submit documentation feedback a b c d e f g h j k l m n p r t u v w 19 vss vss tms n2het1 [10] mibspi5 ncs[0] mibspi1 simo mibspi1 nena mibspi5 clk mibspi5 simo[0] n2het1 [28] dmm_ data[0] can3rx ad1evt ad1in[15] / ad2in[15] ad1in[22] / ad2in[06] ad1in [06] ad1in[11] / ad2in[11] vssad vssad 19 18 vss tck tdo ntrst n2het1 [08] mibspi1 clk mibspi1 somi mibspi5 nena mibspi5 somi[0] n2het1 [0] dmm_ data[1] can3tx nc ad1in[08] / ad2in[08] ad1in[14] / ad2in[14] ad1in[13] / ad2in[13] ad1in [04] ad1in [02] vssad 18 17 tdi rst emif_ addr[21] emif_ nwe mibspi5 somi[1] dmm_ clk mibspi5 simo[3] mibspi5 simo[2] n2het1 [31] emif_ ncs[3] emif_ ncs[2] emif_ ncs[4] emif_ ncs[0] nc ad1in [05] ad1in [03] ad1in[10] / ad2in[10] ad1in [01] ad1in[09] / ad2in[09] 17 16 rtck nc emif_ addr[20] emif_ ba[1] mibspi5 simo[1] dmm_ nena mibspi5 somi[3] mibspi5 somi[2] dmm_ sync nc nc nc nc nc ad1in[23] / ad2in[07] ad1in[12] / ad2in[12] ad1in[19] / ad2in[03] adreflo vssad 16 15 nc nc emif_ addr[19] emif_ addr[18] etm data[06] etm data[05] etm data[04] etm data[03] etm data[02] etm data[16] etm data[17] etm data[18] etm data[19] nc nc ad1in[21] / ad2in[05] ad1in[20] / ad2in[04] adrefhi vccad 15 14 n2het1 [26] nerror emif_ addr[17] emif_ addr[16] etm data[07] vccio vccio vccio vcc vcc vccio vccio vccio vccio nc nc ad1in[18] / ad2in[02] ad1in [07] ad1in [0] 14 13 n2het1 [17] n2het1 [19] emif_ addr[15] nc etm data[12] vccio vccio etm data[01] nc ad1in[17] / ad2in[01] ad1in[16] / ad2in[0] nc 13 12 eclk n2het1 [04] emif_ addr[14] nc etm data[13] vccio vss vss vcc vss vss vccio etm data[0] mibspi5 ncs[3] nc nc nc 12 11 n2het1 [14] n2het1 [30] emif_ addr[13] nc etm data[14] vccio vss vss vss vss vss vccpll etme trace ctl nc nc nc nc 11 10 can1tx can1rx emif_ addr[12] nc etm data[15] vcc vcc vss vss vss vcc vcc etm trace clkout nc nc mibspi3 ncs[0] giob[3] 10 9 n2het1 [27] nc emif_ addr[11] nc etm data[08] vcc vss vss vss vss vss vccio etm trace clkin nc nc mibspi3 clk mibspi3 nena 9 8 nc nc emif_ addr[10] nc etm data[09] vccp vss vss vcc vss vss vccio etm data[31] nc nc mibspi3 somi mibspi3 simo 8 7 linrx lintx emif_ addr[9] nc etm data[10] vccio vccio etm data[30] nc nc n2het1 [09] nporrst 7 6 gioa[4] mibspi5 ncs[1] emif_ addr[8] nc etm data[11] vccio vccio vccio vccio vcc vcc vccio vccio vccio etm data[29] nc nc n2het1 [05] mibspi5 ncs[2] 6 5 gioa[0] gioa[5] emif_ addr[7] emif_ addr[1] etm data[20] etm data[21] etm data[22] fltp2 fltp1 etm data[23] etm data[24] etm data[25] etm data[26] etm data[27] etm data[28] nc nc mibspi3 ncs[1] n2het1 [02] 5 4 n2het1 [16] n2het1 [12] emif_ addr[6] emif_ addr[0] nc nc nc n2het1 [21] n2het1 [23] nc] nc nc nc nc emif_ ncas nc nc nc nc 4 3 n2het1 [29] n2het1 [22] mibspi3 ncs[3] spi2 nena n2het1 [11] mibspi1 ncs[1] mibspi1 ncs[2] gioa[6] mibspi1 ncs[3] emif_ clk emif_ cke nh2et1 [25] spi2 ncs[0] emif_ nwait emif_ nras nc nc nc n2het1 [06] 3 2 vss mibspi3 ncs[2] gioa[1] spi2 somi spi2 clk giob[2] giob[5] can2tx giob[6] giob[1] kelvin_ gnd giob[0] n2het1 [13] n2het1 [20] mibspi1 ncs[0] nc test n2het1 [01] vss 2 1 vss vss gioa[2] spi2 simo gioa[3] giob[7] giob[4] can2rx n2het1 [18] oscin oscout gioa[7] n2het1 [15] n2het1 [24] nc n2het1 [07] n2het1 [03] vss vss 1 a b c d e f g h j k l m n p r t u v w
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3 terminal functions section 4.3.1 and section 4.3.2 identify the external signal names, the associated pin or ball numbers along with the mechanical package designator, the pin or ball type (input, output, i/o, power, or ground), whether the pin or ball has any internal pullup or pulldown, whether the pin or ball can be configured as a gpio, and a functional pin or ball description. the first signal name listed is the primary function for that terminal. the signal name in bold is the function being described. for information on how to select between different multiplexed functions, see the rm48x 16/32-bit risc flash microcontroller technical reference manual ( spnu503 ) . note in the terminal functions table below, the "reset pull state" is the state of the pull applied to the terminal while nporrst is low and immediately after nporrst goes high. the default pull direction may change when software configures the pin for an alternate function. the "pull type" is the type of pull asserted when the signal name in bold is enabled for the given terminal by the iomm control registers. all i/o signals except nrst are configured as inputs while nporrst is low and immediately after nporrst goes high. while nporrst is low, the input buffers are disabled, and the output buffers are disabled with the default pulls enabled. all output-only signals have the output buffer disabled and the default pull enabled while nporrst is low, and are configured as outputs with the pulls disabled immediately after nporrst goes high. 4.3.1 pge package 4.3.1.1 multibuffered analog-to-digital converters (mibadcs) table 4-1. pge multibuffered analog-to-digital converters (mibadc1, mibadc2) terminal reset signal pull pull type description 144 type signal name state pge adrefhi (1) 66 input adc high reference supply adreflo (1) 67 input adc low reference supply n/a none vccad (1) 69 power operating supply for adc vssad (1) 68 ground ad1evt /mii_rx_er/rmii_rx_er 86 i/o pulldown programmable, 20 a adc1 event trigger input, or gpio mibspi3ncs[0]/ ad2evt /giob[2]/n2het2_pin_ndis 55 i/o pullup programmable, 20 a adc2 event trigger input, or gpio ad1in[0] 60 ad1in[1] 71 ad1in[2] 73 ad1in[3] 74 input n/a none adc1 analog input ad1in[4] 76 ad1in[5] 78 ad1in[6] 80 ad1in[7] 61 (1) the adrefhi, adreflo, vccad, and vssad connections are common for both adc cores. 12 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 4-1. pge multibuffered analog-to-digital converters (mibadc1, mibadc2) (continued) terminal reset signal pull pull type description 144 type signal name state pge ad1in[8] / ad2in[8] 83 ad1in[9] / ad2in[9] 70 ad1in[10] / ad2in[10] 72 ad1in[11] / ad2in[11] 75 ad1in[12] / ad2in[12] 77 ad1in[13] / ad2in[13] 79 ad1in[14] / ad2in[14] 82 ad1in[15] / ad2in[15] 85 input n/a none adc1/adc2 shared analog inputs ad1in[16] / ad2in[0] 58 ad1in[17] / ad2in[1] 59 ad1in[18] / ad2in[2] 62 ad1in[19] / ad2in[3] 63 ad1in[20] / ad2in[4] 64 ad1in[21] / ad2in[5] 65 ad1in[22] / ad2in[6] 81 ad1in[23] / ad2in[7] 84 copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 13 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.1.2 enhanced next generation high-end timer (n2het) modules table 4-2. pge enhanced next generation high-end timer modules (n2het1, n2het2) terminal signal reset pull pull type description 144 type state signal name pge n2het1[0] /spi4clk 25 n2het1[1] /spi4nena /usb2.txen/usb_func.pueno 23 /n2het2[8] n2het1[2] /spi4simo[0] 30 n2het1[3] /spi4ncs[0] 24 /usb2.speed/usb_func.puenon/n2het2[10] n2het1[4] 36 n2het1[5] /spi4somi[0]/n2het2[12] 31 n2het1[6] /scirx 38 n2het1[7] / usb2.portpower/usb_func.gzo/n2het2[14] 33 programmable, n2het1[8] /mibspi1simo[1] /mii_txd[3]/ usb1.overcurrent 106 i/o pulldown 20 a n2het1[9] /n2het2[16] 35 /usb2.suspend/usb_func.suspendo n2het1[10] /mii_tx_clk/usb1.txen/mii_tx_avclk4 118 n2het1[11] /mibspi3ncs[4]/n2het2[18] / 6 usb2.overcurrent/usb_func.vbusi n2het1[12] /mii_crs/rmii_crs_dv 124 n2het1[13] /scitx 39 n2het1[14] /usb1.txse0 125 n2het1[15] /mibspi1ncs[4] 41 n2het1[16] 139 n2het1 timer input capture mibspi1ncs[1]/ n2het1[17] /mii_col/ programmable, 130 i/o pullup or output compare, or gio. usb1.suspend 20 a each terminal has a programmable, n2het1[18] 140 i/o pulldown suppression filter with a 20 a programmable duration. programmable, mibspi1ncs[2]/ n2het1[19] /mdio 40 i/o pullup 20 a programmable, n2het1[20] 141 i/o pulldown 20 a programmable, n2het1[22] /usb2.txse0/usb_func.se0o 15 i/o pulldown 20 a programmable, mibspi1nena/ n2het1[23] /mii_rxd[2]/usb1.vp 96 i/o pullup 20 a programmable, n2het1[24] /mibspi1ncs[5] /mii_rxd[0]/rmii_rxd[0] 91 i/o pulldown 20 a programmable, mibspi3ncs[1]/ n2het1[25] /mdclk 37 i/o pullup 20 a programmable, n2het1[26] /mii_rxd[1]/rmii_rxd[1] 92 i/o pulldown 20 a programmable, mibspi3ncs[2]/i2c_sda/ n2het1[27] 4 i/o pullup 20 a programmable, n2het1[28] /mii_rx_clk/rmii_refclk/mii_rx_avclk4 107 i/o pulldown 20 a programmable, mibspi3ncs[3]/i2c_scl/ n2het1[29] 3 i/o pullup 20 a programmable, n2het1[30] /mii_rx_dv/usb1.speed 127 i/o pulldown 20 a programmable, mibspi3nena/mibspi3ncs[5]/ n2het1[31] 54 i/o pullup 20 a programmable, disable selected pwm gioa[5]/extclkin/ n2het1_pin_ndis 14 i/o pulldown 20 a outputs 14 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 4-2. pge enhanced next generation high-end timer modules (n2het1, n2het2) (continued) terminal signal reset pull pull type description 144 type state signal name pge gioa[2]/ usb2.txdat/usb_func.txdo/ n2het2[0] 9 gioa[6]/ n2het2[4] 16 gioa[7]/ n2het2[6] 22 n2het1[1]/spi4nena/ usb2.txen/usb_func.pueno/ 23 n2het2 time input capture n2het2[8] or output compare, or gpio n2het1[3]/spi4ncs[0]/ programmable, 24 i/o pulldown each terminal has a usb2.speed/usb_func.puenon/ n2het2[10] 20 a suppression filter with a n2het1[5]/spi4somi[0]/ n2het2[12] 31 programmable duration. n2het1[7]/ usb2.portpower/usb_func.gzo/ n2het2[14] 33 n2het1[9]/ n2het2[16] /usb2.suspend/ usb_func.suspendo 35 n2het1[11]/mibspi3ncs[4]/ n2het2[18] / 6 usb2.overcurrent/usb_func.vbusi programmable, disable selected pwm mibspi3ncs[0]/ad2evt/giob[2]/ n2het2_pin_ndis 55 i/o pullup 20 a outputs 4.3.1.3 general-purpose input/output (gpio) table 4-3. pge general-purpose input/output (gpio) terminal reset signal pull pull type description 144 type signal name state pge gioa[0] /usb2.vp/usb_func.rxdpi 2 gioa[1] /usb2.vm/usb_func.rxdmi 5 gioa[2] /usb2.txdat/usb_func.txdo/n2het2[0] 9 gioa[5] /extclkin/n2het1_pin_ndis 14 general-purpose i/o. gioa[6] /n2het2[4] 16 pulldown all gpio terminals are programmable, gioa[7] /n2het2[6] 22 i/o capable of generating 20 a interrupts to the cpu on rising giob[0] /usb1.txdat 126 / falling / both edges. giob[1] /usb1.portpower 133 giob[2] /n2het1_pin_ndis 142 mibspi3ncs[0]/ad2evt/ giob[2] /n2het2_pin_ndis 55 (1) pullup giob[3] /usb2.rcv/usb_func.rxdi 1 pulldown (1) the application cannot output a level onto this terminal when it is configured as giob[2]. a pullup is enabled on this input. this pull cannot be disabled, and is not programmable using the gio module pull control registers. 4.3.1.4 controller area network controllers (dcans) table 4-4. pge controller area network controllers (dcan) terminal reset signal pull pull type description 144 type signal name state pge can1rx 90 can1 receive, or gpio can1tx 89 can1 transmit, or gpio can2rx 129 can2 receive, or gpio programmable, i/o pullup 20 a can2tx 128 can2 transmit, or gpio can3rx 12 can3 receive, or gpio can3tx 13 can3 transmit, or gpio copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 15 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.1.5 local interconnect network interface module (lin) table 4-5. pge local interconnect network interface module (lin) terminal reset signal pull pull type description 144 type signal name state pge linrx 131 lin receive, or gpio programmable, i/o pullup 20 a lintx 132 lin transmit, or gpio 4.3.1.6 standard serial communication interface (sci) table 4-6. pge standard serial communication interface (sci) terminal reset signal pull pull type description 144 type signal name state pge n2het1[6]/ scirx 38 sci receive, or gpio programmable, i/o pulldown 20 a n2het1[13]/ scitx 39 sci transmit, or gpio 4.3.1.7 inter-integrated circuit interface module (i2c) table 4-7. pge inter-integrated circuit interface module (i2c) terminal reset signal pull pull type description 144 type signal name state pge mibspi3ncs[2]/ i2c_sda /n2het1[27] 4 i2c serial data, or gpio programmable, i/o pullup 20 a mibspi3ncs[3]/ i2c_scl /n2het1[29] 3 i2c serial clock, or gpio 4.3.1.8 standard serial peripheral interface (spi) table 4-8. pge standard serial peripheral interface (spi) terminal reset signal pull pull type description 144 type signal name state pge n2het1[0]/ spi4clk 25 spi4 clock, or gpio n2het1[3]/ spi4ncs[0] /usb2.speed/ 24 spi4 chip select, or gpio usb_func.puenon/n2het2[10] n2het1[1]/ spi4nena /usb2.txen/ 23 programmable, spi4 enable, or gpio usb_func.pueno/n2het2[8] i/o pulldown 20 a spi4 slave-input master- n2het1[2]/ spi4simo[0] 30 output, or gpio spi4 slave-output master- n2het1[5]/ spi4somi[0] /n2het2[12] 31 input, or gpio 16 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.1.9 multibuffered serial peripheral interface modules (mibspi) table 4-9. pge multibuffered serial peripheral interface modules (mibspi) terminal reset signal pull pull type description 144 type signal name state pge mibspi1clk 95 mibspi1 clock, or gpio mibspi1ncs[0] /mibspi1somi[1] /mii_txd[2]/ 105 usb1.rcv programmable, pullup 20 a mibspi1ncs[1] /n2het1[17] /mii_col/ mibspi1 chip select, or gpio 130 usb1.suspend mibspi1ncs[2] /n2het1[19] /mdio 40 n2het1[15]/ mibspi1ncs[4] 41 programmable, pulldown mibspi1 chip select, or gpio 20 a n2het1[24]/ mibspi1ncs[5] /mii_rxd[0]/rmii_rxd[0] 91 i/o mibspi1nena /n2het1[23] /mii_rxd[2]/ 96 mibspi1 enable, or gpio programmable, usb1.vp pullup 20 a mibspi1simo[0] 93 mibspi1 slave-in master-out, or gpio n2het1[8]/ mibspi1simo[1] /mii_txd[3]/ programmable, 106 pulldown mibspi1 slave-in master-out, or gpio usb1.overcurrent 20 a mibspi1somi[0] 94 programmable, pullup mibspi1 slave-out master-in, or gpio mibspi1ncs[0]/ mibspi1somi[1] /mii_txd[2]/ 20 a 105 usb1.rcv mibspi3clk 53 mibspi3 clock, or gpio mibspi3ncs[0] /ad2evt/giob[2]/n2het2_pin_ndis 55 programmable, mibspi3ncs[1] /n2het1[25]/mdclk 37 pullup 20 a mibspi3 chip select, or gpio mibspi3ncs[2] /i2c_sda/n2het1[27] 4 mibspi3ncs[3] /i2c_scl/n2het1[29] 3 i/o n2het1[11]/ mibspi3ncs[4] /n2het2[18] / programmable, 6 pulldown mibspi3 chip select, or gpio usb2.overcurrent/usb_func.vbusi 20 a mibspi3nena / mibspi3ncs[5] /n2het1[31] 54 mibspi3 chip select, or gpio mibspi3nena /mibspi3ncs[5]/n2het1[31] 54 mibspi3 enable, or gpio programmable, pullup 20 a mibspi3simo[0] 52 mibspi3 slave-in master-out, or gpio mibspi3somi[0] 51 mibspi3 slave-out master-in, or gpio mibspi5clk /mii_txen/rmii_txen 100 mibspi5 clock, or gpio mibspi5ncs[0] 32 mibspi5 chip select, or gpio programmable, mibspi5nena /mii_rxd[3]/usb1.vm 97 i/o pullup mibspi5 enable, or gpio 20 a mibspi5simo[0] /mii_txd[1]/rmii_txd[1] 99 mibspi5 slave-in master-out, or gpio mibspi5somi[0] /mii_txd[0]/rmii_txd[0] 98 mibspi5 slave-out master-in, or gpio 4.3.1.10 ethernet controller table 4-10. pge ethernet controller: mdio interface terminal reset signal pull pull type description 144 type signal name state pge programmable, mibspi3ncs[1]/n2het1[25]/ mdclk 37 output pullup serial clock output 20 a fixed 20 - a mibspi1ncs[2]/n2het1[19]/ mdio 40 i/o pullup serial data input/output pullup copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 17 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 4-11. pge ethernet controller: reduced media independent interface (rmii) terminal reset signal pull pull type description 144 type signal name state pge rmii carrier sense and data n2het1[12]/mii_crs/ rmii_crs_dv 124 valid rmii synchronous reference n2het1[28]/mii_rx_clk/ rmii_refclk /mii_rx_avclk4 107 clock for receive, transmit and fixed 20 - a control interface input pulldown pulldown ad1evt/mii_rx_er/ rmii_rx_er 86 rmii receive error n2het1[24]/mibspi1ncs[5]/mii_rxd[0]/ rmii_rxd[0] 91 rmii receive data n2het1[26]/mii_rxd[1]/ rmii_rxd[1] 92 mibspi5somi[0]/mii_txd[0]/ rmii_txd[0] 98 rmii transmit data mibspi5simo[0]/mii_txd[1]/ rmii_txd[1] 99 output pullup none mibspi5clk/mii_txen/ rmii_txen 100 rmii transmit enable table 4-12. pge ethernet controller: media independent interface (mii) terminal reset signal pull pull type description 144 type signal name state pge mibspi1ncs[1]/n2het1[17]/ mii_col / 130 pullup none collision detect usb1.suspend input fixed 20 - a carrier sense and receive n2het1[12]/ mii_crs /rmii_crs_dv 124 pulldown pulldown valid n2het1[28]/mii_rx_clk /rmii_refclk/ mii_rx_avclk4 107 i/o pulldown none mii output receive clock n2het1[30]/ mii_rx_dv /usb1.speed 127 received data valid input ad1evt/ mii_rx_er /rmii_rx_er 86 receive error fixed 20 - a n2het1[28]/ mii_rx_clk /rmii_refclk/mii_rx_avclk4 107 i/o pulldown receive clock pulldown n2het1[24]/mibspi1ncs[5]/ mii_rxd[0] /rmii_rxd[0] 91 n2het1[26]/ mii_rxd[1] /rmii_rxd[1] 92 input receive data mibspi1nena /n2het1[23]/ mii_rxd[2] / 96 fixed 20 - a usb1.vp pullup pulldown mibspi5nena/ mii_rxd[3] /usb1.vm 97 n2het1[10]/mii_tx_clk/ usb1.txen/ 118 mii output transmit clock mii_tx_avclk4 i/o pulldown none n2het1[10]/ mii_tx_clk /usb1.txen 118 transmit clock /mii_tx_avclk4 mibspi5somi[0]/ mii_txd[0] /rmii_txd[0] 98 mibspi5simo[0]/ mii_txd[1] /rmii_txd[1] 99 pullup none mibspi1ncs[0]/mibspi1somi[1]/ mii_txd[2] / transmit data 105 usb1.rcv output n2het1[8]/mibspi1simo[1]/ mii_txd[3] / 106 pulldown none usb1.overcurrent mibspi5clk/ mii_txen /rmii_txen 100 pullup none transmit enable 18 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.1.11 usb host and device port controller interface the usb host controller includes a root hub with two ports. usb1 pins are for root hub port 0. usb2 pins are for root hub port 1. table 4-13. pge usb host port controller interface (usb1, usb2) terminal reset signal pull pull type description 144 type signal name state pge active-low input, asserted n2het1[8]/mibspi1simo[1] /mii_txd[3] fixed 20 - a 106 pulldown during overcurrent condition / usb1.overcurrent pullup from usb power switch usb receive data, converted mibspi1ncs[0]/mibspi1somi[1] /mii_txd[2]/ 105 from differential (d+/d ? to usb1.rcv input single ended by transceiver) fixed 20 - a pullup single-ended d ? input, driven mibspi5nena /mii_rxd[3]/ usb1.vm 97 pullup by transceiver mibspi1nena/n2het1[23]/ mii_rxd[2]/ single-ended d+ input, driven 96 usb1.vp by transceiver active-high output enable for giob[1]/ usb1.portpower 133 controlling an external usb power switch transmit speed to usb port pulldown none transceiver. n2het1[30] /mii_rx_dv/ usb1.speed 127 0 = low speed 1 = full speed this signal indicates the state of the port, active or suspend. mibspi1ncs[1]/n2het1[17] /mii_col/ 130 pullup none output usb1.suspend 0 = active 1 = suspend single-ended usb data output to usb transceiver. giob[0]/ usb1.txdat 126 use in combination with usb1.txse0 n2het1[10] /mii_tx_clk/ usb1.txen pulldown none active-low output transmit 118 /mii_tx_avclk4 enable to port transceiver active high output ? instructs n2het1[14]/ usb1.txse0 125 transceiver to transmit single- ended zero. 6 input active-low input, asserted n2het1[11]/mibspi3ncs[4]/n2het2[18]/ fixed 20 - a pulldown during overcurrent condition usb2.overcurrent /usb_func.vbusi pullup from usb power switch 1 usb receive data, converted giob[3]/ usb2.rcv /usb_func.rxdi from differential (d+/d ? to single ended by transceiver). fixed 20 - a 5 pulldown single-ended d ? input, driven gioa[1]/ usb2.vm /usb_func.rxdmi pullup by transceiver 2 single-ended d+ input, driven gioa[0]/ usb2.vp /usb_func.rxdpi by transceiver copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 19 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 4-13. pge usb host port controller interface (usb1, usb2) (continued) terminal reset signal pull pull type description 144 type signal name state pge active-high output enable for n2het1[7]/ usb2.portpower / 33 controlling an external usb usb_func.gzo/n2het2[14] power switch transmit speed to usb port transceiver. n2het1[3]/spi4ncs[0]/ usb2.speed / 24 usb_func.puenon/n2het2[10] 0 = low speed 1 = full speed this signal indicates the state of the port, active or suspend. n2het1[9]/n2het2[16]/ usb2.suspend / 35 output pulldown none usb_func.suspendo 0 = active 1 = suspend single-ended usb data output to usb transceiver. gioa[2]/ usb2.txdat /usb_func.txdo/n2het2[0] 9 use in combination with usb2.txse0 n2het1[1]/spi4nena/ usb2.txen / active-low output transmit 23 usb_func.pueno/n2het2[8] enable to port transceiver active high output ? instructs n2het1[22]/ usb2.txse0 /usb_func.se0o 15 transceiver to transmit single- ended zero. table 4-14. pge usb device port controller interface (usb_func) terminal reset signal pull pull type description 144 type signal name state pge active-low output usb device n2het1[7]/usb2.portpower/ usb_func.gzo /n2het2[14] 33 transmit enable to port transceiver pullup enable, allows for n2het1[1]/spi4nena/usb2.txen/ usb_func.pueno / output pulldown none 23 software-programmable usb n2het2[8] device connect/disconnect n2het1[3]/spi4ncs[0]/usb2.speed/ usb_func.puenon / 24 pueno inverted n2het2[10] usb receive data, converted giob[3]/usb2.rcv/ usb_func.rxdi 1 from differential (d+/d ? to single ended by transceiver). fixed 20 - a input pulldown single-ended d ? input, driven gioa[1]/usb2.vm/ usb_func.rxdmi 5 pullup by transceiver single-ended d+ input, driven gioa[0]/usb2.vp/ usb_func.rxdpi 2 by transceiver active high output ? instructs n2het1[22]/usb2.txse0/ usb_func.se0o 15 transceiver to transmit single- ended zero. active high output ? usb device suspend output. this n2het1[9]/n2het2[16]/usb2.suspend/ 35 function is asserted when the usb_func.suspendo output pulldown none usb bus has detected an idle mode during 5 ms. single-ended usb data output to usb transceiver. gioa[2]/usb2.txdat/ usb_func.txdo /n2het2[0] 9 use in combination with usb_func.se0o must be pulled up or down to reflect the state of power on n2het1[11]/mibspi3ncs[4]/n2het2[18]/ fixed 20 - a 6 input pulldown the vbus terminal of the usb usb2.overcurrent/ usb_func.vbusi pulldown device connector. this terminal is not 5 v tolerant. 20 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.1.12 system module interface table 4-15. pge system module interface terminal reset signal pull pull type description 144 type signal name state pge power-on reset, cold reset external power supply monitor circuitry must drive nporrst fixed 100 - a low when any of the supplies nporrst 46 input pulldown pulldown to the microcontroller fall out of the specified range. this terminal has a glitch filter. see section 6.8 . system reset, warm reset, bidirectional. the internal circuitry indicates any reset condition by driving nrst low. the external circuitry can assert a system reset by fixed 100 - a nrst 116 i/o pullup driving nrst low. to ensure pullup that an external reset is not arbitrarily generated, ti recommends that an external pullup resistor is connected to this terminal. this terminal has a glitch filter. see section 6.8 . esm error signal fixed 20 - a nerror 117 i/o pulldown indicates error of high pulldown severity. see section 6.18 . 4.3.1.13 clock inputs and outputs table 4-16. pge clock inputs and outputs terminal reset signal pull pull type description 144 type signal name state pge from external oscin 18 input crystal/resonator, or external clock input n/a none kelvin_gnd 19 input kelvin ground for oscillator oscout 20 output to external crystal/resonator programmable, 20 external prescaled clock eclk 119 i/o pulldown a output, or gio. gioa[5]/ extclkin /n2het1_pin_ndis 14 input pulldown 20 a external clock input #1 4.3.1.14 test and debug modules interface table 4-17. pge test and debug modules interface terminal reset signal pull pull type description signal name 144 type state pge test enable. this terminal must be connected to ground test 34 i/o fixed 100 - a directly or through a pulldown pulldown pulldown resistor. ntrst 109 input jtag test hardware reset rtck 113 output n/a none jtag return test clock fixed 100 - a tck 112 input pulldown jtag test clock pulldown fixed 100 - a tdi 110 i/o pullup jtag test data in pullup copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 21 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 4-17. pge test and debug modules interface (continued) terminal reset signal pull pull type description signal name 144 type state pge 100 a tdo 111 output none jtag test data out pulldown fixed 100 - a tms 108 i/o pullup jtag test select pullup 4.3.1.15 flash supply and test pads table 4-18. pge flash supply and test pads terminal reset signal pull pull type description 144 type signal name state pge 3.3-v vccp 134 n/a none flash pump supply power fltp1 7 flash test pads. these terminals are reserved for ti use only. for proper operation n/a none these terminals must connect fltp2 8 only to a test pad or not be connected at all [no connect (nc)]. 4.3.1.16 supply for core logic: 1.2-v nominal table 4-19. pge supply for core logic: 1.2-v nominal terminal reset signal pull pull type description 144 type signal name state pge vcc 17 vcc 29 vcc 45 vcc 48 vcc 49 vcc 57 1.2-v n/a none 1.2-v core supply power vcc 87 vcc 101 vcc 114 vcc 123 vcc 137 vcc 143 4.3.1.17 supply for i/o cells: 3.3-v nominal table 4-20. pge supply for i/o cells: 3.3-v nominal terminal reset signal pull pull type description signal name 144 type state pge vccio 10 vccio 26 vccio 42 3.3-v 3.3-v operating supply for n/a none power i/os vccio 104 vccio 120 vccio 136 22 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.1.18 ground reference for all supplies except vccad table 4-21. pge ground reference for all supplies except vccad terminal reset signal pull pull type description 144 type signal name state pge vss 11 vss 21 vss 27 vss 28 vss 43 vss 44 vss 47 vss 50 vss 56 ground n/a none ground reference vss 88 vss 102 vss 103 vss 115 vss 121 vss 122 vss 135 vss 138 vss 144 copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 23 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2 zwt package 4.3.2.1 multibuffered analog-to-digital converters (mibadcs) table 4-22. zwt multibuffered analog-to-digital converters (mibadc1, mibadc2) terminal reset signal pull pull type description 337 type signal name state zwt adrefhi (1) v15 input adc high reference supply adreflo (1) v16 input n/a none adc low reference supply vccad (1) w15 power operating supply for adc vssad v19 vssad w16 ground n/a none adc supply power vssad w18 vssad w19 programmable, adc1 event trigger input, or ad1evt /mii_rx_er/rmii_rx_er n19 i/o pulldown 20 a gpio programmable, adc2 event trigger input, or mibspi3ncs[0]/ ad2evt /giob[2]/n2het2_pin_ndis v10 i/o pullup 20 a gpio ad1in[0] w14 ad1in[1] v17 ad1in[2] v18 ad1in[3] t17 input n/a none adc1 analog input ad1in[4] u18 ad1in[5] r17 ad1in[6] t19 ad1in[7] v14 ad1in[8] / ad2in[8] p18 ad1in[9] / ad2in[9] w17 ad1in[10] / ad2in[10] u17 ad1in[11] / ad2in[11] u19 ad1in[12] / ad2in[12] t16 ad1in[13] / ad2in[13] t18 ad1in[14] / ad2in[14] r18 ad1in[15] / ad2in[15] p19 adc1/adc2 shared analog input n/a none inputs ad1in[16] / ad2in[0] v13 ad1in[17] / ad2in[1] u13 ad1in[18] / ad2in[2] u14 ad1in[19] / ad2in[3] u16 ad1in[20] / ad2in[4] u15 ad1in[21] / ad2in[5] t15 ad1in[22] / ad2in[6] r19 ad1in[23] / ad2in[7] r16 (1) the adrefhi, adreflo, vccad, and vssad connections are common for both adc cores. 24 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.2 enhanced next generation high-end timer (n2het) modules table 4-23. zwt enhanced next generation high-end timer (n2het) modules terminal reset signal pull pull type description 337 type signal name state zwt n2het1[0] /spi4clk k18 n2het1[1] /spi4nena /usb2.txen/ v2 usb_func.pueno/n2het2[8] n2het1[2] /spi4simo[0] w5 n2het1[3] /spi4ncs[0] /usb2.speed/ u1 usb_func.puenon/n2het2[10] n2het1[4] b12 n2het1[5] /spi4somi[0]/n2het2[12] v6 n2het1[6] /scirx w3 n2het1[7] /usb2.portpower/ t1 usb_func.gzo/n2het2[14] n2het1[8] /mibspi1simo[1] /mii_txd[3]/ e18 usb1.overcurrent n2het1[9] /n2het2[16] / v7 usb2.suspend/usb_func.suspendo n2het1[10] /mii_tx_clk/ d19 usb1.txen/mii_tx_avclk4 n2het1[11] /mibspi3ncs[4]/n2het2[18] / e3 usb2.overcurrent/usb_func.vbusi n2het1[12] /mii_crs/rmii_crs_dv b4 n2het1[13] /scitx n2 n2het1[14] /usb1.txse0 a11 n2het1[15] /mibspi1ncs[4] n1 n2het1 time input capture or n2het1[16] a4 output compare, or gio. n2het1[17] a13 programmable, i/o pulldown each terminal has a 20 a mibspi1ncs[1]/ n2het1[17] /mii_col/usb1.suspend f3 suppression filter with a n2het1[18] j1 programmable duration. n2het1[19] b13 mibspi1ncs[2]/ n2het1[19] /mdio g3 n2het1[20] p2 n2het1[21] h4 mibspi1ncs[3]/ n2het1[21] j3 n2het1[22] /usb2.txse0/usb_func.se0o b3 n2het1[23] j4 mibspi1nena/ n2het1[23] /mii_rxd[2]/ g19 usb1.vp n2het1[24] /mibspi1ncs[5] /mii_rxd[0]/rmii_rxd[0] p1 n2het1[25] m3 mibspi3ncs[1]/ n2het1[25] /mdclk v5 n2het1[26] /mii_rxd[1]/rmii_rxd[1] a14 n2het1[27] a9 mibspi3ncs[2]/i2c_sda/ n2het1[27] b2 n2het1[28] /mii_rx_clk/rmii_refclk/mii_rx_avclk4 k19 n2het1[29] a3 mibspi3ncs[3]/i2c_scl/ n2het1[29] c3 n2het1[30] /mii_rx_dv/usb1.speed b11 n2het1[31] j17 mibspi3nena/mibspi3ncs[5]/ n2het1[31] w9 programmable, disable selected pwm gioa[5]/extclkin/ n2het1_pin_ndis b5 i/o pulldown 20 a outputs copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 25 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 4-23. zwt enhanced next generation high-end timer (n2het) modules (continued) terminal reset signal pull pull type description 337 type signal name state zwt gioa[2]/ usb2.txdat/usb_func.txdo/ n2het2[0] c1 emif_addr[0]/ n2het2[1] d4 gioa[3]/ n2het2[2] e1 emif_addr[1]/ n2het2[3] d5 gioa[6]/ n2het2[4] h3 emif_ba[1]/ n2het2[5] d16 gioa[7]/ n2het2[6] m1 emif_ncs[0]/rtp_data[15]/ n2het2[7] n17 n2het1[1]/spi4nena/ usb2.txen/ v2 n2het2 time input capture or usb_func.pueno/ n2het2[8] output compare, or gio. emif_ncs[3]/rtp_data[14]/ n2het2[9] k17 programmable, i/o pulldown each terminal has a 20 a n2het1[3]/spi4ncs[0]/ usb2.speed/ u1 suppression filter with a usb_func.puenon/ n2het2[10] programmable duration. emif_addr[6]/rtp_data[13]/ n2het2[11] c4 n2het1[5]/spi4somi[0]/ n2het2[12] v6 emif_addr[7]/rtp_data[12]/ n2het2[13] c5 n2het1[7]/ usb2.portpower/ t1 usb_func.gzo/ n2het2[14] emif_addr[8]/rtp_data[11]/ n2het2[15] c6 n2het1[9]/ n2het2[16] /usb2.suspend/ v7 usb_func.suspendo n2het1[11]/mibspi3ncs[4]/ n2het2[18] / e3 usb2.overcurrent/usb_func.vbusi programmable, disable selected pwm mibspi3ncs[0]/ad2evt/giob[2]/ n2het2_pin_ndis v10 i/o pullup 20 a outputs 26 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.3 general-purpose input/output (gpio) table 4-24. zwt general-purpose input/output (gpio) terminal reset signal pull pull type description 337 type signal name state zwt gioa[0] /usb2.vp/usb_func.rxdpi a5 gioa[1] /usb2.vm/usb_func.rxdmi c2 gioa[2] /usb2.txdat/usb_func.txdo/n2het2[0] c1 gioa[3] /n2het2[2] e1 gioa[4] a6 gioa[5] /extclkin/n2het1_pin_ndis b5 gioa[6] /n2het2[4] h3 general-purpose i/o. all gpio terminals are gioa[7] /n2het2[6] m1 programmable, pulldown capable of generating 20 a giob[0] /usb1.txdat m2 interrupts to the cpu on rising / falling / both edges. giob[1] /usb1.portpower k2 giob[2] f2 i/o giob[3] /usb2.rcv /usb_func.rxdi w10 giob[4] g1 giob[5] g2 giob[6] j2 giob[7] f1 the application cannot output a level onto this terminal when it is configured as fixed 20 a giob[2]. a pullup is enabled mibspi3ncs[0]/ad2evt/ giob[2] /n2het2_pin_ndis v10 pullup pulldown on this input. this pull cannot be disabled, and is not programmable using the gio module pull control registers copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 27 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.4 controller area network controllers (dcans) table 4-25. zwt controller area network controllers (dcans) terminal reset signal pull pull type description 337 type signal name state zwt can1rx b10 can1 receive, or gpio can1tx a10 can1 transmit, or gpio can2rx h1 can2 receive, or gpio programmable, i/o pullup 20 a can2tx h2 can2 transmit, or gpio can3rx m19 can3 receive, or gpio can3tx m18 can3 transmit, or gpio 4.3.2.5 local interconnect network interface module (lin) table 4-26. zwt local interconnect network interface module (lin) terminal reset signal pull pull type description 337 type signal name state zwt linrx a7 lin receive, or gpio programmable, i/o pullup 20 a lintx b7 lin transmit, or gpio 4.3.2.6 standard serial communication interface (sci) table 4-27. zwt standard serial communication interface (sci) terminal reset signal pull pull type description 337 type signal name state zwt n2het1[6]/ scirx w3 sci receive, or gpio programmable, i/o pulldown 20 a n2het1[13]/ scitx n2 sci transmit, or gpio 28 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.7 inter-integrated circuit interface module (i2c) table 4-28. zwt inter-integrated circuit interface module (i2c) terminal reset signal pull pull type description 337 type signal name state zwt mibspi3ncs[2]/ i2c_sda /n2het1[27] b2 i2c serial data, or gpio programmable, i/o pullup 20 a mibspi3ncs[3]/ i2c_scl /n2het1[29] c3 i2c serial clock, or gpio 4.3.2.8 standard serial peripheral interface (spi) table 4-29. zwt standard serial peripheral interface (spi) terminal reset signal pull pull type description 337 type signal name state zwt spi2clk e2 spi2 clock, or gpio spi2ncs[0] n3 spi2 chip select, or gpio spi2nena/ spi2ncs[1] d3 spi2 chip select, or gpio programmable, spi2nena /spi2ncs[1] d3 spi2 enable, or gpio i/o pullup 20 a spi2 slave-input master- spi2simo[0] d1 output, or gpio spi2 slave-output master- spi2somi[0] d2 input, or gpio n2het1[0]/ spi4clk k18 spi4 clock, or gpio n2het1[3]/ spi4ncs[0] /usb2.speed/ u1 spi4 chip select, or gpio usb_func.puenon/n2het2[10] n2het1[1]/ spi4nena /usb2.txen/ v2 programmable, spi4 enable, or gpio usb_func.pueno/n2het2[8] i/o pulldown 20 a spi4 slave-input master- n2het1[2]/ spi4simo[0] w5 output, or gpio spi4 slave-output master- n2het1[5]/ spi4somi[0] /n2het2[12] v6 input, or gpio copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 29 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.9 multibuffered serial peripheral interface modules (mibspi) table 4-30. zwt multibuffered serial peripheral interface modules (mibspi) terminal reset signal pull pull type description 337 type signal name state zwt mibspi1clk f18 mibspi1 clock, or gpio mibspi1ncs[0] /mibspi1somi[1] /mii_txd[2]/ r2 usb1.rcv programmable, mibspi1ncs[1] /n2het1[17] /mii_col/ pullup f3 20 a mibspi1 chip select, or gpio usb1.suspend mibspi1ncs[2] /n2het1[19] /mdio g3 mibspi1ncs[3] /n2het1[21] j3 n2het1[15]/ mibspi1ncs[4] n1 programmable, pulldown mibspi1 chip select, or gpio 20 a n2het1[24]/ mibspi1ncs[5] /mii_rxd[0]/rmii_rxd[0] p1 i/o mibspi1nena /n2het1[23] /mii_rxd[2]/ g19 mibspi1 enable, or gpio usb1.vp programmable, pullup 20 a mibspi1 slave-in master-out, mibspi1simo[0] f19 or gpio programmable, mibspi1 slave-in master-out, n2het1[8]/ mibspi1simo[1] /mii_txd[3]/usb1.overcurrent e18 pulldown 20 a or gpio mibspi1somi[0] g18 programmable, mibspi1 slave-out master-in, pullup mibspi1ncs[0]/ mibspi1somi[1] /mii_txd[2]/ 20 a or gpio r2 usb1.rcv mibspi3clk v9 mibspi3 clock, or gpio mibspi3ncs[0] /ad2evt/giob[2]/n2het2_pin_ndis v10 programmable, mibspi3ncs[1] /n2het1[25]/mdclk v5 pullup 20 a mibspi3 chip select, or gpio mibspi3ncs[2] /i2c_sda/n2het1[27] b2 mibspi3ncs[3] /i2c_scl/n2het1[29] c3 n2het1[11]/ mibspi3ncs[4] /n2het2[18] / programmable, e3 pulldown mibspi3 chip select, or gpio i/o usb2.overcurrent/usb_func.vbusi 20 a mibspi3nena/ mibspi3ncs[5] /n2het1[31] w9 mibspi3 chip select, or gpio mibspi3nena /mibspi3ncs[5]/n2het1[31] w9 mibspi3 enable, or gpio programmable, mibspi3 slave-in master-out, pullup mibspi3simo[0] w8 20 a or gpio mibspi3 slave-out master-in, mibspi3somi[0] v8 or gpio mibspi5clk /dmm_data[4] /mii_txen/rmii_txen h19 mibspi5 clock, or gpio mibspi5ncs[0] /dmm_data[5] e19 mibspi5ncs[1] /dmm_data[6] b6 mibspi5 chip select, or gpio mibspi5ncs[2] /dmm_data[2] w6 mibspi5ncs[3] /dmm_data[3] t12 mibspi5nena /dmm_data[7] /mii_rxd[3]/ h18 mibspi5 enable, or gpio usb1.vm programmable, mibspi5simo[0] /dmm_data[8] /mii_txd[1]/rmii_txd[1] j19 i/o pullup 20 a mibspi5simo[1] /dmm_data[9] e16 mibspi5simo[2] /dmm_data[10] h17 mibspi5simo[3] /dmm_data[11] g17 mibspi5 slave-in master-out, or gpio mibspi5somi[0] /dmm_data[12] /mii_txd[0]/rmii_txd[0] j18 mibspi5somi[1] /dmm_data[13] e17 mibspi5somi[2] /dmm_data[14] h16 mibspi5somi[3] /dmm_data[15] g16 30 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.10 ethernet controller table 4-31. zwt ethernet controller: mdio interface terminal reset signal pull pull type description 337 type signal name state zwt mibspi3ncs[1]/n2het1[25]/ mdclk v5 output pullup none serial clock output mibspi1ncs[2]/n2het1[19]/ mdio g3 i/o pullup fixed, 20 a serial data input/output table 4-32. zwt ethernet controller: reduced media independent interface (rmii) terminal reset signal pull pull type description 337 type signal name state zwt rmii carrier sense and n2het1[12]/mii_crs/ rmii_crs_dv b4 receive data valid rmii synchronous reference n2het1[28]/mii_rx_clk/ rmii_refclk /mii_rx_avclk4 k19 clock for receive, transmit and fixed 12 - a control interface input pulldown pulldown ad1evt/mii_rx_er/ rmii_rx_er n19 rmii receive error n2het1[24]/mibspi1ncs[5]/mii_rxd[0]/ rmii_rxd[0] p1 rmii receive data n2het1[26]/mii_rxd[1]/ rmii_rxd[1] a14 mibspi5somi[0]/dmm_data[12]/mii_txd[0]/ rmii_txd[0] j18 rmii transmit data mibspi5simo[0]/dmm_data[8]/mii_txd[1]/ rmii_txd[1] j19 output pullup none mibspi5clk/dmm_data[4]/mii_txen/ rmii_txen h19 rmii transmit enable table 4-33. zwt ethernet controller: media independent interface (mii) terminal reset signal pull pull type description 337 type signal name state zwt mibspi1ncs[1]/n2het1[17]/ mii_col / f3 pullup none collision detect usb1.suspend input fixed 20 - a carrier sense and receive n2het1[12]/ mii_crs /rmii_crs_dv b4 pulldown pulldown data valid n2het1[28]/mii_rx_clk /rmii_refclk/ mii_rx_avclk4 k19 i/o pulldown none mii output receive clock n2het1[30]/ mii_rx_dv /usb1.speed b11 received data valid input ad1evt/ mii_rx_er /rmii_rx_er n19 receive error fixed 20 - a n2het1[28]/ mii_rx_clk /rmii_refclk/mii_rx_avclk4 k19 i/o pulldown receive clock pulldown n2het1[24]/mibspi1ncs[5]/ mii_rxd[0] /rmii_rxd[0] p1 n2het1[26]/ mii_rxd[1] /rmii_rxd[1] a14 mibspi1nena/n2het1[23]/ mii_rxd[2] / input receive data g19 usb1.vp fixed 20 - a pullup pulldown mibspi5nena/dmm_data[7] / mii_rxd[3] / h18 usb1.vm n2het1[10] /mii_tx_clk/ usb1.txen/ d19 mii output transmit clock mii_tx_avclk4 i/o pulldown none n2het1[10]/ mii_tx_clk /usb1.txen d19 transmit clock /mii_tx_avclk4 mibspi5somi[0]/dmm_data[12] / mii_txd[0] /rmii_txd[0] j18 mibspi5simo[0]/dmm_data[8] / mii_txd[1] /rmii_txd[1] j19 pullup none mibspi1ncs[0]/mibspi1somi[1]/ mii_txd[2] / transmit data r2 usb1.rcv output n2het1[8]/mibspi1simo[1]/ mii_txd[3] / e18 pulldown none usb1.overcurrent mibspi5clk/dmm_data[4] / mii_txen /rmii_txen h19 pullup none transmit enable copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 31 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.11 usb host and device port controller interface the usb host controller includes a root hub with two ports. usb1 pin are for root hub port 0. usb2 pins are for root hub port 1. table 4-34. zwt usb host port controller interface (usb1, usb2) terminal reset signal pull pull type description 337 type signal name state zwt active low input, asserted n2het1[8]/mibspi1simo[1]/ mii_txd[3]/ e18 pulldown fixed, 20 a during overcurrent condition usb1.overcurrent from usb power switch usb receive data, converted mibspi1ncs[0]/mibspi1somi[1] /mii_txd[2]/ r2 from differential (d+/d- to usb1.rcv input single ended by transceiver). pullup fixed, 20 a single-ended d ? input, driven mibspi5nena/dmm_data[7] /mii_rxd[3]/ usb1.vm h18 by transceiver mibspi1nena/n2het1[23]/ mii_rxd[2]/ single-ended d+ input, driven g19 usb1.vp by transceiver active-high output enable for giob[1]/ usb1.portpower k2 controlling an external usb power switch transmit speed to usb port pulldown none transceiver. n2het1[30] /mii_rx_dv/ usb1.speed b11 0 = low speed 1 = full speed this signal indicates the state of the port, active or suspend. mibspi1ncs[1]/n2het1[17]/ mii_col/ f3 pullup none output usb1.suspend 0 = active 1 = suspend single-ended usb data output to usb transceiver. giob[0]/ usb1.txdat m2 use in combination with usb1.txse0 n2het1[10] /mii_tx_clk/ usb1.txen / pulldown none active-low output transmit d19 mii_tx_avclk4 enable to port transceiver active high output ? instructs n2het1[14]/ usb1.txse0 a11 transceiver to transmit single- ended zero active-low input, asserted n2het1[11]/mibspi3ncs[4]/n2het2[18]/ e3 pullup fixed, 20 a during overcurrent condition usb2.overcurrent /usb_func.vbusi from usb power switchg receive data from usb port transceiver. this signal is giob[3]/ usb2.rcv /usb_func.rxdi w10 generated from d+, d ? input differential lines of the usb cable. pulldown fixed, 20 a single-ended d ? input, driven gioa[1]/ usb2.vm /usb_func.rxdmi c2 by transceiver single-ended d+ input, driven gioa[0]/ usb2.vp /usb_func.rxdpi a5 by transceiver. 32 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 4-34. zwt usb host port controller interface (usb1, usb2) (continued) terminal reset signal pull pull type description 337 type signal name state zwt active-high output enable for n2het1[7]/ usb2.portpower / t1 controlling an external usb usb_func.gzo/n2het2[14] power switch transmit speed to usb port transceiver. n2het1[3]/spi4ncs[0]/ usb2.speed / u1 usb_func.puenon/n2het2[10] 0 = low speed 1 = full speed. this signal indicates the state of the port, active or suspend. n2het1[9]/n2het2[16]/ usb2.suspend / v7 output pulldown none usb_func.suspendo 0 = active 1 = suspend single-ended usb data output to usb transceiver. gioa[2]/ usb2.txdat /usb_func.txdo/n2het2[0] c1 use in combination with usb2.txse0 n2het1[1]/spi4nena/ usb2.txen / active-low output; transmit v2 usb_func.pueno/n2het2[8] enable to port transceiver active high output ? instructs n2het1[22]/ usb2.txse0 /usb_func.se0o b3 transceiver to transmit single- ended zero.r table 4-35. zwt usb device port controller interface (usb_func) terminal reset signal pull pull type description 337 type signal name state zwt usb device transmit enable to n2het1[7]/usb2.portpower/ usb_func.gzo /n2het2[14] t1 port transceiver pullup enable, allows for n2het1[1]/spi4nena/usb2.txen/ usb_func.pueno / v2 output pulldown none software-programmable usb n2het2[8] device connect/disconnect n2het1[3]/spi4ncs[0]/usb2.speed/ usb_func.puenon / u1 pueno inverted n2het2[10] usb receive data, converted giob[3]/usb2.rcv/ usb_func.rxdi w10 from differential (d+/d ? to single ended by transceiver). fixed 20 - a input pulldown single-ended d ? input, driven gioa[1]/usb2.vm/ usb_func.rxdmi c2 pullup by transceiver single-ended d+ input, driven gioa[0]/usb2.vp/ usb_func.rxdpi a5 by transceiver active-high output ? instructs n2het1[22]/usb2.txse0/ usb_func.se0o b3 transceiver to transmit single- ended zero. active-high output ? usb device suspend output. this n2het1[9]/n2het2[16]/usb2.suspend/ usb_func.suspendo v7 function is asserted when the output pulldown none usb bus has detected an idle mode during 5 ms. single ended usb data output to usb transceiver. gioa[2]/usb2.txdat/ usb_func.txdo /n2het2[0] c1 use in combination with usb_func.se0o must be pulled up or down to reflect the state of power on n2het1[11]/mibspi3ncs[4]/n2het2[18]/ fixed 20 - a e3 input pulldown the vbus terminal of the usb usb2.overcurrent/ usb_func.vbusi pulldown device connector. this terminal is not 5v tolerant. copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 33 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.12 external memory interface (emif) table 4-36. external memory interface (emif) terminal reset signal pull pull type description 337 type signal name state zwt emif_cke l3 output none emif clock enable emif clock. this is an output signal in functional mode. it is pulldown gated off by default, so that emif_clk k3 i/o none the signal is tri-stated. pinmux29[8] must be cleared to enable this output. etmdata[13]/ emif_noe e12 pulldown none emif output enable fixed 20 - a emif_nwait p3 i/o pullup emif extended wait signal pullup emif_nwe d17 output emif write enable. emif_ncas r4 output pullup emif column address strobe emif_nras r3 output emif row address strobe emif_ncs[0] /rtp_data[15]/n2het2[7] n17 output pulldown emif chip select, sdram emif_ncs[2] l17 output pullup emif chip selects, asynchronous emif_ncs[3] /rtp_data[14]/n2het2[9] k17 output pulldown this applies to chip selects 2, 3, and 4 emif_ncs[4] /rtp_data[7] m17 output pullup etmdata[15]/ emif_ndqm[0] e10 output emif data mask or write strobe. data mask for sdram devices, write strobe for etmdata[14]/ emif_ndqm[1] e11 output connected asynchronous devices. emif bank address or etmdata[12]/ emif_ba[0] e13 output address line emif bank address or emif_ba[1] /n2het2[5] d16 output address line emif_addr[0] /n2het2[1] d4 output emif_addr[1] /n2het2[3] d5 output etmdata[11]/ emif_addr[2] e6 output etmdata[10]/ emif_addr[3] e7 output none etmdata[9]/ emif_addr[4] e8 output pulldown etmdata[8]/ emif_addr[5] e9 output emif_addr[6] /rtp_data[13]/n2het2[11] c4 output emif_addr[7] /rtp_data[12]/n2het2[13] c5 output emif_addr[8] /rtp_data[11]/n2het2[15] c6 output emif_addr[9] /rtp_data[10] c7 output emif_addr[10] /rtp_data[9] c8 output emif address emif_addr[11] /rtp_data[8] c9 output emif_addr[12] /rtp_data[6] c10 output emif_addr[13] /rtp_data[5] c11 output emif_addr[14] /rtp_data[4] c12 output emif_addr[15] /rtp_data[3] c13 output emif_addr[16] /rtp_data[2] d14 output emif_addr[17] /rtp_data[1] c14 output emif_addr[18] /rtp_data[0] d15 output emif_addr[19] /rtp_nena c15 output pulldown emif_addr[20] /rtp_nsync c16 output emif_addr[21] /rtp_clk c17 output 34 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 4-36. external memory interface (emif) (continued) terminal reset signal pull pull type description 337 type signal name state zwt etmdata[16]/ emif_data[0] k15 i/o etmdata[17]/ emif_data[1] l15 i/o etmdata[18]/ emif_data[2] m15 i/o etmdata[19]/ emif_data[3] n15 i/o etmdata[20]/ emif_data[4] e5 i/o etmdata[21]/ emif_data[5] f5 i/o etmdata[22]/ emif_data[6] g5 i/o etmdata[23]/ emif_data[7] k5 i/o fixed 20 - a pulldown emif data pullup etmdata[24]/ emif_data[8] l5 i/o etmdata[25]/ emif_data[9] m5 i/o etmdata[26]/ emif_data[10] n5 i/o etmdata[27]/ emif_data[11] p5 i/o etmdata[28]/ emif_data[12] r5 i/o etmdata[29]/ emif_data[13] r6 i/o etmdata[30]/ emif_data[14] r7 i/o etmdata[31]/ emif_data[15] r8 i/o copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 35 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.13 embedded trace macrocell for cortex-r4f cpu (etm-r4f) table 4-37. embedded trace macrocell for cortex-r4f cpu (etm-r4f) terminal reset signal pull pull type description 337 type signal name state zwt fixed 20 - a etmtraceclkin /extclkin2 r9 input pulldown etm trace clock input pullup etmtraceclkout r10 etm trace clock output etmtracectl r11 etm trace control etmdata[0] r12 etmdata[1] r13 etmdata[2] j15 etmdata[3] h15 etmdata[4] g15 etmdata[5] f15 etmdata[6] e15 etmdata[7] e14 etmdata[8] /emif_addr[5] e9 etmdata[9] /emif_addr[4] e8 etmdata[10] /emif_addr[3] e7 etmdata[11] /emif_addr[2] e6 etmdata[12] /emif_ba[0] e13 etmdata[13] /emif_noe e12 etmdata[14] /emif_ndqm[1] e11 output pulldown none etmdata[15] /emif_ndqm[0] e10 etm data etmdata[16] /emif_data[0] k15 etmdata[17] /emif_data[1] l15 etmdata[18] /emif_data[2] m15 etmdata[19] /emif_data[3] n15 etmdata[20] /emif_data[4] e5 etmdata[21] /emif_data[5] f5 etmdata[22] /emif_data[6] g5 etmdata[23] /emif_data[7] k5 etmdata[24] /emif_data[8] l5 etmdata[25] /emif_data[9] m5 etmdata[26] /emif_data[10] n5 etmdata[27] /emif_data[11] p5 etmdata[28] /emif_data[12] r5 etmdata[29] /emif_data[13] r6 etmdata[30] /emif_data[14] r7 etmdata[31] /emif_data[15] r8 36 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.14 ram trace port (rtp) table 4-38. ram trace port (rtp) terminal reset signal pull pull type description 337 type signal name state zwt emif_addr[21]/ rtp_clk c17 i/o rtp packet clock, or gpio rtp packet handshake, or emif_addr[19]/ rtp_nena c15 i/o gpio emif_addr[20]/ rtp_nsync c16 i/o rtp synchronization, or gpio emif_addr[18]/ rtp_data[0] d15 programmable, emif_addr[17]/ rtp_data[1] c14 pulldown 20 a emif_addr[16]/ rtp_data[2] d14 emif_addr[15]/ rtp_data[3] c13 emif_addr[14]/ rtp_data[4] c12 emif_addr[13]/ rtp_data[5] c11 emif_addr[12]/ rtp_data[6] c10 programmable, emif_ncs[4]/ rtp_data[7] m17 pullup 20 a i/o rtp packet data, or gpio emif_addr[11]/ rtp_data[8] c9 emif_addr[10]/ rtp_data[9] c8 emif_addr[9]/ rtp_data[10] c7 emif_addr[8]/ rtp_data[11] /n2het2[15] c6 programmable, pulldown 20 a emif_addr[7]/ rtp_data[12] /n2het2[13] c5 emif_addr[6]/ rtp_data[13] /n2het2[11] c4 emif_ncs[0]/ rtp_data[15] /n2het2[7] n17 emif_ncs[3]/ rtp_data[14] /n2het2[9] k17 copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 37 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.15 data modification module (dmm) table 4-39. data modification module (dmm) terminal reset signal pull pull type description 337 type signal name state zwt dmm_clk f17 dmm clock, or gpio dmm_nena f16 dmm handshake, or gpio dmm synchronization, or dmm_sync j16 gpio dmm_data[0] l19 dmm_data[1] l18 mibspi5ncs[2]/ dmm_data[2] w6 mibspi5ncs[3]/ dmm_data[3] t12 mibspi5clk/ dmm_data[4] /mii_txen/rmii_txen h19 mibspi5ncs[0]/ dmm_data[5] e19 programmable, i/o pullup mibspi5ncs[1]/ dmm_data[6] b6 20 a mibspi5nena/ dmm_data[7] /mii_rxd[3]/usb1.vm h18 dmm data, or gpio mibspi5simo[0]/ dmm_data[8] /mii_txd[1]/rmii_txd[1] j19 mibspi5simo[1]/ dmm_data[9] e16 mibspi5simo[2]/ dmm_data[10] h17 mibspi5simo[3]/ dmm_data[11] g17 mibspi5somi[0]/ dmm_data[12] /mii_txd[0]/rmii_txd[0] j18 mibspi5somi[1]/ dmm_data[13] e17 mibspi5somi[2]/ dmm_data[14] h16 mibspi5somi[3]/ dmm_data[15] g16 38 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.16 system module interface table 4-40. zwt system module interface terminal reset signal pull pull type description 337 type signal name state zwt power-on reset, cold reset external power supply monitor circuitry must drive nporrst fixed 100 - a low when any of the supplies nporrst w7 input pulldown pulldown to the microcontroller fall out of the specified range. this terminal has a glitch filter. see section 6.8 . system reset, warm reset, bidirectional. the internal circuitry indicates any reset condition by driving nrst low. the external circuitry can assert a system reset by fixed 100 - a nrst b17 i/o pullup driving nrst low. to ensure pullup that an external reset is not arbitrarily generated, ti recommends that an external pullup resistor is connected to this terminal. this terminal has a glitch filter. see section 6.8 . esm error signal fixed 20 - a nerror b14 i/o pulldown indicates error of high pulldown severity. see section 6.18 . 4.3.2.17 clock inputs and outputs table 4-41. zwt clock inputs and outputs terminal reset signal pull pull type description 337 type signal name state zwt from external oscin k1 input crystal/resonator, or external clock input n/a none kelvin_gnd l2 input kelvin ground for oscillator oscout l1 output to external crystal/resonator programmable, external prescaled clock eclk a12 i/o pulldown 20 a output, or gio. gioa[5]/ extclkin /n2het1_pin_ndis b5 input external clock input #1 fixed 20 - a pulldown pulldown etmtraceclkin/ extclkin2 r9 input external clock input #2 1.2-v dedicated core supply for vccpll p11 n/a none power plls copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 39 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.18 test and debug modules interface table 4-42. zwt test and debug modules interface terminal reset signal pull pull type description 337 type signal name state zwt test enable. this terminal must be connected to ground test u2 i/o fixed 100 - a directly or through a pulldown pulldown pulldown resistor. ntrst d18 input jtag test hardware reset rtck a16 output n/a none jtag return test clock fixed 100 - a tck b18 input pulldown jtag test clock pulldown fixed 100 - a tdi a17 i/o pullup jtag test data in pullup 100 a tdo c18 output none jtag test data out pulldown fixed 100 - a tms c19 i/o pullup jtag test select pullup 4.3.2.19 flash supply and test pads table 4-43. zwt flash supply and test pads terminal reset signal pull pull type description 337 type signal name state zwt 3.3-v vccp f8 n/a none flash pump supply power fltp1 j5 flash test pads. these terminals are reserved for ti use only. for proper operation ? n/a none these terminals must connect fltp2 h5 only to a test pad or not be connected at all [no connect (nc)]. 4.3.2.20 reserved table 4-44. reserved terminal reset signal pull pull type description 337 type signal name state zwt reserved a15 ? n/a none reserved. these balls are connected to internal logic but reserved b15 ? n/a none are not outputs nor do they have internal pulls. they are reserved b16 ? n/a none subject to 1 a leakage reserved a8 ? n/a none current. reserved b8 ? n/a none reserved b9 ? n/a none 40 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.21 no connects table 4-45. no connects terminal reset signal pull pull type description 337 type signal name state zwt nc d6 ? n/a none nc d7 ? n/a none nc d8 ? n/a none nc d9 ? n/a none nc d10 ? n/a none nc d11 ? n/a none nc d12 ? n/a none nc d13 ? n/a none nc e4 ? n/a none nc f4 ? n/a none nc g4 ? n/a none nc k4 ? n/a none nc k16 ? n/a none nc l4 ? n/a none nc l16 ? n/a none nc m4 ? n/a none nc m16 ? n/a none nc n4 ? n/a none nc n16 ? n/a none no connects. these balls are nc n18 ? n/a none not connected to any internal logic and can be connected to nc p4 ? n/a none the pcb ground without affecting the functionality of nc p15 ? n/a none the device. nc p16 ? n/a none nc p17 ? n/a none nc r1 ? n/a none nc r14 ? n/a none nc r15 ? n/a none nc t2 ? n/a none nc t3 ? n/a none nc t4 ? n/a none nc t5 ? n/a none nc t6 ? n/a none nc t7 ? n/a none nc t8 ? n/a none nc t9 ? n/a none nc t10 ? n/a none nc t11 ? n/a none nc t13 ? n/a none nc t14 ? n/a none nc u3 ? n/a none nc u4 ? n/a none copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 41 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 4-45. no connects (continued) terminal reset signal pull pull type description 337 type signal name state zwt nc u5 ? n/a none nc u6 ? n/a none nc u7 ? n/a none nc u8 ? n/a none nc u9 ? n/a none nc u10 ? n/a none no connects. these balls are nc u11 ? n/a none not connected to any internal nc u12 ? n/a none logic and can be connected to the pcb ground without nc v3 ? n/a none affecting the functionality of nc v4 ? n/a none the device. nc v11 ? n/a none nc v12 ? n/a none nc w4 ? n/a none nc w11 ? n/a none nc w12 ? n/a none nc w13 ? n/a none 4.3.2.22 supply for core logic: 1.2-v nominal table 4-46. zwt supply for core logic: 1.2-v nominal terminal reset signal pull pull type description 337 type signal name state zwt vcc f9 vcc f10 vcc h10 vcc j14 vcc k6 1.2-v vcc k8 n/a none core supply power vcc k12 vcc k14 vcc l6 vcc m10 vcc p10 42 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 4.3.2.23 supply for i/o cells: 3.3-v nominal table 4-47. zwt supply for i/o cells: 3.3-v nominal terminal reset signal pull pull type description 337 type signal name state zwt vccio f6 vccio f7 vccio f11 vccio f12 vccio f13 vccio f14 vccio g6 vccio g14 vccio h6 vccio h14 vccio j6 3.3-v vccio l14 n/a none operating supply for i/os power vccio m6 vccio m14 vccio n6 vccio n14 vccio p6 vccio p7 vccio p8 vccio p9 vccio p12 vccio p13 vccio p14 copyright ? 2011 ? 2015, texas instruments incorporated terminal configuration and functions 43 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 4.3.2.24 ground reference for all supplies except vccad table 4-48. zwt ground reference for all supplies except vccad terminal reset signal pull pull type description 337 type signal name state zwt vss a1 vss a2 vss a18 vss a19 vss b1 vss b19 vss h8 vss h9 vss h11 vss h12 vss j8 vss j9 vss j10 vss j11 vss j12 ground n/a none ground reference vss k9 vss k10 vss k11 vss l8 vss l9 vss l10 vss l11 vss l12 vss m8 vss m9 vss m11 vss m12 vss v1 vss w1 vss w2 44 terminal configuration and functions copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 5 specifications 5.1 absolute maximum ratings (1) over operating free-air temperature range min max unit v cc (2) ? 0.3 1.43 supply voltage v ccio , v ccp (2) ? 0.3 4.6 v v ccad ? 0.3 6.25 all input pins ? 0.3 4.6 input voltage v adc input pins ? 0.3 6.25 i ik (v i < 0 or v i > v ccio ) ? 20 20 all pins, except ad1in[23:0] and ad2in[15:0] ma input clamp current i ik (v i < 0 or v i > v ccad ) ? 10 10 ad1in[23:0] and ad2in[15:0] total ? 40 40 ma operating free-air temperature, t a : ? 40 105 c operating junction temperature, t j : ? 40 130 c storage temperature, t stg ? 65 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) maximum-rated conditions for extended periods may affect device reliability. all voltage values are with respect to their associated grounds. 5.2 esd ratings value unit human body model (hbm), per ansi/esda/jedec js001 (1) 2 kv v esd electrostatic discharge (esd) performance: charged device model (cdm), per jesd22-c101 (2) all pins 250 v (1) jedec document jep155 states that 500-v hbm allows safe manufacturing with a standard esd control process. (2) jedec document jep157 states that 250-v cdm allows safe manufacturing with a standard esd control process. 5.3 power-on hours (poh) (1) (2) junction nominal core voltage (v cc ) lifetime poh temperature (tj) 1.2 105 o c 100k (1) this information is provided solely for your convenience and does not extend or modify the warranty provided under ti ' s standard terms and conditions for ti semiconductor products. (2) to avoid significant degradation, the device power-on hours (poh) must be limited to those specified in this table. to convert to equivalent poh for a specific temperature profile, see the calculating equivalent power-on-hours for hercules safety mcus application report ( spna207 ). copyright ? 2011 ? 2015, texas instruments incorporated specifications 45 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 5.4 recommended operating conditions (1) min nom max unit v cc digital logic supply voltage (core) 1.14 1.2 1.32 v v ccpll pll supply voltage 1.14 1.2 1.32 v v ccio digital logic supply voltage (i/o) 3 3.3 3.6 v v ccad mibadc supply voltage 3 3.3/5.0 5.25 v v ccp flash pump supply voltage 3 3.3 3.6 v v ss digital logic supply ground 0 v v ssad mibadc supply ground ? 0.1 0.1 v v adrefhi a-to-d high-voltage reference source v ssad v ccad v v adreflo a-to-d low-voltage reference source v ssad v ccad v v slew maximum positive slew rate for v ccio , v ccad and v ccp supplies 1 v/ s t a operating free-air temperature 105 c t j operating junction temperature (2) 130 c (1) all voltages are with respect to v ss , except v ccad , which is with respect to v ssad (2) reliability data is based upon a temperature profile that is equivalent to 100,000 power-on hours at 105 c junction temperature. 46 specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 5.5 switching characteristics for clock domains over recommended operating conditions table 5-1. clock domain timing specifications paramet description conditions min max unit er pipeline mode enabled 220 mhz f hclk hclk - system clock frequency pipeline mode disabled 55 mhz f gclk gclk - cpu clock frequency f hclk mhz f vclk vclk - primary peripheral clock frequency 110 mhz vclk2 - secondary peripheral clock f vclk2 110 mhz frequency vclk3 - secondary peripheral clock f vclk3 110 mhz frequency vclka1 - primary asynchronous peripheral f vclka1 100 mhz clock frequency vclka3 - primary asynchronous peripheral f vclka3 48 mhz clock frequency vclka4 - secondary asynchronous f vclka4 50 mhz peripheral clock frequency f rticlk rticlk - clock frequency f vclk mhz 5.6 wait states required figure 5-1. wait states scheme as shown in figure 5-1 , the tcm ram can support program and data fetches at full cpu speed without any address or data wait states required. the tcm flash can support zero address and data wait states up to a cpu speed of 55 mhz in nonpipelined mode. the flash supports a maximum cpu clock speed of 220 mhz in pipelined mode with one address wait state and three data wait states. the flash wrapper defaults to nonpipelined mode with zero address wait state and one random-read data wait state. copyright ? 2011 ? 2015, texas instruments incorporated specifications 47 submit documentation feedback address wait states data wait states ram address wait states data wait states flash 0mhz 0mhz 0mhz 0mhz 110mhz 0 1 3 0 00 165mhz 2 165mhz 1 220mhz 220mhz 220mhz 220mhz 55mhz
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 5.7 power consumption over recommended operating conditions parameter test conditions min typ max unit f hclk = 220 mhz v cc digital supply current (operating 260 (1) 420 (2) f vclk = 110 mhz, mode) flash in pipelined mode, v ccmax i cc, i ccpll ma v cc digital supply current (lbist mode) lbist clock rate = 110 mhz 690 (3) (4) pbist rom clock frequency = v cc digital supply current (pbist mode) 690 (3) (4) 110 mhz i ccio v ccio supply current (operating mode) no dc load, v ccmax 10 ma single adc operational, v ccadmax 15 i ccad v ccad supply current (operating mode) ma both adcs operational, v ccadmax 30 single adc operational, ad refhimax 3 i adrefhi ad refhi supply current (operating mode) ma both adcs operational, ad refhimax 6 read from 1 bank and program or i ccp v ccp pump supply current 60 ma erase another bank, v ccpmax (1) the typical value is the average current for the nominal process corner and junction temperature of 25 o c. (2) the maximum i cc, value can be derated ? linearly with voltage ? by 1 ma/mhz for lower operating frequency when f hclk = 2 * f vclk ? for lower junction temperature by the equation below where t jk is the junction temperature in kelvin and the result is in milliamperes. 166 - 0.15 e 0.0174 t jk (3) the maximum i cc, value can be derated ? linearly with voltage ? by 1.7 ma/mhz for lower operating frequency when f hclk = 2 * f vclk ? for lower junction temperature by the equation below where t jk is the junction temperature in kelvin and the result is in milliamperes. 166 - 0.15 e 0.0174 t jk (4) lbist and pbist currents are for a short duration, typically less than 10 ms. they are usually ignored for thermal calculations for the device and the voltage regulator 48 specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 5.8 input/output electrical characteristics (1) over recommended operating conditions parameter test conditions min typ max unit v hys input hysteresis all inputs 180 mv v il low-level input voltage all inputs (2) ? 0.3 0.8 v v ih high-level input voltage all inputs (2) 2 v ccio + 0.3 v i ol = i olmax 0.2 v ccio i ol = 50 a, standard 0.2 output mode v ol low-level output voltage v i ol = 50 a, low-emi output mode (see 0.2 v ccio section 5.13 ) i oh = i ohmax 0.8 v ccio i oh = 50 a, standard v ccio ? 0.3 output mode v oh high-level output voltage v i oh = 50 a, low-emi output mode (see 0.8 v ccio section 5.13 ) v i < v ssio ? 0.3 or v i > i ic input clamp current (i/o pins) ? 3.5 3.5 ma v ccio + 0.3 i ih pulldown 20 a v i = v ccio 5 40 i ih pulldown 100 a v i = v ccio 40 195 i i input current (i/o pins) i il pullup 20 a v i = v ss ? 40 ? 5 a i il pullup 100 a v i = v ss ? 195 ? 40 all other pins no pullup or pulldown ? 1 1 c i input capacitance 2 pf c o output capacitance 3 pf (1) source currents (out of the device) are negative while sink currents (into the device) are positive. (2) this does not apply to the nporrst pin. copyright ? 2011 ? 2015, texas instruments incorporated specifications 49 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 5.9 thermal resistance characteristics table 5-2 shows the thermal resistance characteristics for the qfp - pge mechanical package. table 5-3 shows the thermal resistance characteristics for the bga - zwt mechanical package. table 5-2. thermal resistance characteristics (pge package) c / w junction-to-free air thermal resistance, still air using jedec 2s2p test r ja 39 board r jb junction-to-board thermal resistance 26.3 r jc junction-to-case thermal resistance 6.7 jt junction-to-package top, still air 0.10 table 5-3. thermal resistance characteristics (zwt package) c / w junction-to-free air thermal resistance, still air (includes 5 5 thermal via r ja 18.8 cluster in 2s2p pcb connected to first ground plane) r jb junction-to-board thermal resistance 14.1 r jc junction-to-case thermal resistance 7.1 junction-to-package top, still air (includes 5 5 thermal via cluster in jt 0.33 2s2p pcb connected to first ground plane) 50 specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 5.10 output buffer drive strengths table 5-4. output buffer drive strengths low-level output current, i ol for v i =v olmax or signals high-level output current, i oh for v i =v ohmin mibspi5clk, mibspi5somi[0], mibspi5somi[1], mibspi5somi[2], mibspi5somi[3], mibspi5simo[0], mibspi5simo[1], mibspi5simo[2], mibspi5simo[3], tms, tdi, tdo, rtck, 8 ma spi4clk, spi4simo, spi4somi, nerror, n2het2[1], n2het2[3], all emif outputs and i/os, all etm outputs mibspi3somi, mibspi3simo, mibspi3clk, mibspi1simo, mibspi1somi, mibspi1clk, 4 ma nrst ad1evt, can1rx, can1tx, can2rx, can2tx, can3rx, can3tx, dmm_clk, dmm_data[0], dmm_data[1], dmm_nena, dmm_sync, gioa[0-7], giob[0-7], linrx, lintx, 2 ma zero-dominant mibspi1ncs[0], mibspi1ncs[1-3], mibspi1nena, mibspi3ncs[0-3], mibspi3nena, mibspi5ncs[0-3], mibspi5nena, n2het1[0-31], n2het2[0], n2het2[2], n2het2[4], n2het2[5], n2het2[6], n2het2[7], n2het2[8], n2het2[9], n2het2[10], n2het2[11], n2het2[12], n2het2[13], n2het2[14], n2het2[15], n2het2[16], n2het2[18], spi2ncs[0], spi2nena, spi4ncs[0], spi4nena eclk, selectable 8 ma/2 ma spi2clk, spi2simo, spi2somi the default output buffer drive strength is 8 ma for these signals. table 5-5. selectable 8 ma/2 ma control signal control bit address 8 ma 2 ma eclk syspc10[0] 0xffffff78 0 1 spi2clk spi2pc9[9] (1) 0xfff7f668 0 1 spi2simo spi2pc9[10] (1) 0xfff7f668 0 1 spi2somi spi2pc9[11] (1) 0xfff7f668 0 1 (1) either spi2pc9[11] or spi2pc9[24] can change the output strength of the spi2somi pin. in case of a 32-bit write where these 2 bits differ, spi2pc9[11] determines the drive strength. copyright ? 2011 ? 2015, texas instruments incorporated specifications 51 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 5.11 input timings figure 5-2. ttl-level inputs table 5-6. timing requirements for inputs (1) min max unit t pw input minimum pulse width t c(vclk) + 10 (2) ns (1) t c(vclk) = peripheral vbus clock cycle time = 1 / f (vclk) (2) the timing shown in figure 5-2 is only valid for pins used in gpio mode. 5.12 output timings table 5-7. switching characteristics for output timings versus load capacitance (c l ) parameter min max unit cl = 15 pf 2.5 cl = 50 pf 4 rise time, t r cl = 100 pf 7.2 cl = 150 pf 12.5 8 ma low emi pins ns (see table 5-4 ) cl = 15 pf 2.5 cl = 50 pf 4 fall time, t f cl = 100 pf 7.2 cl = 150 pf 12.5 cl = 15 pf 5.6 cl = 50 pf 10.4 rise time, t r cl = 100 pf 16.8 cl = 150 pf 23.2 4 ma low emi pins ns (see table 5-4 ) cl = 15 pf 5.6 cl= 50 pf 10.4 fall time, t f cl = 100 pf 16.8 cl = 150 pf 23.2 cl = 15 pf 8 cl = 50 pf 15 rise time, t r cl = 100 pf 23 cl = 150 pf 33 2 ma-z low emi pins ns (see table 5-4 ) cl = 15 pf 8 cl = 50 pf 15 fall time, t f cl = 100 pf 23 cl = 150 pf 33 52 specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback v ccio v ih v ih v il 0 input t pw v il
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 5-7. switching characteristics for output timings versus load capacitance (c l ) (continued) parameter min max unit cl = 15 pf 2.5 cl = 50 pf 4 rise time, t r cl = 100 pf 7.2 cl = 150 pf 12.5 8 ma mode ns cl = 15 pf 2.5 cl = 50 pf 4 fall time, t f cl = 100 pf 7.2 cl = 150 pf 12.5 selectable 8 ma/2 ma-z pins (see table 5-4 ) cl = 15 pf 8 cl = 50 pf 15 rise time, t r cl = 100 pf 23 cl = 150 pf 33 2 ma-z mode ns cl = 15 pf 8 cl = 50 pf 15 fall time, t f cl = 100 pf 23 cl = 150 pf 33 figure 5-3. cmos-level outputs table 5-8. timing requirements for outputs (1) min max unit delay between low-to-high, or high-to-low transition of general-purpose output t d(parallel_out) signals that can be configured by an application in parallel, for example, all signals in 5 ns a gioa port, or all n2het1 signals, and so forth. (1) this specification does not account for any output buffer drive strength differences or any external capacitive loading differences. check table 5-4 for output buffer drive strength information on each signal. copyright ? 2011 ? 2015, texas instruments incorporated specifications 53 submit documentation feedback t f t r v ccio v oh v oh v ol v ol 0 output
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 5.13 low-emi output buffers the low-emi output buffer has been designed explicitly to address the issue of decoupling sources of emissions from the pins which they drive. this is accomplished by adaptively controlling the impedance of the output buffer, and is particularly effective with capacitive loads. this is not the default mode of operation of the low-emi output buffers and must be enabled by setting the system module gpcr1 register for the desired module or signal, as shown in table 5-9 . the adaptive impedance control circuit monitors the dc bias point of the output signal. the buffer internally generates two reference levels, vreflow and vrefhigh, which are set to approximately 10% and 90% of vccio, respectively. once the output buffer has driven the output to a low level, if the output voltage is below vreflow, then the impedance of the output buffer will increase to hi-z. a high degree of decoupling between the internal ground bus and the output pin will occur with capacitive loads, or any load in which no current is flowing, for example, the buffer is driving low on a resistive path to ground. current loads on the buffer which try to pull the output voltage above vreflow will be opposed by the impedance of the output buffer so as to maintain the output voltage at or below vreflow. conversely, once the output buffer has driven the output to a high level, if the output voltage is above vrefhigh then the impedance of the output buffer will again increase to hi-z. a high degree of decoupling between internal power bus ad output pin will occur with capacitive loads or any loads in which no current is flowing, for example, buffer is driving high on a resistive path to vccio. current loads on the buffer which try to pull the output voltage below vrefhigh will be opposed by the impedance of the buffer output so as to maintain the output voltage at or above vrefhigh. the bandwidth of the control circuitry is relatively low, so that the output buffer in adaptive impedance control mode cannot respond to high-frequency noise coupling into the power buses of the buffer. in this manner, internal bus noise approaching 20% peak-to-peak of vccio can be rejected. unlike standard output buffers which clamp to the rails, an output buffer in impedance control mode will allow a positive current load to pull the output voltage up to vccio + 0.6 v without opposition. also, a negative current load will pull the output voltage down to vssio ? 0.6 v without opposition. this is not an issue because the actual clamp current capability is always greater than the ioh / iol specifications. the low-emi output buffers are automatically configured to be in the standard buffer mode when the device enters a low-power mode. table 5-9. low-emi output buffer hookup control register to module or signal name enable low-emi mode module: mibspi1 gpreg1.0 module: spi2 gpreg1.1 module: mibspi3 gpreg1.2 reserved gpreg1.3 reserved gpreg1.4 reserved gpreg1.5 reserved gpreg1.6 reserved gpreg1.7 signal: tms gpreg1.8 signal: tdi gpreg1.9 signal: tdo gpreg1.10 signal: rtck gpreg1.11 signal: test gpreg1.12 signal: nerror gpreg1.13 54 specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 5-9. low-emi output buffer hookup (continued) control register to module or signal name enable low-emi mode reserved gpreg1.14 reserved gpreg1.15 copyright ? 2011 ? 2015, texas instruments incorporated specifications 55 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6 system information and electrical specifications 6.1 device power domains the device core logic is split up into multiple power domains in order to optimize the power for a given application use case. there are eight core power domains in total: pd1, pd2, pd3, pd4, pd5, ram_pd1, ram_pd2, and ram_pd3. the actual contents of these power domains are indicated in section 1.4 . pd1 is an "always-on" power domain, which cannot be turned off. each of the other core power domains can be turned on/off one time during device initialization as per the application requirement. refer to the power management module (pmm) chapter of rm48x technical reference manual ( spnu503 ) for more details. note the clocks to a module must be turned off before powering down the core domain that contains the module. note the logic in the modules that are powered down lose power completely. any access to modules that are powered down results in an abort being generated. when power is restored, the modules power up to their default states (after normal power up). no register or memory contents are preserved in the core domains that are turned off. 56 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.2 voltage monitor characteristics a voltage monitor is implemented on this device. the purpose of this voltage monitor is to eliminate the requirement for a specific sequence when powering up the core and i/o voltage supplies. 6.2.1 important considerations ? the voltage monitor does not eliminate the need of a voltage supervisor circuit to guarantee that the device is held in reset when the voltage supplies are out of range. ? the voltage monitor only monitors the core supply (vcc) and the i/o supply (vccio). the other supplies are not monitored by the vmon. for example, if the vccad or vccp are supplied from a source different from that for vccio, then there is no internal voltage monitor for the vccad and vccp supplies. 6.2.2 voltage monitor operation the voltage monitor generates the power good mcu signal (pgmcu) as well as the i/os power good io signal (pgio) on the device. during power-up or power-down processes, the pgmcu and pgio are driven low when the core or i/o supplies are lower than the specified minimum monitoring thresholds. the pgio and pgmcu being low isolates the core logic as well as the i/o controls during power up or power down of the supplies. this allows the core and i/o supplies to be powered up or down in any order. when the voltage monitor detects a low voltage on the i/o supply, it will assert a power-on reset. when the voltage monitor detects an out-of-range voltage on the core supply, it asynchronously makes all output pins high impedance, and asserts a power-on reset. the voltage monitor is disabled when the device enters a low-power mode. the vmon also incorporates a glitch filter for the nporrst input. refer to section 6.3.3.1 for the timing information on this glitch filter. table 6-1. voltage monitoring specifications parameter min typ max unit vcc low - vcc level below this threshold is detected as too 0.75 0.9 1.13 low. voltage monitoring vcc high - vcc level above this threshold is detected as v mon 1.40 1.7 2.1 v thresholds too high. vccio low - vccio level below this threshold is detected 1.85 2.4 2.9 as too low. 6.2.3 supply filtering the vmon has the capability to filter glitches on the vcc and vccio supplies. table 6-2 shows the characteristics of the supply filtering. glitches in the supply larger than the maximum specification cannot be filtered. table 6-2. vmon supply glitch filtering capability parameter min max unit width of glitch on vcc that can be filtered 250 1000 ns width of glitch on vccio that can be filtered 250 1000 ns copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 57 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.3 power sequencing and power on reset 6.3.1 power-up sequence there is no timing dependency between the ramp of the vccio and the vcc supply voltage. the power- up sequence starts with the i/o voltage rising above the minimum i/o supply threshold, (see table 6-4 for more details), core voltage rising above the minimum core supply threshold and the release of power-on reset. the high-frequency oscillator will start up first and its amplitude will grow to an acceptable level. the oscillator start up time is dependent on the type of oscillator and is provided by the oscillator vendor. the different supplies to the device can be powered up in any order. the device goes through the following sequential phases during power up. table 6-3. power-up phases oscillator start-up and validity check 1032 oscillator cycles efuse autoload 1180 oscillator cycles flash pump power up 688 oscillator cycles flash bank power up 617 oscillator cycles total 3517 oscillator cycles the cpu reset is released at the end of the sequence in table 6-3 and fetches the first instruction from address 0x00000000. 58 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.3.2 power-down sequence the different supplies to the device can be powered down in any order. 6.3.3 power-on reset: nporrst this is the power-on reset. this reset must be asserted by an external circuitry whenever the i/o or core supplies are outside the specified recommended range. this signal has a glitch filter on it. it also has an internal pulldown. 6.3.3.1 nporrst electrical and timing requirements table 6-4. electrical requirements for nporrst no. parameter min max unit v ccporl v cc low supply level when nporrst must be active during power up 0.5 v v cc high supply level when nporrst must remain active during power v ccporh 1.14 v up and become active during power down v ccio / v ccp low supply level when nporrst must be active during v ccioporl 1.1 v power up v ccio / v ccp high supply level when nporrst must remain active v ccioporh 3.0 v during power up and become active during power down v il(porrst) low-level input voltage of nporrst v ccio > 2.5v 0.2 * v ccio v low-level input voltage of nporrst v ccio < 2.5v 0.5 v setup time, nporrst active before v ccio and v ccp > v ccioporl during 3 t su(porrst) 0 ms power up 6 t h(porrst) hold time, nporrst active after v cc > v ccporh 1 ms 7 t su(porrst) setup time, nporrst active before v cc < v ccporh during power down 2 s 8 t h(porrst) hold time, nporrst active after v ccio and v ccp > v ccioporh 1 ms 9 t h(porrst) hold time, nporrst active after v cc < v ccporl 0 ms filter time nporrst pin; t f(nporrst) 500 2000 ns pulses less than min will be filtered out, pulses greater than max will generate a reset. figure 6-1. nporrst timing diagram copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 59 submit documentation feedback 3.3 v v ccioporh 1.2 v v ccporh v ccioporl v (1.2 v) v / v (3.3 v) cc ccio ccp nporrst 8 6 6 7 7 9 3 v ccporl v il(porrst) v / v ccio ccp v cc v ccporl v il(porrst) v il v il v il v ccioporh v ccporh v ccioporl note: there is no timing dependency between the ramp of the vccio and the vcc supply voltage; this is just an exemplary drawing.
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.4 warm reset (nrst) this is a bidirectional reset signal. the internal circuitry drives the signal low on detecting any device reset condition. an external circuit can assert a device reset by forcing the signal low. on this terminal, the output buffer is implemented as an open drain (drives low only). to ensure an external reset is not arbitrarily generated, ti recommends that an external pullup resistor is connected to this terminal. this terminal has a glitch filter. it also has an internal pullup 6.4.1 causes of warm reset table 6-5. causes of warm reset device event system status flag power-up reset exception status register, bit 15 oscillator fail global status register, bit 0 pll slip global status register, bits 8 and 9 watchdog exception / debugger reset exception status register, bit 13 cpu reset (driven by the cpu stc) exception status register, bit 5 software reset exception status register, bit 4 external reset exception status register, bit 3 6.4.2 nrst timing requirements table 6-6. nrst timing requirements min max unit t v(rst) valid time, nrst active after nporrst inactive 2256t c(osc) (1) ns valid time, nrst active (all other system reset conditions) 32t c(vclk) t f(nrst) filter time nrst pin; pulses less than min will be filtered out; pulses greater 475 2000 ns than max will generate a reset. see section 6.8 . (1) assumes the oscillator has started up and stabilized before nporrst is released . 60 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.5 arm cortex-r4f cpu information 6.5.1 summary of arm cortex-r4f cpu features the features of the arm cortex-r4f cpu include: ? an integer unit with integral embeddedice-rt logic. ? high-speed advanced microprocessor bus architecture (amba) advanced extensible interfaces (axi) for level two (l2) master and slave interfaces. ? floating point coprocessor ? dynamic branch prediction with a global history buffer, and a 4-entry return stack ? low interrupt latency. ? nonmaskable interrupt. ? a harvard level one (l1) memory system with: ? tightly coupled memory (tcm) interfaces with support for error correction or parity checking memories ? armv7-r architecture memory protection unit (mpu) with 12 regions ? dual core logic for fault detection in safety-critical applications. ? an l2 memory interface: ? single 64-bit master axi interface ? 64-bit slave axi interface to tcm ram blocks ? a debug interface to a coresight debug access port (dap). ? six hardware breakpoints ? two watchpoints ? a trace interface to a coresight etm-r4. ? a performance monitoring unit (pmu). ? a vectored interrupt controller (vic) port. for more information on the arm cortex-r4f cpu see www.arm.com . 6.5.2 arm cortex-r4f cpu features enabled by software the following cpu features are disabled on reset and must be enabled by the application if required. ? ecc on tcm accesses ? hardware vic port ? floating point coprocessor ? mpu 6.5.3 dual core implementation the device has two cortex-r4f cores, where the output signals of both cpus are compared in the ccm- r4 unit. to avoid common mode impacts the signals of the cpus to be compared are delayed by two clock cycles as shown in figure 6-3 . the cpus have a diverse cpu placement given by following requirements: ? different orientation; for example, cpu1 = "north" orientation, cpu2 = "flip west" orientation ? dedicated guard ring for each cpu copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 61 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 6-2. dual-cpu orientation 6.5.4 duplicate clock tree after gclk the cpu clock domain is split into two clock trees, one for each cpu, with the clock of the second cpu running at the same frequency and in phase to the clock of cpu1. see figure 6-3 . 6.5.5 arm cortex-r4f cpu compare module (ccm-r4) for safety this device has two arm cortex-r4f cpu cores, where the output signals of both cpus are compared in the ccm-r4 unit. to avoid common mode impacts the signals of the cpus to be compared are delayed in a different way as shown in figure 6-3 . figure 6-3. dual core implementation to avoid an erroneous ccm-r4 compare error, the application software must initialize the registers of both cpus before the registers are used, including function calls where the register values are pushed onto the stack. 6.5.6 cpu self-test the cpu stc (self-test controller) is used to test the two cortex-r4f cpu cores using the deterministic logic bist controller as the test engine. the main features of the self-test controller are: ? ability to divide the complete test run into independent test intervals 62 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback cpu 1 cpu 2 2 cycle delay 2 cycle delay ccm-r4 ccm-r4 compare cpu1clk cpu2clk compare error input + control output + control north flip west f f
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 ? capable of running the complete test as well as running few intervals at a time ? ability to continue from the last executed interval (test set) as well as ability to restart from the beginning (first test set) ? complete isolation of the self-tested cpu core from rest of the system during the self-test run ? ability to capture the failure interval number ? time-out counter for the cpu self-test run as a fail-safe feature 6.5.6.1 application sequence for cpu self-test 1. configure clock domain frequencies. 2. select number of test intervals to be run. 3. configure the time-out period for the self-test run. 4. enable self-test. 5. wait for cpu reset. 6. in the reset handler, read cpu self-test status to identify any failures. 7. retrieve cpu state if required. for more information see the device specific technical reference manual. 6.5.6.2 cpu self-test clock configuration the maximum clock rate for the self-test is 110 mhz. the stcclk is divided down from the cpu clock. this divider is configured by the stcclkdiv register at address 0xffffe108. for more information see the device specific technical reference manual. 6.5.6.3 cpu self-test coverage table 6-7 shows cpu test coverage achieved for each self-test interval. it also lists the cumulative test cycles. the test time can be calculated by multiplying the number of test cycles with the stc clock period. table 6-7. cpu self-test coverage intervals test coverage, % test cycles 0 0 0 1 62.13 1365 2 70.09 2730 3 74.49 4095 4 77.28 5460 5 79.28 6825 6 80.90 8190 7 82.02 9555 8 83.10 10920 9 84.08 12285 10 84.87 13650 11 85.59 15015 12 86.11 16380 13 86.67 17745 14 87.16 19110 15 87.61 20475 16 87.98 21840 17 88.38 23205 18 88.69 24570 19 88.98 25935 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 63 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-7. cpu self-test coverage (continued) intervals test coverage, % test cycles 20 89.28 27300 21 89.50 28665 22 89.76 30030 23 90.01 31395 24 90.21 32760 64 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.6 clocks 6.6.1 clock sources table 6-8 lists the available clock sources on the device. each of the clock sources can be enabled or disabled using the csdisx registers in the system module. the clock source number in the table corresponds to the control bit in the csdisx register for that clock source. table 6-8 also shows the default state of each clock source. table 6-8. available clock sources clock default source name description state no. 0 oscin main oscillator enabled 1 pll1 output from pll1 disabled 2 reserved reserved disabled 3 extclkin1 external clock input #1 disabled 4 clk80k low-frequency output of internal reference oscillator enabled 5 clk10m high-frequency output of internal reference oscillator enabled 6 pll2 output from pll2 disabled 7 extclkin2 external clock input #2 disabled 6.6.1.1 main oscillator the oscillator is enabled by connecting the appropriate fundamental resonator/crystal and load capacitors across the external oscin and oscout pins as shown in figure 6-4 . the oscillator is a single stage inverter held in bias by an integrated bias resistor. this resistor is disabled during leakage test measurement and low power modes. ti strongly encourages each customer to submit samples of the device to the resonator/crystal vendors for validation. the vendors are equipped to determine what load capacitors will best tune their resonator/crystal to the microcontroller device for optimum start-up and operation over temperature/voltage extremes. an external oscillator source can be used by connecting a 3.3-v clock signal to the oscin pin and leaving the oscout pin unconnected (open) as shown in figure 6-4 . figure 6-4. recommended crystal/clock connection copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 65 submit documentation feedback oscin oscout c1 (see note a) c2 crystal (a) oscin oscout (b) external (toggling 0 v to 3.3 v) clock signal note a: the values of c1 and c2 should be provided by the resonator/crystal vendor. kelvin_gnd note b: kelvin_gnd should not be connected to any other gnd. (see note b)
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.6.1.1.1 timing requirements for main oscillator table 6-9. timing requirements for main oscillator min max unit t c(osc) cycle time, oscin (when using a sine-wave input) 50 200 ns t c(osc_sqr) cycle time, oscin, (when input to the oscin is a square wave ) 50 200 ns t w(oscil) pulse duration, oscin low (when input to the oscin is a square wave) 6 ns t w(oscih) pulse duration, oscin high (when input to the oscin is a square wave) 6 ns 66 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.6.1.2 low-power oscillator (lpo) the lpo is comprised of two oscillators ? hf lpo and lf lpo, in a single macro. 6.6.1.2.1 features the main features of the lpo are: ? supplies a clock at extremely low power for power-saving modes. this is connected as clock source # 4 of the gcm. ? supplies a high-frequency clock for nontiming-critical systems. this is connected as clock source # 5 of the gcm. ? provides a comparison clock for the crystal oscillator failure detection circuit. figure 6-5. lpo block diagram figure 6-5 shows a block diagram of the internal reference oscillator. this is an lpo and provides two clock sources: one nominally 80 khz and one nominally 10 mhz. 6.6.1.2.2 lpo electrical and timing specifications table 6-10. lpo specifications parameter min typ max unit oscillator fail frequency - lower threshold, using 1.375 2.4 4.875 untrimmed lpo output clock detection oscillator fail frequency - higher threshold, using mhz 22 38.4 78 untrimmed lpo output untrimmed frequency 5.5 9 19.5 trimmed frequency 8 9.6 11 mhz lpo - hf oscillator start-up time from standby (lpo bias_en high for (f hflpo ) 10 s at least 900 s) cold start-up time 900 s untrimmed frequency 36 85 180 khz lpo - lf oscillator start-up time from standby (lpo bias_en high for 100 s (f lflpo ) at least 900 s) cold start-up time 2000 s copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 67 submit documentation feedback bias_en low-power oscillator lfen lf_trim hfen hf_trim clk80kclk10m clk10m_valid nporrst
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.6.1.3 phase locked loop (pll) clock modules the pll is used to multiply the input frequency to some higher frequency. the main features of the pll are: ? frequency modulation can be optionally superimposed on the synthesized frequency of pll1. the frequency modulation capability of pll2 is permanently disabled. ? configurable frequency multipliers and dividers. ? built-in pll slip monitoring circuit. ? option to reset the device on a pll slip detection. 6.6.1.3.1 block diagram figure 6-6 shows a high-level block diagram of the two pll macros on this microcontroller. pllctl1 and pllctl2 are used to configure the multiplier and dividers for the pll1. pllctl3 is used to configure the multiplier and dividers for pll2. figure 6-6. zwt pllx block diagram 6.6.1.3.2 pll timing specifications table 6-11. pll timing specifications parameter min max unit f intclk pll1 reference clock frequency 1 20 mhz f post_odclk post-odclk ? pll1 post-divider input clock frequency 400 mhz f vcoclk vcoclk ? pll1 output divider (od) input clock frequency 150 550 mhz f intclk2 pll2 reference clock frequency 1 20 mhz f post_odclk2 post-odclk ? pll2 post-divider input clock frequency 400 mhz f vcoclk2 vcoclk ? pll2 output divider (od) input clock frequency 150 550 mhz 68 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback /nr /1 to /64 oscin pll intclk /od /1 to /8 vcoclk /r /1 to /32 post_odclk /nf /1 to /256 pllclk /nr2 /1 to /64 oscin pll#2 intclk2 /od2 /1 to /8 vcoclk2 /r2 /1 to /32 post_odclk2 /nf2 /1 to /256 pll2clk f pllclk = (f oscin / nr) * nf / (od * r) f pll2clk = (f oscin / nr2) * nf2 / (od2 * r2)
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.6.1.4 external clock inputs the device supports up to two external clock inputs. this clock input must be a square wave input. the electrical and timing requirements for these clock inputs are specified in table 6-12 . the external clock sources are not checked for validity. they are assumed valid when enabled. table 6-12. external clock timing and electrical specifications parameter description min max unit f extclkx external clock input frequency 80 mhz t w(extclkin)h extclk high-pulse duration 6 ns t w(extclkin)l extclk low-pulse duration 6 ns v il(extclkin) low-level input voltage -0.3 0.8 v v ih(extclkin) high-level input voltage 2 vccio + 0.3 v 6.6.2 clock domains 6.6.2.1 clock domain descriptions table 6-13 lists the device clock domains and their default clock sources. the table also shows the system module control register that is used to select an available clock source for each clock domain. table 6-13. clock domain descriptions clock source clock domain default clock selection description name source register hclk oscin ghvsrc ? is disabled via the cddisx registers bit 1 ? used for all system modules including dma, esm gclk oscin ghvsrc ? always the same frequency as hclk ? in phase with hclk ? is disabled separately from hclk through the cddisx registers bit 0 ? can be divided by 1 up to 8 when running cpu self-test (lbist) using the clkdiv field of the stcclkdiv register at address 0xffffe108 gclk2 oscin ghvsrc ? always the same frequency as gclk ? 2 cycles delayed from gclk ? is disabled along with gclk ? gets divided by the same divider setting as that for gclk when running cpu self-test (lbist) vclk oscin ghvsrc ? divided down from hclk ? can be hclk/1, hclk/2, ... or hclk/16 ? is disabled separately from hclk through the cddisx registers bit 2 vclk2 oscin ghvsrc ? divided down from hclk ? can be hclk/1, hclk/2, ... or hclk/16 ? frequency must be an integer multiple of vclk frequency ? is disabled separately from hclk through the cddisx registers bit 3 vclk3 oscin ghvsrc ? divided down from hclk ? can be hclk/1, hclk/2, ... or hclk/16 ? is disabled separately from hclk through the cddisx registers bit 8 vclka1 vclk vclkasrc ? defaults to vclk as the source ? is disabled via the cddisx registers bit 4 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 69 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-13. clock domain descriptions (continued) clock source clock domain default clock selection description name source register vclka3 vclk vclkacon1 ? defaults to vclk as the source ? frequency can be as fast as hclk frequency. ? is disabled through the cddisx registers bit 10 vclka3_divr vclk vclkacon1 ? divided down from the vclka3 using the vclka3r field of the vclkacon1 register at address 0xffffe140 ? frequency can be vclka3/1, vclka3/2, ..., or vclka3/8 ? default frequency is vclka3/2 ? is disabled separately through the vclkacon1 register vclka3_div_cddis bit only if the vclka3 clock is not disabled vclka4 vclk vclkacon1 ? defaults to vclk as the source ? is disabled through the cddisx registers bit 11 rticlk vclk rclksrc ? defaults to vclk as the source ? if a clock source other than vclk is selected for rticlk, then the rticlk frequency must be less than or equal to vclk/3 ? application can ensure this by programming the rti1div field of the rclksrc register, if necessary ? is disabled through the cddisx registers bit 6 70 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.6.2.2 mapping of clock domains to device modules each clock domain has a dedicated functionality as shown in figure 6-7 . figure 6-7. device clock domains copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 71 submit documentation feedback hclk (to system) gclk, gclk2 (to cpu) gcm vclk _peri (vclk to peripherals on pcr1) vclk2 (to n2hetx and htux) vclka1 (to dcanx) to 0 /1..16 /1..16 rticlk (to rti, dwwd) /1, 2, 4, or 8 vclk oscin low power oscillator 10mhz 80khz pll #1 (fmzpll) 1 04 5 /1..64 x1..256 /1..8 /1..32 6 pll # 2 * /1,2,..256 spix,mibspix /2,3..2 24 lin, sci spi lin / sci /1,2..32 mibadcx adclk /1,2..65536 external clock eclk vclk2 n2hetx hrp /1..64 lrp /2 0 ..2 5 loop resolution clock high baud rate baud rate vclk2 ethernet vclka4 /1..64 x1..256 /1..8 /1..32 * 1 4 5 6 vclk vclka4 (to ethernet, as alternate extclkin 1 extclkin2 37 37 0 1 4 5 6 vclk 37 0 1 4 5 6 37 vclk3 vclk3 (to ethernet, usb) /1..16 vclk_sys (vclk to system modules) * the frequency at this node must notexceed the maximum hclk specifiation. /1,2..256 i2c i2c baud rate for miitxclk and/or miirxclk) 0 1 4 5 6 vclk 37 ntu[1] ntu[0] ntu[2] ntu[3] rti pll#2 output extclkin1 reservedreserved vclk /1,2,..1024 phase_seg2 can baud rate phase_seg1 vclka1 prop_seg (fmzpll) vclka3 (to usb) /divr vclka3_divr(to usb host / 12 mhz) usb host vclka3_divr vclka3_s dcanx emif usb device vclka3_s n2hetx tu
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.6.3 clock test mode the rm4x platform architecture defines a special mode that allows various clock signals to be brought out on to the eclk pin and n2het1[12] device outputs. this mode is called the clock test mode. it is very useful for debugging purposes and can be configured through the clktest register in the system module. table 6-14. clock test mode options sel_ecp_pin sel_gio_pin = signal on eclk = signal on n2het1[12] clktest[3-0] clktest[11-8] 0000 oscillator 0000 oscillator valid status 0001 main pll free-running clock output 0001 main pll valid status 0010 reserved 0010 reserved 0011 extclkin1 0011 reserved 0100 clk80k 0100 reserved 0101 clk10m 0101 clk10m valid status 0110 secondary pll free-running clock output 0110 secondary pll valid status 0111 extclkin2 0111 reserved 1000 gclk 1000 clk80k 1001 rti base 1001 reserved 1010 reserved 1010 reserved 1011 vclka1 1011 reserved 1100 reserved 1100 reserved 1101 vclka3 1101 reserved 1110 vclka4 1110 reserved 1111 reserved 1111 reserved 72 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.7 clock monitoring the lpo clock detect (lpoclkdet) module consists of a clock monitor (clkdet) and an internal lpo. the lpo provides two different clock sources ? a low frequency (lflpo) and a high frequency (hflpo). the clkdet is a supervisor circuit for an externally supplied clock signal (oscin). in case the oscin frequency falls out of a frequency window, the clkdet flags this condition in the global status register (glbstat bit 0: osc fail) and switches all clock domains sourced by oscin to the hflpo clock (limp mode clock). the valid oscin frequency range is defined as: f hflpo / 4 < f oscin < f hflpo * 4. 6.7.1 clock monitor timings for more information on lpo and clock detection, refer to table 6-10 . figure 6-8. lpo and clock detection, untrimmed hflpo 6.7.2 external clock (eclk) output functionality the eclk pin can be configured to output a prescaled clock signal indicative of an internal device clock. this output can be externally monitored as a safety diagnostic. 6.7.3 dual clock comparators the dual clock comparator (dcc) module determines the accuracy of selectable clock sources by counting the pulses of two independent clock sources (counter 0 and counter 1). if one clock is out of spec, an error signal is generated. for example, the dcc1 can be configured to use clk10m as the reference clock (for counter 0) and vclk as the "clock under test" (for counter 1). this configuration allows the dcc1 to monitor the pll output clock when vclk is using the pll output as its source. an additional use of this module is to measure the frequency of a selectable clock source, using the input clock as a reference, by counting the pulses of two independent clock sources. counter 0 generates a fixed-width counting window after a preprogrammed number of pulses. counter 1 generates a fixed-width pulse (1 cycle) after a preprogrammed number of pulses. this pulse sets as an error signal if counter 1 does not reach 0 within the counting window generated by counter 0. 6.7.3.1 features ? takes two different clock sources as input to two independent counter blocks. ? one of the clock sources is the known-good, or reference clock; the second clock source is the "clock under test." ? each counter block is programmable with initial, or seed values. ? the counter blocks start counting down from their seed values at the same time; a mismatch from the expected frequency for the clock under test generates an error signal which is used to interrupt the cpu. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 73 submit documentation feedback f[mhz] 1.375 4.875 22 78 fail lower threshold pass upper threshold fail
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.7.3.2 mapping of dcc clock source inputs table 6-15. dcc1 counter 0 clock sources clock source [3:0] clock name others oscillator (oscin) 0x5 high-frequency lpo 0xa test clock (tck) table 6-16. dcc1 counter 1 clock sources key [3:0] clock source [3:0] clock name others - n2het1[31] 0x0 main pll free-running clock output 0x1 reserved 0x2 low-frequency lpo 0xa 0x3 high-frequency lpo 0x4 flash hd pump oscillator 0x5 extclkin1 0x6 extclkin2 0x7 ring oscillator 0x8 - 0xf vclk table 6-17. dcc2 counter 0 clock sources clock source [3:0] clock name others oscillator (oscin) 0xa test clock (tck) table 6-18. dcc2 counter 1 clock sources key [3:0] clock source [3:0] clock name others - n2het2[0] 0xa 00x0 - 0x7 reserved 0x8 - 0xf vclk 74 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.8 glitch filters a glitch filter is present on the following signals. table 6-19. glitch filter timing specifications pin parameter min max unit filter time nporrst pin; nporrst t f(nporrst) 475 2000 ns pulses less than min will be filtered out, pulses greater than max will generate a reset (1) filter time nrst pin; nrst t f(nrst) 475 2000 ns pulses less than min will be filtered out, pulses greater than max will generate a reset filter time test pin; test t f(test) 475 2000 ns pulses less than min will be filtered out, pulses greater than max will pass through (1) the glitch filter design on the nporrst signal is designed such that no size pulse will reset any part of the microcontroller (flash pump, i/o pins, and so forth) without also generating a valid reset signal to the cpu. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 75 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.9 device memory map 6.9.1 memory map diagram figure 6-9 shows the device memory map. figure 6-9. rm48l952 memory map the flash memory is mirrored to support ecc logic testing. the base address of the mirrored flash image is 0x20000000. 76 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback flash (3mb) ram (256kb) 0x00000000 0x002fffff 0x08000000 0x0803ffff crc 0xfe000000 peripherals - frame 1 0xff000000 system modules 0xffffffff 0xf07fffff ram - ecc 0x08400000 0x0843ffff reserved reserved reserved 0xf0000000 emif (16mb * 3) 0x60000000 0x6fffffff reserved flash (3mb) (mirrored image) 0x20000000 0x202fffff reserved reserved peripherals - frame 2 0xfc000000 0xfcffffff 0xfff80000 emif (128mb) 0x80000000 0x87ffffff cs0 reserved reserved async ram sdram 0x64000000 0x68000000 0x6c000000 flash module bus2 interface reserved (flash ecc, otp and eeprom accesses) cs4cs3 cs2
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.9.2 memory map table table 6-20. device memory map frame address range response for access to frame chip frame actual module name unimplemented locations in select size size start end frame memories tightly coupled to the arm cortex-r4f cpu tcm flash cs0 0x00000000 0x00ffffff 16mb 3mb tcm ram + ram csram0 0x08000000 0x0bffffff 64mb 256kb abort ecc mirrored flash flash mirror frame 0x20000000 0x20ffffff 16mb 3mb external memory accesses emif chip select 2 emif select 2 0x60000000 0x63ffffff 64mb 16mb (asynchronous) emif chip select 3 emif select 3 0x64000000 0x67ffffff 64mb 16mb (asynchronous) access to "reserved" space will generate abort emif chip select 4 emif select 4 0x68000000 0x6bffffff 64mb 16mb (asynchronous) emif chip select 0 emif select 0 0x80000000 0x87ffffff 128mb 128mb (synchronous) flash module bus2 interface customer otp, 0xf0000000 0xf0001fff 8kb 4kb tcm flash bank 0 customer otp, 0xf0002000 0xf0003fff 8kb 4kb tcm flash bank 1 customer otp, 0xf000e000 0xf000ffff 8kb 2kb eeprom bank 7 customer otp ? ecc, tcm 0xf0040000 0xf00403ff 1kb 512b flash bank 0 customer otp ? ecc, tcm 0xf0040400 0xf00407ff 1kb 512b flash bank 1 customer otp ? ecc, 0xf0041c00 0xf0041fff 1kb 256b eeprom bank 7 ti otp, tcm flash 0xf0080000 0xf0081fff 8kb 4kb bank 0 abort ti otp, tcm flash 0xf0082000 0xf0083fff 8kb 4kb bank 1 ti otp, eeprom 0xf008e000 0xf008ffff 8kb 2kb bank 7 ti otp ? ecc, tcm 0xf00c0000 0xf00c03ff 1kb 512b flash bank 0 ti otp ? ecc, tcm 0xf00c0400 0xf00c07ff 1kb 512b flash bank 1 ti otp ? ecc, 0xf00c1c00 0xf00c1fff 1kb 256b eeprom bank 7 eeprom 0xf0100000 0xf013ffff 256kb 8kb bank ? ecc eeprom bank 0xf0200000 0xf03fffff 2mb 64kb flash data space 0xf0400000 0xf04fffff 1mb 384kb ecc ethernet and emif slave interfaces cppi memory slave 0xfc520000 0xfc521fff 8kb 8kb abort (ethernet ram) emac slave 0xfcf78000 0xfcf787ff 2kb 2kb no error (ethernet slave) emacss wrapper 0xfcf78800 0xfcf788ff 256b 256b no error (ethernet wrapper) ethernet mdio 0xfcf78900 0xfcf789ff 256b 256b no error interface copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 77 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-20. device memory map (continued) frame address range response for access to frame chip frame actual module name unimplemented locations in select size size start end frame w2fc (usb device 0xfcf78a00 0xfcf78a7f 128b 128b abort controller registers) ohci (usb host 0xfcf78b00 0xfcf78bff 256b 256b abort controller registers) emif registers 0xfcffe800 0xfcffe8ff 256b 256b abort cyclic redundancy checker (crc) module registers crc crc frame 0xfe000000 0xfeffffff 16mb 512b accesses above 0x200 generate abort. peripheral memories mibspi5 ram pcs[5] 0xff0a0000 0xff0bffff 128kb 2kb abort for accesses above 2kb mibspi3 ram pcs[6] 0xff0c0000 0xff0dffff 128kb 2kb abort for accesses above 2kb mibspi1 ram pcs[7] 0xff0e0000 0xff0fffff 128kb 2kb abort for accesses above 2kb wrap around for accesses to unimplemented address offsets lower than dcan3 ram pcs[13] 0xff1a0000 0xff1bffff 128kb 2kb 0x7ff. abort generated for accesses beyond offset 0x800. wrap around for accesses to unimplemented address offsets lower than dcan2 ram pcs[14] 0xff1c0000 0xff1dffff 128kb 2kb 0x7ff. abort generated for accesses beyond offset 0x800. wrap around for accesses to unimplemented address offsets lower than dcan1 ram pcs[15] 0xff1e0000 0xff1fffff 128kb 2kb 0x7ff. abort generated for accesses beyond offset 0x800. wrap around for accesses to unimplemented address offsets lower than mibadc2 ram pcs[29] 0xff3a0000 0xff3bffff 128kb 8kb 0x1fff. abort generated for accesses beyond 0x1fff. wrap around for accesses to unimplemented address offsets lower than mibadc1 ram pcs[31] 0xff3e0000 0xff3fffff 128kb 8kb 0x1fff. abort generated for accesses beyond 0x1fff. wrap around for accesses to unimplemented address offsets lower than n2het2 ram pcs[34] 0xff440000 0xff45ffff 128kb 16kb 0x3fff. abort generated for accesses beyond 0x3fff. wrap around for accesses to unimplemented address offsets lower than n2het1 ram pcs[35] 0xff460000 0xff47ffff 128kb 16kb 0x3fff. abort generated for accesses beyond 0x3fff. htu2 ram pcs[38] 0xff4c0000 0xff4dffff 128kb 1kb abort htu1 ram pcs[39] 0xff4e0000 0xff4fffff 128kb 1kb abort debug components coresight debug cscs0 0xffa00000 0xffa00fff 4kb 4kb reads: 0, writes: no effect rom cortex-r4f debug cscs1 0xffa01000 0xffa01fff 4kb 4kb reads: 0, writes: no effect etm-r4 cscs2 0xffa02000 0xffa02fff 4kb 4kb reads: 0, writes: no effect coresight tpiu cscs3 0xffa03000 0xffa03fff 4kb 4kb reads: 0, writes: no effect pom cscs4 0xffa04000 0xffa04fff 4kb 4kb abort peripheral control registers htu1 ps[22] 0xfff7a400 0xfff7a4ff 256b 256b reads: 0, writes: no effect htu2 ps[22] 0xfff7a500 0xfff7a5ff 256b 256b reads: 0, writes: no effect n2het1 ps[17] 0xfff7b800 0xfff7b8ff 256b 256b reads: 0, writes: no effect n2het2 ps[17] 0xfff7b900 0xfff7b9ff 256b 256b reads: 0, writes: no effect gpio ps[16] 0xfff7bc00 0xfff7bcff 256b 256b reads: 0, writes: no effect mibadc1 ps[15] 0xfff7c000 0xfff7c1ff 512b 512b reads: 0, writes: no effect mibadc2 ps[15] 0xfff7c200 0xfff7c3ff 512b 512b reads: 0, writes: no effect i2c ps[10] 0xfff7d400 0xfff7d4ff 256b 256b reads: 0, writes: no effect dcan1 ps[8] 0xfff7dc00 0xfff7ddff 512b 512b reads: 0, writes: no effect 78 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-20. device memory map (continued) frame address range response for access to frame chip frame actual module name unimplemented locations in select size size start end frame dcan2 ps[8] 0xfff7de00 0xfff7dfff 512b 512b reads: 0, writes: no effect dcan3 ps[7] 0xfff7e000 0xfff7e1ff 512b 512b reads: 0, writes: no effect lin ps[6] 0xfff7e400 0xfff7e4ff 256b 256b reads: 0, writes: no effect sci ps[6] 0xfff7e500 0xfff7e5ff 256b 256b reads: 0, writes: no effect mibspi1 ps[2] 0xfff7f400 0xfff7f5ff 512b 512b reads: 0, writes: no effect mibspi3 ps[1] 0xfff7f800 0xfff7f9ff 512b 512b reads: 0, writes: no effect spi4 ps[1] 0xfff7fa00 0xfff7fbff 512b 512b reads: 0, writes: no effect mibspi5 ps[0] 0xfff7fc00 0xfff7fdff 512b 512b reads: 0, writes: no effect system modules control registers and memories dma ram ppcs0 0xfff80000 0xfff80fff 4kb 4kb abort wrap around for accesses to vim ram ppcs2 0xfff82000 0xfff82fff 4kb 1kb unimplemented address offsets between 1kb and 4kb. rtp ram ppcs3 0xfff83000 0xfff83fff 4kb 4kb abort flash module ppcs7 0xfff87000 0xfff87fff 4kb 4kb abort efuse controller ppcs12 0xfff8c000 0xfff8cfff 4kb 4kb abort power management ppse0 0xffff0000 0xffff01ff 512b 512b abort module (pmm) test controller ppse1 0xffff0400 0xffff07ff 1kb 1kb reads: 0, writes: no effect (fmtm) pcr registers pps0 0xffffe000 0xffffe0ff 256b 256b reads: 0, writes: no effect system module - frame 2 (see device pps0 0xffffe100 0xffffe1ff 256b 256b reads: 0, writes: no effect trm) pbist pps1 0xffffe400 0xffffe5ff 512b 512b reads: 0, writes: no effect generates address error interrupt, if stc pps1 0xffffe600 0xffffe6ff 256b 256b enabled iomm multiplexing pps2 0xffffea00 0xffffebff 512b 512b reads: 0, writes: no effect control module dcc1 pps3 0xffffec00 0xffffecff 256b 256b reads: 0, writes: no effect dma pps4 0xfffff000 0xfffff3ff 1kb 1kb reads: 0, writes: no effect dcc2 pps5 0xfffff400 0xfffff4ff 256b 256b reads: 0, writes: no effect esm pps5 0xfffff500 0xfffff5ff 256b 256b reads: 0, writes: no effect ccmr4 pps5 0xfffff600 0xfffff6ff 256b 256b reads: 0, writes: no effect dmm pps5 0xfffff700 0xfffff7ff 256b 256b reads: 0, writes: no effect ram ecc even pps6 0xfffff800 0xfffff8ff 256b 256b reads: 0, writes: no effect ram ecc odd pps6 0xfffff900 0xfffff9ff 256b 256b reads: 0, writes: no effect rtp pps6 0xfffffa00 0xfffffaff 256b 256b reads: 0, writes: no effect rti + dwwd pps7 0xfffffc00 0xfffffcff 256b 256b reads: 0, writes: no effect vim parity pps7 0xfffffd00 0xfffffdff 256b 256b reads: 0, writes: no effect vim pps7 0xfffffe00 0xfffffeff 256b 256b reads: 0, writes: no effect system module - frame 1 (see device pps7 0xffffff00 0xffffffff 256b 256b reads: 0, writes: no effect trm) copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 79 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.9.3 master/slave access privileges table 6-21 lists the access permissions for each bus master on the device. a bus master is a module that can initiate a read or a write transaction on the device. each slave module on the main interconnect is listed in the table. a "yes" indicates that the module listed in the "masters" column can access that slave module. table 6-21. master / slave access matrix masters access mode slaves on main scr flash module non-cpu crc emif, ethernet, peripheral bus2 interface: accesses to usb slave control otp, ecc, program flash interfaces registers, all eeprom bank and cpu data peripheral ram memories, and all system module control registers and memories cpu read user/privilege yes yes yes yes yes cpu write user/privilege no yes yes yes yes dma user yes yes yes yes yes pom user yes yes yes yes yes dmm user yes yes yes yes yes dap privilege yes yes yes yes yes htu1 privilege no yes yes yes yes htu2 privilege no yes yes yes yes emac dma user no yes no yes no ohci user no yes no yes no 6.9.3.1 special notes on accesses to certain slaves write accesses to the power domain management module (pmm) control registers are limited to the cpu (master id = 1). the other masters can only read from these registers. a debugger can also write to the pmm registers. the master-id check is disabled in debug mode. the device contains dedicated logic to generate a bus error response on any access to a module that is in a power domain that has been turned off. 80 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.9.4 pom overlay considerations ? the pom overlay can map onto up to 8mb of the internal or external memory space. the starting address and the size of the memory overlay are configurable via the pom module control registers. care must be taken to ensure that the overlay is mapped on to available memory. ? ecc must be disabled by software via cp15 in case pom overlay is enabled; otherwise ecc errors will be generated. ? pom overlay must not be enabled when the flash and internal ram memories are swapped via the mem swap field of the bus matrix module control register 1 (bmmcr1). ? when pom is used to overlay the flash onto internal or external ram, there is a bus contention possibility when another master accesses the tcm flash. this results in a system hang. ? the pom module implements a time-out feature to detect this exact scenario. the time-out needs to be enabled whenever pom overlay is enabled. ? the time-out can be enabled by writing 1010 to the enable timeout (eto) field of the pom global control register (pomglbctrl, address = 0xffa04000). ? in case a read request by the pom cannot be completed within 32 hclk cycles, the time-out (to) flag is set in the pom flag register (pomflg, address = 0xffa0400c). also, an abort is generated to the cpu. this can be a prefetch abort for an instruction fetch or a data abort for a data fetch. ? the prefetch- and data-abort handlers must be modified to check if the to flag in the pom module is set. if so, then the application can assume that the time-out is caused by a bus contention between the pom transaction and another master accessing the same memory region. the abort handlers need to clear the to flag, so that any further aborts are not misinterpreted as having been caused due to a time-out from the pom. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 81 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.10 flash memory 6.10.1 flash memory configuration flash bank: a separate block of logic consisting of 1 to 16 sectors. each flash bank normally has a customer-otp and a ti-otp area. these flash sectors share input/output buffers, data paths, sense amplifiers, and control logic. flash sector: a contiguous region of flash memory which must be erased simultaneously due to physical construction constraints. flash pump: a charge pump which generates all the voltages required for reading, programming, or erasing the flash banks. flash module: interface circuitry required between the host cpu and the flash banks and pump module. table 6-22. flash memory banks and sectors sector segment memory arrays (or banks) (1) low address high address no. (bytes) bank0 (1.5mb) 0 32kb 0x00000000 0x00007fff 1 32kb 0x00008000 0x0000ffff 2 32kb 0x00010000 0x00017fff 3 32kb 0x00018000 0x0001ffff 4 128kb 0x00020000 0x0003ffff 5 128kb 0x00040000 0x0005ffff 6 128kb 0x00060000 0x0007ffff 7 128kb 0x00080000 0x0009ffff 8 128kb 0x000a0000 0x000bffff 9 128kb 0x000c0000 0x000dffff 10 128kb 0x000e0000 0x000fffff 11 128kb 0x00100000 0x0011ffff 12 128kb 0x00120000 0x0013ffff 13 128kb 0x00140000 0x0015ffff 14 128kb 0x00160000 0x0017ffff bank1 (1.5mb) 0 128kb 0x00180000 0x0019ffff 1 128kb 0x001a0000 0x001bffff 2 128kb 0x001c0000 0x001dffff 3 128kb 0x001e0000 0x001fffff (3mb devices only) 4 128kb 0x00200000 0x0021ffff 5 128kb 0x00220000 0x0023ffff 6 128kb 0x00240000 0x0025ffff 7 128kb 0x00260000 0x0027ffff 8 128kb 0x00280000 0x0029ffff 9 128kb 0x002a0000 0x002bffff 10 128kb 0x002c0000 0x002dffff 11 128kb 0x002e0000 0x002fffff bank7 (64kb) for eeprom emulation (2) (3) 0 16kb 0xf0200000 0xf0203fff 1 16kb 0xf0204000 0xf0207fff 2 16kb 0xf0208000 0xf020bfff 3 16kb 0xf020c000 0xf020ffff (1) the flash banks are 144-bit-wide bank with ecc support. (2) the flash bank7 can be programmed while executing code from flash bank0 or bank1. (3) code execution is not allowed from flash bank7. 82 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.10.2 main features of flash module ? support for multiple flash banks for program and/or data storage ? simultaneous read access on a bank while performing program or erase operation on any other bank ? integrated state machines to automate flash erase and program operations ? software interface for flash program and erase operations ? pipelined mode operation to improve instruction access interface bandwidth ? support for single error correction double error detection (secded) block inside cortex-r4f cpu ? error address is captured for host system debugging ? support for a rich set of diagnostic features 6.10.3 ecc protection for flash accesses all accesses to the program flash memory are protected by single error correction double error detection (secded) logic embedded inside the cpu. the flash module provides 8 bits of ecc code for 64 bits of instructions or data fetched from the flash memory. the cpu calculates the expected ecc code based on the 64 bits received and compares it with the ecc code returned by the flash module. a single-bit error is corrected and flagged by the cpu, while a multibit error is only flagged. the cpu signals an ecc error via its event bus. this signaling mechanism is not enabled by default and must be enabled by setting the 'x' bit of the performance monitor control register, c9. mrc p15,#0,r1,c9,c12,#0 ;enabling event monitor states orr r1, r1, #0x00000010 mcr p15,#0,r1,c9,c12,#0 ;set 4th bit ( ? x ? ) of pmnc register mrc p15,#0,r1,c9,c12,#0 the application must also explicitly enable the cpu's ecc checking for accesses on the cpu's atcm and btcm interfaces. these are connected to the program flash and data ram respectively. ecc checking for these interfaces can be done by setting the b1tcmpcen, b0tcmpcen and atcmpcen bits of the system control coprocessor's auxiliary control register, c1. mrc p15, #0, r1, c1, c0, #1 orr r1, r1, #0x0e000000 ;enable ecc checking for atcm and btcms dmb mcr p15, #0, r1, c1, c0, #1 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 83 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.10.4 flash access speeds for information on flash memory access speeds and the relevant wait states required, refer to section 5.6 . 6.10.5 flash program and erase timings for program flash table 6-23. timing specifications for program flash parameter min nom max unit t prog (144bit) wide word (144bit) programming time 40 300 s ? 40 c to 105 c 32 s t prog (total) 3-mb programming time (1) 0 c to 60 c, for first 25 cycles 8 16 s ? 40 c to 105 c 0.03 4 s t erase sector/bank erase time (2) 0 c to 60 c, for first 25 cycles 16 100 ms write/erase cycles with 15-year data t wec ? 40 c to 105 c 1000 cycles retention requirement (1) this programming time includes overhead of state machine, but does not include data transfer time. the programming time assumes programming 144 bits at a time at the maximum specified operating frequency. (2) during bank erase, the selected sectors are erased simultaneously. the time to erase the bank is specified as equal to the time to erase a sector. 6.10.6 flash program and erase timings for data flash table 6-24. timing specifications for data flash parameter min nom max unit t prog (144bit) wide word (144bit) programming time 40 300 s ? 40 c to 105 c 660 ms t prog (total) 64-kb programming time (1) 0 c to 60 c, for first 25 cycles 165 330 ms ? 40 c to 105 c 0.2 8 s t erase sector/bank erase time (2) 0 c to 60 c, for first 25 cycles 14 100 ms write/erase cycles with 15-year data t wec ? 40 c to 105 c 100000 cycles retention requirement (1) this programming time includes overhead of state machine, but does not include data transfer time. the programming time assumes programming 144 bits at a time at the maximum specified operating frequency. (2) during bank erase, the selected sectors are erased simultaneously. the time to erase the bank is specified as equal to the time to erase a sector. 84 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.11 tightly coupled ram (tcram) interface module figure 6-10 illustrates the connection of the tightly coupled ram (tcram) to the cortex-r4f cpu. figure 6-10. tcram block diagram 6.11.1 features the features of the tcram module are: ? acts as slave to the btcm interface of the cortex-r4f cpu ? supports cpu's internal ecc scheme by providing 64-bit data and 8-bit ecc code ? monitors cpu event bus and generates single or multibit error interrupts ? stores addresses for single and multibit errors ? supports ram trace module ? provides cpu address bus integrity checking by supporting parity checking on the address bus ? performs redundant address decoding for the ram bank chip select and ecc select generation logic ? provides enhanced safety for the ram addressing by implementing two 36-bit-wide byte-interleaved ram banks and generating independent ram access control signals to the two banks ? supports auto-initialization of the ram banks along with the ecc bits 6.11.2 tcram interface ecc support the tcram interface passes on the ecc code for each data read by the cortex-r4f cpu from the ram. it also stores the ecc port contents of the cpu in the ecc ram when the cpu does a write to the ram. the tcram interface monitors the event bus of the cpu and provides registers for indicating singlebit or multibit errors and also for identifying the address that caused the single or multibit error. the event signaling and the ecc checking for the ram accesses must be enabled inside the cpu. for more information see the device specific technical reference manual. 6.12 parity protection for peripheral rams most peripheral rams are protected by odd/even parity checking. during a read access the parity is calculated based on the data read from the peripheral ram and compared with the good parity value stored in the parity ram for that peripheral. if any word fails the parity check, the module generates a parity error signal that is mapped to the error signaling module. the module also captures the peripheral ram address that caused the parity error. the parity protection for peripheral rams is not enabled by default and must be enabled by the application. each individual peripheral contains control registers to enable the parity protection for accesses to its ram. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 85 submit documentation feedback tcm bus tcm bus 72 bit data + ecc 72 bit data + ecc upper 32 bits data & 4 ecc bits lower 32 bits data & 4 ecc bits 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram upper 32 bits data & 4 ecc bits lower 32 bits data & 4 ecc bits 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram 36 bitwide ram tcram interface 1 cortex-r4f b0 tcm b1 tcm tcram interface 2
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com note the cpu read access gets the actual data from the peripheral. the application can choose to generate an interrupt whenever a peripheral ram parity error is detected. 86 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.13 on-chip sram initialization and testing 6.13.1 on-chip sram self-test using pbist 6.13.1.1 features ? extensive instruction set to support various memory test algorithms ? rom-based algorithms allow application to run ti production-level memory tests ? independent testing of all on-chip sram 6.13.1.2 pbist ram groups table 6-25. pbist ram grouping test pattern (algorithm) march 13n (1) march 13n (1) triple read triple read two port single port memory ram group test clock mem type slow read fast read (cycles) (cycles) algo mask algo mask algo mask algo mask 0x1 0x2 0x4 0x8 pbist_rom 1 rom clk rom 24578 8194 stc_rom 2 rom clk rom 19586 6530 dcan1 3 vclk dual port 25200 dcan2 4 vclk dual port 25200 dcan3 5 vclk dual port 25200 esram1 (2) 6 hclk single port 266280 mibspi1 7 vclk dual port 33440 mibspi3 8 vclk dual port 33440 mibspi5 9 vclk dual port 33440 vim 10 vclk dual port 12560 mibadc1 11 vclk dual port 4200 dma 12 hclk dual port 18960 n2het1 13 vclk dual port 31680 htu1 14 vclk dual port 6480 rtp 15 hclk dual port 37800 mibadc2 18 vclk dual port 4200 n2het2 19 vclk dual port 31680 htu2 20 vclk dual port 6480 esram5 (3) 21 hclk single port 266280 esram6 (4) 22 hclk single port 266280 23 8700 dual port ethernet 24 vclk3 6360 25 single port 133160 26 dual port 4240 usb vclk3 27 single port 66600 esram8 (5) 28 hclk single port 266280 (1) there are several memory testing algorithms stored in the pbist rom. however, ti recommends the march13n algorithm for application testing. (2) esram1: address 0x08000000 - 0x0800ffff (always on power domain) (3) esram5: address 0x08010000 - 0x0801ffff (ram power domain 1) (4) esram6: address 0x08020000 - 0x0802ffff (ram power domain 2) (5) esram8: address 0x08030000 - 0x0803ffff (ram power domain 3) copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 87 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com the pbist rom clock frequency is limited to 110 mhz, if 110 mhz < hclk < = hclkmax, or hclk, if hclk < = 110 mhz. the pbist rom clock is divided down from hclk. the divider is selected by programming the rom_div field of the memory self-test global control register (mstgcr) at address 0xffffff58. 6.13.2 on-chip sram auto initialization this microcontroller allows some of the on-chip memories to be initialized to zero through the memory hardware initialization mechanism in the system module. this hardware mechanism allows an application to program the memory arrays with error detection capability to a known state based on their error detection scheme (odd/even parity or ecc). the minitgcr register enables the memory initialization sequence, and the msinena register selects the memories that are to be initialized. for more information on these registers see the device specific technical reference manual. the mapping of the different on-chip memories to the specific bits of the msinena registers is shown in table 6-26 . table 6-26. memory initialization address range msinena register connecting module bit no. base address ending address ram (pd#1) 0x08000000 0x0800ffff 0 (1) ram (ram_pd#1) 0x08010000 0x0801ffff 0 (1) ram (ram_pd#2) 0x08020000 0x0802ffff 0 (1) ram (ram_pd#3) 0x08030000 0x0803ffff 0 (1) mibspi5 ram 0xff0a0000 0xff0bffff 12 (2) mibspi3 ram 0xff0c0000 0xff0dffff 11 (2) mibspi1 ram 0xff0e0000 0xff0fffff 7 (2) dcan3 ram 0xff1a0000 0xff1bffff 10 dcan2 ram 0xff1c0000 0xff1dffff 6 dcan1 ram 0xff1e0000 0xff1fffff 5 mibadc2 ram 0xff3a0000 0xff3bffff 14 mibadc1 ram 0xff3e0000 0xff3fffff 8 n2het2 ram 0xff440000 0xff45ffff 15 n2het1 ram 0xff460000 0xff47ffff 3 htu2 ram 0xff4c0000 0xff4dffff 16 htu1 ram 0xff4e0000 0xff4fffff 4 dma ram 0xfff80000 0xfff80fff 1 vim ram 0xfff82000 0xfff82fff 2 usb device ram ram is not cpu-addressable n/a ethernet ram (cppi memory 0xfc520000 0xfc521fff n/a slave) (1) the tcm ram wrapper has separate control bits to select the ram power domain that is to be auto-initialized. (2) the mibspix modules perform an initialization of the transmit and receive rams as soon as the module is released from its local reset via the spigcr0 register. this is independent of whether the application chooses to initialize the mibspix rams using the system module auto-initialization method. before the mibspi ram can be initialized using the system module auto-initialization method: (i) the module must be released from its local reset, and (ii) the application must poll for the " buf init active " status flag in the spiflg register to become cleared (zero) 88 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.14 external memory interface (emif) 6.14.1 features the emif includes many features to enhance the ease and flexibility of connecting to external asynchronous memories or sdram devices. the emif features includes support for: ? 3 addressable chip select for asynchronous memories of up to 16mb each ? 1 addressable chip select space for sdrams up to 128mb ? 8- or 16-bit data bus width ? programmable cycle timings such as setup, strobe, and hold times as well as turnaround time ? select strobe mode ? extended wait mode ? data bus parking 6.14.2 electrical and timing specifications 6.14.2.1 asynchronous ram figure 6-11. asynchronous memory read timing copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 89 submit documentation feedback emif_ncs[3:2] emif_ba[1:0] 13 12 emif_addr[21:0] emif_noe emif_data[15:0] emif_nwe 10 5 9 7 4 8 6 3 1 emif_ndqm[1:0] 30 29
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 6-12. emifnwait read timing requirements figure 6-13. asynchronous memory write timing 90 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback emif_ncs[3:2] emif_ba[1:0] emif_addr[21:0] emif_nwe emif_data[15:0] emif_noe 15 1 16 18 20 22 24 17 19 21 23 26 27 emif_ndqm[1:0] emif_ncs[3:2] 11 asserted deasserted 2 2 emif_ba[1:0] emif_addr[21:0] emif_data[15:0] emif_noe emif_wait setup extended due to emif_wait strobe hold 14 strobe
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 figure 6-14. emifnwait write timing requirements table 6-27. emif asynchronous memory timing requirements no. min nom max unit reads and writes e emif clock period 9 ns pulse duration, emifnwait 2 t w(em_wait) 2e ns assertion and deassertion reads t su(emdv-emoeh) setup time, emifdata[15:0] 12 30 ns valid before emifnoe high t h(emoeh-emdiv) hold time, emifdata[15:0] valid 13 0.5 ns after emifnoe high setup time, emifnwait 14 t su(emoel-emwait) asserted before end of strobe 4e+30 ns phase (1) writes setup time, emifnwait 28 t su(emwel-emwait) asserted before end of strobe 4e+30 ns phase (1) (1) setup before end of strobe phase (if no extended wait states are inserted) by which emifnwait must be asserted to add extended wait states. figure 6-12 and figure 6-14 describe emif transactions that include extended wait states inserted during the strobe phase. however, cycles inserted as part of this extended wait period should not be counted; the 4e requirement is to the start of where the hold phase would begin if there were no extended wait cycles. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 91 submit documentation feedback emif_ncs[3:2] 25 asserted 2 2 emif_ba[1:0] emif_addr[21:0] emif_data[15:0] emif_nwe emif_wait setup extended due to emif_wait 28 deasserted strobe strobe hold
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-28. emif asynchronous memory switching characteristics (1) (2) (3) no. parameter min nom max unit reads and writes 1 t d(turnaround) turn around time (ta)*e-4 (ta)*e (ta)*e+3 ns reads emif read cycle time (ew = 0) (rs+rst+rh)*e-3 (rs+rst+rh)*e (rs+rst+rh)*e+3 3 t c(emrcycle) ns (rs+rst+rh+(ewc*16))* (rs+rst+rh+(ewc*16))* (rs+rst+rh+(ewc*16))* emif read cycle time (ew = 1) e-3 e e+3 output setup time, emifncs[4:2] (rs)*e-4 (rs)*e (rs)*e+3 low to emifnoe low (ss = 0) 4 t su(emcel-emoel) ns output setup time, emifncs[4:2] -3 0 +3 low to emifnoe low (ss = 1) output hold time, emifnoe high (rh)*e-4 (rh)*e (rh)*e+3 to emifncs[4:2] high (ss = 0) 5 t h(emoeh-emceh) ns output hold time, emifnoe high -3 0 +3 to emifncs[4:2] high (ss = 1) output setup time, emifba[1:0] 6 t su(embav-emoel) (rs)*e-4 (rs)*e (rs)*e+3 ns valid to emifnoe low output hold time, emifnoe high 7 t h(emoeh-embaiv) (rh)*e-4 (rh)*e (rh)*e+3 ns to emifba[1:0] invalid output setup time, 8 t su(emav-emoel) emifaddr[21:0] valid to (rs)*e-4 (rs)*e (rs)*e+3 ns emifnoe low output hold time, emifnoe high 9 t h(emoeh-emaiv) (rh)*e-4 (rh)*e (rh)*e+3 ns to emifaddr[21:0] invalid emifnoe active low width (rst)*e-3 (rst)*e (rst)*e+3 (ew = 0) 10 t w(emoel) ns emifnoe active low width (rst+(ewc*16))*e-3 (rst+(ewc*16))*e (rst+(ewc*16))*e+3 (ew = 1) delay time from emifnwait 11 t d(emwaith-emoeh) 3e-3 4e 4e+30 ns deasserted to emifnoe high output setup time, 29 t su(emdqmv-emoel) emifndqm[1:0] valid to (rs)*e-4 (rs)*e (rs)*e+3 ns emifnoe low output hold time, emifnoe high 30 t h(emoeh-emdqmiv) (rh)*e-4 (rh)*e (rh)*e+3 ns to emifndqm[1:0] invalid writes emif write cycle time (ew = 0) (ws+wst+wh)* e-3 (ws+wst+wh)*e (ws+wst+wh)* e+3 15 t c(emwcycle) ns (ws+wst+wh+(ewc*16))* (ws+wst+wh+(ewc*16))* (ws+wst+wh+(ewc*16))* emif write cycle time (ew = 1) e-3 e e+3 output setup time, emifncs[4:2] (ws)*e -4 (ws)*e (ws)*e + 3 low to emifnwe low (ss = 0) 16 t su(emcel-emwel) ns output setup time, emifncs[4:2] -4 0 +3 low to emifnwe low (ss = 1) output hold time, emifnwe high (wh)*e-4 (wh)*e (wh)*e+3 to emifncs[4:2] high (ss = 0) 17 t h(emweh-emceh) ns output hold time, emifnwe high -4 0 +3 to emifcs[4:2] high (ss = 1) output setup time, emifba[1:0] 18 t su(emdqmv-emwel) (ws)*e-4 (ws)*e (ws)*e+3 ns valid to emifnwe low output hold time, emifnwe high 19 t h(emweh-emdqmiv) (wh)*e-4 (wh)*e (wh)*e+3 ns to emifba[1:0] invalid output setup time, emifba[1:0] 20 t su(embav-emwel) (ws)*e-4 (ws)*e (ws)*e+3 ns valid to emifnwe low output hold time, emifnwe high 21 t h(emweh-embaiv) (wh)*e-4 (wh)*e (wh)*e+3 ns to emifba[1:0] invalid (1) ta = turn around, rs = read setup, rst = read strobe, rh = read hold, ws = write setup, wst = write strobe, wh = write hold, mewc = maximum external wait cycles. these parameters are programmed via the asynchronous bank and asynchronous wait cycle configuration registers. these support the following ranges of values: ta[4 ? 1], rs[16 ? 1], rst[64 ? 1], rh[8 ? 1], ws[16 ? 1], wst[64 ? 1], wh[8 ? 1], and mewc[1 ? 256]. see the rm48x technical reference manual ( spnu503 ) for more information. (2) e = emif_clk period in ns. (3) ewc = external wait cycles determined by emifnwait input signal. ewc supports the following range of values. ewc[256 ? 1]. note that the maximum wait time before time-out is specified by bit field mewc in the asynchronous wait cycle configuration register. see the rm48x technical reference manual ( spnu503 ) for more information. 92 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-28. emif asynchronous memory switching characteristics (1) (2) (3) (continued) no. parameter min nom max unit output setup time, 22 t su(emav-emwel) emifaddr[21:0] valid to (ws)*e-4 (ws)*e (ws)*e+3 ns emifnwe low output hold time, emifnwe high 23 t h(emweh-emaiv) (wh)*e-4 (wh)*e (wh)*e+3 ns to emifaddr[21:0] invalid emifnwe active low width (ew (wst)*e-3 (wst)*e (wst)*e+3 = 0) 24 t w(emwel) ns emifnwe active low width (ew (wst+(ewc*16))*e-3 (wst+(ewc*16))*e (wst+(ewc*16))* e+3 = 1) delay time from emifnwait 25 t d(emwaith-emweh) 3e-4 4e 4e+30 ns deasserted to emifnwe high output setup time, 26 t su(emdv-emwel) emifdata[15:0] valid to (ws)*e-4 (ws)*e (ws)*e+3 ns emifnwe low output hold time, emifnwe high 27 t h(emweh-emdiv) (wh)*e-4 (wh)*e (wh)*e+3 ns to emifdata[15:0] invalid output setup time, 31 t su(emdqmv-emwel) emifndqm[1:0] valid to (wh)*e-4 (wh)*e (wh)*e+3 ns emifnwe low output hold time, emifnwe high 32 t h(emweh-emdqmiv) (wh)*e-4 (wh)*e (wh)*e+3 ns to emifndqm[1:0] invalid 6.14.2.2 synchronous timing figure 6-15. basic sdram read operation copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 93 submit documentation feedback emif_clk emif_ba[1:0] emif_addr[21:0] emif_data[15:0] 1 2 2 4 6 8 8 12 14 19 20 3 5 7 7 11 13 17 18 2 em_clk delay basic sdram read operation emif_ncs[0] emif_ndqm[1:0] emif_nras emif_ncas emif_nwe
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 6-16. basic sdram write operation table 6-29. emif synchronous memory timing requirements no. min max unit input setup time, read data valid on 19 t su(emifdv-em_clkh) 2 ns emifdata[15:0] before emif_clk rising input hold time, read data valid on 20 t h(clkh-div) 1.5 ns emifdata[15:0] after emif_clk rising table 6-30. emif synchronous memory switching characteristics no. parameter min max unit 1 t c(clk) cycle time, emif clock emif_clk 18 ns 2 t w(clk) pulse width, emif clock emif_clk high or low 5 ns 3 t d(clkh-csv) delay time, emif_clk rising to emifncs[0] valid 13 ns output hold time, emif_clk rising to emifncs[0] 4 t oh(clkh-csiv) 1 ns invalid delay time, emif_clk rising to emifndqm[1:0] 5 t d(clkh-dqmv) 13 ns valid output hold time, emif_clk rising to 6 t oh(clkh-dqmiv) 1 ns emifndqm[1:0] invalid delay time, emif_clk rising to emifaddr[21:0] 7 t d(clkh-av) 13 ns and emifba[1:0] valid output hold time, emif_clk rising to 8 t oh(clkh-aiv) 1 ns emifaddr[21:0] and emifba[1:0] invalid delay time, emif_clk rising to emifdata[15:0] 9 t d(clkh-dv) 13 ns valid 94 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback emif_clk emif_ba[1:0] emif_addr[21:0] emif_data[15:0] 1 2 2 4 6 8 8 12 10 16 3 5 7 7 11 13 15 9 basic sdram write operation emif_cs[0] emif_dqm[1:0] emif_nras emif_ncas emif_nwe
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-30. emif synchronous memory switching characteristics (continued) no. parameter min max unit output hold time, emif_clk rising to 10 t oh(clkh-div) 1 ns emifdata[15:0] invalid 11 t d(clkh-rasv) delay time, emif_clk rising to emifnras valid 13 ns output hold time, emif_clk rising to emifnras 12 t oh(clkh-rasiv) 1 ns invalid 13 t d(clkh-casv) delay time, emif_clk rising to emifncas valid 13 ns output hold time, emif_clk rising to emifncas 14 t oh(clkh-casiv) 1 ns invalid 15 t d(clkh-wev) delay time, emif_clk rising to emifnwe valid 13 ns output hold time, emif_clk rising to emifnwe 16 t oh(clkh-weiv) 1 ns invalid delay time, emif_clk rising to emifdata[15:0] 17 t dis(clkh-dhz) 7 ns tri-stated output hold time, emif_clk rising to 18 t ena(clkh-dlz) 1 ns emifdata[15:0] driving copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 95 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.15 vectored interrupt manager the vectored interrupt manager (vim) provides hardware assistance for prioritizing and controlling the many interrupt sources present on this device. interrupts are caused by events outside of the normal flow of program execution. normally, these events require a timely response from the central processing unit (cpu); therefore, when an interrupt occurs, the cpu switches execution from the normal program flow to an interrupt service routine (isr). 6.15.1 vim features the vim module has the following features: ? supports 96 interrupt channels. ? provides programmable priority and enable for interrupt request lines. ? provides a direct hardware dispatch mechanism for fastest irq dispatch. ? provides two software dispatch mechanisms when the cpu vic port is not used. ? index interrupt ? register vectored interrupt ? parity protected vector interrupt table 6.15.2 interrupt request assignments table 6-31. interrupt request assignments default vim modules interrupt sources interrupt channel esm esm high level interrupt (nmi) 0 reserved reserved 1 rti rti compare interrupt 0 2 rti rti compare interrupt 1 3 rti rti compare interrupt 2 4 rti rti compare interrupt 3 5 rti rti overflow interrupt 0 6 rti rti overflow interrupt 1 7 rti rti time base interrupt 8 gpio gpio interrupt a 9 n2het1 n2het1 level 0 interrupt 10 htu1 htu1 level 0 interrupt 11 mibspi1 mibspi1 level 0 interrupt 12 lin lin level 0 interrupt 13 mibadc1 mibadc1 event group interrupt 14 mibadc1 mibadc1 sw group 1 interrupt 15 dcan1 dcan1 level 0 interrupt 16 reserved reserved 18 crc crc interrupt 19 esm esm low level interrupt 20 system software interrupt (ssi) 21 cpu pmu interrupt 22 gpio gpio interrupt b 23 n2het1 n2het1 level 1 interrupt 24 htu1 htu1 level 1 interrupt 25 mibspi1 mibspi1 level 1 interrupt 26 96 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-31. interrupt request assignments (continued) default vim modules interrupt sources interrupt channel lin lin level 1 interrupt 27 mibadc1 mibadc1 sw group 2 interrupt 28 dcan1 dcan1 level 1 interrupt 29 mibadc1 mibadc1 magnitude compare interrupt 31 reserved reserved 32 dma ftca interrupt 33 dma lfsa interrupt 34 dcan2 dcan2 level 0 interrupt 35 dmm dmm level 0 interrupt 36 mibspi3 mibspi3 level 0 interrupt 37 mibspi3 mibspi3 level 1 interrupt 38 dma hbca interrupt 39 dma btca interrupt 40 emif aemifint3 41 dcan2 dcan2 level 1 interrupt 42 dmm dmm level 1 interrupt 43 dcan1 dcan1 if3 interrupt 44 dcan3 dcan3 level 0 interrupt 45 dcan2 dcan2 if3 interrupt 46 fpu "or" of the six cortex r4f fpu exceptions 47 reserved reserved 48 spi4 spi4 level 0 interrupt 49 mibadc2 mibadc2 event group interrupt 50 mibadc2 mibadc2 sw group1 interrupt 51 reserved reserved 52 mibspi5 mibspi5 level 0 interrupt 53 spi4 spi4 level 1 interrupt 54 dcan3 dcan3 level 1 interrupt 55 mibspi5 mibspi5 level 1 interrupt 56 mibadc2 mibadc2 sw group2 interrupt 57 reserved reserved 58 mibadc2 mibadc2 magnitude compare interrupt 59 dcan3 dcan3 if3 interrupt 60 fmc fsm_done interrupt 61 reserved reserved 62 n2het2 n2het2 level 0 interrupt 63 sci sci level 0 interrupt 64 htu2 htu2 level 0 interrupt 65 i2c i2c level 0 interrupt 66 usb host ohci_int 67 usb device usb_func.irqisoon 68 usb device usb_func.irqgenion 69 usb device usb_func.irqnonisoon 70 usb device not (usb_func.dswakereqon) 71 usb device usb_func.usbreseto 72 n2het2 n2het2 level 1 interrupt 73 sci sci level 1 interrupt 74 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 97 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-31. interrupt request assignments (continued) default vim modules interrupt sources interrupt channel htu2 htu2 level 1 interrupt 75 ethernet c0_misc_pulse 76 ethernet c0_tx_pulse 77 ethernet c0_thresh_pulse 78 ethernet c0_rx_pulse 79 hwag1 hwa_int_req_h 80 hwag2 hwa_int_req_h 81 dcc1 dcc1 done interrupt 82 dcc2 dcc2 done interrupt 83 reserved reserved 84 pbist pbist_done 85 reserved reserved 86 reserved reserved 87 hwag1 hwa_int_req_l 88 hwag2 hwa_int_req_l 89 reserved reserved 90-95 note address location 0x00000000 in the vim ram is reserved for the phantom interrupt isr entry; therefore only request channels 0 to 94 can be used and are offset by 1 address in the vim ram. note the lower-order interrupt channels are higher priority channels than the higher-order interrupt channels. note the application can change the mapping of interrupt sources to the interrupt channels via the interrupt channel control registers (chanctrlx) inside the vim module. 98 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.16 dma controller the dma controller is used to transfer data between two locations in the memory map in the background of cpu operations. typically, the dma is used to: ? transfer blocks of data between external and internal data memories ? restructure portions of internal data memory ? continually service a peripheral 6.16.1 dma features ? cpu independent data transfer ? one master port - portb (64 bits wide) that interfaces to the rm4x memory system. ? fifo buffer (4 entries deep and each 64 bits wide) ? channel control information is stored in ram protected by parity ? 16 channels with individual enable ? channel chaining capability ? 32 peripheral dma requests ? hardware and software dma requests ? 8-, 16-, 32-, or 64-bit transactions supported ? multiple addressing modes for source/destination (fixed, increment, offset) ? auto-initiation ? power-management mode ? memory protection with four configurable memory regions copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 99 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.16.2 default dma request map the dma module on this microcontroller has 16 channels and up to 32 hardware dma requests. the module contains dreqasix registers which are used to map the dma requests to the dma channels. by default, channel 0 is mapped to request 0, channel 1 to request 1, and so on. some dma requests have multiple sources, as shown in table 6-32 . the application must ensure that only one of these dma request sources is enabled at any time. table 6-32. dma request line connection modules dma request sources dma request mibspi1 mibspi1[1] (1) dmareq[0] mibspi1 mibspi1[0] (2) dmareq[1] spi2 spi2 receive dmareq[2] spi2 spi2 transmit dmareq[3] mibspi1 / mibspi3 / dcan2 mibspi1[2] / mibspi3[2] / dcan2 if3 dmareq[4] mibspi1 / mibspi3 / dcan2 mibspi1[3] / mibspi3[3] / dcan2 if2 dmareq[5] dcan1 / mibspi5 dcan1 if2 / mibspi5[2] dmareq[6] mibadc1 / mibspi5 mibadc1 event / mibspi5[3] dmareq[7] mibspi1 / mibspi3 / dcan1 mibspi1[4] / mibspi3[4] / dcan1 if1 dmareq[8] mibspi1 / mibspi3 / dcan2 mibspi1[5] / mibspi3[5] / dcan2 if1 dmareq[9] mibadc1 / i2c / mibspi5 mibadc1 g1 / i2c receive / mibspi5[4] dmareq[10] mibadc1 / i2c / mibspi5 mibadc1 g2 / i2c transmit / mibspi5[5] dmareq[11] rti / mibspi1 / mibspi3 rti dmareq0 / mibspi1[6] / mibspi3[6] dmareq[12] rti / mibspi1 / mibspi3 rti dmareq1 / mibspi1[7] / mibspi3[7] dmareq[13] mibspi3 / usb device / mibadc2 / mibspi5 mibspi3[1] (1) / usb_func.dmatxreq_on[0] / dmareq[14] mibadc2 event / mibspi5[6] mibspi3 / usb device / mibspi5 mibspi3[0] (2) / usb_func.dmarxreq_on[0] / dmareq[15] mibspi5[7] mibspi1 / mibspi3 / dcan1 / mibadc2 mibspi1[8] / mibspi3[8] / dcan1 if3 / mibadc2 g1 dmareq[16] mibspi1 / mibspi3 / dcan3 / mibadc2 mibspi1[9] / mibspi3[9] / dcan3 if1 / mibadc2 g2 dmareq[17] rti / usb device / mibspi5 rti dmareq2 / usb_func.dmatxreq_on[1] / dmareq[18] mibspi5[8] rti / usb device / mibspi5 rti dmareq3 / usb_func.dmarxreq_on[1] / dmareq[19] mibspi5[9] n2het1 / n2het2 / dcan3 n2het1 dmareq[4] / n2het2 dmareq[4] / dcan3 dmareq[20] if2 n2het1 / n2het2 / dcan3 n2het1 dmareq[5] / n2het2 dmareq[5] / dcan3 dmareq[21] if3 mibspi1 / mibspi3 / mibspi5 mibspi1[10] / mibspi3[10] / mibspi5[10] dmareq[22] mibspi1 / mibspi3 / mibspi5 mibspi1[11] / mibspi3[11] / mibspi5[11] dmareq[23] n2het1 / n2het2 / spi4 / mibspi5 n2het1 dmareq[6] / n2het2 dmareq[6] / spi4 dmareq[24] receive / mibspi5[12] n2het1 / n2het2 / spi4 / mibspi5 n2het1 dmareq[7] / n2het2 dmareq[7] / spi4 dmareq[25] transmit / mibspi5[13] crc / mibspi1 / mibspi3 crc dmareq[0] / mibspi1[12] / mibspi3[12] dmareq[26] crc / mibspi1 / mibspi3 crc dmareq[1] / mibspi1[13] / mibspi3[13] dmareq[27] lin / usb device / mibspi5 lin receive / usb_func.dmatxreq_on[2] / dmareq[28] mibspi5[14] lin / usb device / mibspi5 lin transmit / usb_func.dmarxreq_on[2] / dmareq[29] mibspi5[15] mibspi1 / mibspi3 / sci / mibspi5 mibspi1[14] / mibspi3[14] / sci receive / dmareq[30] mibspi5[1] (1) (1) spi1, spi3, spi5 receive in mode (2) spi1, spi3, spi5 transmit in mode 100 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-32. dma request line connection (continued) modules dma request sources dma request mibspi1 / mibspi3 / sci / mibspi5 mibspi1[15] / mibspi3[15] / sci transmit / dmareq[31] mibspi5[0] (2) copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 101 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.17 real time interrupt module the real-time interrupt (rti) module provides timer functionality for operating systems and for benchmarking code. the rti module incorporates two 64-bit counters that define the time bases needed for scheduling an operating system. the timers also allow you to benchmark certain areas of code by reading the values of the counters at the beginning and the end of the desired code range and calculating the difference between the values. 6.17.1 features the rti module has the following features: ? two independent 64 bit counter blocks ? four configurable compares for generating operating system ticks or dma requests. each event can be driven by either counter block 0 or counter block 1. ? fast enabling/disabling of events ? two time-stamp (capture) functions for system or peripheral interrupts, one for each counter block 6.17.2 block diagrams figure 6-17 shows a high-level block diagram for one of the two 64-bit counter blocks inside the rti module. both the counter blocks are identical except the network time unit (ntux) inputs are only available as time base inputs for the counter block 0. figure 6-17. counter block diagram 102 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 31 0 31 0 rticlk 31 0 31 0 31 0 external control cap event source 0 cap event source 1 = up counter capture up counter compare up counter free running counter capture rtifrcx free running counter rticafrcx ovlintx rticpucx rtiucx rticaucx to compare unit ntu0ntu1 ntu2 ntu3
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 figure 6-18. compare block diagram 6.17.3 clock source options the rti module uses the rti1clk clock domain for generating the rti time bases. the application can select the clock source for the rti1clk by configuring the rclksrc register in the system module at address 0xffffff50. the default source for rti1clk is vclk. for more information on clock sources refer to table 6-8 and table 6-13 . 6.17.4 network time synchronization inputs the rti module supports four ntu inputs that signal internal system events, and which can be used to synchronize the time base used by the rti module. on this device, these ntu inputs are connected as shown in table 6-33 . table 6-33. network time synchronization inputs ntu input source 0 reserved 1 reserved 2 pll2 clock output 3 extclkin1 clock input copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 103 submit documentation feedback 31 0 compare control inty dmareqy compare update compare from counter block 0 from counter block 1 rtiudcpy rticompy 31 0 = +
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.18 error signaling module the error signaling module (esm) manages the various error conditions on the rm4x microcontroller. the error condition is handled based on a fixed severity level assigned to it. any severe error condition can be configured to drive a low level on a dedicated device terminal called nerror. this can be used as an indicator to an external monitor circuit to put the system into a safe state. 6.18.1 features the features of the esm are: ? 128 interrupt/error channels are supported, divided into 3 different groups ? 64 channels with maskable interrupt and configurable error pin behavior ? 32 error channels with nonmaskable interrupt and predefined error pin behavior ? 32 channels with predefined error pin behavior only ? error pin to signal severe device failure ? configurable time base for error signal ? error forcing capability 6.18.2 esm channel assignments the esm integrates all the device error conditions and groups them in the order of severity. group1 is used for errors of the lowest severity while group3 is used for errors of the highest severity. the device response to each error is determined by the severity group it is connected to. table 6-35 shows the channel assignment for each group. table 6-34. esm groups error group interrupt characteristics influence on error pin group1 maskable, low or high priority configurable group2 nonmaskable, high priority fixed group3 no interrupt generated fixed table 6-35. esm channel assignments error sources group channels reserved group1 0 mibadc2 - parity group1 1 dma - mpu group1 2 dma - parity group1 3 reserved group1 4 dma /dmm - imprecise read error group1 5 fmc - correctable error: bus1 and bus2 interfaces group1 6 (does not include accesses to eeprom bank) n2het1/n2het2 - parity group1 7 htu1/htu2 - parity group1 8 htu1/htu2 - mpu group1 9 pll - slip group1 10 clock monitor - interrupt group1 11 reserved group1 12 dma /dmm - imprecise write error group1 13 reserved group1 14 vim ram - parity group1 15 reserved group1 16 mibspi1 - parity group1 17 mibspi3 - parity group1 18 104 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-35. esm channel assignments (continued) error sources group channels mibadc1 - parity group1 19 reserved group1 20 dcan1 - parity group1 21 dcan3 - parity group1 22 dcan2 - parity group1 23 mibspi5 - parity group1 24 reserved group1 25 ram even bank (b0tcm) - correctable error group1 26 cpu - self-test group1 27 ram odd bank (b1tcm) - correctable error group1 28 reserved group1 29 dcc1 - error group1 30 ccm-r4 - self-test group1 31 reserved group1 32 reserved group1 33 reserved group1 34 fmc - correctable error (eeprom bank access) group1 35 fmc - uncorrectable error (eeprom bank access) group1 36 iomm - mux configuration error group1 37 power domain controller compare error group1 38 power domain controller self-test error group1 39 efuse controller error ? this error signal is generated when any bit in the efuse controller error status register is set. the application can choose to generate an group1 40 interrupt whenever this bit is set to service any efuse controller error conditions. efuse controller - self test error. this error signal is generated only when a self test on the efuse controller generates an error condition. when an ecc self test group1 41 error is detected, group 1 channel 40 error signal will also be set. pll2 - slip group1 42 ethernet controller master interface group1 43 usb host controller master interface group1 44 reserved group1 45 reserved group1 46 reserved group1 47 reserved group1 48 reserved group1 49 reserved group1 50 reserved group1 51 reserved group1 52 reserved group1 53 reserved group1 54 reserved group1 55 reserved group1 56 reserved group1 57 reserved group1 58 reserved group1 59 reserved group1 60 reserved group1 61 dcc2 - error group1 62 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 105 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-35. esm channel assignments (continued) error sources group channels reserved group1 63 group 2 reserved group2 0 reserved group2 1 ccmr4 - compare group2 2 reserved group2 3 fmc - uncorrectable error (address parity on bus1 accesses) group2 4 reserved group2 5 ram even bank (b0tcm) - uncorrectable error group2 6 reserved group2 7 ram odd bank (b1tcm) - uncorrectable error group2 8 reserved group2 9 ram even bank (b0tcm) - address bus parity error group2 10 reserved group2 11 ram odd bank (b1tcm) - address bus parity error group2 12 reserved group2 13 reserved group2 14 reserved group2 15 tcm - ecc live lock detect group2 16 reserved group2 17 reserved group2 18 reserved group2 19 reserved group2 20 reserved group2 21 reserved group2 22 reserved group2 23 rti_wwd_nmi group2 24 reserved group2 25 reserved group2 26 reserved group2 27 reserved group2 28 reserved group2 29 reserved group2 30 reserved group2 31 group 3 reserved group3 0 efuse controller - autoload error group3 1 reserved group3 2 ram even bank (b0tcm) - ecc uncorrectable error group3 3 reserved group3 4 ram odd bank (b1tcm) - ecc uncorrectable error group3 5 reserved group3 6 fmc - uncorrectable error: bus1 and bus2 interfaces group3 7 (does not include address parity error and errors on accesses to eeprom bank) reserved group3 8 reserved group3 9 reserved group3 10 reserved group3 11 106 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-35. esm channel assignments (continued) error sources group channels reserved group3 12 reserved group3 13 reserved group3 14 reserved group3 15 reserved group3 16 reserved group3 17 reserved group3 18 reserved group3 19 reserved group3 20 reserved group3 21 reserved group3 22 reserved group3 23 reserved group3 24 reserved group3 25 reserved group3 26 reserved group3 27 reserved group3 28 reserved group3 29 reserved group3 30 reserved group3 31 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 107 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.19 reset / abort / error sources table 6-36. reset/abort/error sources esm hookup error source system mode error response group.channel cpu transactions precise write error (ncnb/strongly ordered) user/privilege precise abort (cpu) n/a precise read error (ncb/device or normal) user/privilege precise abort (cpu) n/a imprecise write error (ncb/device or normal) user/privilege imprecise abort (cpu) n/a undefined instruction trap illegal instruction user/privilege n/a (cpu) (1) mpu access violation user/privilege abort (cpu) n/a sram b0 tcm (even) ecc single error (correctable) user/privilege esm 1.26 abort (cpu), esm = > b0 tcm (even) ecc double error (noncorrectable) user/privilege 3.3 nerror b0 tcm (even) uncorrectable error (for example, redundant user/privilege esm = > nmi = > nerror 2.6 address decode) b0 tcm (even) address bus parity error user/privilege esm = > nmi = > nerror 2.10 b1 tcm (odd) ecc single error (correctable) user/privilege esm 1.28 abort (cpu), esm = > b1 tcm (odd) ecc double error (noncorrectable) user/privilege 3.5 nerror b1 tcm (odd) uncorrectable error (for example, redundant user/privilege esm = > nmi = > nerror 2.8 address decode) b1 tcm (odd) address bus parity error user/privilege esm = > nmi = > nerror 2.12 flash fmc correctable error - bus1 and bus2 interfaces user/privilege esm 1.6 fmc uncorrectable error - bus1 accesses abort (cpu), esm = > user/privilege 3.7 (does not include address parity error) nerror fmc uncorrectable error - bus2 accesses (does not include address parity error and eeprom bank user/privilege esm = > nerror 3.7 accesses) fmc uncorrectable error - address parity error on bus1 user/privilege esm = > nmi = > nerror 2.4 accesses fmc correctable error - accesses to eeprom bank user/privilege esm 1.35 fmc uncorrectable error - accesses to eeprom bank user/privilege esm 1.36 dma transactions external imprecise error on read (illegal transaction with ok user/privilege esm 1.5 response) external imprecise error on write (illegal transaction with ok user/privilege esm 1.13 response) memory access permission violation user/privilege esm 1.2 memory parity error user/privilege esm 1.3 dmm transactions external imprecise error on read (illegal transaction with ok user/privilege esm 1.5 response) external imprecise error on write (illegal transaction with ok user/privilege esm 1.13 response) htu1 ncnb (strongly ordered) transaction with slave error response user/privilege interrupt = > vim n/a external imprecise error (illegal transaction with ok response) user/privilege interrupt = > vim n/a memory access permission violation user/privilege esm 1.9 (1) the undefined instruction trap is not detectable outside the cpu. the trap is taken only if the instruction reaches the execute stage of the cpu. 108 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 6-36. reset/abort/error sources (continued) esm hookup error source system mode error response group.channel memory parity error user/privilege esm 1.8 htu2 ncnb (strongly ordered) transaction with slave error response user/privilege interrupt = > vim n/a external imprecise error (illegal transaction with ok response) user/privilege interrupt = > vim n/a memory access permission violation user/privilege esm 1.9 memory parity error user/privilege esm 1.8 n2het1 memory parity error user/privilege esm 1.7 n2het2 memory parity error user/privilege esm 1.7 ethernet master interface any error reported by slave being accessed user/privilege esm 1.43 usb host controller (ohci) master interface any error reported by slave being accessed user/privilege esm 1.44 mibspi mibspi1 memory parity error user/privilege esm 1.17 mibspi3 memory parity error user/privilege esm 1.18 mibspi5 memory parity error user/privilege esm 1.24 mibadc mibadc1 memory parity error user/privilege esm 1.19 mibadc2 memory parity error user/privilege esm 1.1 dcan dcan1 memory parity error user/privilege esm 1.21 dcan2 memory parity error user/privilege esm 1.23 dcan3 memory parity error user/privilege esm 1.22 pll pll slip error user/privilege esm 1.10 pll #2 slip error user/privilege esm 1.42 clock monitor clock monitor interrupt user/privilege esm 1.11 dcc dcc1 error user/privilege esm 1.30 dcc2 error user/privilege esm 1.62 ccm-r4 self-test failure user/privilege esm 1.31 compare failure user/privilege esm = > nmi = > nerror 2.2 vim memory parity error user/privilege esm 1.15 voltage monitor vmon out of voltage range n/a reset n/a cpu self-test (lbist) cpu self-test (lbist) error user/privilege esm 1.27 copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 109 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-36. reset/abort/error sources (continued) esm hookup error source system mode error response group.channel pin multiplexing control mux configuration error user/privilege esm 1.37 power domain control pscon compare error user/privilege esm 1.38 pscon self-test error user/privilege esm 1.39 efuse controller efuse controller autoload error user/privilege esm = > nerror 3.1 efuse controller - any bit set in the error status register user/privilege esm 1.40 efuse controller self-test error user/privilege esm 1.41 windowed watchdog wwd nonmaskable interrupt exception n/a esm = > nmi = > nerror 2.24 errors reflected in the sysesr register power-up reset n/a reset n/a oscillator fail / pll slip (2) n/a reset n/a watchdog exception n/a reset n/a cpu reset (driven by the cpu stc) n/a reset n/a software reset n/a reset n/a external reset n/a reset n/a (2) oscillator fail/pll slip can be configured in the system register (sys.pllctl1) to generate a reset. 6.20 digital windowed watchdog this device includes a digital windowed watchdog (dwwd) module that protects against runaway code execution. the dwwd module allows the application to configure the time window within which the dwwd module expects the application to service the watchdog. a watchdog violation occurs if the application services the watchdog outside of this window, or fails to service the watchdog at all. the application can choose to generate a system reset or a nonmaskable interrupt to the cpu in case of a watchdog violation. the watchdog is disabled by default and must be enabled by the application. once enabled, the watchdog can only be disabled upon a system reset. 110 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21 debug subsystem 6.21.1 block diagram the device contains an icepick module to allow jtag access to the scan chains (see figure 6-19 ). figure 6-19. debug subsystem block diagram note the etm, rtp and dmm exist in silicon, but are not supported in the pge package. 6.21.2 debug components memory map table 6-37. debug components memory map frame address range response for access to frame chip frame actual module name unimplemented locations in select size size start end frame coresight debug cscs0 0xffa00000 0xffa00fff 4kb 4kb reads: 0, writes: no effect rom cortex-r4f cscs1 0xffa01000 0xffa01fff 4kb 4kb reads: 0, writes: no effect debug etm-r4 cscs2 0xffa02000 0xffa02fff 4kb 4kb reads: 0, writes: no effect coresight tpiu cscs3 0xffa03000 0xffa03fff 4kb 4kb reads: 0, writes: no effect 6.21.3 jtag identification code the jtag id code for this device is the same as the device icepick identification code (see table 6-38 ). copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 111 submit documentation feedback trst tms tck tdi tdo rtck icepick_c boundary scan bsr/bsdl boundary scan i/f secondary tap 0 dap debug apb debug rom1 apb slave cortex r4f apb muxahb-ap pom etm tpiu to scr1 via a2a frompcr1/bridge secondary tap 1 dmm rtp tap 0 tap 1 secondary tap 2 ajsm
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-38. jtag id code silicon revision id rev a 0x0b8a002f rev b 0x2b8a002f rev c 0x3b8a002f rev d 0x4b8a002f 6.21.4 debug rom the debug rom stores the location of the components on the debug apb bus (see table 6-39 ). table 6-39. debug rom table address description value 0x000 pointer to cortex-r4f 0x00001003 0x001 etm-r4 0x00002003 0x002 tpiu 0x00003003 0x003 pom 0x00004003 0x004 end of table 0x00000000 112 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21.5 jtag scan interface timings table 6-40. jtag scan interface timing (1) no. parameter min max unit ftck tck frequency (at hclkmax) 12 mhz frtck rtck frequency (at tckmax and hclkmax) 10 mhz 1 td(tck -rtck) delay time, tck to rtck 24 ns 2 tsu(tdi/tms - rtckr) setup time, tdi, tms before rtck rise (rtckr) 26 ns 3 th(rtckr -tdi/tms) hold time, tdi, tms after rtckr 0 ns 4 th(rtckr -tdo) hold time, tdo after rtckf 0 ns 5 td(tckf -tdo) delay time, tdo valid after rtck fall (rtckf) 12 ns (1) timings for tdo are specified for a maximum of 50-pf load on tdo figure 6-20. jtag timing copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 113 submit documentation feedback 1 1 2 3 4 5 tms tdi tdo rtck tck
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 6.21.6 advanced jtag security module this device includes an advanced jtag security module (ajsm) which provides maximum security to the memory content of the device by letting users secure the device after programming. figure 6-21. ajsm unlock the device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the otp address 0xf0000000. the otp contents are xor-ed with the "unlock by scan" register contents (see figure 6-21 ). the outputs of these xor gates are again combined with a set of secret internal tie-offs. the output of this combinational logic is compared against a secret hard-wired 128-bit value. a match results in the unlock signal being asserted, so that the device is now unsecure. a user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. changing a 0 to 1 is not possible because the visible unlock code is stored in the one time programmable (otp) flash region. also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the device. once secured, a user can unsecure the device by scanning an appropriate value into the "unlock by scan" register of the ajsm module. the value to be scanned is such that the xor of the otp contents and the unlock-by-scan register contents results in the original visible unlock code. the unlock-by-scan register is reset only upon asserting power-on reset (nporrst). a secure device only permits jtag accesses to the ajsm scan chain via the secondary tap # 2 of the icepick module. all other secondary taps, test taps and the boundary scan interface are not accessible in this state. 114 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback h l h l h l l h . . . . . . 128-bit comparator h l l h h l l h unlock flash module output otp contents unlock by scan register internal tie-offs (example only) (example) l h h l l internal tie-offs (example only) l h h
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21.7 embedded trace macrocell (etm-r4) the device contains a etm-r4 module with a 32-bit internal data port. the etm-r4 module is connected to a tpiu with a 32-bit data bus; the tpiu provides a 35-bit (32-bit data, 3-bit control) external interface for trace. the etm-r4 is coresight compliant and follows the etm v3 specification; for more details see arm coresight etm-r4 trm specification. 6.21.7.1 etm traceclkin selection the etm clock source can be selected as either vclk or the external etmtraceclkin pin. the selection is done by the extctlout[1:0] control bits of the tpiu; the default is '00' (see table 6-41 ). the address of this register is tpiu base address + 0x404. before you begin accessing tpiu registers, tpiu should be unlocked via coresight key and 1 or 2 should be written to this register. table 6-41. tpiu / traceclkin selection extctlout[1:0] tpiu/traceclkin 00 [default] tied-zero 01 vclk 10 etmtraceclkin 11 tied-zero 6.21.7.2 timing specifications figure 6-22. etmtraceclkout timing table 6-42. etmtraceclk timing parameter min max unit t cyc(etm) clock period t (hclk) * 4 ns t l(etm) low pulse width 20 ns t h(etm) high pulse width 20 ns t r(etm) clock and data rise time 3 ns t f(etm) clock and data fall time 3 ns copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 115 submit documentation feedback t r(etm) t h(etm) t l(etm) t f(etm) t cyc(etm)
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 6-23. etmdata timing table 6-43. etmdata timing parameter min max unit delay time, etm trace clock high to etm t d(etmtraceclkh-etmdatav) 1.5 7 ns data valid delay time, etm trace clock low to etm t d(etmtraceclkl-etmdatav) 1.5 7 ns data valid note the etmtraceclk and etmdata timing is based on a 15-pf load and for ambient temperature lower than 85 c. 116 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21.8 ram trace port (rtp) the rtp provides the ability to datalog the ram contents of the rm4x devices or accesses to peripherals without program intrusion. it can trace all data write or read accesses to internal ram. in addition, it provides the capability to directly transfer data to a fifo to support a cpu-controlled transmission of the data. the trace data is transmitted over a dedicated external interface. 6.21.8.1 features the rtp offers the following features: ? two modes of operation - trace mode and direct data mode ? trace mode ? nonintrusive data trace on write or read operation ? visibility of ram content at any time on external capture hardware ? trace of peripheral accesses ? 2 configurable trace regions for each ram module to limit amount of data to be traced ? fifo to store data and address of data of multiple read/write operations ? trace of cpu and/or dma accesses with indication of the master in the transmitted data packet ? direct data mode ? directly write data with the cpu or trace read operations to a fifo, without transmitting header and address information ? dedicated synchronous interface to transmit data to external devices ? free-running clock generation or clock stop mode between transmissions ? up to 100 mbps/pin transfer rate for transmitting data ? pins not used in functional mode can be used as gios 6.21.8.2 timing specifications figure 6-24. rtpclk timing table 6-44. rtpclk timing parameter min max unit clock period, prescaled from hclk; must not be t cyc(rtp) 11 (= 90 mhz) ns faster than hclk / 2 t h(rtp) high pulse width ((t cyc(rtp) )/2) - ((t r +t f )/2) ns t l(rtp) low pulse width ((t cyc(rtp) )/2) - ((t r +t f )/2) ns copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 117 submit documentation feedback t cyc(rtp) t r t f t h(rtp) t l(rtp)
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 6-25. rtpdata timing table 6-45. rtpdata timing parameter min max unit t d(rtpclkh-rtpsyncv) delay time, rtpclk high to rtpsync valid ? 5 4 ns t d(rtpclkh-rtpdatav) delay time, rtpclk high to rtpdata valid ? 5 4 ns figure 6-26. rtpnena timing table 6-46. rtpnena timing parameter min max unit time rtpnena must go high before what would t dis(rtp) be the next rtpsync, to ensure delaying the 3t c(hclk) + t r(rtpsync) + 12 ns next packet time after rtpnena goes low before a packet that t ena(rtp) 4t c(hclk) + t r(rtpsync) 5t c(hclk) + t r(rtpsync) + 12 ns has been halted, resumes 118 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback hclk rtpclk rtpena rtpsync rtpdata hclk rtpclk rtpena rtpsync rtpdata t ena(rtp) t dis(rtp) hclk rtpclk rtpnena rtpsync rtpdata 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 d1 d2 d3 d4 d5 d6 d7 d8 divide by 1
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21.9 data modification module (dmm) the data modification module (dmm) provides the capability to modify data in the entire 4-gb address space of the rm4x devices from an external peripheral, with minimal interruption of the application. 6.21.9.1 features the dmm has the following features: ? acts as a bus master, thus enabling direct writes to the 4-gb address space without cpu intervention ? writes to memory locations specified in the received packet (leverages packets defined by trace mode of the ram trace port (rtp) module ? writes received data to consecutive addresses, which are specified by the dmm (leverages packets defined by direct data mode of rtp module) ? configurable port width (1, 2, 4, 8, 16 pins) ? up to 100 mbps/pin data rate ? unused pins configurable as gpio pins 6.21.9.2 timing specifications figure 6-27. dmmclk timing table 6-47. timing requirements for dmmclk min max unit t cyc(dmm) cycle time, dmmclk period t c(hclk) * 2 ns t h(dmm) pulse duration, dmmclk high ((t cyc(dmm) )/2) - ((t r +t f )/2) ns t l(dmm) pulse duration, dmmclk low ((t cyc(dmm) )/2) - ((t r +t f )/2) ns figure 6-28. dmmdata timing copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 119 submit documentation feedback dmmsync dmmclk dmmdata t ssu(dmm) t sh(dmm) t dsu(dmm) t dh(dmm) t cyc(dmm) t r t f t h(dmm) t l(dmm)
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 6-48. timing requirements for dmmdata min max unit t ssu(dmm) sync active to clk falling edge setup time 2 ns t sh(dmm) clk falling edge to sync inactive hold time 3 ns t dsu(dmm) data to clk falling edge setup time 2 ns t dh(dmm) clk falling edge to data hold time 3 ns figure 6-29. dmmnena timing figure 6-29 shows a case with 1 dmm packet per 2 dmmclk cycles (mode = direct data mode, data width = 8, port width = 4) where none of the packets received by the dmm are sent out, leading to filling up of the internal buffers. the dmmnena signal is shown asserted, after the first two packets have been received and synchronized to the hclk domain. here, the dmm has the capacity to accept packets d4x, d5x, d6x, d7x. packet d8 would result in an overflow. once dmmnena is asserted, the dmm expects to stop receiving packets after 4 hclk cycles; once dmmnena is deasserted, the dmm can handle packets immediately (after 0 hclk cycles). 120 system information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback hclk dmmclk dmmsync dmmdata dmmnena d00 d01 d10 d11 d20 d21 d30 d31 d40 d41 d50
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 6.21.10 boundary scan chain the device supports ieee1149.1-compliant boundary scan for testing pin-to-pin compatibility. the boundary scan chain is connected to the boundary scan interface of the icepick module (see figure 6- 30 ). figure 6-30. boundary scan implementation (conceptual diagram) data is serially shifted into all boundary-scan buffers through tdi and out through tdo. copyright ? 2011 ? 2015, texas instruments incorporated system information and electrical specifications 121 submit documentation feedback trst tmstck tdi tdo rtck ic e p ick boundary bsdl boundary scan interface scan device pins (conceptual) tdi tdo
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7 peripheral information and electrical specifications 7.1 peripheral legend table 7-1. peripheral legend abbreviation full name mibadc analog-to-digital converter ccm-r4f cpu compare module - cortex-r4f crc cyclic redundancy checker dcan controller area network dcc dual clock comparator dma direct memory access dmm data modification module emif external memory interface esm error signaling module etm-r4f embedded trace macrocell - cortex-r4f gpio general-purpose input/output htu high-end timer transfer unit i2c inter-integrated circuit lin local interconnect network mibspi multibuffered serial peripheral interface n2het platform next generation high-end timer pom parameter overlay module rti real-time interrupt module rtp ram trace port spi serial peripheral interface usb universal serial bus vim vectored interrupt manager 7.2 multibuffered 12-bit analog-to-digital converter the multibuffered a-to-d converter (mibadc) has a separate power bus for its analog circuitry that enhances the a-to-d performance by preventing digital switching noise on the logic circuitry which could be present on v ss and v cc from coupling into the a-to-d analog stage. all a-to-d specifications are given with respect to ad reflo unless otherwise noted. table 7-2. mibadc overview description value resolution 12 bits monotonic assured output conversion code 00h to fffh [00 for v ai ad reflo ; fff for v ai ad refhi ] 122 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.2.1 features ? 10-/12-bit resolution ? ad refhi and ad reflo pins (high and low reference voltages) ? total sample/hold/convert time: 600 ns typical minimum at 30 mhz adclk ? one memory region per conversion group is available (event, group 1, group 2) ? allocation of channels to conversion groups is completely programmable ? memory regions are serviced either by interrupt or by dma ? programmable interrupt threshold counter is available for each group ? programmable magnitude threshold interrupt for each group for any one channel ? option to read either 8-, 10-, or 12-bit values from memory regions ? single or continuous conversion modes ? embedded self-test ? embedded calibration logic ? enhanced power-down mode ? optional feature to automatically power down adc core when no conversion is in progress ? external event pin (adevt) programmable as general-purpose i/o 7.2.2 event trigger options the adc module supports three conversion groups: event group, group1, and group2. each of these three groups can be configured to be hardware event-triggered. in that case, the application can select from among eight event sources to be the trigger for a group's conversions. 7.2.2.1 default mibadc1 event trigger hookup table 7-3. mibadc1 event trigger hookup event # source select bits for g1, g2 or event trigger (g1src[2:0], g2src[2:0] or evsrc[2:0]) 1 000 adevt 2 001 n2het1[8] 3 010 n2het1[10] 4 011 rti compare 0 interrupt 5 100 n2het1[12] 6 101 n2het1[14] 7 110 giob[0] 8 111 giob[1] note for adevt, n2het1, and giob trigger sources, the connection to the mibadc1 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control), or by driving the function from an external trigger source as input. if the mux control module is used to select different functionality instead of the adevt, n2het1[x], or giob[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections. note for the rti compare 0 interrupt source, the connection is made directly from the output of the rti module. that is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the cpu. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 123 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.2.2.2 alternate mibadc1 event trigger hookup table 7-4. alternate mibadc1 event trigger hookup source select bits for g1, g2 or event event # trigger (g1src[2:0], g2src[2:0] or evsrc[2:0]) 1 000 adevt 2 001 n2het2[5] 3 010 n2het1[27] 4 011 rti compare 0 interrupt 5 100 n2het1[17] 6 101 n2het1[19] 7 110 n2het1[11] 8 111 n2het2[13] the selection between the default mibadc1 event trigger hook-up versus the alternate event trigger hook- up is done by multiplexing control module register 30 bits 0 and 1. if 30[0] = 1, then the default mibadc1 event trigger hook-up is used. if 30[0] = 0 and 30[1] = 1, then the alternate mibadc1 event trigger hook-up is used. note for adevt trigger source, the connection to the mibadc1 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by configuring adevt as an output function on to the pad (via the mux control), or by driving the adevt signal from an external trigger source as input. if the mux control module is used to select different functionality instead of the adevt signal, then care must be taken to disable adevt from triggering conversions; there is no multiplexing on the input connection. note for n2hetx trigger sources, the connection to the mibadc1 module trigger input is made from the input side of the output buffer (at the n2hetx module boundary). this way, a trigger condition can be generated even if the n2hetx signal is not selected to be output on the pad. note for the rti compare 0 interrupt source, the connection is made directly from the output of the rti module. that is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the cpu. 124 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.2.2.3 default mibadc2 event trigger hookup table 7-5. mibadc2 event trigger hookup source select bits for g1, g2 or event event # trigger (g1src[2:0], g2src[2:0] or evsrc[2:0]) 1 000 ad2evt 2 001 n2het1[8] 3 010 n2het1[10] 4 011 rti compare 0 5 100 n2het1[12] 6 101 n2het1[14] 7 110 giob[0] 8 111 giob[1] note for ad2evt, n2het1 and giob trigger sources, the connection to the mibadc2 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by configuring the function as output onto the pad (via the mux control), or by driving the function from an external trigger source as input. if the mux control module is used to select different functionality instead of the ad2evt, n2het1[x] or giob[x] signals, then care must be taken to disable these signals from triggering conversions; there is no multiplexing on the input connections. note for the rti compare 0 interrupt source, the connection is made directly from the output of the rti module. that is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the cpu. 7.2.2.4 alternate mibadc2 event trigger hookup table 7-6. alternate mibadc2 event trigger hookup source select bits for g1, g2 or event event # trigger (g1src[2:0], g2src[2:0] or evsrc[2:0]) 1 000 ad2evt 2 001 n2het2[5] 3 010 n2het1[27] 4 011 rti compare 0 5 100 n2het1[17] 6 101 n2het1[19] 7 110 n2het1[11] 8 111 n2het2[13] the selection between the default mibadc2 event trigger hook-up versus the alternate event trigger hook- up is done by multiplexing control module register 30 bits 0 and 1. if 30[0] = 1, then the default mibadc2 event trigger hook-up is used. if 30[0] = 0 and 30[1] = 1, then the alternate mibadc2 event trigger hook-up is used. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 125 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com note for ad2evt trigger source, the connection to the mibadc2 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by configuring ad2evt as an output function on to the pad (via the mux control), or by driving the ad2evt signal from an external trigger source as input. if the mux control module is used to select different functionality instead of the ad2evt signal, then care must be taken to disable ad2evt from triggering conversions; there is no multiplexing on the input connections. note for n2hetx trigger sources, the connection to the mibadc2 module trigger input is made from the input side of the output buffer (at the n2hetx module boundary). this way, a trigger condition can be generated even if the n2hetx signal is not selected to be output on the pad. note for the rti compare 0 interrupt source, the connection is made directly from the output of the rti module. that is, the interrupt condition can be used as a trigger source even if the actual interrupt is not signaled to the cpu. 126 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.2.3 adc electrical and timing specifications table 7-7. mibadc recommended operating conditions parameter min max unit ad refhi a-to-d high-voltage reference source ad reflo v ccad (1) v ad reflo a-to-d low-voltage reference source v ssad (1) ad refhi v v ai analog input voltage ad reflo ad refhi v analog input clamp current (2) i aik ? 2 2 ma (vai < vssad ? 0.3 or vai > vccad + 0.3) (1) for v ccad and v ssad recommended operating conditions, see section 5.4 . (2) input currents into any adc input channel outside the specified limits could affect conversion results of other channels. table 7-8. mibadc electrical characteristics over full ranges of recommended operating conditions parameter description/conditions min max unit analog input mux on- r mux see figure 7-1 250 resistance adc sample switch on- r samp see figure 7-1 250 resistance c mux input mux capacitance see figure 7-1 16 pf c samp adc sample capacitance see figure 7-1 13 pf v ssad v in < v ssad + 100 mv ? 300 200 analog off-state input leakage v ccad = 3.6 v i ail v ssad + 100 mv v in v ccad - 200 mv ? 200 200 na current maximum v ccad - 200 mv < v in v ccad ? 200 500 v ssad v in < v ssad + 300 mv ? 1000 250 analog off-state input leakage v ccad = 5.5 v i ail v ssad + 300 mv v in v ccad - 300 mv ? 250 250 na current maximum v ccad - 300 mv < v in v ccad ? 250 1000 v ssad v in < v ssad + 100 mv ? 8 2 adc1 analog on-state input v ccad = 3.6 v i aosb1 (1) v ssad + 100 mv < v in < v ccad - 200 mv ? 4 2 a bias current maximum v ccad - 200 mv < v in < v ccad ? 4 12 v ssad v in < v ssad + 100 mv ? 7 2 adc2 analog on-state input v ccad = 3.6 v i aosb2 (1) v ssad + 100 mv v in v ccad - 200 mv ? 4 2 a bias current maximum v ccad - 200 mv < v in v ccad ? 4 10 v ssad v in < v ssad + 300 mv ? 10 3 adc1 analog on-state input v ccad = 5.5 v i aosb1 (1) v ssad + 300 mv v in v ccad - 300 mv ? 5 3 a bias current maximum v ccad - 300 mv < v in v ccad ? 5 14 v ssad v in < v ssad + 300 mv ? 8 3 adc2 analog on-state input v ccad = 5.5 v i aosb2 (1) v ssad + 300 mv v in v ccad - 300 mv ? 5 3 a bias current maximum v ccad - 300 mv < v in v ccad ? 5 12 i adrefhi ad refhi input current ad refhi = v ccad , ad reflo = v ssad 3 ma normal operating mode 15 ma i ccad static supply current adc core in power down mode 5 a (1) if a shared channel is being converted by both adc converters at the same time, the on-state leakage is equal to i aosl1 + i aosl2 copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 127 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-1. mibadc input equivalent circuit table 7-9. mibadc timing specifications parameter min nom max unit t c(adclk) (1) cycle time, mibadc clock 0.033 s t d(sh) (2) delay time, sample and hold time 0.2 s t d(pu-adv) delay time from adc power on until first input can be sampled 1 s 12-bit mode t d(c) delay time, conversion time 0.4 s t d(shc) (3) delay time, total sample/hold and conversion time 0.6 s 10-bit mode t d(c) delay time, conversion time 0.33 s t d(shc) (3) delay time, total sample/hold and conversion time 0.53 s (1) the mibadc clock is the adclk, generated by dividing down the vclk by a prescale factor defined by the adclockcr register bits 4:0. (2) the sample and hold time for the adc conversions is defined by the adclk frequency and the ad < gp > samp register for each conversion group. the sample time needs to be determined by accounting for the external impedance connected to the input channel as well as the internal impedance of the adc. (3) this is the minimum sample/hold and conversion time that can be achieved. these parameters are dependent on many factors, for example, the prescale settings. 128 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback v s1 on-state bias current off-state leakages v s2 v s24 i aosb i ail i ail r ext r ext r ext p in s mux r mux p in s mux r mux p in s mux r mux s samp r samp c samp c ext i ail i ail i ail i ail c mux c ext c ext
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 7-10. mibadc operating characteristics over full ranges of recommended operating conditions parameter description/conditions min nom max unit cr conversion range over ad refhi - ad reflo which specified accuracy is 3 5.5 v maintained z set zero scale offset difference between the first ideal transition 10-bit mode 1 lsb (1) (from code 000h to 001h) and the actual 12-bit mode 2 lsb (2) transition f set full scale offset difference between the range of the 10-bit mode 2 lsb measured code transitions (from first to last) 12-bit mode 3 lsb and the range of the ideal code transitions e dnl differential nonlinearity difference between the actual step width and 10-bit mode 1.5 lsb error the ideal value. (see figure 7-2 ) 12-bit mode 2 lsb e inl integral nonlinearity error maximum deviation from the best straight line 10-bit mode 2 lsb through the mibadc. mibadc transfer characteristics, excluding the quantization 12-bit mode 2 lsb error. e tot total unadjusted error maximum value of the difference between an 10-bit mode 2 lsb analog value and the ideal midstep value. 12-bit mode 4 lsb (1) 1 lsb = (ad refhi ? ad reflo )/ 2 10 for 10-bit mode (2) 1 lsb = (ad refhi ? ad reflo )/ 2 12 for 12-bit mode copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 129 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.2.4 performance (accuracy) specifications 7.2.4.1 mibadc nonlinearity errors the differential nonlinearity error shown in figure 7-2 (sometimes referred to as differential linearity) is the difference between an actual step width and the ideal value of 1 lsb. figure 7-2. differential nonlinearity (dnl) error 130 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback differential linearity error (C? lsb) 1 lsb 1 lsb differential linearity error (C? lsb) 0 ... 110 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 digital output code analog input value (lsb) note a: 1 lsb = (ad C ad )/2 refhi reflo 12
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 the integral nonlinearity error shown in figure 7-3 (sometimes referred to as linearity error) is the deviation of the values on the actual transfer function from a straight line. figure 7-3. integral nonlinearity (inl) error copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 131 submit documentation feedback 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 digital output code analog input value (lsb) 0 ... 110 6 7 at transition 011/100 (C? lsb) at transition 001/010 (C1/4 lsb) actual transition ideal transition end-point lin. error note a: 1 lsb = (ad C ad )/2 refhi reflo 12
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.2.4.2 mibadc total error the absolute accuracy or total error of an mibadc as shown in figure 7-4 is the maximum value of the difference between an analog value and the ideal midstep value. figure 7-4. absolute accuracy (total) error 132 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 0 ... 111 0 ... 101 0 ... 100 0 ... 011 0 ... 010 0 ... 001 0 ... 000 0 1 2 3 4 5 digital output code analog input value (lsb) 0 ... 110 6 7 total error at step 0 ... 001 (1/2 lsb) total error at step 0 ... 101 (C1 1/4 lsb) note a: 1 lsb = (ad C ad )/2 refhi reflo 12
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.3 general-purpose input/output the gpio module on this device supports two ports, gioa and giob. the i/o pins are bidirectional and bit-programmable. both gioa and giob support external interrupt capability. 7.3.1 features the gpio module has the following features: ? each i/o pin can be configured as: ? input ? output ? open drain ? the interrupts have the following characteristics: ? programmable interrupt detection either on both edges or on a single edge (set in giointdet) ? programmable edge-detection polarity, either rising or falling edge (set in giopol register) ? individual interrupt flags (set in gioflg register) ? individual interrupt enables, set and cleared through gioenaset and gioenaclr registers, respectively ? programmable interrupt priority, set through giolvlset and giolvlclr registers ? internal pullup or pulldown allows unused i/o pins to be left unconnected for information on input and output timings see section 5.11 and section 5.12 copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 133 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.4 enhanced next generation high-end timer (n2het) the n2het is an advanced intelligent timer that provides sophisticated timing functions for real-time applications. the timer is software-controlled, using a reduced instruction set, with a specialized timer micromachine and an attached i/o port. the n2het can be used for pulse width modulated outputs, capture or compare inputs, or general-purpose i/o. it is especially well suited for applications requiring multiple sensor information and drive actuators with complex and accurate time pulses. 7.4.1 features the n2het module has the following features: ? programmable timer for input and output timing functions ? reduced instruction set (30 instructions) for dedicated time and angle functions ? 160 words of instruction ram protected by parity ? user-defined number of 25-bit virtual counters for timer, event counters and angle counters ? 7-bit hardware counters for some pins allow up to 32-bit resolution in conjunction with the 25-bit virtual counters ? up to 32 pins usable for input signal measurements or output signal generation ? programmable suppression filter for each input pin with adjustable limiting frequency ? low cpu overhead and interrupt load ? efficient data transfer to or from the cpu memory with dedicated high-end-timer transfer unit (htu) or dma ? diagnostic capabilities with different loopback mechanisms and pin status readback functionality 7.4.2 n2het ram organization the timer ram uses 4 ram banks, where each bank has two port access capability. this means that one ram address may be written while another address is read. the ram words are 96 bits wide, which are split into three 32-bit fields (program, control, and data). 7.4.3 input timing specifications the n2het instructions pcnt and wcap impose some timing constraints on the input signals. figure 7-5. n2het input capture timings 134 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback n2hetx 3 4 2 1
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 7-11. input timing requirements for the n2het input capture functionality no. min (1) (2) max (1) (2) unit input signal period, pcnt or wcap for rising edge to rising 1 2 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns edge input signal period, pcnt or wcap for falling edge to falling 2 2 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns edge input signal high phase, pcnt or wcap for rising edge to 3 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns falling edge input signal low phase, pcnt or wcap for falling edge to 4 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns rising edge (1) hr = high-resolution prescaler, configured using the hrpfc field of the prescale factor register (hetpfr). (2) lr = loop-resolution prescaler, configured using the lfprc field of the prescale factor register (hetpfr). both n2het1 and n2het2 have channels that are enhanced to be able to capture inputs with smaller pulse widths than that specified in table 7-11 . see table 7-13 for a list of which pins support small pulse capture. the input capture capability for these channels is specified in table 7-12 . table 7-12. input timing requirements for n2het channels with enhanced pulse capture no. min max unit input signal period, pcnt or wcap for rising edge to rising 1 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns edge input signal period, pcnt or wcap for falling edge to falling 2 (hr) (lr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns edge input signal high phase, pcnt or wcap for rising edge to 3 2 (hr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns falling edge input signal low phase, pcnt or wcap for falling edge to 4 2 (hr) tc (vclk2) + 2 2 25 (hr) (lr) tc (vclk2) - 2 ns rising edge table 7-13. input capture pin capability channel supports 32-bit capture enhanced pulse capture n2het1[00] yes no n2het1[01] yes no n2het1[02] yes no n2het1[03] yes no n2het1[04] yes no n2het1[05] yes no n2het1[06] yes no n2het1[07] yes no n2het1[08] yes no n2het1[09] yes no n2het1[10] yes no n2het1[11] yes no n2het1[12] yes no n2het1[13] yes no n2het1[14] yes no n2het1[15] yes yes n2het1[16] yes no n2het1[17] yes no n2het1[18] yes no n2het1[19] yes no n2het1[20] yes yes copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 135 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com table 7-13. input capture pin capability (continued) channel supports 32-bit capture enhanced pulse capture n2het1[21] yes no n2het1[22] yes no n2het1[23] yes no n2het1[24] yes no n2het1[25] yes no n2het1[26] yes no n2het1[27] yes no n2het1[28] yes no n2het1[29] yes no n2het1[30] yes no n2het1[31] yes yes n2het2[00] yes no n2het2[01] no no n2het2[02] no no n2het2[03] no no n2het2[04] yes no n2het2[05] no no n2het2[06] yes no n2het2[07] no no n2het2[08] no no n2het2[09] no no n2het2[10] no no n2het2[11] no no n2het2[12] yes yes n2het2[13] no no n2het2[14] yes yes n2het2[15] no no n2het2[16] yes yes n2het2[18] no no 7.4.4 n2het1-n2het2 interconnections in some applications the n2het resolutions must be synchronized. some other applications require a single time base to be used for all pwm outputs and input timing captures. the n2het provides such a synchronization mechanism. the clk_master/slave (hetgcr.16) configures the n2het in master or slave mode (default is slave mode). a n2het in master mode provides a signal to synchronize the prescalers of the slave n2het. the slave n2het synchronizes its loop resolution to the loop resolution signal sent by the master. the slave does not require this signal after it receives the first synchronization signal. however, anytime the slave receives the resynchronization signal from the master, the slave must synchronize itself again.. figure 7-6. n2het1 ? n2het2 synchronization hookup 136 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback nhet_loop_sync ext_loop_sync ext_loop_sync nhet_loop_sync n2het1 n2het2
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.4.5 n2het checking 7.4.5.1 internal monitoring to assure correctness of the high-end timer operation and output signals, the two n2het modules can be used to monitor each other ? s signals as shown in figure 7-7 . the direction of the monitoring is controlled by the i/o multiplexing control module. figure 7-7. n2het monitoring 7.4.5.2 output monitoring using dual clock comparator (dcc) n2het1[31] is connected as a clock source for counter 1 in dcc1. this allows the application to measure the frequency of the pulse-width modulated (pwm) signal on n2het1[31]. similarly, n2het2[0] is connected as a clock source for counter 1 in dcc2. this allows the application to measure the frequency of the pulse-width modulated (pwm) signal on n2het2[0]. both n2het1[31] and n2het2[0] can be configured to be internal-only channels. that is, the connection to the dcc module is made directly from the output of the n2hetx module (from the input of the output buffer). for more information on dcc see section 6.7.3 . 7.4.6 disabling n2het outputs some applications require the n2het outputs to be disabled under some fault condition. the n2het module provides this capability via the "pin disable" input signal. this signal, when driven low, causes the n2het outputs identified by a programmable register (hetpindis) to be tri-stated. see the device specific technical reference manual for more details on the "n2het pin disable" feature. gioa[5] is connected to the "pin disable" input for n2het1, and giob[2] is connected to the "pin disable" input for n2het2. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 137 submit documentation feedback n2het1n2het2 iomm mux control signal x n2het1[1,3,5,7,9,11] / n2het2[8,10,12,14,16,18] n2het1[1,3,5,7,9,11] n2het2[8,10,12,14,16,18]
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.4.7 high-end timer transfer unit (htu) a high-end timer transfer unit (htu) can perform dma type transactions to transfer n2het data to or from main memory. an mpu is built into the htu. 7.4.7.1 features ? cpu and dma independent ? master port to access system memory ? 8 control packets supporting dual buffer configuration ? control packet information is stored in ram protected by parity ? event synchronization (het transfer requests) ? supports 32- or 64-bit transactions ? addressing modes for het address (8 byte or 16 byte) and system memory address (fixed, 32 bit or 64 bit) ? one shot, circular and auto switch buffer transfer modes ? request lost detection 7.4.7.2 trigger connections table 7-14. htu1 request line connection modules request source htu1 request n2het1 htureq[0] htu1 dcp[0] n2het1 htureq[1] htu1 dcp[1] n2het1 htureq[2] htu1 dcp[2] n2het1 htureq[3] htu1 dcp[3] n2het1 htureq[4] htu1 dcp[4] n2het1 htureq[5] htu1 dcp[5] n2het1 htureq[6] htu1 dcp[6] n2het1 htureq[7] htu1 dcp[7] table 7-15. htu2 request line connection modules request source htu2 request n2het2 htureq[0] htu2 dcp[0] n2het2 htureq[1] htu2 dcp[1] n2het2 htureq[2] htu2 dcp[2] n2het2 htureq[3] htu2 dcp[3] n2het2 htureq[4] htu2 dcp[4] n2het2 htureq[5] htu2 dcp[5] n2het2 htureq[6] htu2 dcp[6] n2het2 htureq[7] htu2 dcp[7] 138 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.5 controller area network (dcan) the dcan supports the can 2.0b protocol standard and uses a serial, multimaster communication protocol that efficiently supports distributed real-time control with robust communication rates of up to 1 mbps. the dcan is ideal for applications operating in noisy and harsh environments (for example, automotive and industrial fields) that require reliable serial communication or multiplexed wiring. 7.5.1 features features of the dcan module include: ? supports can protocol version 2.0 part a, b ? bit rates up to 1 mbps ? the can kernel can be clocked by the oscillator for baud-rate generation. ? 64 mailboxes on each dcan ? individual identifier mask for each message object ? programmable fifo mode for message objects ? programmable loop-back modes for self-test operation ? automatic bus on after bus-off state by a programmable 32-bit timer ? message ram protected by parity ? direct access to message ram during test mode ? can rx / tx pins configurable as general purpose io pins ? message ram auto initialization ? dma support for more information on the dcan, see the rm48x 16/32-bit risc flash microcontroller technical reference manual ( spnu503 ). 7.5.2 electrical and timing specifications table 7-16. dynamic characteristics for the dcanx tx and rx pins parameter min max unit t d(canntx) delay time, transmit shift register to canntx pin (1) 15 ns t d(cannrx) delay time, cannrx pin to receive shift register 5 ns (1) these values do not include rise/fall times of the output buffer. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 139 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.6 local interconnect network interface (lin) the sci/lin module can be programmed to work either as an sci or as a lin. the core of the module is an sci. the hardware features of the sci are augmented to achieve lin compatibility. the sci module is a universal asynchronous receiver-transmitter (uart) that implements the standard nonreturn to zero format. the sci can be used to communicate, for example, through an rs-232 port or over a k-line. the lin standard is based on the sci (uart) serial data link format. the communication concept is single-master/multiple-slave with a message identification for multicast transmission between any network nodes. 7.6.1 lin features the following are features of the lin module: ? compatible to lin 1.3, 2.0, and 2.1 protocols ? multibuffered receive and transmit units dma capability for minimal cpu intervention ? identification masks for message filtering ? automatic master header generation ? programmable synch break field ? synch field ? identifier field ? slave automatic synchronization ? synch break detection ? optional baudrate update ? synchronization validation ? 2 31 programmable transmission rates with 7 fractional bits ? error detection ? 2 interrupt lines with priority encoding 140 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.7 serial communication interface (sci) 7.7.1 features ? standard uart communication ? supports full- or half-duplex operation ? standard nonreturn to zero (nrz) format ? double-buffered receive and transmit functions ? configurable frame format of 3 to 13 bits per character based on the following: ? data word length programmable from 1 to 8 bits ? additional address bit in address-bit mode ? parity programmable for zero or 1 parity bit, odd or even parity ? stop programmable for 1 or 2 stop bits ? asynchronous or isosynchronous communication modes ? two multiprocessor communication formats allow communication between more than two devices. ? sleep mode is available to free cpu resources during multiprocessor communication. ? the 24-bit programmable baud rate supports 2 24 different baud rates provide high accuracy baud rate selection. ? four error flags and five status flags provide detailed information regarding sci events. ? capability to use dma for transmit and receive data. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 141 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.8 inter-integrated circuit (i2c) the inter-integrated circuit (i2c) module is a multimaster communication module providing an interface between the rm4x microcontroller and devices compliant with philips semiconductor i2c-bus specification version 2.1 and connected by an i 2 c-bus ? . this module will support any slave or master i2c compatible device. 7.8.1 features the i2c has the following features: ? compliance to the philips i 2 c-bus specification, v2.1 (the i2c specification, philips document number 9398 393 40011) ? bit/byte format transfer ? 7-bit and 10-bit device addressing modes ? general call ? start byte ? multimaster transmitter/ slave receiver mode ? multimaster receiver/ slave transmitter mode ? combined master transmit/receive and receive/transmit mode ? transfer rates of 10 kbps up to 400 kbps (phillips fast-mode rate) ? free data format ? two dma events (transmit and receive) ? dma event enable/disable capability ? seven interrupts that can be used by the cpu ? module enable/disable capability ? the sda and scl are optionally configurable as general-purpose i/o ? slew rate control of the outputs ? open-drain control of the outputs ? programmable pullup/pulldown capability on the inputs ? supports ignore nack mode note this i2c module does not support: ? high-speed (hs) mode ? c-bus compatibility mode ? the combined format in 10-bit address mode (the i2c module sends the slave address second byte every time it sends the slave address first byte) 142 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.8.2 i2c i/o timing specifications table 7-17. i2c signals (sda and scl) switching characteristics (1) standard mode fast mode parameter unit min max min max cycle time, internal module clock for i2c, t c(i2cclk) 75.2 149 75.2 149 ns prescaled from vclk f (scl) scl clock frequency 0 100 0 400 khz t c(scl) cycle time, scl 10 2.5 s setup time, scl high before sda low (for a t su(sclh-sdal) 4.7 0.6 s repeated start condition) hold time, scl low after sda low (for a repeated t h(scll-sdal) 4 0.6 s start condition) t w(scll) pulse duration, scl low 4.7 1.3 s t w(sclh) pulse duration, scl high 4 0.6 s t su(sda-sclh) setup time, sda valid before scl high 250 100 ns hold time, sda valid after scl low (for i2c bus t h(sda-scll) 0 3.45 (2) 0 0.9 s devices) pulse duration, sda high between stop and t w(sdah) 4.7 1.3 s start conditions setup time, scl high before sda high (for stop t su(sclh-sdah) 4.0 0.6 s condition) t w(sp) pulse duration, spike (must be suppressed) 0 50 ns c b (3) capacitive load for each bus line 400 400 pf (1) the i2c pins sda and scl do not feature fail-safe i/o buffers. these pins could potentially draw current when the device is powered down. (2) the maximum t h(sda-scll) for i2c bus devices has only to be met if the device does not stretch the low period (t w(scll) ) of the scl signal. (3) c b = the total capacitance of one bus line in pf. figure 7-8. i2c timings copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 143 submit documentation feedback sda scl t w(sdah) t w(scll) t w(sclh) t w(sp) t h(scll-sdal) t h(sda-scll) t h(scll-sdal) t su(sclh-sdal) t f(scl) t c(scl) t r(scl) t su(sclh-sdah) stop start repeated start stop t su(sda-sclh)
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com note ? a device must internally provide a hold time of at least 300 ns for the sda signal (referred to the vihmin of the scl signal) to bridge the undefined region of the falling edge of scl. ? the maximum t h(sda-scll) has only to be met if the device does not stretch the low period (t w(scll) ) of the scl signal. ? a fast-mode i2c-bus device can be used in a standard-mode i2c-bus system, but the requirement t su(sda-sclh) 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line tr max + t su(sda-sclh) . ? c b = total capacitance of one bus line in pf. if mixed with fast-mode devices, faster fall- times are allowed. 144 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.9 multibuffered / standard serial peripheral interface the mibspi is a high-speed synchronous serial input/output port that allows a serial bit stream of programmed length (2 to 16 bits) to be shifted in and out of the device at a programmed bit-transfer rate. typical applications for the spi include interfacing to external peripherals, such as i/os, memories, display drivers, and analog-to-digital converters. 7.9.1 features both standard and mibspi modules have the following features: ? 16-bit shift register ? receive buffer register ? 11-bit baud clock generator ? spiclk can be internally-generated (master mode) or received from an external clock source (slave mode) ? each word transferred can have a unique format ? spi i/os not used in the communication can be used as digital input/output signals table 7-18. mibspi/spi configurations mibspix/spix i/os mibspi1 mibspi1simo[1:0], mibspi1somi[1:0], mibspi1clk, mibspi1ncs[5:0], mibspi1nena mibspi3 mibspi3simo, mibspi3somi, mibspi3clk, mibspi3ncs[5:0], mibspi3nena mibspi5 mibspi5simo[3:0], mibspi5somi[3:0], mibspi5clk, mibspi5ncs[3:0], mibspi5nena spi2 spi2simo, spi2somi, spi2clk, spi2ncs[1:0], spi2nena spi4 spi4simo, spi4somi, spi4clk, spi4ncs[0], spi4nena 7.9.2 mibspi transmit and receive ram organization the multibuffer ram is comprised of 128 buffers. each entry in the multibuffer ram consists of 4 parts: a 16-bit transmit field, a 16-bit receive field, a 16-bit control field and a 16-bit status field. the multibuffer ram can be partitioned into multiple transfer group with variable number of buffers each. 7.9.3 mibspi transmit trigger events each of the transfer groups can be configured individually. for each of the transfer groups a trigger event and a trigger source can be chosen. a trigger event can be for example a rising edge or a permanent low level at a selectable trigger source. for example, up to 15 trigger sources are available which can be used by each transfer group. these trigger options are listed in table 7-19 for mibspi1, section 7.9.3.2 for mibspi3 and section 7.9.3.3 for mibspi5. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 145 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.9.3.1 mibspi1 event trigger hookup table 7-19. mibspi1 event trigger hookup event # tgxctrl trigsrc[3:0] trigger disabled 0000 no trigger source event0 0001 gioa[0] event1 0010 gioa[1] event2 0011 gioa[2] event3 0100 gioa[3] event4 0101 gioa[4] event5 0110 gioa[5] event6 0111 gioa[6] event7 1000 gioa[7] event8 1001 n2het1[8] event9 1010 n2het1[10] event10 1011 n2het1[12] event11 1100 n2het1[14] event12 1101 n2het1[16] event13 1110 n2het1[18] event14 1111 internal tick counter note for n2het1 trigger sources, the connection to the mibspi1 module trigger input is made from the input side of the output buffer (at the n2het1 module boundary). this way, a trigger condition can be generated even if the n2het1 signal is not selected to be output on the pad. note for giox trigger sources, the connection to the mibspi1 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by selecting the giox pin as an output pin, or by driving the giox pin from an external trigger source. 7.9.3.2 mibspi3 event trigger hookup table 7-20. mibspi3 event trigger hookup event # tgxctrl trigsrc[3:0] trigger disabled 0000 no trigger source event0 0001 gioa[0] event1 0010 gioa[1] event2 0011 gioa[2] event3 0100 gioa[3] event4 0101 gioa[4] event5 0110 gioa[5] event6 0111 gioa[6] event7 1000 gioa[7] event8 1001 het[8] event9 1010 n2het1[10] event10 1011 n2het1[12] event11 1100 n2het1[14] 146 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 7-20. mibspi3 event trigger hookup (continued) event # tgxctrl trigsrc[3:0] trigger event12 1101 n2het1[16] event13 1110 n2het1[18] event14 1111 internal tick counter note for n2het1 trigger sources, the connection to the mibspi3 module trigger input is made from the input side of the output buffer (at the n2het1 module boundary). this way, a trigger condition can be generated even if the n2het1 signal is not selected to be output on the pad. note for giox trigger sources, the connection to the mibspi3 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by selecting the giox pin as an output pin, or by driving the giox pin from an external trigger source. 7.9.3.3 mibspi5 event trigger hookup table 7-21. mibspi5 event trigger hookup event # tgxctrl trigsrc[3:0] trigger disabled 0000 no trigger source event0 0001 gioa[0] event1 0010 gioa[1] event2 0011 gioa[2] event3 0100 gioa[3] event4 0101 gioa[4] event5 0110 gioa[5] event6 0111 gioa[6] event7 1000 gioa[7] event8 1001 n2het1[8] event9 1010 n2het1[10] event10 1011 n2het1[12] event11 1100 n2het1[14] event12 1101 n2het1[16] event13 1110 n2het1[18] event14 1111 internal tick counter note for n2het1 trigger sources, the connection to the mibspi5 module trigger input is made from the input side of the output buffer (at the n2het1 module boundary). this way, a trigger condition can be generated even if the n2het1 signal is not selected to be output on the pad. copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 147 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com note for giox trigger sources, the connection to the mibspi5 module trigger input is made from the output side of the input buffer. this way, a trigger condition can be generated either by selecting the giox pin as an output pin + selecting the pin to be a giox pin, or by driving the giox pin from an external trigger source. if the mux control module is used to select different functionality instead of the giox signal, then care must be taken to disable giox from triggering mibspi5 transfers; there is no multiplexing on the input connections. 148 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.9.4 mibspi/spi master mode i/o timing specifications table 7-22. spi master mode external timing parameters (clock phase = 0, spiclk = output, spisimo = output, and spisomi = input) (1) (2) (3) no. parameter min max unit 1 t c(spc)m cycle time, spiclk (4) 40 256t c(vclk) ns pulse duration, spiclk high (clock t w(spch)m 0.5t c(spc)m ? t r(spc)m ? 3 0.5t c(spc)m + 3 polarity = 0) 2 (5) ns pulse duration, spiclk low (clock t w(spcl)m 0.5t c(spc)m ? t f(spc)m ? 3 0.5t c(spc)m + 3 polarity = 1) pulse duration, spiclk low (clock t w(spcl)m 0.5t c(spc)m ? t f(spc)m ? 3 0.5t c(spc)m + 3 polarity = 0) 3 (5) ns pulse duration, spiclk high (clock t w(spch)m 0.5t c(spc)m ? t r(spc)m ? 3 0.5t c(spc)m + 3 polarity = 1) delay time, spisimo valid before t d(spch-simo)m 0.5t c(spc)m ? 6 spiclk low (clock polarity = 0) 4 (5) ns delay time, spisimo valid before t d(spcl-simo)m 0.5t c(spc)m ? 6 spiclk high (clock polarity = 1) valid time, spisimo data valid after t v(spcl-simo)m 0.5t c(spc)m ? t f(spc) ? 4 spiclk low (clock polarity = 0) 5 (5) ns valid time, spisimo data valid after t v(spch-simo)m 0.5t c(spc)m ? t r(spc) ? 4 spiclk high (clock polarity = 1) setup time, spisomi before spiclk t su(somi-spcl)m t f(spc) + 2.2 low (clock polarity = 0) 6 (5) ns setup time, spisomi before spiclk t su(somi-spch)m t r(spc) + 2.2 high (clock polarity = 1) hold time, spisomi data valid after t h(spcl-somi)m 10 spiclk low (clock polarity = 0) 7 (5) ns hold time, spisomi data valid after t h(spch-somi)m 10 spiclk high (clock polarity = 1) c2tdelay*t c(vclk) + 2*t c(vclk) (c2tdelay+2) * t c(vclk) - cshold = 0 setup time cs active - t f(spics) + t r(spc) ? 7 t f(spics) + t r(spc) + 5.5 until spiclk high c2tdelay*t c(vclk) + 3*t c(vclk) (c2tdelay+3) * t c(vclk) - (clock polarity = 0) cshold = 1 - t f(spics) + t r(spc) ? 7 t f(spics) + t r(spc) + 5.5 8 (6) t c2tdelay ns c2tdelay*t c(vclk) + 2*t c(vclk) (c2tdelay+2) * t c(vclk) - cshold = 0 setup time cs active - t f(spics) + t f(spc) ? 7 t f(spics) + t f(spc) + 5.5 until spiclk low c2tdelay*t c(vclk) + 3*t c(vclk) (c2tdelay+3) * t c(vclk) - (clock polarity = 1) cshold = 1 - t f(spics) + t f(spc) ? 7 t f(spics) + t f(spc) + 5.5 0.5*t c(spc)m + 0.5*t c(spc)m + hold time spiclk low until cs inactive t2cdelay*t c(vclk) + t c(vclk) - t2cdelay*t c(vclk) + t c(vclk) - (clock polarity = 0) t f(spc) + t r(spics) - 7 t f(spc) + t r(spics) + 11 9 (6) t t2cdelay ns 0.5*t c(spc)m + 0.5*t c(spc)m + hold time spiclk high until cs t2cdelay*t c(vclk) + t c(vclk) - t2cdelay*t c(vclk) + t c(vclk) - inactive (clock polarity = 1) t r(spc) + tr(spics) - 7 t r(spc) + t r(spics) + 11 (c2tdelay+1) * t c(vclk) - ns 10 t spiena spienan sample point (c2tdelay+1)*t c(vclk) t f(spics) ? 29 spienan sample point from write to ns 11 t spienaw (c2tdelay+2)*t c(vclk) buffer (1) the master bit (spigcr1.0) is set and the clock phase bit (spifmtx.16) is cleared. (2) t c(vclk) = interface clock cycle time = 1 / f (vclk) (3) for rise and fall timings, see table 5-7 . (4) when the spi is in master mode, the following must be true: for ps values from 1 to 255: t c(spc)m (ps +1)t c(vclk) 40 ns, where ps is the prescale value set in the spifmtx.[15:8] register bits. for ps values of 0: t c(spc)m = 2t c(vclk) 40 ns. the external load on the spiclk pin must be less than 60 pf. (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spifmtx.17). (6) c2tdelay and t2cdelay is programmed in the spidelay register copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 149 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-9. spi master mode external timing (clock phase = 0) figure 7-10. spi master mode chip select timing (clock phase = 0) 150 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback spiclk (clock polarity=0) spisimo spicsn master out data is valid 9 spiclk (clock polarity=1) spienan 10 write to buffer 11 8 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) master in data must be valid master out data is valid 3 2 1 5 4 6 6 7
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 7-23. spi master mode external timing parameters (clock phase = 1, spiclk = output, spisimo = output, and spisomi = input) (1) (2) (3) no. parameter min max unit 1 t c(spc)m cycle time, spiclk (4) 40 256t c(vclk) ns pulse duration, spiclk high (clock t w(spch)m 0.5t c(spc)m ? t r(spc)m ? 3 0.5t c(spc)m + 3 polarity = 0) 2 (5) ns pulse duration, spiclk low (clock t w(spcl)m 0.5t c(spc)m ? t f(spc)m ? 3 0.5t c(spc)m + 3 polarity = 1) pulse duration, spiclk low (clock t w(spcl)m 0.5t c(spc)m ? t f(spc)m ? 3 0.5t c(spc)m + 3 polarity = 0) 3 (5) ns pulse duration, spiclk high (clock t w(spch)m 0.5t c(spc)m ? t r(spc)m ? 3 0.5t c(spc)m + 3 polarity = 1) valid time, spiclk high after t v(simo-spch)m spisimo data valid (clock polarity = 0.5t c(spc)m ? 6 0) 4 (5) ns valid time, spiclk low after t v(simo-spcl)m spisimo data valid (clock polarity = 0.5t c(spc)m ? 6 1) valid time, spisimo data valid after t v(spch-simo)m 0.5t c(spc)m ? t r(spc) ? 4 spiclk high (clock polarity = 0) 5 (5) ns valid time, spisimo data valid after t v(spcl-simo)m 0.5t c(spc)m ? t f(spc) ? 4 spiclk low (clock polarity = 1) setup time, spisomi before t su(somi-spch)m t r(spc) + 2.2 spiclk high (clock polarity = 0) 6 (5) ns setup time, spisomi before t su(somi-spcl)m t f(spc) + 2.2 spiclk low (clock polarity = 1) valid time, spisomi data valid after t v(spch-somi)m 10 spiclk high (clock polarity = 0) 7 (5) ns valid time, spisomi data valid after t v(spcl-somi)m 10 spiclk low (clock polarity = 1) 0.5*t c(spc)m + 0.5*t c(spc)m + cshold = 0 (c2tdelay+2) * t c(vclk) - (c2tdelay+2) * t c(vclk) - setup time cs t f(spics) + t r(spc) ? 7 t f(spics) + t r(spc) + 5.5 active until spiclk high (clock polarity = 0.5*t c(spc)m + 0.5*t c(spc)m + 0) cshold = 1 (c2tdelay+3) * t c(vclk) - (c2tdelay+3) * t c(vclk) - t f(spics) + t r(spc) ? 7 t f(spics) + t r(spc) + 5.5 8 (6) t c2tdelay ns 0.5*t c(spc)m + 0.5*t c(spc)m + cshold = 0 (c2tdelay+2) * t c(vclk) - (c2tdelay+2) * t c(vclk) - setup time cs t f(spics) + t f(spc) ? 7 t f(spics) + t f(spc) + 5.5 active until spiclk low (clock polarity = 0.5*t c(spc)m + 0.5*t c(spc)m + 1) cshold = 1 (c2tdelay+3) * t c(vclk) - (c2tdelay+3) * t c(vclk) - t f(spics) + t f(spc) ? 7 t f(spics) + t f(spc) + 5.5 t2cdelay*t c(vclk) + t2cdelay*t c(vclk) + hold time spiclk low until cs t c(vclk) - t f(spc) + t r(spics) - t c(vclk) - t f(spc) + t r(spics) + inactive (clock polarity = 0) 7 11 9 (6) t t2cdelay ns t2cdelay*t c(vclk) + t2cdelay*t c(vclk) + hold time spiclk high until cs t c(vclk) - t r(spc) + t r(spics) - t c(vclk) - t r(spc) + t r(spics) + inactive (clock polarity = 1) 7 11 (c2tdelay+1)* t c(vclk) - ns 10 t spiena spienan sample point (c2tdelay+1)*t c(vclk) t f(spics) ? 29 spienan sample point from write to ns 11 t spienaw (c2tdelay+2)*t c(vclk) buffer (1) the master bit (spigcr1.0) is set and the clock phase bit (spifmtx.16) is set. (2) t c(vclk) = interface clock cycle time = 1 / f (vclk) (3) for rise and fall timings, see the table 5-7 . (4) when the spi is in master mode, the following must be true: for ps values from 1 to 255: t c(spc)m (ps +1)t c(vclk) 40 ns, where ps is the prescale value set in the spifmtx.[15:8] register bits. for ps values of 0: t c(spc)m = 2t c(vclk) 40 ns. the external load on the spiclk pin must be less than 60 pf. (5) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spifmtx.17). (6) c2tdelay and t2cdelay is programmed in the spidelay register copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 151 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-11. spi master mode external timing (clock phase = 1) figure 7-12. spi master mode chip select timing (clock phase = 1) 152 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback spiclk (clock polarity=0) spisimo spicsn master out data is valid 9 spiclk (clock polarity=1) spienan 10 write to buffer 11 8 spisomi spisimo spiclk (clock polarity = 1) spiclk (clock polarity = 0) data valid master in data must be valid master out data is valid 3 2 1 5 4 7 6
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.9.5 spi slave mode i/o timings table 7-24. spi slave mode external timing parameters (clock phase = 0, spiclk = input, spisimo = input, and spisomi = output) (1) (2) (3) (4) no. parameter min max unit 1 t c(spc)s cycle time, spiclk (5) 40 ns 2 (6) t w(spch)s pulse duration, spiclk high (clock polarity = 0) 14 ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 14 3 (6) t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 14 ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 14 4 (6) delay time, spisomi valid after spiclk high (clock t d(spch-somi)s t rf(somi) + 20 polarity = 0) ns delay time, spisomi valid after spiclk low (clock polarity t d(spcl-somi)s t rf(somi) + 20 = 1) 5 (6) hold time, spisomi data valid after spiclk high (clock t h(spch-somi)s 2 polarity =0) ns hold time, spisomi data valid after spiclk low (clock t h(spcl-somi)s 2 polarity =1) 6 (6) setup time, spisimo before spiclk low (clock polarity = t su(simo-spcl)s 4 0) ns setup time, spisimo before spiclk high (clock polarity = t su(simo-spch)s 4 1) hold time, spisimo data valid after spiclk low (clock t h(spcl-simo)s 2 polarity = 0) 7 (6) ns hold time, spisimo data valid after s piclk high (clock t h(spch-simo)s 2 polarity = 1) delay time, spienan high after last spiclk low (clock 2.5t c(vclk) +t r(enan) + t d(spcl-senah)s 1.5t c(vclk) polarity = 0) 22 8 ns delay time, spienan high after last spiclk high (clock 2.5t c(vclk) + t r(enan) + t d(spch-senah)s 1.5t c(vclk) polarity = 1) 22 delay time, spienan low after spicsn low (if new data 9 t d(scsl-senal)s t f(enan) t c(vclk) +t f(enan) +27 ns has been written to the spi buffer) (1) the master bit (spigcr1.0) is cleared and the clock phase bit (spifmtx.16) is cleared. (2) if the spi is in slave mode, the following must be true: t c(spc)s (ps + 1) t c(vclk) , where ps = prescale value set in spifmtx.[15:8]. (3) for rise and fall timings, see table 5-7 . (4) t c(vclk) = interface clock cycle time = 1 /f (vclk) (5) when the spi is in slave mode, the following must be true: for ps values from 1 to 255: t c(spc)s (ps +1)t c(vclk) 40 ns, where ps is the prescale value set in the spifmtx.[15:8] register bits. for ps values of 0: t c(spc)s = 2t c(vclk) 40 ns. (6) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spifmtx.17). copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 153 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-13. spi slave mode external timing (clock phase = 0) figure 7-14. spi slave mode enable timing (clock phase = 0) 154 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback spisomi spiclk (clock polarity = 1) spiclk (clock polarity = 0) 3 2 1 5 4 7 spisimo data must be valid spisomi data is valid 6 6 6 spisimo spiclk (clock polarity=0) spicsn 8 spiclk (clock polarity=1) spienan 9
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 table 7-25. spi slave mode external timing parameters (clock phase = 1, spiclk = input, spisimo = input, and spisomi = output) (1) (2) (3) (4) no. parameter min max unit 1 t c(spc)s cycle time, spiclk (5) 40 ns t w(spch)s pulse duration, spiclk high (clock polarity = 0) 14 2 (6) ns t w(spcl)s pulse duration, spiclk low (clock polarity = 1) 14 t w(spcl)s pulse duration, spiclk low (clock polarity = 0) 14 3 (6) ns t w(spch)s pulse duration, spiclk high (clock polarity = 1) 14 dealy time, spisomi data valid after spiclk low t d(somi-spcl)s t rf(somi) + 20 (clock polarity = 0) 4 (6) ns delay time, spisomi data valid after spiclk high t d(somi-spch)s t rf(somi) + 20 (clock polarity = 1) hold time, spisomi data valid after spiclk high t h(spcl-somi)s 2 (clock polarity =0) 5 (6) ns hold time, spisomi data valid after spiclk low (clock t h(spch-somi)s 2 polarity =1) setup time, spisimo before spiclk high (clock t su(simo-spch)s 4 polarity = 0) 6 (6) ns setup time, spisimo before spiclk low (clock polarity t su(simo-spcl)s 4 = 1) high time, spisimo data valid after spiclk high t v(spch-simo)s 2 (clock polarity = 0) 7 (6) ns high time, spisimo data valid after spiclk low (clock t v(spcl-simo)s 2 polarity = 1) delay time, spienan high after last spiclk high t d(spch-senah)s 1.5t c(vclk) 2.5t c(vclk) +t r(enan) + 22 (clock polarity = 0) 8 ns delay time, spienan high after last spiclk low (clock t d(spcl-senah)s 1.5t c(vclk) 2.5t c(vclk) +t r(enan) + 22 polarity = 1) delay time, spienan low after spicsn low (if new data 9 t d(scsl-senal)s t f(enan) t c(vclk) +t f(enan) + 27 ns has been written to the spi buffer) delay time, somi valid after spicsn low (if new data 10 t d(scsl-somi)s t c(vclk) 2t c(vclk) +t rf(somi) + 28 ns has been written to the spi buffer) (1) the master bit (spigcr1.0) is cleared and the clock phase bit (spifmtx.16) is set. (2) if the spi is in slave mode, the following must be true: tc(spc)s (ps + 1) tc(vclk), where ps = prescale value set in spifmtx.[15:8]. (3) for rise and fall timings, see table 5-7 . (4) t c(vclk) = interface clock cycle time = 1 /f (vclk) (5) when the spi is in slave mode, the following must be true: for ps values from 1 to 255: t c(spc)s (ps +1)t c(vclk) 40 ns, where ps is the prescale value set in the spifmtx.[15:8] register bits. for ps values of 0: t c(spc)s = 2t c(vclk) 40 ns. (6) the active edge of the spiclk signal referenced is controlled by the clock polarity bit (spifmtx.17). copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 155 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-15. spi slave mode external timing (clock phase = 1) figure 7-16. spi slave mode enable timing (clock phase = 1) 156 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback spisomi slave out data is valid spiclk (clock polarity=0) spicsn 8 spiclk (clock polarity=1) spienan 9 10 spisimo spisomi 5 7 spisimo data must be valid spisomi data is valid 6 6 6 spiclk (clock polarity = 1) spiclk (clock polarity = 0) 3 2 1 4
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.10 ethernet media access controller the ethernet media access controller (emac) provides an efficient interface between the cpu and the network. the emac supports both 10base-t and 100base-tx, or 10 mbits/second (mbps) and 100 mbps in either half- or full-duplex mode, with hardware flow control and quality of service (qos) support. the emac controls the flow of packet data from the rm4x device to the phy. the mdio module controls phy configuration and status monitoring. both the emac and the mdio modules interface to the rm4x device through a custom interface that allows efficient data transmission and reception. this custom interface is referred to as the emac control module, and is considered integral to the emac/mdio peripheral. the control module is also used to multiplex and control interrupts. 7.10.1 ethernet mii electrical and timing specifications figure 7-17. mii receive timing table 7-26. timing requirements for emac mii receive no. min max unit t su(miirxd - miirxclkh) setup time, mii_rxd[3:0] before mii_rx_clk rising edge 8 ns 1 t su(miirxdv - miirxclkh) setup time, mii_rx_dv before mii_rx_clk rising edge 8 ns t su(miirxer - miirxclkh) setup time, mii_rx_er before mii_rx_clk rising edge 8 ns t h(miirxclkh - miirxd) hold time, mii_rxd[3:0] valid after mii_rx_clk rising edge 8 ns 2 t h(miirxclkh - miirxdv) hold time, mii_rx_dv valid after mii_rx_clk rising edge 8 ns t h(miirxclkh - miirxer) hold time, mii_rx_er valid after mii_rx_clk rising edge 8 ns copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 157 submit documentation feedback 1 2 mii_rx_clk mii_rxd[3:0] mii_rx_dv mii_rx_er valid
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-18. mii transmit timing table 7-27. switching characteristics over recommended operating conditions for emac mii transmit no. parameter min max unit t d(miirxclkh - miitxd) delay time, mii_tx_clk rising edge to mii_txd[3:0] valid 5 25 ns 1 t d(miirxclkh - miitxen) delay time, mii_tx_clk rising edge to mii_txen valid 5 25 ns 158 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback 1 mii_tx_clk mii_txd[3:0] mii_txen valid
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.10.2 ethernet rmii electrical and timing specifications figure 7-19. rmii timing diagram table 7-28. timing requirements for emac rmii receive and rmii_refclk no. min nom max unit 1 t c(refclk) cycle time, rmii_refclk 20 ns 2 t w(refclkh) pulse width, rmii_refclk high 7 13 ns 3 t w(refclkl) pulse width, rmii_refclk low 7 13 ns 6 t su(rxd-refclk) input setup time, rmii_rxd[1:0] valid before rmii_refclk high 4 ns 7 t h(refclk-rxd) input hold time, rmii_rxd[1:0] valid after rmii_refclk high 2 ns 8 t su(crsdv-refclk) input setup time, rmii_crs_dv valid before rmii_refclk high 4 ns 9 t h(refclk-crsdv) input hold time, rmii_crs_dv valid after rmii_refclk high 2 ns 10 t su(rxer-refclk) input setup time, rmii_rx_er valid before rmii_refclk high 4 ns 11 t h(refclk-rxer) input hold time, rmii_rx_er valid after rmii_refclk high 2 ns table 7-29. switching characteristics over recommended operating conditions for emac rmii transmit no. parameter min max unit 4 t d(refclk-txd) output delay time, rmii_refclk high to rmii_txd[1:0] valid 2 ns 5 t d(refclk-txen) output delay time, rmii_refclk high to rmii_txen valid 2 ns copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 159 submit documentation feedback 1 2 3 rmii_refclk rmii_txen rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv rmii_rx_er 6 7 11 9 8 5 4 10 5
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 7.10.3 management data input/output (mdio) electrical and timing specifications figure 7-20. mdio input timing table 7-30. timing requirements for mdio input no. min max unit 1 t c(mdclk) cycle time, mdclk 400 - ns 2 t w(mdclk) pulse duration, mdclk high or low 180 - ns 3 t t(mdclk) transition time, mdclk - 5 ns setup time, mdio data input valid before ns 4 t su(mdio-mdclkh) 33 (1) - mdclk high hold time, mdio data input valid after ns 5 t h(mdclkh-mdio) 10 - mdclk high (1) this is a discrepancy to ieee 802.3, but is compatible with many phy devices. figure 7-21. mdio output timing table 7-31. mdio output timing requirements no. min max unit 1 tc(mdclk) cycle time, mdclk 400 ? ns delay time, mdclk low to mdio data output 7 td(mdclkl-mdio) ? 7 100 ns valid 160 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback mdclk mdio (output) 1 7 3 mdclk mdio (input) 1 3 4 5
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 7.11 universal serial bus (usb) host and device controllers 7.11.1 features this device provides several varieties of usb functionality, including: ? one full-speed usb device port compatible with the usb specification revision 2.0 and usb specification revision 1.1 ? two usb host ports compatible with usb specification revision 2.0, which is based on the ohci specification for usb release 1.0. 7.11.2 electrical and timing specifications table 7-32. full-speed usb interface timing requirements (1) no. min max unit host time duration, usbx.vp and usbx.vm low together during 15 transition (2) fsu20 t d(vpl, vml) ns device time duration, usbx.vp and usbx.vm low together during 15 transition host time duration, usbx.vp and usbx.vm high together during 15 transition (2) fsu21 t d(vph, vmh) ns device time duration, usbx.vp and usbx.vm high together during 15 transition (1) the capacitive loading is equivalent to 15 pf. (2) applies to both host ports, usb1 and usb2 table 7-33. full-speed usb interface switching characteristics (1) no. parameter min max unit host delay time usbx.txen active ? 2.1 2.2 to usbx.txdat valid (2) fsu15 t d(txenl ? datv) ns device delay time usbx.txen active 0.6 7 to usbx.txdat valid host delay time usbx.txen active ? 2.0 2.5 to usbx.txse0 valid (2) fsu16 t d(txenl ? se0v) ns device delay time usbx.txen active ? 1.9 1.0 to usbx.txse0 valid host skew between usbx.txdat 0 1.7 and usbx.txse0 transition (2) fsu17 t s(dat ? se0) ns device skew between usbx.txdat 0 7.6 and usbx.txse0 transition host delay time usbx.txen inactive ? 2.2 1.8 to usbx.txdat invalid (2) fsu18 t d(txenh ? dati) ns device delay time usbx.txen 0.8 7.1 inactive to usbx.txdat invalid host delay time usbx.txen inactive ? 2.1 1.8 to usbx.txse0 invalid (2) fsu19 t d(txenh ? se0i) ns device delay time usbx.txen ? 1.9 1.1 inactive to usbx.txse0 invalid (1) the capacitive loading is equivalent to 15 pf. (2) applies to both host ports, usb1 and usb2 copyright ? 2011 ? 2015, texas instruments incorporated peripheral information and electrical specifications 161 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 7-22. full-speed usb interface ? transmit and receive modes 162 peripheral information and electrical specifications copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback usbx.txen usbx.txdat usbx.txse0 usbx.vp usbx.vm usbx.rcv transmit receive fsu15 fsu18 fsu16 fsu19 fsu17 fsu20 fsu20 fsu21 fsu21
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 8 device and documentation support 8.1 device support 8.1.1 development support texas instruments (ti) offers an extensive line of development tools for the tms570lsxrm48lx family of mcus, including tools to evaluate the performance of the processors, generate code, develop algorithm implementations, and fully integrate and debug software and hardware modules. the following products support development: software development tools ? code composer studio ? (ccs) integrated development environment (ide) ? ? c/c++ compiler ? code generation tools ? assembler/linker ? fpu optimized libraries ? application algorithms ? sample applications code hardware development tools ? development and evaluation boards ? jtag-based emulators - xds510 ? class, xds560 ? emulator, xds100v2, xds110, xds200 ? flash programming tools for a complete listing of development-support tools, visit the texas instruments website at www.ti.com . 8.1.2 device nomenclature to designate the stages in the product development cycle, ti assigns prefixes to the part numbers of all mcu devices. each mcu commercial family member has one of three prefixes: x, p, or null [blank] (for example, xrm48l952). these prefixes represent evolutionary stages of product development from engineering prototypes (x) through fully qualified production devices (null[blank]). device development evolutionary flow: x experimental device that is not necessarily representative of the final device's electrical specifications. p final silicon die that conforms to the device's electrical specifications but has not completed quality and reliability verification. null fully-qualified production device. x and p devices are shipped against the following disclaimer: "developmental product is intended for internal evaluation purposes." production devices have been characterized fully, and the quality and reliability of the device have been demonstrated fully. ti's standard warranty applies. predictions show that prototype devices (x or p) have a greater failure rate than the standard production devices. texas instruments recommends that these devices not be used in any production system because their expected end-use failure rate still is undefined. only qualified production devices are to be used. figure 8-1 shows the numbering and symbol nomenclature for the rm48l952. for additional information on the device nomenclature markings, see the device-specific silicon errata document listed in section 8.2.1 , related documentation from texas instruments . copyright ? 2011 ? 2015, texas instruments incorporated device and documentation support 163 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 8-1. rm48x device numbering conventions 164 device and documentation support copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback x r m 4 8 l 9 5 2 d z w t t r prefix:x = not qualified removed when qualified rm = real time microcontroller cpu: 4 = arm cortex-r4 flash / ram size: 9 = 3mb flash, 256kb ram series number architecture: l = lockstep temperature range: t = C40 c to 105 c o o shipping options: r = tape and reel package type: zwt = 337-pin plastic bga with pb-free solder ball pge = 144-pin plastic quad flatpack network interfaces:5 = ethernet and usb frequency: 2 = 220 mhz die revision: blank = die revision c d = die revision d
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 8.2 documentation support 8.2.1 related documentation from texas instruments the following documents describe the rm48l952 microcontroller. spnu503 rm48x 16/32-bit risc flash microcontroller technical reference manual details the integration, the environment, the functional description, and the programming models for each peripheral and subsystem in the device. spnz196 rm48x microcontroller, silicon revision c, silicon errata describes the usage notes and known exceptions to the functional specifications for the device silicon revision c. spnz223 rm48x microcontroller, silicon revision d, silicon errata describes the usage notes and known exceptions to the functional specifications for the device silicon revision d. spna207 calculating equivalent power-on-hours for hercules ? safety mcus details how to use the spreadsheet to calculate the aging effect of temperature on texas instruments hercules safety mcus. 8.3 community resources the following links connect to ti community resources. linked contents are provided "as is" by the respective contributors. they do not constitute ti specifications and do not necessarily reflect ti's views; see ti's terms of use . ti e2e ? online community ti's engineer-to-engineer (e2e) community. created to foster collaboration among engineers. at e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. ti embedded processors wiki texas instruments embedded processors wiki. established to help developers get started with embedded processors from texas instruments and to foster innovation and growth of general knowledge about the hardware and software surrounding these devices. 8.4 trademarks code composer studio, xds510, xds560, e2e are trademarks of texas instruments. coresight is a trademark of arm limited. arm, cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. all other trademarks are the property of their respective owners. 8.5 electrostatic discharge caution this integrated circuit can be damaged by esd. texas instruments recommends that all integrated circuits be handled with appropriate precautions. failure to observe proper handling and installation procedures can cause damage. esd damage can range from subtle performance degradation to complete device failure. precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. 8.6 glossary slyz022 ? ti glossary . this glossary lists and explains terms, acronyms, and definitions. 8.7 device identification code register the device identification code register identifies several aspects of the device including the silicon version. the details of the device identification code register are shown in table 8-1 . the device identification code register value for this device is: ? rev a = 0x802aad05 ? rev b = 0x802aad15 ? rev c = 0x802aad1d ? rev d = 0x802aad25 copyright ? 2011 ? 2015, texas instruments incorporated device and documentation support 165 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com figure 8-2. device id bit allocation register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 cp-15 unique id tech r-1 r-00000000010101 r-0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 perip i/o h ram tech volt flash ecc version 1 0 1 parit ecc age y r-101 r-0 r-1 r-10 r-1 r-00000 r-1 r-0 r-1 legend: r/w = read/write; r = read only; - n = value after reset table 8-1. device id bit allocation register field descriptions bit field value description 31 cp15 indicates the presence of coprocessor 15 1 cp15 present 30-17 unique id 10101 silicon version (revision) bits. this bit field holds a unique number for a dedicated device configuration (die). 16-13 tech process technology on which the device is manufactured. 0101 f021 12 i/o voltage i/o voltage of the device. 0 i/o are 3.3 v 11 peripheral peripheral parity parity 1 parity on peripheral memories 10-9 flash ecc flash ecc 10 program memory with ecc 8 ram ecc indicates if ram memory ecc is present. 1 ecc implemented 7-3 revision revision of the device. 2-0 101 the platform family id is always 0b101 166 device and documentation support copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 8.8 die identification registers the two die id registers at addresses 0xffffff7c and 0xffffff80 form a 64-bit die id with the information as shown in table 8-2 . table 8-2. die-id registers item number of bits bit location x coord. on wafer 12 0xffffff7c[11:0] y coord. on wafer 12 0xffffff7c[23:12] wafer # 8 0xffffff7c[31:24] lot # 24 0xffffff80[23:0] reserved 8 0xffffff80[31:24] copyright ? 2011 ? 2015, texas instruments incorporated device and documentation support 167 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 8.9 module certifications the following communications modules have received certification of adherence to a standard. 168 device and documentation support copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 8.9.1 dcan certification figure 8-3. dcan certification copyright ? 2011 ? 2015, texas instruments incorporated device and documentation support 169 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 8.9.2 lin certification 8.9.2.1 lin master mode figure 8-4. lin certification - master mode 170 device and documentation support copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 8.9.2.2 lin slave mode - fixed baud rate figure 8-5. lin certification - slave mode - fixed baud rate copyright ? 2011 ? 2015, texas instruments incorporated device and documentation support 171 submit documentation feedback
rm48l952 spns177d ? september 2011 ? revised june 2015 www.ti.com 8.9.2.3 lin slave mode - adaptive baud rate figure 8-6. lin certification - slave mode - adaptive baud rate 172 device and documentation support copyright ? 2011 ? 2015, texas instruments incorporated submit documentation feedback
rm48l952 www.ti.com spns177d ? september 2011 ? revised june 2015 9 mechanical packaging and orderable information 9.1 packaging information the following pages include mechanical packaging and orderable information. this information is the most current data available for the designated devices. this data is subject to change without notice and without revision of this document. for browser-based versions of this data sheet, refer to the left-hand navigation. copyright ? 2011 ? 2015, texas instruments incorporated mechanical packaging and orderable information 173 submit documentation feedback
package option addendum www.ti.com 23-oct-2015 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples RM48L952DPGET active lqfp pge 144 60 green (rohs & no sb/br) cu nipdau level-3-260c-168 hr -40 to 105 rm48 l952dpget rm48l952dzwtt active nfbga zwt 337 90 green (rohs & no sb/br) snagcu level-3-260c-168 hr -40 to 105 rm48 l952dzwtt (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release.
package option addendum www.ti.com 23-oct-2015 addendum-page 2 in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.

mechanical data mtqf017a october 1994 revised december 1996 1 post office box 655303 ? dallas, texas 75265 pge (s-pqfp-g144) plastic quad flatpack 4040147 / c 10/96 0,27 72 0,17 37 73 0,13 nom 0,25 0,75 0,45 0,05 min 36 seating plane gage plane 108 109 144 sq sq 22,20 21,80 1 19,80 17,50 typ 20,20 1,35 1,45 1,60 max m 0,08 0 7 0,08 0,50 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. falls within jedec ms-026
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