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1 features applications description SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 two channel sata 3-gbps redriver ? < 200 mw typ data rates up to 3.0 gbps ? < 5 mw (in sleep mode) sata gen 2.6, esata compliant excellent jitter and loss compensation capability to over 20 inch fr4 trace sata hot-plug capable 20-pin 4 4 qfn package supports common-mode biasing for oob signaling with fast turn-on channel selectable pre-emphasis notebooks, desktops, docking stations, fixed receiver equalization servers, workstations integrated termination low power the SN75LVCP412 is a dual channel, single lane sata redriver and signal conditioner supporting data rates up to 3.0 gbps. the device complies with sata specification revision 2.6 and esata requirements. the SN75LVCP412 operates from a single 3.3-v supply and has 100- ? line termination with self-biasing feature making the device suitable for ac coupling. the inputs incorporate an oob detector, which automatically squelches the output while maintaining a stable output common-mode voltage compliant to sata link. the device is also designed to handle ssc transmission per the sata specification. the SN75LVCP412 handles interconnect losses at both its input and output. the built-in transmitter pre-emphasis feature is capable of applying 0 db or 2.5 db of relative amplification at higher frequencies to counter the expected interconnect loss. on the receive side the device applies a fixed equalization of 7 db to boost input frequencies near 1.5 ghz. collectively, the input equalization and output pre-emphasis features of the device work to fully restore sata signal integrity over extended cable and backplane pathways. the device is hot-plug capable (1) preventing device damage under device hot-insertion such as async signal plug/removal, unpowered plug/removal, powered plug/removal, or surprise plug/removal. (1) requires use of ac coupling capacitors at differential inputs and outputs. ordering information (1) part number part marking package SN75LVCP412rtjr lvcp412 20-pin rtj reel (large) (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2008, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters.
typical application SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. 2 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412 ich r hdd sata cable (2m) esata connector pc motherboard r = SN75LVCP412 ich r notebook dock dock connector in notebook and desktop motherboard in notebook dock hdd sata cable (2m) esata connector r = SN75LVCP412
SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 figure 1. data flow block diagram table 1. control logic en d0 d1 function 0 x x low power mode 1 0 0 normal sata output (default state); ch 0 and ch 1 0 db 1 1 0 ch 0 2.5 db pre-emphasis; ch 1 0 db 1 0 1 ch 1 2.5 db pre-emphasis; ch 0 0 db 1 1 1 ch 0 and ch 1 2.5 db pre-emphasis copyright ? 2008, texas instruments incorporated submit documentation feedback 3 product folder link(s): SN75LVCP412 ctrl rtrt rtrt en [7] gnd [3, 13, 17-19] vcm = 1.6 v rx rx_0p [1] rx_0n [2] tx_op [15] tx_on [14] equalizer driver oob detect vcm rx rx_1n [12] rx_1p [11] SN75LVCP412 equalizer driver oob detect tx_1n [4] tx_1p [5] d1 [8] d0 [9] v [6, 10, 16, 20] cc
pin assignment SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com terminal functions pin name description pin name description 1 rx_0p input 0, non-inverting 11 rx_1p input 1, non-inverting 2 rx_0n input 0, inverting 12 rx_1n input 1, inverting 3 gnd ground 13 gnd ground 4 tx_1n output 1, inverting 14 tx_0n output 0, inverting 5 tx_1p output 1, non-inverting 15 tx_0p output 0, non-inverting 6 vcc power 16 vcc power 7 en (1) enable 17 gnd ground 8 d1 (2) pre-emphasis_1 18 gnd ground 9 d0 (2) pre-emphasis _0 19 gnd ground 10 vcc power 20 vcc power (1) en tied to vcc via internal pu resistor (2) d0 and d1 are tied to gnd via internal pd resistor 4 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412 20 19 18 17 16 7 8 9 10 1 2 3 4 5 thermal pad should be soldered to pcb gnd plane for efficient thermal performance 15 14 13 12 11 lvcp412rtj 6 rx_0p rx_0n gnd tx_1n tx_1p tx_0p tx_0n gnd rx_1n rx_1p vcc gndgnd gnd vcc vccen d1 d0 vcc bottom view 16 17 18 19 20 10 9 8 7 6 lvcp412rtj 1 2 3 4 5 11 12 13 14 15 vcc gndgnd gnd vcc vccen d1 d0 vcc tx_0p tx_0n gnd rx_1n rx_1p rx_0p rx_0n gnd tx_1n tx_1p top view
typical device implementation detailed description input equalization output pre-emphasis low power mode SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 each differential input of the SN75LVCP412 has 7 db of fixed equalization in its front stage. the equalization amplifies high frequency signals to correct for loss from the transmission channel. the input equalizer is designed to recover a signal even when no eye is present at the receiver and effectively supports fr4 trace at the input anywhere from < 4 inches to 20 inches or < 10 cm to > 50 cm. the SN75LVCP412 provides single step pre-emphasis from 0 db to 2.5 db at each of its differential outputs. pre-emphasis is controlled independently for each channel and is set by the control pins d0 and d1 as shown in table 1 . the pre-emphasis duration is 0.4 ui or 133 ps (typ) at sata 3-gbps speed. two low power modes are supported by the SN75LVCP412: sleep mode (triggered by en pin, en = 0v) ? low power mode is controlled by enable (en) pin. in its default state this pin is internally pulled high. pulling this pin low will put the device in sleep mode within 2 m s (max). in this mode all active components of the device are driven to their quiescent level and differential outputs are driven to hi-z (open). max power dissipation in this mode is 5 mw. exiting from this mode to normal operation requires a maximum latency of 20 m s. auto low power mode (triggered when a given channel is in electrical idle state; en = v cc ) ? the device enters and exits low power mode by actively monitoring input signal (v idp-p ) level on each of its channel independently. when input signal on either or both channel is in the electrical idle state, i.e. v idp-p < 50 mv and stays in this state for 3 m s the associated channel(s) enters into the low power state. in this copyright ? 2008, texas instruments incorporated submit documentation feedback 5 product folder link(s): SN75LVCP412 note: 1) place supply caps close to device pin 2) en can be left open or tied to supply when no external contro l is implemented 3) output pre-emphasis (d1, d0) is shown enabled. setting wi ll depend on device placement relative to esata connector 16 17 18 19 20 10 9 8 7 6 15 14 13 12 11 12 3 4 5 en 3.3 v lvcp412 rtj esat a con nec tor gpio rx_0p rx_0n tx_1n tx_1p tx_0p tx_0n rx_1n rx_1p d 1 d 0 4.7 k 4. 7k 1 f m 0.1 f m sata hos t 10 nf 10 nf 10 nf 10 nf 10 nf 10 nf 10 nf 10 nf 0.01 f m
out-of-band (oob) support device power absolute maximum ratings dissipation ratings thermal characteristics SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com state, output of the associated channel(s) is driven to vcm and device selectively shuts off some circuitry to lower power by up to 20% of its normal operating power. exit time from auto low power mode is less than 50 ns. ? as an example, if under normal operating conditions device is consuming typical power of 200 mw. when device enters this mode, i.e. condition for auto-low power mode is met, power consumption can drop down to 160 mw. the device enters normal operation within 50 ns of signal activity detection. the squelch detector circuit within the device enables full detection of oob signaling as specified in sata specification 2.6. differential signal amplitude at the receiver input of 50 mv p-p or less is not detected as an activity and hence is not passed to the output. differential signal amplitude of 150 mv p-p or more is detected as an activity and therefore passed to the output indicating activity. squelch circuit on/off time is 5 ns max. while in squelch mode outputs are held to vcm. the sn75lvcl412 is designed to operate from a single 3.3-v supply. always practice proper power supply sequencing procedures. apply v cc first before any input signals are applied to the device. the power down sequence is in reverse order. over operating free-air temperature range (unless otherwise noted) (1) value unit supply voltage range (2) v cc ? 0.5 to 6 v voltage range differential i/o ? 0.5 to 4 v control i/o ? 0.5 to v cc + 0.5 v electrostatic discharge human body model (3) 8000 v charged-device model (4) 1000 v machine model (5) 200 v continuous power dissipation see dissipation rating table (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) all voltage values, except differential voltages, are with respect to network ground terminal. (3) tested in accordance with jedec standard 22, test method a114-b. (4) tested in accordance with jedec standard 22, test method c101-a. (5) tested in accordance with jedec standard 22, test method a115-a. pcb jedec derating factor (1) t a = 85 c package t a 25 c standard above t a = 25 c power rating 20-pin qfn (rtj) low-k 1176 mw 11.76 mw/ c 470 mw high-k 2631 mw 26.3 mw/ c 1052 mw (1) this is the inverse of the junction-to-ambient thermal resistance when board-mounted and with no air flow. over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max (1) unit r q jb junction-to-board thermal resistance 10 c/w r q jc junction-to-case thermal resistance 60 c/w r q jp junction-to-pad thermal resistance 15.2 c/w (1) the maximum rating is simulated under 3.6-v v cc . 6 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412
recommended operating conditions electrical characteristics SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 thermal characteristics (continued) over operating free-air temperature range (unless otherwise noted) parameter test conditions min typ max (1) unit p d device power dissipation, active mode en = 3.3 v, k28.5 pattern at 3 gbps, 300 mw v id = 700 mv p-p , v cc = 3.6 v p sd device power dissipation, sleep mode en = 0 v, k28.5 pattern at 3 gbps, v id = 700 5 mw mv p-p , v cc = 3.6 v with typical values measured at v cc = 3.3 v, t a = 25 c; all temperature limits are assured by design parameter conditions min typ max units v cc supply voltage 3 3.3 3.6 v c coupling coupling capacitor 12 nf t a operating free-air temperature 0 85 c over recommended operating conditions (unless otherwise noted) parameter conditions min typ max units device parameters i cc supply current, active mode en = 3.3 v, k28.5 pattern at 3 gbps, v id = 700 55 70 ma mv p-p , v cc = 3.3 v i ccsleep shutdown current, sleep mode en = 0v 1 ma maximum data rate 3.0 gbps t pdelay propagation delay measured using k28.5 pattern, see figure 2 320 400 ps t enb device enable time enb = l h 20 m s t dis device disable time enb = h l 2 m s v oob input oob threshold see figure 3 50 150 mv p-p t oob1 oob mode enter see figure 3 3 5 ns t oob2 oob mode exit see figure 3 3 5 ns control logic v ih high-level input voltage 1.4 v v il low-level input voltage 0.5 v v inhys input hysteresis 115 mv i ih high-level input current 10 m a i il low-level input current 10 m a receiver ac/dc z diffrx differential input impedance 85 100 115 ? z serx single-ended input impedance 40 ? vcm rx common-mode voltage 1.6 v rl diffrx differential mode return loss f = 150 mhz ? 300 mhz 18 db f = 300 mhz ? 600 mhz 14 f = 600 mhz ? 1.2 ghz 10 f = 1.2 ghz ? 2.4 ghz 8 f = 2.4 ghz ? 3.0 ghz 3 rl cmrx common-mode return loss f = 150 mhz ? 300 mhz 5 db f = 300 mhz ? 600 mhz 5 f = 600 mhz ? 1.2 ghz 2 f = 1.2 ghz ? 2.4 ghz 1 f = 2.4 ghz ? 3.0 ghz 1 copyright ? 2008, texas instruments incorporated submit documentation feedback 7 product folder link(s): SN75LVCP412
SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com electrical characteristics (continued) over recommended operating conditions (unless otherwise noted) parameter conditions min typ max units v diffrx differential input voltage pp f = 150 mhz ? 300 mhz 200 2000 mv/ppd ib rx impedance balance f = 150 mhz ? 300 mhz 30 db f = 300 mhz ? 600 mhz 30 f = 600 mhz ? 1.2 ghz 20 f = 1.2 ghz ? 2.4 ghz 10 f = 2.4 ghz ? 3.0 ghz 4 t 20-80rx rise/fall time rise times and fall times measured between 20% and 67 136 ps 80% of the signal t skewrx differential skew difference between the single-ended mid-point of the 50 ps rx+ signal rising/falling edge, and the single-ended mid-point of the rx ? signal falling/rising edge transmitter ac/dc z difftx pair differential impedance 85 115 ? z setx single-ended input impedance 40 ? output pre-emphasis at 1.5 ghz when enabled 2.5 db rl difftx differential mode return loss f = 150 mhz ? 300 mhz 14 db f = 300 mhz ? 600 mhz 8 f = 600 mhz ? 1.2 ghz 6 f = 1.2 ghz ? 2.4 ghz 6 f = 2.4 ghz ? 3.0 ghz 3 rl cmtx common-mode return loss f = 150 mhz ? 300 mhz 5 db f = 300 mhz ? 600 mhz 5 f = 600 mhz ? 1.2 ghz 2 f = 1.2 ghz ? 2.4 ghz 1 f = 2.4 ghz ? 3.0 ghz 1 ib tx impedance balance f = 150 mhz ? 300 mhz 30 db f = 300 mhz ? 600 mhz 20 f = 600 mhz ? 1.2 ghz 10 f = 1.2 ghz ? 2.4 ghz 10 f = 2.4 ghz ? 3.0 ghz 4 diff vpptx differential output voltage pp f = 1.5 ghz, d0/d1 = 0 400 525 600 mv/ppd diff vpptx_pe differential output voltage pp f = 1.5 ghz, d0/d1 = 1 600 700 800 mv/ppd t de pre-emphasis width see figure 4 0.4 ui v cmtx common-mode voltage 1.97 v t 20-80tx rise/fall time rise times and fall times measured between 20% and 67 100 136 ps 80% of the signal, d1, d0 = 0 v t skewtx differential skew difference between the single-ended mid-point of the 20 ps tx+ signal rising/falling edge, and the single-ended mid-point of the tx ? signal falling/rising edge, d1, d0 = v cc tj tx total jitter (1) ui = 333 ps, +k28.5 control character 0.2 0.3 ui p-p dj tx deterministic jitter (1) ui = 333 ps, +k28.5 control character 0.13 0.2 ui p-p rj tx random jitter (1) ui = 333 ps, +k28.7 control character 2.0 2.15 ps/rms (1) t j = (14.1 rj sd + dj) where rj sd is one standard deviation value of rj gaussian distribution. t j measurement is at the sata connector and includes jitter generated at the package connection on the printed circuit board, and at the board interconnect as shown in figure 2 . 8 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412
SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 figure 2. jitter measurement test condition figure 3. propagation delay timing diagram figure 4. oob enter and exit timing copyright ? 2008, texas instruments incorporated submit documentation feedback 9 product folder link(s): SN75LVCP412 t pdelay t pdelay in out 50 mv in+vcm in- out+ vcm out- t oob2 t oob1 lossless signal source 10" fr4 ch 0 ch 1 lvcp412 sata compliance measurement point 6" fr4 lossless signal source sata compliance measurement point jitter measurement setup host device
bench test data eye diagram SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com figure 5. tx differential output with 2.5 db pre-emphasis step differential output voltage ? diff vpptx , 2 inches from device pin, v cc = 3.3 v, t a = 25 c, pattern = k28.5, bit rate = 3 gbps parameter test conditions channel input vid do/d1 min mean maximum ch0 700 mv 0 524.87mv 524.87mv 525.72mv v cc = 3.3 v, t a = diff vpptx ch1 700 mv 0 515.68mv 516.72mv 518.85mv 25 c, pattern = k28.5, bit rate = 3 ch0 700 mv 1 665.07mv 666.48mv 668.07mv diff vpptxde gbps ch1 700 mv 1 656.32mv 658.34mv 660.40mv 10 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412 0db 2.5 db vcm 0db 1-bit 1 to n bits 1-bit 1 to n bits t de t de 2.5 db diff tx vpp diff tx_pe vpp eye pattern measurement setup test condition ? vcc = 3.3 v ? temp = 25c ? rx input voltage = 700 mvp-p ? input pattern k28.5+ @3 gbps ? d1/d0/enb = vcc ? trace width = 4 mil on pcb x (inch) scope data generator ch0/1 lvcp412 y (inch) 12 nf 12 nf
SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 figure 6. eye pattern copyright ? 2008, texas instruments incorporated submit documentation feedback 11 product folder link(s): SN75LVCP412
SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com figure 7. eye pattern 12 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412 x=5.7, y =5.7 (eye height/width) eye width ey e heig ht
SN75LVCP412 www.ti.com ............................................................................................................................................................................................ slls912 ? november 2008 figure 8. eye pattern copyright ? 2008, texas instruments incorporated submit documentation feedback 13 product folder link(s): SN75LVCP412
SN75LVCP412 slls912 ? november 2008 ............................................................................................................................................................................................ www.ti.com figure 9. eye pattern 14 submit documentation feedback copyright ? 2008, texas instruments incorporated product folder link(s): SN75LVCP412

packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) SN75LVCP412rtjr active qfn rtj 20 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year SN75LVCP412rtjt active qfn rtj 20 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 1-dec-2008 addendum-page 1
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant SN75LVCP412rtjr qfn rtj 20 3000 330.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 SN75LVCP412rtjt qfn rtj 20 250 180.0 12.4 4.3 4.3 1.5 8.0 12.0 q2 package materials information www.ti.com 5-dec-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) SN75LVCP412rtjr qfn rtj 20 3000 346.0 346.0 29.0 SN75LVCP412rtjt qfn rtj 20 250 190.5 212.7 31.8 package materials information www.ti.com 5-dec-2008 pack materials-page 2

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