UCC1570 ucc2570 ucc3570 low power pulse width modulator description the UCC1570 family of pulse width modulators is intended for application in isolated switching supplies using primary side control and a voltage mode feedback loop. made with a bicmos process, these devices feature low startup current for efficient off-line starting with a bootstrapped low volt- age supply. operating current is also very low; yet these devices maintain the ability to drive a power mosfet gate at frequencies above 500khz. voltage feedforward provides fast and accurate response to wide line volt- age variation without the noise sensitivity of current mode control. fast cur- rent limiting is included with the ability to latch off after a programmable number of repetitive faults has occurred. this allows the power supply to ride through a temporary overload, while still shutting down in the event of a permanent fault. additional versatility is provided with a maximum duty cycle clamp programmable within a 20% to 80% range and line voltage sensing with a programmable window of allowable operation. 10 i 3 10 i 4 i3 i4 i4 i4 10 7 4 11 9 vfwd freq slope ramp iset clock generator 1v 4v high line low line 1v feedbk softst curlim current limit clk ramp valley ramp peak ramp latch 4v 1v s r 5v generator 4.5v vref 15v gnd 13/9v vcc out pgnd pwm pwm latch r d s r 0.2v clk count 8 14 2 1 4v shutdown latch shutdown 0.6v r s d 6 12 13 3 5 s d block diagram 04/99 features low power bicmos process 85 m a start-up current 1ma run current 1a peak gate drive output voltage feed forward programmable duty cycle clamp optocoupler interface 500khz operation soft start fault counting shutdown fault latch off or automatic restart
2 UCC1570 ucc2570 ucc3570 supply voltage (limit supply current to 20ma) . . . . . . . self limiting at 15v supply current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . + 20ma analog inputs (curlim, vfwd, feebk) . . . . . . . . . . . . . . 6v programming current i slope ,i iset . . . . . . . . . . . . . . . . . C1ma output current i out dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180ma pulse (0.5ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2a note : all voltages are with respect to gnd. currents are posi- tive into the specified terminal. consult packaging section of databook for thermal limitations and considerations of pack- age. absolute maximum ratings connection diagrams dil-14 (top view) n or j package plcc-20 (top view) q package soic-14 (top view) d package electrical characteristics: unless otherwise stated, these specifications apply for t a = 0 to 70 c for the ucc3570, t a = C40 to 85 c for the ucc2570, t a =C55 to 125 c for the UCC1570, r iset =100k, r slope =121k, c freq =180pf, c ramp =150pf, vcc=11v and t a =t j . parameter test conditions min typ max units reference vref vcc =10 to 13v, i vref = 0 to 2ma 4.9 5 5.1 v line regulation vcc = 10 to 13v 2 10 mv load regulation i vref = 0 to 2ma 2 10 mv short circuit current vref = 0 10 50 ma vcc vth (on) 12 13 v vth (off) 8 9 10 v hysteresis 345v vcc i vcc = 10ma 13.5 15 16 v i vcc start vcc = 11v, vcc comparator off 85 150 m a i vcc run vcc comparator on 1 1.5 ma temperature range package UCC1570j C55 c to +125 c ceramic dip ucc2570d C40 c to +85 c soic ucc2750n plastic dip ucc3570d 0 c to +70 c soic ucc3570n plastic dip ucc3570q plcc ordering information
3 UCC1570 ucc2570 ucc3570 electrical characteristics: unless otherwise stated, these specifications apply for t a = 0 to 70 c for the ucc3570, t a = C40 to 85 c for the ucc2570, t a =C55 to 125 c for the UCC1570, r iset =100k, r slope =121k, c freq =180pf, c ramp =150pf, vcc=11v and t a =t j . parameter test conditions min typ max units line sense vth high line comparator 3.9 4 4.1 v vth low line comparator 0.96 1 1.04 v lib (vfwd) 0 100 na oscillator frequency 90 100 110 khz ramp generator i ramp /i slope 9 10 11 a/a Ci ramp /i iset 9 10 11 a/a peak ramp voltage 3.8 4 4.2 v valley ramp voltage 0.95 1 1.05 v iset voltage level 0.95 1 1.05 v soft start saturation vcc = 11v, vcc comparator off 25 100 mv i softst /i iset 0.8 1 1.2 a/a pulse width modulator lib(feedbk) 0 100 n a feedbk zero duty cycle 0.9 1 1.1 v maximum duty cycle, (note 1) 3.8 4 4.2 v current limit lib(curlim) 0 100 na vth current limit 180 200 220 mv vth shutdown 500 600 700 mv fault counter vth 3.8 4 4.2 v vsat 0 100 mv i count /i iset 0.8 1 1.2 a/a output driver vsat high i out = C100ma 0.4 1 v vsat low i out = 100ma 0.4 1 v rise/fall time c out = 1nf, (note 1) 20 100 ns note 1: this parameter guaranteed by design but not 100% tested in production. vcc : chip supply voltage pin. bypass to pgnd with a low esl/esr 0.1 m f capacitor plus a capacitor for gate charge storage. lead lengths must be minimum. pgnd : ground pin for the output driver. keep connec- tions less than 2cm. carefully maintain low impedance path for high current return. out : gate drive output pin. connect to the gate of a power mosfet with a resistor greater than 2 w . keep connection lengths under 2cm. vfwd : voltage feed forward and line sense pin. con- nect to input dc line using a resistive divider. slope : program the charging current for ramp with a resistor from this pin to gnd. this pin will follow vfwd. feedbk : input to the pulse width modulator comparator. drive this pin with an optocoupler to gnd and a resistor to vref. modulation input range is from 1v to 4v. iset: a resistor from this pin to gnd programs ramp discharge current, freq current, softst current, and count current. pin descriptions
4 UCC1570 ucc2570 ucc3570 ramp : ramp pin. connect a capacitor to gnd. rising slope is programmed by current in slope. this slope is compared to feedbk for pulse width modulation. the falling slope is programmed by the current in iset and used to limit maximum duty cycle. freq : oscillator pin. program the frequency with a ca- pacitor to gnd. vref : precision 5v reference, and bypass point for inter- nal circuitry. bypass this pin with a 1 m f minimum capaci- tor to gnd. gnd : analog ground. connect to a low impedance ground plane containing all analog low current returns. softst : soft start pin. program with a capacitor to gnd. count : program the time that fault events will be toler- ated before shutdown occurs with a capacitor and resis- tor to gnd. curlim : current limit sense pin. terminates out gate drive pulse for inputs over 0.2v. enables fault counting function (count). for inputs over 0.6v, the shutdown latch is activated. pin descriptions (cont.) (note: refer to typical application for external compo- nent names.) all the equations given below should be considered as first order approximations with final values determined empirically for a specific application. power sequencing vcc normally connects through a high impedance (r5) to the rectified line, with an additional path(r6) to a low voltage, bootstrap on the winding power transformer. vfwd normally connects to a divider (r1 and r2) from the rectified line. for circuit activation, all of the following considerations are required: 1. vfwd between 1v and 4v 2. vcc has been under 9v (to reset the shutdown latch) 3. vcc over 13v at this time, the circuit will activate. i vcc will increase from its start up value of 85 m a to its run value of 1ma. the capacitor on softst is charged with a current de- termined by: C i v r softst = 1 4 . when softst rises above 1v, output pulses will begin and i vcc will further rise to a level dictated by gate charge requirements asi vcc ? 1ma + qtfs. with output pulses, the low voltage bootstrap winding should now power the controller. if vcc falls below 9v, the controller will turn off and the start sequence will reset and retry. vcc clamp an internal shunt regulator clamps vcc so that it will not exceed 15v. output inhibit during normal operation, out is driven high at the start of a clock period and back low when ramp either crosses feedbk or equals 4v. if, however, any of the fol- lowing occur, out is immediately driven low for the re- mainder of the clock period: 1. vfwd is outside the range of 1v to 4v 2. curlim is greater than 0.2v 3. feedbk or softst is less than 1v normal output pulses will not resume until the beginning of the next clock period in which none of the above con- ditions exist. current limiting curlim is monitored by two internal comparators. the current limit comparator threshold is 0.2v. if the current limit comparator is triggered, out is immediately driven low and held low for the remainder of the clock cycle, providing pulse-by-pulse overcurrent control for exces- sive loads. this comparator also causes c f to be charged for the remainder of the clock cycle. the charg- ing current is C i v r count = 1 4 . if repetitive cycles are terminated by the current limit comparator causing count to rise above 4v, the shut- down latch is set. the count integration delay feature will be bypassed by the shutdown comparator which has a 0.6v threshold. the shutdown comparator immediately sets the shutdown latch. r f in parallel with c f resets the count integrator following transient faults. r f must be greater than () () 44 1 - r d max . application information
5 UCC1570 ucc2570 ucc3570 latched shutdown if curlim rises above 0.6v, or count rises to 4v, the shutdown latch will be set. this will force out low, dis- charge softst and count, and reduce i vcc to ap- proximately 1ma. when, and if, vcc falls below 9v, the shutdown latch will reset and i vcc will fall to 85 m a, allow- ing the circuit to restart. if vcc remains above 9v, an al- ternate restart will occur if vfwd is momentarily reduced below 1v. external shutdown commands from any source may be added into either the count or curlim pins. deadtime control the voltage waveform on ramp has independently con- trolled rising and falling edges. at the start of the clock period, ramp is at 1v and rises to 4v. it then discharges back to 1v and awaits the next clock period. out can only be high during the rising part of the waveform, while it is positively blanked off during the falling portion. set- ting the Cdv/dt slope by r4 from iset to gnd estab- lishes a minimum deadtime as: td r c r = 03 4 . choose r4 between 20k and 200k and c r greater than 50pf. in order to have a pulse at out in the next clock period, ramp must fall to 1v prior to the end of the cur- rent period. if it does not, out will remain low for the en- tire next clock period. voltage feedforward the +dv/dt on ramp is made proportional to line volt- age. the slope is: () dv dt vfwd rc r = 10 3 where vfwd is line voltage scaled by r1 and r2. there- fore, a changing line voltage will accomplish an immedi- ate proportionate pulse width change without any action from the feedback amplifier. this will result in constant volt-second drive to the power transformer providing both international voltage operation, and excellent dynamic line regulation. vfwd is intended to operate over a 4:1 range (1v to 4v) with undervoltage and overvoltage sen- sors designed to drive out low if this range is exceeded. choose r3 between 20k and 200k. application information (cont.) figure 1. UCC1570 typical application.
6 UCC1570 ucc2570 ucc3570 frequency set a capacitor from freq to gnd will determine a constant clock frequency. frequency is: () f rc t = 18 4 . if required, frequency can be trimmed down from the above equation by the addition of r t from freq to gnd. the reduction in frequency is a function of the ratio of r t/ r4. r t should be greater than 2.4 r4 for reliable op- eration. external synchronization can be accomplished by cou- pling a narrow pulse to a resistor inserted in series with the ground side of c t. the value should be less than r4/200 and the synchronizing pulse width should be less than 5% of the oscillator period. external synchronization can also be accomplished by driving freq with an cmos inverter. the inverter must be able to sink (4 i4) with at a voltage less than the 3.5v upper threshold of the oscillator. it must also be able to source 36 i4 at a voltage greater than the 1.5v lower threshold of the oscillator. as long as freq is held high, the output is guaranteed to be low. gate drive output the UCC1570 is capable of 1a peak output current. by- pass vcc with at least 0.1 m f directly to pgnd. use a capacitor with low equivalent series resistance and in- ductance. the connection from out to the mosfet gate should have a 2 w or greater damping resistor and the length should be minimized. a low impedance con- nection must be established between the mosfet source (or the ground side of the current sense resistor), the vcc bypass capacitor and pgnd. pgnd should then be connected by a single path (shown as rgnd in the application) to gnd. application information (cont.) high v in clock feedbk ramp out low v in fault v in figure 2. ramp and pwm waveforms.
7 UCC1570 ucc2570 ucc3570 figure 4. external clock synchronization. figure 5. frequency dependence on rt/ r4 ratio. figure 3. clock generator. application information (cont.)
8 UCC1570 ucc2570 ucc3570 unitrode corporation 7 continental blvd. ? merrimack, nh 03054 tel. (603) 424-2410 fax (603) 424-3460 application information (cont.)
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