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general description the max1437b evaluation kit (ev kit) is a fully assem-bled and tested circuit board that contains all the components necessary to evaluate the max1437b octal, 12-bit, 50msps analog-to-digital converter (adc). the max1437b accepts differential analog input signals and the ev kit generates these signals from user-supplied single-ended input sources. the ev kit? digital outputs produced by the adc can be easily sampled with a user-supplied high-speed logic analyz- er or data-acquisition system. the ev kit also features an on-board deserializer to simplify integration with standard logic analysis systems. the ev kit operates from 1.8v and 3.3v (plus 1.5v if the fpga is used) power supplies and includes circuitry that generates a clock signal from an ac signal supplied by the user. the max1437b ev kit comes standard with the max1437b installed. however, the ev kit can also be used to evaluate the max1438b by replacing the max1437b (u1) with a max1438b octal 64msps adc ic. features ? low-voltage and power operation ? optional on-board clock-shaping circuitry ? serial, scalable low-voltage signaling (slvs)/low-voltage differential signaling (lvds) outputs ? on-board lvpecl differential output drivers ? on-board deserializer ? lvds test mode ? fully assembled and tested evaluates: max1437b/max1438b max1437b evaluation kit ________________________________________________________________ maxim integrated products 1 19-4287; rev 1; 8/09 component list for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. designation qty description clock, in0?n7 9 sma pc-mount connectors c1?8, c10, c11, c12, c57?64,c81?85, c139, c140, c147?156 36 0.1? ?0%, 10v x5r ceramiccapacitors (0402) tdk c1005x5r1a104k murata grm155r61a104k c9, c29?44, c56, c77, c78,c80, c92, c93, c146 24 1.0? ?0%, 6.3v x5r ceramiccapacitors (0402) tdk c1005x5r0j105k murata grm155r60j105k c13?20, c65?72 0 not installed, ceramiccapacitors?horted by pcb (0603) c21?28, c126?133 16 39pf ?%, 50v c0g ceramiccapacitors (0402) tdk c1005c0g1h390j murata grm1555c1h390j c45, c46, c47, c86?89, c143 8 220? ?0%, 6.3v tantalumcapacitors (c case) avx tpsc227m006r0250 avx tpsc227m006r0125 kemet t495c227k006ate225 c48, c49, c50, c144 0 not installed, ceramic capacitors(c case) designation qty description c51, c52, c53, c90, c91, c145 6 10? ?0%, 10v x5r ceramiccapacitors (1210) tdk c3225x5r1a106m murata grm32er61a106k c54 1 2.2? ?0%, 6.3v x5r ceramiccapacitor (0603) tdk c1608x5r0j225m murata grm188r60j225k c55, c157?176 21 0.01??0%, 25v x7r ceramiccapacitors (0402) tdk c1005x7r1e103k murata grm155r71e103k c73?76, c122?125 0 not installed, ceramic capacitors(0402) c79, c138, c142 3 10? ?0%, 4v x5r ceramiccapacitors (0603) tdk c1608x5r0g106m murata grm188r60j106m c94?121 28 0.1? ?0%, 6.3v x5r ceramiccapacitors (0201) tdk c0603x5r0j104m murata grm033r60j104k c141 1 100? ?0%, 6.3v x5r ceramiccapacitor (1210) tdk c3225x5r0j107m murata grm32er60j107m ordering information part type MAX1437BEVKIT+ ev kit + denotes lead(pb)-free and rohs compliant. downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 2 _______________________________________________________________________________________ component list (continued) designation qty description d1 1 dual schottky diode (sot23) central semiconductor cmpd6263s+ or zetex bat54s d2, d3 2 green surface-mount leds (0603) j1?8, ju14 9 2-pin headers (cut to fit) j9?13, j15 6 dual-row (2 x 20) 40-pin headers j14 1 9-pin header (cut to fit) ju1?u6, ju 8ju 11, ju 13 11 3-pin headers (cut to fit) ju12 1 dual-row (2 x 4) 8-pin header n1 1 digital logic n-channel mosfet(sot23) central semiconductor 2n7002fc (top mark: 702) zetex 2n7002ta r1?8, r22?25, r62?73 0 not installed, resistors?horted bypcb (0603) r9?16, r26?34, r35,r77, r78?81, r87?93, r98 0 not installed, resistors (0402)r9?16, r35, and r77 are open; r26?34, r78?81, r87?93, and r98 are shorted by pcb r17?21, r58?61 9 49.9 ?% resistors (0603) r36, r105?133 30 49.9 ?% resistors (0402) r37?44, r74, r75, r76, r82?86 16 10 ?% resistors (0805) r45?50, r100?103 10 100 ?% resistors (0603) r51 1 100k potentiometer, 19-turn, 3/8in r52, r53, r56 3 4.02k ?% resistors (0603) r54 1 5k potentiometer, 19-turn, 3/8in r55 1 2k ?% resistor (0603) designation qty description r57 1 13.0k ?% resistor (0603) r94, r95 2 4.7k ?% resistors (0603) r96, r97 2 330 ?% resistors (1206) r99 1 162 ?% resistor (0603) r104 1 10k ?% resistor (0603) sw1 1 momentary tact switch t1?8 8 1:1 800mhz rf transformersmini-circuits adt1-1wt+ tp1?p8, tp13, tp14, tp15 0 not installed, test points tp9?p12 4 pc test points (red) tp16 1 pc test point (black) u1 1 o ctal 12- b i t ser i al ad c ( 68 tqfn - e p *) maxim max1437betk+ u2 1 single lvds line receiver (8 so)maxim max9111esa+ u3 1 low-noise, low-distortion op amp(5 sot23) maxim max4250euk+ u4 1 tinylogic uhs dual inverter (6 sc70)fairchild nc7wz04p6x_nl (top mark: z04) u5 1 virtex ii platform fpga (256 fgbga)xilinx xc2v80-5fgg256c xilinx xc2v80-5fgg256i u6 1 prom (20 so)xilinx xc18v01sog20c u7?16 10 lvds/anything-to-lvpecl translator(8 ?ax ) maxim max9375eua+ 13 shunts 1 pcb: max1437b evaluation kit+ ?ax is a registered trademark of maxim integrated products, inc. * ep = exposed pad. downloaded from: http:///
quick start recommended equipment dc power supplies: clock (cvdd) 3.3v, 100maanalog (avdd) 1.8v, 500ma digital (ovdd) 1.8v, 150ma buffers (vpecl) 3.3v, 400ma (optional) deserializer core (vd1.5) 1.5v, 200ma (optional) deserializer i/o (vd3.3) 3.3v, 200ma (optional) signal generator with low phase noise and low jitter for clock input signal (e.g., hp 8662a, hp 8644b) signal generator for analog signal inputs (e.g., hp 8662a, hp 8644b) logic analyzer or data-acquisition system (e.g., hp 16500c, tla621) analog bandpass filters (e.g., allen avionics, k&l microwave) for input signal and clock signal digital voltmeter procedure the max1437b ev kit is a fully assembled and testedsurface-mount board. follow the steps below to verify board operation. caution: do not turn on power sup- plies or enable signal generators until all connec-tions are completed. 1) verify that shunts are installed in the following loca- tions: ju1 (pins 2-3) single termination ju2 (pins 2-3) lvds outputs ju3 (pins 2-3) normal operation ju4 (pins 2-3) chip enabled ju8 (pins 2-3) fpga enabled ju9, ju10, ju11 (pins 2-3) channels 0? output from fpgaju12 (pins 3-4) internal reference enabled ju14 (not installed) disconnect external reference buffer 2) verify that shunts are installed in the following loca- tions: ju5, ju6, ju13 (pins 2-3) 45mhz to 50mhz clock frequency range 3) connect the clock signal generator to the input of the clock bandpass filter. 4) connect the output of the clock bandpass filter to the clock sma connector. 5) connect the analog input signal generator to the input of the analog bandpass filter. 6) connect the output of the analog bandpass filter to either one of the sma connectors labeled in0?n8.the analog input signals can also be monitored at the 2-pin headers (j1?8). note: all 8 channels can be operated independently or simultaneously. 7) connect the logic analyzer to either header j9 (slvs or lvds compatible signals) or j12, j13 (deserial-ized 3.3v cmos-compatible signals). see the output bit locations section for header connections. 8) connect the 1.8v, 500ma power supply to avdd. connect the ground terminal of this supply to gnd. 9) connect the 1.8v, 150ma power supply to ovdd. connect the ground terminal of this supply to gnd. 10) connect the 3.3v, 100ma power supply to cvdd. connect the ground terminal of this supply to gnd. 11) connect the 3.3v, 400ma power supply to vpecl. connect the ground terminal of this supply to gnd. 12) connect the 1.5v, 200ma power supply to vd1.5. connect the ground terminal of this supply to gnd. evaluates: max1437b/max1438b max1437b evaluation kit _______________________________________________________________________________________ 3 component suppliers supplier phone website avx corporation 843-946-0238 www.avxcorp.com central semiconductor corp. 631-435-1110 www.centralsemi.com fairchild semiconductor 888-522-5372 www.fairchildsemi.com kemet corp. 864-963-6300 www.kemet.com mini-circuits 718-934-4500 www.minicircuits.com murata electronics north america, inc. 770-436-1300 www.murata-northamerica.com tdk corp. 847-803-6100 www.component.tdk.com zetex semiconductors 631-543-7100 www.zetex.com note: indicate that you are using the max1437b when contacting these component suppliers. downloaded from: http:///
evaluates: max1437b/max1438b 13) connect the 3.3v, 200ma power supply to vd3.3. connect the ground terminal of this supply to gnd. 14) turn on the vd3.3 power supply. 15) turn on the vd1.5 power supply. 16) verify that the programming led (d2) and the locked led (d3) are off. 17) turn on the rest of the power supplies. 18) enable the signal generators. set the clock signal generator to output as specified to configuration signal with 2.6v p-p amplitude or higher. set the analog input signal generators to output the desired frequency with an amplitude 1.4v p-p . all signal generators should be phase-locked. 19) verify that the programming led (d2) is off. 20) momentarily press switch sw1, and verify that the locked led (d3) is on. 21) enable the logic analyzer. 22) collect data using the logic analyzer. detailed description of hardware the max1437b ev kit is a fully assembled and testedcircuit board that contains all the components necessary to evaluate the performance of the max1437b adc. the max1437b adc accepts differential input signals; however, on-board rf transformers (t1?8) convert the single-ended signals applied to the in0?n7 sma con- nectors to the required differential signal. the input sig- nals of the adc can be measured using a differential oscilloscope probe at headers j1?8. output level translators (u7?16) buffer and convert the slvs or lvds output signals of the adc to higher voltage lvpecl signals, which can be captured by a wide variety of logic analyzers. the slvs/lvds output signals are accessible at header j9 and the lvpecl outputs signals are accessible at header j15. the ev kit pcb is designed as a six-layer board to opti- mize performance of the max1437b. separate analog, digital, clock, and buffer power planes minimize noise coupling between analog and digital signals. 50 coplanar transmission lines are used for analog andclock inputs. 100 differential coplanar transmission lines are used for all digital lvds outputs. all differentialoutputs are terminated with 100 termination resistors between the true and complementary digital outputs.the trace lengths of the 100 differential slvs/lvds lines are matched to within a few thousands of an inchto minimize layout-dependent data skew. power supplies for best performance, the ev kit requires separate ana-log, digital, clock, and buffer power supplies. two 1.8v power supplies are used to power the analog (avdd) and digital (ovdd) portion of the adc. the clock cir- cuitry (cvdd) is powered by a 3.3v power supply. a separate 3.3v power supply (vpecl) is used to power the output buffers (u7?16) of the ev kit. 1.5v (vd1.5) and 3.3v (vd3.3) power supplies are required to power the deserializer circuit. standby jumper ju4 controls the power-management standbyfeature of data converter u1. see table 1 for jumper ju4 shunt positions. clock by default, the user-supplied ac-coupled clock signalapplied to the ev kit? clock sma connector is buffered on board with two inverters (u4). in this mode, diode d1 limits the amplitude of the clock signal. overdriving the clock input can increase the slew rate of the differential signal, thereby reducing clock jitter. the frequency of the signal should not exceed the max- imum sampling rate of the adc. the sinusoidal input signal frequency (f clk ) determines the sampling rate of the adc. the clock signal applied to the adc can beobserved at test point tp10. optional clock-shaping circuit the ev kit also features an optional on-board clock-shaping circuit that generates a clock signal with vari- able duty cycle from the ac-coupled sine-wave signal applied to the clock sma connector. the max9111 differential line receiver (u2) processes the clock input signal and generates the required cmos clock signal. to use this circuitry, cut the trace on the pcb at r78 and install 0 resistors at r77 and r35. the signal? duty cycle can be adjusted with potentiometer r54.with a 3.3v clock supply voltage (cvdd), a clock sig- nal with a 50% duty cycle (recommended) can be achieved by adjusting r54 until a voltage of 1.32v is produced across test points tp12 and tp16. max1437b evaluation kit 4 _______________________________________________________________________________________ table 1. standby shunt settings (ju4) shunt position power-down connections ev kit function 1-2 avdd u1 in standby mode 2-3* gnd u1 enabled * default position. downloaded from: http:///
pll frequency mode selection when driving the ev kit with clock signals lower thanthe maximum specified sampling rate of the adc, the phase-locked-loop (pll) circuit of the adc must be set accordingly. refer to the pll inputs (pll0, pll1, pll3) section in the max1437b ic data sheet for furtherdetails about the operation of the internal pll. jumpers ju5, ju6, and ju13 control the pll mode of the adc. see table 2 for shunt positions. configure jumpers ju5, ju6, and ju13 accordingly and ensure that the clock signal frequency falls between the minimum and maxi- mum limits listed in table 2. input signal although the max1437b adc accepts differential ana-log input signals, the ev kit only requires a single- ended analog input signal with amplitude of less than 1.4v p-p provided by the user. on-board transformers (t1?8) convert the single-ended analog input signaland generate differential analog signals at the adc? differential input pins. connect the single-ended analog input signals to sma connectors in0?n7 for channel 0?hannel 7, respectively. reference voltage the ev kit can be configured to use the adc? 1.24vinternal reference, or a stable, low-noise, external refer- ence. use dual-row (2 x 4) 8-pin header ju12 to config- ure the desired reference mode. see table 3 for the appropriate shunt settings. output signal the max1437b adc features eight serial lvds-com-patible digital outputs. each output transmits the con- verted analog input signals of channel 0?hannel 7. two additional outputs (clkout and frame) are pro- vided for data synchronization. refer to the max1437b ic data sheet for more details. double-termination settings the max1437b adc features trimmed, internal 100 termination resistors between the positive (true) andnegative (complementary) line of each output (d0?7, clk, and frame). the ev kit circuit also features 100 termination resistors located at the far end of each dif-ferential output pair. activating the internal termination helps eliminate unwanted reflections on the signal traces. use jumper ju1 to activate either single or dou- ble termination. see table 4 for appropriate shunt posi- tions that select the termination architecture. evaluates: max1437b/max1438b max1437b evaluation kit _______________________________________________________________________________________ 5 table 4. double-termination shuntsettings (ju1) shunt position dt pin connection ev kit function 1-2 avdd double termination selected( outp uts ar e d oub l e ter m i nated ) 2-3* gnd single termination selected( outp uts ar e si ng l e ter m i nated ) * default position. table 2. max1437b pll shunt settings(ju5, ju6, ju13) shunt position clock input range (mhz) ju13 (pll1) ju6 (pll2) ju5 (pll3) min max 2-3* 2-3* 2-3* 45.0 50.0 2-3 2-3 1-2 32.5 45.0 2-3 1-2 2-3 22.5 32.5 2-3 1-2 1-2 16.3 22.5 1-2 2-3 2-3 11.3 16.3 1-2 2-3 1-2 8.1 11.3 1-2 1-2 2-3 5.6 8.1 1-2 1-2 1-2 4.0 5.6 * default position. table 3. reference shunt settings (ju12) shunt position refadj pin connection ev kit function 1-2 connected to avdd internal reference disabled.apply an external reference voltage at the refio pad. verify that a shunt is installed on jumper ju14. 3-4* connected to gnd internal reference enabled.verify that a shunt is not installed on jumper ju14. 5-6** connected to refio through r57 and r51 increase full-scale range byadjusting potentiometer r51. 7-8** connected to gnd through r57 and r51 compensate for gain errorsby adjusting potentiometer r51. * default position. ** refer to the full-scale range adjustments using the internal reference section in the max1437b ic data sheet. downloaded from: http:///
evaluates: max1437b/max1438b slvs/lvds outputs the max1437b adc is capable of generating slvs orlvds signals at its outputs. jumper ju2 controls this feature of the adc. see table 5 for shunt positions. regardless of which output signal type is selected, the output buffers (u7?16) will convert the data to lvpecl logic levels. when operating in slvs output mode, ju1 must be configured for double termination (shunt across pins 1-2). lvds test pattern to debug signal integrity problems, the max1437badc can generate a factory-set test pattern on all of the output channels. jumper ju3 controls this feature. see table 6 for the appropriate shunt positions. the test pattern for the max1437b is 0000 1011 1101. output bit locations the digital outputs of the max1437b adc are connect-ed to 40-pin header j9. all pcb trace lengths are matched to minimize data skew and improve the overall dynamic performance of the device. additionally, 10 drivers (u7?16) buffer and level-translate the digital outputs to lvpecl-compatible signals. the drivers increase the differential voltage swing, and are capable of driving large capacitive loads that may be present at the logic analyzer connection. the outputs of the buffers are connected with 40-pin header j15. see table 7 for output bit locations of headers j9 and j15. max1437b evaluation kit 6 _______________________________________________________________________________________ table 5. slvs/lvds shunt settings (ju2) shunt position slvs/lvds pin connection adc output 1-2 avdd slvs 2-3* gnd lvds * default position. table 6. lvds test pattern shuntsettings (ju3) shunt position lvdstest pin connection ev kit function 1-2 avdd test pattern transmitted, lsb fi r st, on al l s lv s /lv d s outp uts 2-3* gnd normal operation * default position. table 7. output bit locations signal unbuffered (lvds or slvs) buffered (lvpecl) description p j9-1 j15-1 ch0 n j9-2 j15-2 channel 0 p j9-5 j15-5 ch1 n j9-6 j15-6 channel 1 p j9-9 j15-9 ch2 n j9-10 j15-10 channel 2 p j9-13 j15-13 ch3 n j9-14 j15-14 channel 3 p j9-17 j15-17 clkout n j9-18 j15-18 clock p j9-21 j15-21 frame n j9-22 j15-22 frame p j9-25 j15-25 ch4 n j9-26 j15-26 channel 4 p j9-29 j15-29 ch5 n j9-30 j15-30 channel 5 p j9-33 j15-33 ch6 n j9-34 j15-34 channel 6 p j9-37 j15-37 ch7 n j9-38 j15-38 channel 7 p = true. n = complementary. downloaded from: http:///
on-board deserializer the max1437b ev kit features an on-board deserializerthat converts the serial outputs of the adc to a parallel data stream. the deserializer uses a delayed-locked loop (dll) to synchronize itself with the incoming serial data stream. after every change in adc clock fre- quency, reset this dll by pressing switch sw1. if led d3 is not lit, the serial data stream is not synchro-nized and the outputs of the deserializer are not valid. channel 0?hannel 7 data is captured on headers j10?13. only 4 channels can be captured at a time on the ev kit. configure jumpers ju9, ju10, and ju11 to select the location of the channels. see table 8 for jumpers ju9, ju10, and ju11 configuration. see table 9 for output bit locations. deserializer output enables jumper ju8 controls the output enables of the deserial-izer. see table 10 for jumper ju8 configuration. evaluates: max1437b/max1438b max1437b evaluation kit _______________________________________________________________________________________ 7 table 8. output channel locations (ju9,ju10, ju11) shunt position channel location ju9 (s2) ju10 (s1) ju11 (s0) j10 j11 j12 j13 2-3 2-3 2-3 ch0 ch1 ch2 ch3 2-3 2-3 1-2 ch4 ch5 ch6 ch7 2-3 1-2 2-3 ch0 ch4 ch1 ch5 2-3 1-2 1-2 ch0 ch6 ch1 ch7 1-2 2-3 2-3 ch2 ch4 ch3 ch5 1-2 2-3 1-2 ch2 ch6 ch3 ch7 table 9. output bit locations (j10?13) bit location clk j10-38 j11-38 j12-38 j13-38 d11 j10-26 j11-26 j12-26 j13-26 d10 j10-24 j11-24 j12-24 j13-24 d9 j10-22 j11-22 j12-22 j13-22 d8 j10-20 j11-20 j12-20 j13-20 d7 j10-18 j11-18 j12-18 j13-18 d6 j10-16 j11-16 j12-16 j13-16 d5 j10-14 j11-14 j12-14 j13-14 d4 j10-12 j11-12 j12-12 j13-12 d3 j10-10 j11-10 j12-10 j13-10 d2 j10-8 j11-8 j12-8 j13-8 d1 j10-6 j11-6 j12-6 j13-6 d0 j10-4 j11-4 j12-4 j13-4 note: odd-numbered pins are connected to ground. remaining pins are not connected. table 10. deserializer output enables(ju8) shunt position ev kit function 1-2 deserializer output disabled 2-3* deserializer output enabled * default position. downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 8 _______________________________________________________________________________________ figure 1a. max1437b ev kit schematic?dc downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit _______________________________________________________________________________________ 9 figure 1b. max1437b ev kit schematic?lock, voltage reference downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 10 ______________________________________________________________________________________ figure 1c. max1437b ev kit schematic?vpecl level translators (sheet 1 of 2) downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 11 figure 1d. max1437b ev kit schematic?vpecl level translators (sheet 2 of 2) downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 12 ______________________________________________________________________________________ figure 1e. max1437b ev kit schematic?eserializer input and outputs downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 13 figure 1f. max1437b ev kit schematic?rom and fpga downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 14 ______________________________________________________________________________________ figure 2. max1437b ev kit component placement guide?omponent side downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 15 figure 3. max1437b ev kit pcb layout?omponent side downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 16 ______________________________________________________________________________________ figure 4. max1437b ev kit pcb layout (inner layer 2)?round planes downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 17 figure 5. max1437b ev kit pcb layout (inner layer 3)?ower planes downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 18 ______________________________________________________________________________________ figure 6. max1437b ev kit pcb layout (inner layer 4)?ignal layer downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 19 figure 7. max1437b ev kit pcb layout (inner layer 5)?ignal layer downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit 20 ______________________________________________________________________________________ figure 8. max1437b ev kit pcb layout?older side downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit ______________________________________________________________________________________ 21 figure 9. max1437b ev kit component placement guide?older side downloaded from: http:///
evaluates: max1437b/max1438b max1437b evaluation kit revision history reision number reision date description pages changed 0 9/08 initial release 1 8/09 added max1438b to parts evaluated 1C21 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 22 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. downloaded from: http:///

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