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1 of 24 071107 features ? 16384 bits electrically programmable read only memory (eprom) communicates with the economy of one signal plus ground ? unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike ? built-in multidrop controller ensures compatibility with other 1-wire ? net products ? eprom partitioned into sixty-four 256-bit pages for randomly acce ssing packetized data records ? each memory page can be permanently write- protected to prevent tampering ? device is an add only memory where additional data can be programmed into eprom without disturbing existing data ? architecture allows software to patch data by superseding an old page in favor of a newly programmed page ? reduces control, address, data, power, and programming signals to a single data pin ? directly connects to a single port pin of a microprocessor and communicates at up to 16.3 kbits per second ? 8-bit family code specifies ds2505 communications requirements to reader ? presence detector acknowledges when the reader first applies voltage ? low cost to-92 or 6-pin tsoc surface mount package ? reads over a wide voltage range of 2.8v to 6.0v from -40c to +85c; programs at 11.5v to 12.0v from -40c to +50c ds2505 pin assignment note: the leads of to-92 packages on tape- and-reel are formed to approximately 100 mil (2.54 mm) spacing. for details see the package information section. ordering information ds2505 to-92 package ds2505/t&r to-92 package, tape & reel ds2505p tsoc package ds2505p/t&r tsoc package, tape & reel ds2505+ to-92 package ds2505+t&r to-92 package, tape & reel ds2505p+ tsoc package ds2505p+t&r tsoc package, tape & reel + denotes a lead(pb)-free/rohs-compliant package. top view 3.7 x 4.0 x 1.5 mm data 1 2 3 6 54 side view see mech. drawing section tsoc package gnd nc nc nc nc 16kb add-only memory www.maxim-ic.com 1-wire is a registered trademark of maxim integrated products, inc. to-92 dallas ds2505 gnd data nc 1 2 3 bottom view downloaded from: http:///
ds2505 silicon label description the ds2505 16kb addConly memory identifies and stor es relevant informati on about the product to which it is associated. this lot or product specific information can be accessed with minimal interface, for example a single port pin of a microcontroller. the ds2505 consists of a f actory-lasered registration number that includes a unique 48-bit serial number, an 8-bit crc, and an 8-bit family code (0bh) plus 16kb of user-programmable eprom. the power to program and read the ds2505 is derived entirely from the 1-wire ? communication line. data is transferred serially via the 1- wire protocol which requires only a single data lead and a ground return. th e entire device can be programmed and then write- protected if desired. alternatively, the part ma y be programmed multiple times with new data being appended to, but not overwriting, existing data with each subsequent programming of the device. note: individual bits can be changed only fr om a logical 1 to a logical 0, never from a logical 0 to a logical 1. a provision is also included for in dicating that a certain page or pages of data are no longer valid and have been replaced with new or updated data that is now residi ng at an alternate page address. this page address redirection allows so ftware to patch data and enhance the flex ibility of the device as a standalone database. the 48-bit serial number that is f actory-lasered into each ds2505 provides a guaranteed- unique identity which allows for absolute traceab ility. the to-92 and tsoc packages provide a compact enclosure that allows standard assembly equi pment to handle the device easily for attachment to printed circuit boards or wiring. typical applications include st orage of calibration constants, maintenance records, asset tracking, pr oduct revision status and access codes. overview the block diagram in figure 1 shows the relationships between the major control and memory sections of the ds2505. the ds2505 has three main data compone nts: 1) 64-bit lasere d rom, 2) 16384-bits eprom data memory, and 3) 704 bits eprom status memory. the device derives its power for read operations entirely from the 1-wire communication line by storing ener gy on an internal capacitor during periods of time when the signal line is high and conti nues to operate off of this parasite power source during the low times of the 1-wire lin e until it returns high to replenish the parasite (capacitor) supply. during programming, 1-wire communication occurs at normal voltage levels and then is pulsed momentarily to the programming voltage to cause th e selected eprom bits to be programmed. the 1-wire line must be able to provide 12 volts an d 10 milliamperes to adequately program the eprom portions of the part. whenever programming voltages are present on the 1-wire line a special high voltage detect circuit within the ds2505 generates an in ternal logic signal to indicate this condition. the hierarchical structure of the 1-wire protocol is shown in figure 2. th e bus master must first provide one of the four rom function commands: 1) read rom, 2) match rom, 3) search rom, 4) skip rom. these commands operate on the 64-bit lasered rom portion of each device and can singulate a specific device if many are present on the 1-wire line as well as indicate to the bus ma ster how many and what types of devices are present. the protocol requir ed for these rom function commands is described in figure 8. after a rom function command is successfully executed, the memory functions that operate on the eprom portions of the ds2505 become accessible and the bus master may issue any one of the five memory function commands speci fic to the ds2505 to read or program the various data fields. the protocol for these memory function commands is de scribed in figure 5. all data is read and written least significant bit first. 64-bit lasered rom each ds2505 contains a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 3.) the 64-bit rom and rom function cont rol section allow the ds2505 to ope rate as a 1-wire device and follow the 1-wire protocol detailed in the section 1-wire bus system. the memory functions required to read and program the eprom sections of th e ds2505 are not accessible until the rom function 2 of 24 downloaded from: http:///
ds2505 protocol has been satisfied. this protocol is descri bed in the rom functions flow chart (figure 8). the 1-wire bus master must first provide one of fo ur rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. af ter a rom function sequence has been successfully executed, the bus master may then provide any one of the memory function commands specific to the ds2505 (figure 5). the 1-wire crc of the lasered rom is generated using the polynomial x 8 + x 5 + x 4 + 1. additional information about the dallas semiconductor 1-wire cy clic redundancy check is available in the book of ds19xx i button standards. the shift register acting as the crc accumulator is initialized to 0. then starting with the least significant bit of the family code, one bit at a time is shifted in. after the 8th bit of the family code has been entered, then th e serial number is entered. after the 48 th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all zeroes. ds2505 block diagram figure 1 3 of 24 downloaded from: http:///
ds2505 4 of 24 hierarchical structure for 1-wire protocol figure 2 64-bit lasered rom figure 3 8-bit crc code 48-bit serial number 8-bit family code (0bh) msb lsb msb lsb msb lsb 16384-bits eprom the memory map in figure 4 shows the 16384-bit epro m section of the ds2505 which is configured as 64 pages of 32 bytes each. the 8-bit scratchpad is an additional register that acts as a buffer when programming the memory. data is first written to the scratchpad and then ve rified by reading a 16-bit crc from the ds2505 that confirms proper receipt of th e data and address. if the buffer contents are correct, a programming voltage should be applied and th e byte of data will be wr itten into the selected address in memory. this process ensures data integrity when progra mming the memory. the details for reading and programming the 16384-bit eprom por tion of the ds2505 are given in the memory function commands section. downloaded from: http:///
ds2505 eprom status bytes in addition to the 16384 bits of data memory the ds2505 provides 704 bits of st atus memory accessible with separate commands. the eprom status bytes can be r ead or programmed to indicate vari ous conditions to the software interrogating the ds2505. the first 8 bytes of the eprom status memory (addresses 000 to 007h) contain the write protect page b its which inhibit programming of th e corresponding page in the 16384-bit main memory area if the appropriate write prot ection bit is programmed. once a bit has been programmed in the write protect page section of the status memory, the entire 32-byte page that corresponds to that bit can no longer be altered but may still be read. the next 8 bytes of the eprom st atus memory (addresses 020 to 027h) contain the write protect bits which inhibit altering the page address redirection byte corresponding to each page in the 16384-bit main memory area. the following 8 bytes within the eprom status memo ry (addresses 040 to 047h) are reserved for use by the i button operating software tmex. their purpose is to indicate which memory pages are already in use. originally, all of these bits are unprogrammed, indicating that th e device does not store any data. as soon as data is written to any page of the device under control of tmex, the bit insi de this bitmap corresponding to that page will be programmed to 0, marking this page as used. these bits are application flags only and have no impact on the internal logi c of the ds2505. the next 64 bytes of the eprom status memory (a ddresses 100h to 13fh) contain the page address redirection bytes which indicate if one or more of the pages of data in the 16384-bit eprom section have been invalidated by software and redirected to the page addr ess contained in the appropriate redirection byte. the hardware of the ds2505 makes no decisions based on the contents of the page address redirection bytes. these additional bytes of status eprom allow for the redirection of an entire page to another page address, indicating that the data in the orig inal page is no longer considered relevant or valid. with eprom technology, bits within a page can be changed from a logical 1 to a logical 0 by programming, but cannot be changed back. therefore, it is not possible to simply rewrite a page if the data requires changing or updating, but with space permitting, an entire page of data can be redirected to another page within the ds2505 by writing the ones comp lement of the new page address into the page address redirection byte that corresponds to the original (replaced) page. this architecture allows the users software to ma ke a data patch to the eprom by indicating that a particular page or pages should be replaced with those indicated in the page address redirection bytes. to leave an authentic audit trail of data patches, it is recommended to also program the write protect bit of the page address redirection byte , after the page redirection is pr ogrammed. without this protection, it is still possible to modify the page address redi rection byte, making it point to a different memory page than the true one. if a page address redirection byte has a ffh value, the data in the main memory that corresponds to that page is valid. if a page a ddress redirection byte has some othe r hex value, the data in the page corresponding to that redirection byte is invalid, and the valid data can now be found at the ones complement of the page address i ndicated by the hex value stored in the associated page address redirection byte. a value of fdh in the redirection byte for page 1, fo r example, would indicate that the updated data is now in page 2. the details for readi ng and programming the ep rom status memory portion of the ds2505 are given in th e memory function commands section. 5 of 24 downloaded from: http:///
ds2505 the status memory address range of the ds2505 ex tends from 000 to 13fh. the memory locations 008h to 01fh, 028h to 03fh, 048h to 0ffh and 140h to 7ffh are physically not implemented. reading these locations will usually result in ffh bytes . attempts to write to these locations will be ignored. if the bus master sends a starting address higher than 7ffh, the five most significant address bits are set to 0s by the internal circuitry of the ch ip. this will result in a mismatch between the crc calculated by the ds2505 and the crc calculated by th e bus master, indicating an error condition. ds2505 memory map figure 4 status memory map 6 of 24 downloaded from: http:///
ds2505 7 of 24 memory function commands the memory function flow chart (figure 5) de scribes the protocols ne cessary for accessing the various data fields within the ds2505. the memory function control section, 8-bit scratchpad, and the program voltage detect circuit combine to interpre t the commands issued by the bus master and create the correct control signals within the device. a 3- byte protocol is issued by the bus master. it is comprised of a command byte to determine the type of operation and two addres s bytes to determine the specific starting byte location within a data field. th e command byte indicates if the device is to be read or written. writing data involves not only issuing the correct command sequence but also providing a 12-volt programming voltage at the appropriate times. to execute a write sequence, a byte of data is first loaded into the scratchpad and then programmed into th e selected address. write sequences always occur a byte at a time. to execute a read sequence, the starting ad dress is issued by the bus master and data is read from the part beginning at that initial location a nd continuing to the end of th e selected data field or until a reset sequence is issued. a ll bits transferred to the ds2505 and received back by the bus master are sent least significant bit first. read memory [f0h] the read memory command is used to read data from the 16384-bit eprom data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) th at indicates a starting byte location within the data field. with every subseque nt read data time slot the bus master receives data from the ds2505 starting at the initial address and c ontinuing until the end of the 16384-bit data field is reached or until a reset pulse is issued. if readi ng occurs through the end of memory space, the bus master may issue sixteen additional read time slot s and the ds2505 will respond with a 16-bit crc of the command, address bytes and all data bytes read from the initial starting byte through the last byte of memory. this crc is the result of clearing the crc generator and then shifting in the command byte followed by the 2 address bytes and the data bytes be ginning at the first addr essed memory location and continuing through to the last byte of the eprom data memory. after the crc is received by the bus master, any subsequent read time slot s will appear as logical 1s until a reset pulse is issued. any reads ended by a reset pulse prior to reaching the end of memory will not have the 16-bit crc available. typically a 16-bit crc would be stored with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see book of ds19xx i button standards, chapter 7 for the recommended file structure to be used with the 1-wire environment.) if crc values are imbedded w ithin the data, a reset puls e may be issued at the end of memory space during a read memory command. read status [aah] the read status command is used to read data fr om the eprom status data field. the bus master follows the command byte with a 2-byte address (ta1 =(t7:t0), ta2=(t15:t8)) th at indicates a starting byte location within the data field. with every subseque nt read data time slot the bus master receives data from the ds2505 starting at the supp lied address and continuing until the end of an 8-byte page of the eprom status data field is reached. at that poi nt the bus master will receive a 16-bit crc of the command byte, address bytes and status data bytes. this crc is computed by the ds2505 and read back by the bus master to check if the command word, starting address and data were received correctly. if the crc read by the bus master is incorrect, a reset pulse must be issued and the entire sequence must be repeated. downloaded from: http:///
ds2505 memory function flow chart figure 5 8 of 24 downloaded from: http:///
ds2505 9 of 24 memory function flow chart figure 5 (contd) downloaded from: http:///
ds2505 memory function flow chart figure 5 (contd) 10 of 24 downloaded from: http:///
ds2505 note that the initial pass through the read status fl ow chart will generate a 16-bit crc value that is the result of clearing the crc generator and then shifting in the command byte followed by the 2 address bytes, and finally the data bytes be ginning at the first addressed memo ry location and continuing through to the last byte of the addressed eprom status data pa ge. the last byte of a st atus data page always has an ending address of xx7 or xxfh. subsequent passes through the read st atus flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the new data bytes, starting at the first byte of the next pa ge of the eprom status data field. this feature is provided since the eprom stat us information may change over time, making it impossible to program the data once and include an accompanying crc that w ill always be valid. therefore, the read status command supplies a 16-bit crc that is based on and alwa ys is consistent with the current data stored in the eprom status data fi eld. after the 16-bit crc of the last eprom status data page is read, the bus master will receive logical 1s from the ds2505 until a re set pulse is issued. the read status command sequence can be ended at any point by i ssuing a reset pulse. extended read memory [a5h] the extended read memory command supports page redirection when reading data from the 16384-bit eprom data field. one major difference between the extended read memory and the basic read memory command is that the bus master receives th e redirection byte first before investing time in reading data from the addressed memory location. this allows the bus master to quickly decide whether to continue and access the data at th e selected starting page or to term inate and restart the reading process at the redirected page address. a non-redirected page is identified by a redirection byte with a value of ffh (see description of eprom status bytes). if the redirection byte is different than this, the master has to complement it to obtain the new page number. multiplying the page number by 32 (20h) results in the new address the master has to send to the ds2505 to read the updated data replacing the old data. there is no logical limitation in the number of redirec tions of any page. the onl y limit is the number of available memory pages within the ds2505. in addition to page redirection, the extended r ead memory command also supports bit-oriented applications where the user cannot st ore a 16-bit crc with the data itself . with bit-oriented applications the eprom information may change over time within a page boundary, making it impossible to include an accompanying crc that will always be valid. therefore, the extended read memory command concludes each page with the ds2505 generating and supplying a 16-bit crc that is based on and therefore always consistent with the current data stored in each pa ge of the 16384-bit eprom data field. after having sent the command code of the exte nded read memory command, the bus master follows the command byte with a 2-byte address (ta1=(t7:t 0), ta2=(t15:t8)) that i ndicates a starting byte location within the data field. by sending eight read data ti me slots, the master receives the redirection byte associated with the page given by the starting address. with the next 16 read data time slots, the bus master receives a 16-bit crc of the command byte, addr ess bytes and the redirection byte. this crc is computed by the ds2505 and read back by the bus mast er to check if the command word, starting address and redirection byte we re received correctly. if the crc read by the bus master is incorrect, a rese t pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, the bus master issues read time slots and receives data from the ds2505 starting at the initi al address and continuing until the end of a 32-byte page is reached. at that point the bus master will send 16 additional read time slots and receive a 16-bit crc that is the result of shifting in to the crc generator all of the data bytes from the initial starting byte to the last byte of the current page. 11 of 24 downloaded from: http:///
ds2505 with the next 24 read data time slots the master wi ll receive the redirection byte of the next page followed by a 16-bit crc of the redirection byte. after this, data is again read from the 16,384-bit eprom data field starting at the beginning of the new page. this sequence will continue until the final page and its accompanying crc ar e read by the bus master. the extended read memory command provides a 16-b it crc at two locations within the transaction flow chart: 1) after the redirecti on byte and 2) at the end of each me mory page. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory location of the eprom data page until the last byte of this page. the crc received by the bus master directly followi ng the redirection byte, is calculated in two different ways. with the initial pass through th e extended read memory flow chart the 16-bit crc value is the result of shifti ng the command byte into the cleare d crc generator, followed by the 2 address bytes and the redirecti on byte. subsequent passes through the extended read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. after the 16-bit crc of the last page is read, the bus master will receive logi cal 1s from the ds2505 until a reset pulse is issued. the extended read memo ry command sequence can be exited at any point by issuing a reset pulse. write memory [0fh]/spe ed write memory [f3] the write memory command is used to program the 16384-bit eprom data field. the bus master will follow the command byte with a 2- byte starting address (ta1=(t7:t 0), ta2=(t15:t8)) and a byte of data (d7:d0). a 16-bit crc of the command byte, address bytes, and data byte is computed by the ds2505 and read back by the bus master to confirm that the correct command wo rd, starting address, and data byte were received. the highest starting address within the ds2505 is 07ffh. if the bus master sends a starting address higher than this, the 5 most significant address bits are set to 0 by the internal circuitry of the chip. this will result in a mismatch between the crc calcula ted by the ds2505 and the crc calculated by the bus master, indicating an error condition. if the crc read by the bus master is incorrect, a rese t pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, a programming pulse (12 volts on the 1-wire bus for 480 s) is issued by the bus mast er. prior to programmi ng, the entire unprogrammed 16384-bit eprom data field will appear as logical 1s. for each bit in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the 16384-bit eprom will be programmed to a logical 0 after the programming pulse has been applied at that byte location. after the 480 s programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have b een programmed. the ds2505 responds with the data from the se lected eprom address sent least si gnificant bit first. this byte contains the logical and of all bytes written to th is eprom data address. if the eprom data byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the current byte address should be programmed again. if the ds2505 eprom data byte contains 0s in the same bit positions as the da ta byte, the programming wa s successful and the ds2505 will automatically increment its address counter to select the next byte in the 16384-bit eprom data field. the new 2-byte addre ss will also be loaded in to the 16-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. 12 of 24 downloaded from: http:///
ds2505 13 of 24 as the ds2505 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the current address a nd the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus mast er will read this 16-bit crc from the ds2505 with sixteen read time slots to confirm that the address incr emented properly and the data byte was received correctly. if the crc is incorrect, a reset pu lse must be issued and the write memory command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write memory flow chart will generate a 16-bit crc value that is the result of shifting the command byte into the crc generator, followed by the two address bytes, and finally the data byte. subsequent passes through the write memory flow chart due to the ds2505 automatically incrementing its address counter will gene rate a 16-bit crc that is the result of loading (not shifting) the new (incremented) address into th e crc generator and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2505) is made entirely by the bus master, since th e ds2505 will not be able to determ ine if the 16-bit crc calculated by the bus master agrees with the 16-bit crc calculate d by the ds2505. if an inco rrect crc is ignored and a program pulse is applied by the bus master, inco rrect programming could occur within the ds2505. also note that the ds2505 will always increment its inte rnal address counter after the receipt of the eight read time slots used to confirm th e programming of the selected epro m byte. the decision to continue is again made entirely by the bus master. therefor e, if the eprom data byte does not match the supplied data byte but the master continue s with the write memory command, in correct programming could occur within the ds2505. the write memory command sequenc e can be ended at any point by issuing a reset pulse. to save time when writing more than 1 consecutive byt e of the ds2505s data memory it is possible to omit reading the 16-bit crc which allows verification of data and address before th e data is copied to the eprom memory. this saves 16 time slots or 976 s for every byte to be programmed. this speed- programming mode is accessed with the command code f3h instead of 0fh. it follows basically the same flow chart as the write memory command, but skips sending the crc i mmediately preceding the program pulse. this command should only be used if the electrical contact between bus master and the ds2505 is firm, since a poor contact may result in corrupted data inside the eprom memory. write status [55h]/speed write status [f5] the write status command is used to program the eprom status data field. the bus master will follow the command byte with a 2-byte star ting address (ta1=(t7:t0), ta2=(t15: t8)) and a byte of status data (d7:d0). a 16-bit crc of the command byte, addres s bytes, and data byte is computed by the ds2505 and read back by the bus master to confirm that th e correct command word, st arting address, and data byte were received. if the crc read by the bus master is incorrect, a rese t pulse must be issued and the entire sequence must be repeated. if the crc received by the bus master is correct, a programming pulse (12 volts on the 1-wire bus for 480 s) is issued by the bus master. prior to programming, the eprom status data field will appear as logical 1s. for each b it in the data byte provided by the bus master that is set to a logical 0, the corresponding bit in the selected byte of the eprom status data fi eld will be programmed to a logical 0 after the programming pulse has b een applied at that byte location. after the 480 s programming pulse is applied and the data line returns to the idle level, the bus master issues eight read time slots to verify that the appropriate bits have b een programmed. the ds2505 downloaded from: http:///
ds2505 14 of 24 responds with the data from the selected eprom status address sent least signifi cant bit first. this byte contains the logical and of all bytes written to this eprom status byte address. if the eprom status byte contains 1s in bit positions where the byte issued by the master contained 0s, a reset pulse should be issued and the curren t byte address should be programmed agai n. if the ds2505 eprom status byte contains 0s in the same bit positions as the da ta byte, the programming wa s successful and the ds2505 will automatically increment its address counter to select the next byte in the eprom status data field. the new 2-byte address will also be loaded into th e 16-bit crc generator as a starting value. the bus master will issue the next byte of data using eight write time slots. as the ds2505 receives this byte of data into the scra tchpad, it also shifts the da ta into the crc generator that has been preloaded with the current address a nd the result is a 16-bit crc of the new data byte and the new address. after supplying the data byte, the bus mast er will read this 16-bit crc from the ds2505 with 16 read time slots to confirm that the address incremen ted properly and the data byte was received correctly. if the crc is incorrect, a reset pulse must be i ssued and the write status command sequence must be restarted. if the crc is correct, the bus master will issue a programming pulse and the selected byte in memory will be programmed. note that the initial pass through the write status fl ow chart will generate a 16-bit crc value that is the result of shifting the command byte into the crc genera tor, followed by the 2 a ddress bytes, and finally the data byte. subsequent passe s through the write status flow ch art due to the ds 2505 automatically incrementing its address counter will generate a 16-bit crc that is the re sult of loading ( not shifting) the new (incremented) address into the crc genera tor and then shifting in the new data byte. for both of these cases, the decision to continue (to apply a program pulse to the ds2505) is made entirely by the bus master, since th e ds2505 will not be able to determ ine if the 16-bit crc calculated by the bus master agrees with the 16-bit crc calculate d by the ds2505. if an inco rrect crc is ignored and a program pulse is applied by the bus master, inco rrect programming could occur within the ds2505. also note that the ds2505 will always increment its inte rnal address counter after the receipt of the eight read time slots used to confirm th e programming of the selected epro m byte. the decision to continue is again made entirely by the bus master; therefor e if the eprom data byte does not match the supplied data byte but the master contin ues with the write status command, incorrect programming could occur within the ds2505. the write status command sequenc e can be ended at any point by issuing a reset pulse. to save time when writing more than 1 consecutive byte of the ds2505s status memory it is possible to omit reading the 16-bit crc which allows verification of data and address before th e data is copied to the eprom memory. this saves 16 time slots or 976 s for every byte to be programmed. this speed- programming mode is accessed with the command code f5h instead of 55h. it follows basically the same flow chart as the write status command, but skips sending the crc immediately preceding the program pulse. this command should only be used if the electrical contact between bus master and the ds2505 is firm since a poor contact may result in co rrupted data inside th e eprom status memory. 1-wire bus system the 1-wire bus is a system which has a single bus ma ster and one or more slaves. in all instances, the ds2505 is a slave device. the bus master is typica lly a microcontroller. th e discussion of this bus system is broken down into three topics: hardware conf iguration, transaction sequence, and 1-wire signaling (signal type and timing). a 1-wire protocol defines bus transactions in terms of the bus state during specified time slots that are initiated on the falli ng edge of sync pulses from the bus master. for a more detailed protocol de scription, refer to chapte r 4 of the book of ds19xx i button standards. downloaded from: http:///
ds2505 15 of 24 hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this , each device attached to the 1-wire bus must have an open drain connection or 3-state out puts. the ds2505 is an open drain part with an internal circuit equivalent to that shown in figure 6. the bus master can be the same equivale nt circuit. if a bi- directional pin is not availabl e, separate output and input pins can be tied together. the bus master requires a pullup re sistor at the master end of the bus, with the bus master circuit equivalent to the one shown in figures 7a and 7b. the value of the pullup resistor should be approximately 5 k ? for short line lengths. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus has a maximum data rate of 16.3 kbits per second. if the bus master is also required to perform programming of the eprom portions of the ds2505, a programming supply capable of delivering up to 10 milliamps at 12 volts for 480 s is required. the id le state for the 1-wire bus is high. if, for any reason, a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. transaction sequence the sequence for accessing the ds2505 via the 1-wire port is as follows: ? initialization ? rom function command ? memory function command ? read/write memory/status initialization all transactions on the 1-wire bus begin with an initialization sequ ence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by a presence pulse(s) transmitted by the slave(s). the presence pulse lets the bus ma ster know that the ds2505 is on the bu s and is ready to operate. for more details, see the 1-wire signaling section. rom function commands once the bus master has detected a presence, it can issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (refer to flowchart in figure 8): read rom [33h] this command allows the bus master to read th e ds2505s 8-bit family code, unique 48Cbit serial number, and 8-bit crc. this command can be used onl y if there is a single ds2505 on the bus. if more than one slave is present on the bus, a data collision will occur when all slaves try to transmit at the same time (open drain will produce a wired-and result). downloaded from: http:///
ds2505 16 of 24 ds2505 equivalent circuit figure 6 bus master circuit figure 7 downloaded from: http:///
ds2505 17 of 24 rom functions flow chart figure 8 downloaded from: http:///
ds2505 match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds2505 on a multidrop bus. only the ds2505 that exactly matches the 64-bit rom sequence will respond to the subsequent memory function co mmand. all slaves that do not match the 64-bit rom sequence will wait for a reset pulse. this command can be used with a single or multiple devices on the bus. skip rom [cch] this command can save time in a single-drop bus sy stem by allowing the bus master to access the memory functions without providing the 64-bit rom code . if more than one sl ave is present on the bus and a read command is issued following the skip ro m command, data collision will occur on the bus as multiple slaves transmit simultaneously (open dr ain pulldowns will produce a wired-and result). search rom [f0h] when a system is initially br ought up, the bus master might not know the number of devices on the 1-wire bus or their 64-bit rom codes. the sear ch rom command allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave de vices on the bus. the rom search process is the repetition of a simple, three-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple , three-step routin e on each bit of the rom. after one complete pass, the bus master knows the contents of the rom in one device. the remaining number of devices and th eir rom codes may be identified by additional passes. see chapter 5 of the book of ds19xx i button standards for a comprehensive disc ussion of a rom s earch, including an actual example. 1-wire signaling the ds2505 requires strict protocols to ensure data integrity. the prot ocol consists of five types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, read data and program pulse. all these signals except pres ence pulse are initiated by the bus master. the initialization sequence required to begin any communication with the ds2505 is shown in figure 9. a reset pulse followed by a presence pulse indicates the ds2505 is ready to accept a rom command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). th e 1-wire bus is pulled to a high st ate via the pullup resistor. after detecting the rising edge on the data pin, the ds2505 waits (t pdh , 15-60 s) and then transmits the presence pulse (t pdl , 60-240 s). read/write time slots the definitions of write and read time slots are illus trated in figure 10. all tim e slots are initiated by the master driving the data line low. the falling edge of the data line synchronizes the ds2505 to the master by triggering a delay circuit in th e ds2505. during write time slots, th e delay circuit determines when the ds2505 will sample the data line. for a read data time slot, if a 0 is to be transmitted, the delay circuit determines how long the ds2505 will hold th e data line low overriding the 1 generated by the master. if the data bit is a 1, the device will leave the read data time slot unchanged. program pulse to copy data from the 8-bit scratchpad to the ep rom data or status memory, a program pulse of 12 volts is applied to the data line after the bus mast er has confirmed that the crc for the current byte is correct. during programming, the bus ma ster controls the transition from a state where the data line is idling high via the pullup resistor to a state where the data line is actively driven to a programming voltage of 12 volts providing a minimum of 10 ma of current to the ds2505. this programming voltage 18 of 24 downloaded from: http:///
ds2505 (figure 11) should be applied for 480 s, after which the bus master return s the data line to an idle high state controlled by the pullup resist or. note that due to the high voltage programming requirements for any 1-wire eprom device, it is not possible to multidrop non-eprom based 1-wire devices with the ds2505 during programming. an internal diode w ithin the non-eprom based 1-wire devices will attempt to clamp the data line at approximately 8 volts and could potentiall y damage these devices. initialization procedure r eset and prese nce pulses figure 9 19 of 24 * in order not to mask interrupt signaling by other devices on the 1-wire bus, t rstl + t r should always be less than 960 s. read/write timing diagram figure 10 resistor master downloaded from: http:///
ds2505 20 of 24 read/write timing diagram figure 10 (contd) note: for read-data time slots the optimal sampling point for th e master is as close as possible to the end of the t rdv period without exceeding the 15 s window. for the case of a read -one time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high land. for a read-zero time slot it ensures that a read will occur before the fastest 1-wire device releases the line (t release = 0). downloaded from: http:///
ds2505 program pulse timing diagram figure 11 crc generation with the ds2505 there are two different types of c rcs (cyclic redundancy checks). one crc is an 8-bit type and is stored in the mo st significant byte of the 64-bit rom. the bus master can compute a crc value from the first 56 bits of the 64-bit rom a nd compare it to the value stored within the ds2505 to determine if the rom data has been received erro r-free by the bus master. the equivalent polynomial function of this crc is: x 8 + x 5 + x 4 + 1. this 8-bit crc is received in the true (non-inverted) form when reading the rom of the ds2505. it is computed once at the f actory and lasered into the rom. the other crc is a 16-bit type, ge nerated according to the standard ized crc16-polynomial function x 16 + x 15 + x 2 + 1. this crc is used to safeguard user-def ined eprom data when reading data memory or status memory. it is the same type of crc as is used with nv ram based i buttons to safeguard data packets of the i button file structure. in contrast to the 8- bit crc, the 16-bit crc is always returned in the complemented (inverted) form. a crc-generator in side the ds2505 chip (figur e 12) will calculate a new 16-bit crc at every situation shown in the command flow chart of figure 5. the ds2505 provides this crc-value to the bus master to validate the transfer of command, address, and data to and from the bus master. when reading th e data memory of the ds 2505 with the read memory command, the 16-bit crc is only transmitted as the end of the memory is reached. this crc is generated by clearing the crc genera tor, shifting in the command, low address, high address and every data byte starting at the first addressed memory lo cation and continuing until the end of the implemented data memory is reached. when reading the status memory with the read status command, the 16-bit crc is transmitted when the end of each 8-byte page of the status memory is reache d. at the initial pass through the read status flow chart the 16-bit crc will be generated by clearing the crc generator, shifting in the command byte, low address, high address and the data bytes beginning at the first addressed memory location and continuing until the last byte of the addressed eprom status data page is reach ed. subsequent passes through the read status flow chart will genera te a 16-bit crc that is the result of clearing the crc generator and then shifting in the new data bytes starting at the fi rst byte of the next page of the eprom status data field and continuing until the last byte of the page is reached. 21 of 24 downloaded from: http:///
ds2505 when reading the data memory of the ds2505 with the extended read memory command, there are two situations where a 16-bit crc is transmitted. one 16-bit crc follows each redirection byte; another 16-bit crc is received after the last byte of a memory data page is read. the crc at the end of the memory page is always the result of clearing the crc generator and shifting in the data bytes beginning at the first addressed memory locatio n of the eprom data page until the la st byte of this page. with the initial pass through the extended read memory flow chart the 16-bit crc value is the result of shifting the command byte into the cleared crc generator, fo llowed by the 2 address by tes and the redirection byte. subsequent passes through the extended read memory flow chart will generate a 16-bit crc that is the result of clearing the crc generator and then shifting in the redirection byte only. when writing to the ds2505 (either data memory or st atus memory), the bus master receives a 16-bit crc to verify the correctness of the data transfer before applying the programming pulse. with the initial pass through the write memo ry/status flow chart the 16-bit crc will be generated by clearing the crc-generator, shifting in the command, address low, address high and the data byte. subsequent passes through the write memory/status fl ow chart due to the ds2505 automa tically incrementing its address counter will generate an 16-bit crc that is the result of loading (not shifti ng) the new (incremented) address into the crc generator and th en shifting in the new data byte. the comparison of crc values and deci sion to continue with an operatio n are determined entirely by the bus master. there is no circuitry on the ds2505 that prevents a command sequence from proceeding if the crc stored in or calculated by the ds2505 does not match the value generated by the bus master. for more details on generating crc values including example implementations in both hardware and software, see the book of ds19xx i button standards. crc-16 hardware descriptio n and polynomial figure 12 22 of 24 downloaded from: http:///
ds2505 absolute maxi mum ratings* voltage on any pin relative to ground -0.5v to +12.0v operating temperature -40c to +85c storage temperature -55c to +125c soldering temperature see j-std-020a specification * this is a stress rating only and f unctional operation of the device at these or any other conditions outside those indicated in the opera tion sections of this specification is not implied. exposure to absolute maximum rating conditions for extende d periods of time may affect reliability. dc electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes logic 1 v ih 2.2 v 1, 6 logic 0 v il -0.3 +0.8 v 1, 10 output logic low @ 4 ma v ol 0.4 v 1 output logic high v oh v pup 6.0 v 1, 2 input load current i l 5 a 3 operating charge q op 30 nc 7, 8 programming voltage @ 10 ma v pp 11.5 12.0 v 11 capacitance (t a = 25c) parameter symbol min typ max units notes data (1-wire) c in/out 800 pf 9 ac electrical characteristics (v pup =2.8v to 6.0v; -40c to +85c) parameter symbol min typ max units notes time slot t slot 60 120 s write 1 low time t low1 1 15 s write 0 low time t low0 60 120 s read data valid t rdv 15 s 12 release time t release 0 15 45 s read data setup t su 1 s 5 recovery time t rec 1 s reset time high t rsth 480 s 4 reset time low t rstl 480 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s delay to program t dp 5 s delay to verify t dv 5 s program pulse width t pp 480 s 11 program voltage rise time t rp 0.5 5.0 s 11 program voltage fall time t fp 0.5 5.0 s 11 23 of 24 downloaded from: http:///
ds2505 notes: 1. all voltages are referenced to ground. 2. v pup = external pullup voltage. if v pup is lower than 3.0v the first byte read (any read command) may not reproduce the correct memory contents. therefore, under low voltage conditions, it is recommended to set either the most significant bit or all five most significant bits of ta2 to 1. internal circuitry of the chip will force these 5 bits back to 0 before they are shifted in the address counter and crc generator. 3. input load is to ground. 4. an additional reset or communication sequence ca nnot begin until the rese t high time has expired. 5. read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge and will remain valid for 14 s minimum. (15 s total from falling edge on 1-wire bus.) 6. v ih is a function of the external pullup resistor and v pup . 7. 30 nanocoulombs per 72 time slots @ 5.0v. 8. at v cc =5.0v with a 5 k ? pullup to v cc and a maximum time slot of 120 s. 9. capacitance on the data pin could be 800 pf when power is first applied. if a 5 k ? resistor is used to pull up the data line to v cc , 5 s after power has been applied th e parasite capacitance will not affect normal communications. 10. under certain low voltage conditions v ilmax may have to be reduced to as much as 0.5v to always guarantee a presence pulse. 11. operational temperature range for memory programming is -40 ? c to +50 ? c. 12. for read-data time slots the optimal sampling point for the master is as close as possible to the end of the t rdv period without exceeding the 15 s window. fo r the case of a read-o ne time slot, this maximizes the amount of time for the pull-up resistor to recover the line to a high land. for a read- zero time slot it ensures that a read will occur be fore the fastest 1-wire device releases the line (t release = 0) package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 3 to92 q3+4 21-0250 3 to92 q3+1 21-0248 6 tsoc d6+1 21-0382 24 of 24 downloaded from: http:///

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