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this is information on a product in full production. april 2014 docid024620 rev 3 1/39 39 led2472g 24-channels led driver with error detection and gain control datasheet - production data features ? 24 constant current output channels ? output current: from 4 ma to 72 ma ? 8 x 3 independently controlled channels (rgb) ? current programmable through external resistor ? 7-bit global current gain adjustment in two ranges ? error detection mode (both open and shorted led) ? programmable shorted led detection thresholds ? auto power-saving / auto wakeup ? gradual output delay (selectable) ? supply voltage: 3 v to 5.5 v ? thermal shutdown and thermal flag ? up to 30 mhz clk 4 wires interface ? 20 v current generators rated voltage applications ? full color large displays ? led signage ? led screens for indoor and outdoor billboards description the led2472g is a monolithic, low voltage, low current power 24-bit shift register designed for led panel displays with particular features oriented to indoor and outdoor led screen billboards. the led2472g guarantees 20 v of output driving capability, allowing several leds to be connected in series. the device is configured in 3 groups (red, green and blue) of 8 independently-controlled channels. the led current can be separately regulated for each color within the range from 4 ma to 72 ma. this range is divided into two sub-ranges and the current can be adjusted within each range in 64 steps of resolution (6 bits per color). a single external resistor is required. all the controls and the shift register data are accessible via serial interface. a single 24-bit configuration register is used to choose features and settings to fit the application. the led failure detection circuit checks 3 different conditions that can occur at the output line: short to gnd, short to led power supply rail or open channel. the auto power shutdown and auto power-on feature (selectable) allows the device to save power without any external intervention. thermal management includes overtemperature flag and the output thermal shutdown (170 c). the high clock frequency of up to 30 mhz makes the device suitable for high data rate transmission. a selectable gradual output delay reduces the inrush current. the supply voltage ranges from 3 v and 5.5 v. 0/34(3[ 74)3(3 table 1. device summary order code package packaging led2472gbtr tqfp48-ep tape and reel LED2472GQTR mlpq40-ep 5x5 www.st.com
contents led2472g 2/39 docid024620 rev 3 contents 1 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 6 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7 simplified internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.1 equivalent circuits of inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . 16 8 digital blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.3 current ranges (cfg 0-cfg 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.4 error detection conditions (cfg 3-cfg 5) . . . . . . . . . . . . . . . . . . . . . . . . 21 8.5 auto power shutdown / wakeup (cfg 6) . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.6 sdo delay (cfg 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.7 gradual output delay (cfg 8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 8.8 data flow management (cfg 9-cfg 11) . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.9 gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 9 current adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 led error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 11 thermal shutdown and thermal alert . . . . . . . . . . . . . . . . . . . . . . . . . . 30
docid024620 rev 3 3/39 led2472g contents 12 dropout voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 13 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
list of tables led2472g 4/39 docid024620 rev 3 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 4. thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 table 5. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 6. switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 7. digital keys summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 8. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. diagnostic thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 10. gradual output delay values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 11. gain register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 12. current adjustment example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 13. thermal alert status summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 table 14. minimum dropout voltage for some current values (only one channel on) . . . . . . . . . . . . 31 table 15. tqfp48-ep mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 16. mlpq40-ep 5x5 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 17. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
docid024620 rev 3 5/39 led2472g list of figures list of figures figure 1. pinout for tqfp48ep (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. pinout for mlpq40 (top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 3. typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 4. timing for clock, serial-in, serial-out, latch enable and outputs . . . . . . . . . . . . . . . . . . . . . 15 figure 5. oe and outputs timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 6. led2472g simplified block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 figure 7. input terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 8. data input time diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 9. digital key timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 10. configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 11. sdo delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 12. gradual delay on first four channels of red color group . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 13. different color sequence in data loading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. i out vs. gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 15. external resistor to connect to iset pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 figure 16. error detection process. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 17. le high for 14 clk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 18. typical dropout voltage vs. output current (only one channel on) . . . . . . . . . . . . . . . . . . . 31 figure 19. tqfp48-ep package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. tqfp48-ep recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 21. mlpq40-ep 5x5 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 22. mlpq40-ep 5x5 recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
pin description led2472g 6/39 docid024620 rev 3 1 pin description figure 1. pinout for tqfp48ep (top view) figure 2. pinout for mlpq40 (top view) $09 74)3h[srvhgsdg 1& 6', /( &/. 1& 1& 1& 5(6(59(' 5(6(59(' 1& 1& 1& 1& 6'2 52( *2( %2( 9'' *1' *1' 1& ,6(7 1& 1& 5 * % 5 * % 5 * % 5 * % % * 5 % * 5 % * 5 % * 5 $09 0/34/[ 5 6', /( &/. 1& 5 5(6(59(' 5(6(59(' % 6'2 52( *2( %2( 9'' *1' *1' % ,6(7 1& 1& * % 5 * % 5 * % 5 * * 5 % * 5 % * 5 % *
docid024620 rev 3 7/39 led2472g pin description table 2. pin description pin symbol name and function tqfp48 mlpq40 29, 30 23, 24 gnd ground 2 2 sdi serial data input 3 3 le latch enable 8,9 8, 9 reserved not used in applications 47clkclock 1, 5, 6, 7, 10, 11, 12, 25, 26, 28, 36 4, 5, 6 nc not connected 31 25 vdd power supply voltage 13 10 r1 red output 1 14 11 g1 green output 1 15 12 b1 blue output 1 16 13 r2 red output 2 17 14 g2 green output 2 18 15 b2 blue output 2 19 16 r3 red output 3 20 17 g3 green output 3 21 18 b3 blue output 3 22 19 r4 red output 4 23 20 g4 green output 4 24 21 b4 blue output 4 27 22 iset current setup 32 26 boe blue output enable 33 27 goe green output enable 34 28 roe red output enable 35 29 sdo serial data output 37 30 b5 red output 5 38 31 g5 green output 5 39 32 r5 blue output 5 40 33 b6 red output 6 41 34 g6 green output 6 42 35 r6 blue output 6 43 36 b7 red output 7 44 37 g7 green output 7 45 38 r7 blue output 7 46 39 b8 red output 8
pin description led2472g 8/39 docid024620 rev 3 47 40 g8 green output 8 48 1 r8 blue output 8 table 2. pin description (continued) pin symbol name and function tqfp48 mlpq40
docid024620 rev 3 9/39 led2472g absolute maximum ratings 2 absolute maximum ratings stressing the device above the ratings listed in the tab le 3 may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 3 thermal characteristics table 3. absolute maximum ratings symbol parameter value unit v dd supply voltage -0. 4 to 7 v v i digital inputs voltage -0.4 to vdd+0.4 v out driver outputs voltage (r<1:8>, g<1:8>, b<1:8>) 20 v io output current 80 ma ignd gnd terminal current 1.9 a esd electrostatic discharge protection hbm human body model 2 kv electrostatic discharge protection mm machine model 2 00 v table 4. thermal characteristics symbol parameter value unit ta operative free-air temperature range (1) -40 to +85 c tj-opr operative thermal junction temperature range -40 to +125 tstg storage temperature range -55 to +150 rth ja junction-ambient thermal resistance; qfn40-ep (2) 25.3 c/w junction-ambient thermal resistance; tssop48-ep (1) 33 c/w 1. this data must be considered in adequate power dissipati on conditions. the junction temperature must be maintained below 150 c. 2. in accordance with jedec st andard 51-7b. the exposed pad should be soldered di rectly to the pcb to obtain the thermal benefits.
electrical characteristics led2472g 10/39 docid024620 rev 3 4 electrical characteristics vdd = 3.3 v, tj = 25 c, grg = ?1? (gain reg), r ext = 13 k ? , unless otherwise specified. table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit vdd supply voltage 3 5.5 v v out output voltage for all outputs - - 19 v ih input voltage 0.7?vdd - vdd v il gnd - 0. 3 ? vdd v ol serial data output voltage (sdo) v dd = 3 to 5.5 v i = +/- 1 ma --0.4 v oh v dd -0.4 - - i oleak output leakage current vo = 19 v , all outputs off - - 0.5 ua v uvlo1 uvlo threshold voltage (rising) 2.7 2.9 v v uvlo1 uvlo threshold voltage (falling) 2.2 2.3 v hy uvlo uvlo hysteresis 400 mv ? i ol1 output current precision channel-to-channel per each color group (all outputs on) (1)(2) v o = 0.3 v; (io=5 ma) cfg-0 = cfg-1 = cfg-2 = ?0? grg = ?0? --4 % ? i ol3 v o = 0.6 v; (io = 21 ma) cfg-0 = cfg-1 = cfg-2 = ?0? --3 ? i ol2 v o = 0.5 v; (io=15 ma) cfg-0 = cfg-1 = cfg-2 = ?1? grg = ?0? --3 ? i ol4 vo = 1.2 v; (io=61 ma) cfg-0 = cfg-1 = cfg-2 = ?1? --3 ? i ol1a output current error device-to- device per each color group (all outputs on) (1) v o = 0.3 v; (io = 5 ma) cfg-0 = cfg-1 = cfg-2 = ?0? grg = ?0? --6 ? i ol3a v o = 0.6 v; (io=21 ma) cfg-0 = cfg-1 = cfg-2 = ?0? --6 ? i ol2a v o = 0.5 v; (io = 15 ma) cfg-0 = cfg-1 = cfg-2 = ?1? grg = ?0? --6 ? i ol4a vo = 1.2 v; (io = 61 ma) cfg-0 = cfg-1 = cfg-2 = ?1? --6
docid024620 rev 3 11/39 led2472g electrical characteristics %/ v out output current vs. output voltage regulation (3) v o from 1.2 v to 3 v; (io = 61 ma) cfg-0 = cfg-1 = cfg-2 = ?1? -0.2- %/v %/ v dd output current vs. supply voltage regulation (4) vdd from 3 v to 5.5 v v o = 1.2 v; (io = 61 ma) cfg-0 = cfg-1 = cfg-2 = ?1? -1- rup pull-up resistor for oe pin 400 500 650 k ? rdw pull-down resistor for le pin r ext external current setup resistance 100 i dd1 supply current (off) no data transfers, all outputs off, cfg-0 = cfg-1 = cfg-2 = ?0? grg = ?0?; cfg-6 = ?0? 8 ma i dd2 no data transfers, all outputs off, cfg-0 = cfg-1 = cfg-2 = ?1? cfg-6 = ?0? 16 i dd1 supply current (on) no data transfers, all outputs on, cfg-0 = cfg-1 = cfg-2 = ?0? grg = ?0? -8 ma i dd2 no data transfers, all outputs on, cfg-0 = cfg-1 = cfg-2 = ?1? -15 idd (autooff) supply current (autooff) all output off cfg-6 = ?1? - 200 500 a sde 1 led short detection voltage cfg-3 = cfg-4 = cfg-5 = ?0? 2.0 v sde 2 cfg-3 = cfg-4 = cfg-5 = ?1? 3.0 odc led open detection current 0.5 i ol table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
electrical characteristics led2472g 12/39 docid024620 rev 3 4.1 typical application circuit figure 3. typical application circuit tflg thermal flag 150 c tsd thermal shutdown (5) 170 ts d - h y thermal shutdown hysteresis (5) 15 20 1. tested with just one output loaded 2. ((iout n - iout avg1-15 )/ iout avg1-15 ) x 100 3. 4. 5. not tested, guaranteed by design. table 5. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit 1 3 100 ) v 0 . 1 voutn @ ioutn ( ) v 0 . 1 voutn @ ioutn ( ) v 0 . 3 voutn @ ioutn ( ) v / (% ? = = ? = = 3 5 . 5 100 ) v 0 . 3 vdd @ ioutn ( ) v 0 . 3 vdd @ ioutn ( ) v 5 . 5 vdd @ ioutn ( ) v / (% ? = = ? = = $09 2xwsxwhqdeohiru hdfkfrorujurxs 'dwdordglqjdqg uhjlvwhuvdffhvv wkurxjkvhuldo lqwhuidfh 6xsso\yrowdjh /('yrowdjhudlo
docid024620 rev 3 13/39 led2472g switching characteristics 5 switching characteristics vdd = 3.3 v, tj = 25 c, grg = ?1? (gain reg), r ext = 13 k ? , unless otherwise specified. table 6. switching characteristics (1)(2) symbol parameter conditions min. typ. max. unit f clk clock frequency cascade operation - - 30 mhz tr (sdo) sdo rise time r ext = 13 k ? ; iout = 21 ma vout = 0.6 v vih = vdd; vil = gnd rl = 56 ; cl = 10 pf cfg-0 = cfg-1 = cfg-2 = ?0? -5- ns tf (sdo) sdo fall time - 5 - tplh2 le - outn (3) propagation delay time (?l? to ?h?) -70- tplh3 oe - outn (3) - 100 - tplh clk - sdo cfg-7 = ?0? 81525 tphl2 le - outn (3) propagation delay time (?h? to ?l?) -70- tphl3 oe - outn (3) -1 00 - tphl clk - sdo cfg-7= ?0? 81525 tw(clk) clk pulse width 20 - - t w (oe )oe 150 (4) -- tw(l) le 20 - - t gr-d gradual delay ch to ch 10 t su(l) setup time for le 5 - - t h(l) hold time for le 5 - - t su(d) setup time for sdi 5 - - t h(d) hold time for sdi 10 - - tor (5) maximum clk rise time - - 5 s tof (5) maximum clk fall time - - 5 i out-ov output current turn-on overshoot vout = 0.3 to 3 v cl = 10 pf; iout = 5 to 61 ma --10% t n-err normal error detection minimum output on time --1s
switching characteristics led2472g 14/39 docid024620 rev 3 t shut-down auto power shutdown time (autooff) from le falling edge to r ext voltage reference at -10% -75-ns t wake-up auto power wakeup time from le falling edge to r ext voltage reference at 90% -1-s 1. all table limits are guaranteed by design. 2. not tested in production. 3. cfg-8 = ?1? (no output gradual delay) 4. in normal error detection mode must be longer than 1s 5. if devices are connected in cascade and t or or t of is large, it may be critical to ac hieve the timing required for data transfer between two cascaded devices table 6. switching characteristics (1)(2) symbol parameter conditions min. typ. max. unit
docid024620 rev 3 15/39 led2472g timing 6 timing figure 4. timing for clock, serial-in, serial-out, latch enable and outputs correct sampling of the data depends on the stability of the data at sdi on the rising edge of the clock signal and it is assured by a proper data setup and hold time (t su(d) and t h(d) ), as shown in figure 4 . the same figure shows the propagation delay from clk to sdo (t plh /t phl ). figure 4 describes also the minimum duration of clk and le pulses (t w(clk) and t w(l) , respectively) and the propagation delay from le to out n (t plh1 /t phl1 and t plh2 /t phl2 , respectively). finally, figure 5 also defines the turn-on and turn-off time (t of and t or ) of the output voltage. figure 5. oe and outputs timing am13690v1 $09
simplified internal block diagram led2472g 16/39 docid024620 rev 3 7 simplified internal block diagram figure 6. led2472g simplified block diagram 7.1 equivalent circuits of inputs and outputs input terminals le and /oe have pull-down and pull-up connections, respectively. clk and sdi must be connected to external circuits to fix the logic level. $09
docid024620 rev 3 17/39 led2472g simplified internal block diagram figure 7. input terminals am13692v1 oe terminal le terminal clk, sdi terminal sdo terminal
digital blocks led2472g 18/39 docid024620 rev 3 8 digital blocks the data inputs come in through the serial interface at each clk rising edge and after 24 clk cycles all data are loaded into the shift register. the le signal is used to latch the loaded data and also to generate digital keys for cfg management, scrolling, thermal check and led error detection. when one of the output enable signal (oer, oeb or oeg) is low, the corresponding data are transferred to the relative output drivers. the data flow is ?first in, first out?. to latch the data, the le signal must be high during the last data loading clk rising edge ( table 7 ). when one of the output enable signals (oer, oeb or oeg) is at low level, output terminals (r1-r8,g1-g8, b1-b8) respond to the data either on or off. when one of the output enable signals (oer, oeb or oeg) goes to ?1?, all outputs switch off all the data on the output terminal. le and /oe signals are asynchronous with respect to the clk signal. the time diagram below refers to rgb flow setting. figure 8. data input time diagram 8.1 register access access to the different registers of the device (configuration register, gain register, etc.) is achieved by using different digital keys, defined as a number of clk pulses during which the le signal is asserted. the available digital keys are summarized in table 7 . $09 6', &/. /( 2( 5*% 5 5 * * % % * 2)) 21 2)) 21 2)) 21 2)) 21 2)) 21 2)) 21 2)) 21 elwgdwd
docid024620 rev 3 19/39 led2472g digital blocks figure 9. digital key timing diagram 8.2 configuration register the configuration register is used to enable or disable some device features, to program some parameters and to change other settings. access to this register (read or write) is table 7. digital keys summary #clk rising edges with the le asserted description 1-2 data latch 3-4 write configuration register 5-6 read configuration register 7-8 write gain 9-10 read gain 11 open detection 12 short detection 13 open/short detection 14 thermal alert reading 15 reserved 16 reserved $09 'dwdodwfk :ulwh&5 5hdg&5 :ulwhjdlq 5hdgjdlq 2shqghwhfwlrq 6kruwghwhfwlrq 2shqvkruwghwhfwlrq 7khupdodohuw &/. /( /( /( /( /( /( /( /( 6', ' ' ' ' ' ' ' ' ' 3uhylrxvgdwd 3uhylrxvgdwd 1h[wgdwd ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' '
digital blocks led2472g 20/39 docid024620 rev 3 managed as described in tab le 8 where a description is provided for each bit. the default value of the configuration register (when the device is switched on or after a reset) is all bits set to ?0?. to change anything in the configuration register, a 24-bit digital word must be sent (cfg-0 represents the lsb, cfg-23 the msb). figure 10. configuration register table 8. configuration register bit definition attribute read/write configuration register function description default cfg-0 red current range r/w ?0? low current range ?1? high current range 0 cfg-1 green current range r/w ?0? low current range ?1? high current range 0 cfg-2 blue current range r/w ?0? low current range ?1? high current range 0 cfg-3 red voltage det. thr. r/w ?0? led short-circuit detection threshold 2 v ?1? led short-circuit detection threshold 3 v 0 cfg-4 green voltage det. thr. r/w ?0? led short-circuit detection threshold 2 v ?1?le d short-circuit detection threshold 3 v 0 cfg-5 blue voltage det . thr. r/w ?0? led short-circuit detection threshold 2 v ?1? led short-circuit detection threshold 3 v 0 cfg-6 auto off r/w ?0? device always on ?1? auto power shutdown active (auto off) 0 cfg-7 sdo delay r/w ?0? sdo half clock delay disabled ?1? sdo half clock delay enabled 0 cfg-8 gradual output delay r/w ?0? gradual outputs delay is applied ?1? all channels switch on and off simultaneously 0 &/. 6', /( elwgdwd $09
docid024620 rev 3 21/39 led2472g digital blocks 8.3 current ranges (cfg 0-cfg 2) the output led currents can be programmed using an external resistor connected to gnd from the iset pin and can be adjusted using 6 bits in a dedicated gain register with two possible current ranges selectable in the configuration register. each range can be separately selected for each color by the bits cfg-0, cfg-1 and cfg-2, respectively, for the red, green and blue channels. 8.4 error detection conditions (cfg 3-cfg 5) during error detection phases for each channel, the following are checked: ? output current for open circuit detection ? output voltage for short-circuit detection the thresholds for the error diagnostics are summarized in the table 9 : 8.5 auto power shutdown / wakeup (cfg 6) this feature reduces the power consumption when all outputs are off. it is active when the bit cfg-6 of the configuration register is at ?1?. the auto power shutdown (auto off) starts when the data latched is ?0? for all channels, and the device will be active again (wakeup) at the first latched data string including at least one bit equal to ?1? (at least one channel on). cfg-9 data flow r/w color data flow management cfg9 cfg10 cfg11 0 00 0 rgb 00 1 gbr cfg-10 01 0 grb 0 01 1 bgr cfg-11 10 0 brg 0 10 1 rbg cfg 12 23 don?t care table 8. configuration register (continued) bit definition attribute read/write configuration register function description default table 9. diagnostic thresholds error detection checked malfunction cfg-x (1) thresholds open detection combined mode open line or output short to gnd don?t care io < 0.5 x io_programmed short detection short on led or short to vled 0 vo > 2 v 1 vo > 3 v 1. x=3 for red, x=4 for green, x=5 for blue
digital blocks led2472g 22/39 docid024620 rev 3 timings for shutdown and wakeup are present in the dynamic features table. while the auto power shutdown is active, the device ignores any other command except channel power-on. 8.6 sdo delay (cfg 7) normally, on sdo terminals data is shifted out at the rising edge of the clk signal with a propagation delay of about 15 ns [signal (1) in figure 11 ]. the device provides the possibility to shift data out also at the falling edge of the clk signal with a propagation delay of few ns [signal (2) in figure 11 ]. this feature can be activated by setting to ?1? the bit cfg-7 of the configuration register. the default setting for this bit is ?0?, hence the sdo delay is not activated by default. this feature is particularly useful when multiple devices are connected in daisy chain configuration with non-matched delays between the clk and sdo data paths (board routing). figure 11. sdo delay 8.7 gradual output delay (cfg 8) the gradual output delay consists in turning on gradually the current generators, avoiding turning on all channels at the same time. this feature prevents large inrush current and reduces the bypass capacitor values. the fixed delay time can be activated by bit cfg-8 of the configuration register, and the typical delay is 10 ns for each group of 8 outputs r, g, b (e.g. r1, g1, b1 has no delay, r2, g2, b2 has 10 ns of delay and r3, g3, b3, has 20 ns delay, and so on), as described in table 10 .
docid024620 rev 3 23/39 led2472g digital blocks figure 12 shows an example of the effect of the output gradual delay on the red color group outputs. figure 12. gradual delay on first four channels of red color group 8.8 data flow management (cfg 9-cfg 11) the 8x3 shift registers have a default rgb sequence serial data flow according to the table shown into the configuration register (bit cfg-9, cfg-10 and cfg-11). figure 13 shows how serial data are loaded in accordance with the data flow sequence selected through the configuration register. the default sequence is rgb (first bit will be r8, last bit b1 then: r8- r1, g8-g1, b8-b1). table 10. gradual output delay values delay time (ns) from the falling edge of xoe r1 g1 b1 r2 g2 b2 r3 g3 b3 r4 g4 b4 r5 g5 b5 r6 g6 b6 r7 g7 b7 r8 g8 b8 cfg-8 = ?0? 0 10 20 30 40 50 60 70 cfg-8 = ?1? 0000000 0 $09 z z? z? ze
digital blocks led2472g 24/39 docid024620 rev 3 figure 13. different color sequence in data loading 8.9 gain register the led current can be programmed using an external resistor connected to gnd from r- ext pin and can be adjusted using the dedicated bits of the gain register (g-0 to g-17 defines the gain and cfg-0/1/2 the current range within the gain can be adjusted). the device can regulate the current up to 72 ma and down to 4 ma. to change anything in the gain register, a 24-bit digital word must be sent (cfg-0 represents the lsb, cfg-23 the msb). the accuracy of the led current depends on the selected range and it is assured only in the ranges indicated in the static electrical characteristics (see tab le 5 ). /6%odvwelw 5*% 5 5 * * % % *%5 * * % % 5 5 *5% * * 5 5 % % %*5 % % * * 5 5 %5* % % 5 5 * * 5%* 5 5 % % * * &)* jurxs jurxs jurxs 06%iluvwelw elwvgdwdvwuhdp $09 table 11. gain register bit definition attribute read/write register function description default g-0 red current gain adjustment r/w 6-bit dac allows adjustment of the device output current in 64 steps for each range (defined by cfg-0). default: gain = 1 1 g-1 1 g-2 1 g-3 1 g-4 1 g-5 1 g-6 green current gain adjustment r/w 6-bit dac allows adjustment of the device output current in 64 steps for each range (defined by cfg-1). default: gain = 1 1 g-7 1 g-8 1 g-9 1 g-10 1 g-11 1
docid024620 rev 3 25/39 led2472g digital blocks figure 14. i out vs. gain g-12 blue current gain adjustment r/w 6-bit dac allows adjustment of the device output current in 64 steps for each range (defined by cfg-2). default: gain = 1 1 g-13 1 g-14 1 g-15 1 g-16 1 g-17 1 g-18 to g-23 don?t care table 11. gain register (continued) bit definition attribute read/write register function description default $09 x x ?x ?x ex ?x x x ? ? ? ?? ? ?? e e? ? ?? ? ?<za ?<za ?<za ?<za 5 udqjhvhohfwlrq5h[w .ru. *dlquhjlvwhughflpdoydoxh ,rxwp$
current adjustment led2472g 26/39 docid024620 rev 3 9 current adjustment the led2472g is designed to provide a current in the range between 4 ma and 72 ma per channel. the current is programmed for all color groups by connecting an external resistor (see figure 15 ) to the pin iset and then adjusted separately for each color by the gain register. the current ranges can be separately selected for each color by the bits cfg-0, cfg-1, cfg-2 of the configuration register (respectively, for red, green and blue). the current for each color can be adjusted in 64 steps using 6 bits (per color) contained in the gain register. figure 15. external resistor to connect to iset pin when the device is switched on, the default value of the gain register together with the bits of the configuration register selecting the current range set a current value that can be calculated as follows: where v ref 1.23 v is the voltage of the iset pin and k is the mirroring current ratio, whose value depends on the selected current range: k = 55 with low current range selected (cfg-0, cfg-1 or cfg-2 set to ?0?) k = 160 with high current range selected (cfg-0, cfg-1 or cfg-2 set to ?1?) the relationship between the programmed current and the current gain settings is the following: where g is the current gain (decimal value) defined by the dedicated bits of the current gain register. i step can be instead defined as follows: $09 5 6(7 5 6(7 1& ,6(7 1& 1& % * 5 % k r v i ext ref default ol ? = _ ) ( _ step default ol ol i g i i ? + =
docid024620 rev 3 27/39 led2472g current adjustment the recommended resistor values to cover the above mentioned current range are 11- 18 k ? , which respectively define the following ranges: the current values in bold in the table 12 are the current default values. the above mentioned resistor values are not mandatory, but only suggested to cover precisely the current range indicated for this device. due to internal power dissipation, it is important to highlight that, loading at the maximum current of all device channels simultaneously can cause a current shift for each output. in the worst case, with all channels loaded at the maximum current of about 72 ma, the regulated current could decrease in the range of about 3-5%. table 12. current adjustment example range r set [ k ? ]cfg-x (1) 1. x = 0 for red, x = 1 for green, x = 2 for blue g-y to g-z (2) 2. y = 0 & z = 5 for red, y = 6 & z = 11 for green, y = 12 & z = 17 for blue led current (3) [ma] 3. the indicated values may be slightly different on the actual device low 18 0 000000 4 18 0 111111 15 high 18 1 000000 11 18 1 111111 44 low 13 0 000000 5 13 0 111111 21 high 13 1 000000 15 13 1 111111 61 low 11 0 000000 6 11 0 111111 25 high 11 1 000000 18 11 1 111111 72 21 _ default ol step i i =
led error detection led2472g 28/39 docid024620 rev 3 10 led error detection the led error detection implemented by the led2472g is performed in order to detect shorted led and open led conditions. the shorted led condition is determined by checking the voltage across each current generator. if this voltage is higher than the threshold, programmed by bits cfg-3, cfg-4 and cfg-5 of the configuration register, the led connected to that generator is considered shorted. the open led condition is determined by measuring the current flowing through each current generator. if this current is lower than half the expected current, the led connected to that generator is considered open. the error detection request and the acquisition of the results of the detection are managed by the serial interface. the steps to follow for correct performance of error detection are summarized as follows (see figure 16 ): ? enter the error detection . to do this, the appropriate digital key must be provided (see figure 9 ). there is both the possibility of ?generic? error detection (open/short detection) and the possibility to specifically select the type of failure (short detection or open detection). ? performing the error detection . when the roe, goe and boe signals become low, error detection starts. these signals must be kept low for at least 1 s in order to correctly complete the error detection process. after this time, at least one clk pulse must be provided in order to make the detection result available at the sdo pin while the output enable signals are still low. the bit shifted out of sdo after this clock pulse represents the first bit of the detection result word. ? detection results . to complete the detection result acquisition, at least another 23 clk pulses must be provided after the xoe signals have been set high again (24 clk pulses in total). the detection result will be always in rgb sequence regardless of any different programmed data flow (cfg9-cfg11). the detection result indicates ?1? for each channel considered good, ?0? for each channel that has a failure (shorted or open led). to check the status of all channels and to obtain an accurate detection result, it is important to set all outputs to on before starting the error detection process. if this is not done, it is worth noting that the detection result will indicate a ?0? also for those channels not set to on before the detection process, although they may not actually have any failure.
docid024620 rev 3 29/39 led2472g led error detection figure 16. error detection process $09
thermal shutdown and thermal alert led2472g 30/39 docid024620 rev 3 11 thermal shutdown and thermal alert the device can monitor the internal temperature. based on the temperature value, the device can simply provide an alert (if the temperature exceeds 150 c) through the serial interface, or trigger a thermal shutdown (if the temperature exceeds 170 c). the effect of the thermal shutdown is to turn off all channels until the temperature falls (considering a hysteresis of around 15 c). the thermal alert can be read by running the digital key ?thermal alert reading?, holding the le high for 14 clk rising edges (see figure 17 ). if thermal alert is asserted, a 24-bit string at ?1? will be sent through sdo at the next 24 clk rising edge. figure 17. le high for 14 clk table 13. thermal alert status summary thermal alert status meaning ?0000 0000 0000 0000 0000 0000? device temperature under 150 c ?1111 1111 1111 1111 1111 1111? device temperature over 150 c $09
docid024620 rev 3 31/39 led2472g dropout voltage 12 dropout voltage in order to correctly regulate the channel current, a minimum voltage (v drop ) across each current generator must be guaranteed. figure 18 and table 14 show the minimum v drop related to the current to regulate. a v drop lower than the minimum recommended implies the regulation of a current lower than that expected. however, an excess of v drop increases the power dissipation. when all outputs are loaded simultaneously, the minimum working drop rises. in full load condition at 61 ma per channel the minimum voltage to apply on each channel must be increased by about 400 mv (550 mv at 72 ma). figure 18. typical dropout voltage vs. output current (only one channel on) table 14. minimum dropout voltage for some current values (only one channel on) output nominal current [ma] minimum v drop [mv] v dd = 3.3 v 5120 15 280 21 320 61 800 75 1050 9gurs >p9@ ,rxw >p$@ 7\ s gurs yv,rxw # 9gg 9 $09
package mechanical data led2472g 32/39 docid024620 rev 3 13 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark. figure 19. tqfp48-ep package dimensions b(
docid024620 rev 3 33/39 led2472g package mechanical data table 15. tqfp48-ep mechanical data dim. mm min. typ. max. a 1.20 a1 0.05 0.15 a2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 0.20 d 8.80 9.00 9.20 d1 6.80 7.00 7.20 d2 2.00 d3 5.50 e 8.80 9.00 9.20 e1 6.80 7.00 7.20 e2 2.00 e3 5.50 e 0.50 l 0.45 0.60 0.75 l1 1.00 k03.57 ccc 0.08
package mechanical data led2472g 34/39 docid024620 rev 3 figure 20. tqfp48-ep recommended footprint b(
docid024620 rev 3 35/39 led2472g package mechanical data figure 21. mlpq40-ep 5x5 package dimensions b$
package mechanical data led2472g 36/39 docid024620 rev 3 table 16. mlpq40-ep 5x5 mechanical data dim. mm min. typ. max. a 0.90 0.80 1.00 a1 0.02 0.00 0.05 b 0.20 0.15 0.25 d 5 e 5 d2 3.65 3.50 3.75 e2 3.65 3.50 3.75 e 0.40 l1 0.377 0.277 0.477 l2 0.40 0.30 0.50 k0.20
docid024620 rev 3 37/39 led2472g package mechanical data figure 22. mlpq40-ep 5x5 recommended footprint b$
revision history led2472g 38/39 docid024620 rev 3 14 revision history table 17. document revision history date revision changes 19-aug-2013 1 initial release. 05-mar-2014 2 modified footnote1 in table 6: switching characteristics added footnote 2 in table 6: switching characteristics and footnote 5 in table 5: electrical characteristics . 22-apr-2014 3 document status promoted from preliminary data to production data.
docid024620 rev 3 39/39 led2472g please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. st products are not designed or authorized for use in: (a) safety critical applications such as life supporting, active implanted devices or systems with product functional safety requirements; (b) aeronautic applications; (c) automotive applications or environments, and/or (d) aerospace applications or environments. where st products are not designed for such use, the purchaser shall use products at purchaser?s sole risk, even if st has been informed in writing of such usage, unless a product is expressly designated by st as being intended for ?automotive, automotive safety or medical? industry domains according to st product design specifications. products formally escc, qml or jan qualified are deemed suitable for use in aerospace by the corresponding governmental agency. resale of st products with provisions different from the statem ents and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2014 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - swed en - switzerland - united kingdom - united states of america www.st.com

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