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general description the max35103 is a time-to-digital converter with built-in amplifier and comparator targeted as a low-cost analog front-end solution for the ultrasonic heat meter and flow meter markets. it is similar to the max35101, but con - sumes about half the average power and increases the maximum tof measurement frequency in event timing mode from 2hz to 16hz. with a time measurement accuracy of 20ps and auto - matic differential time-of-flight (tof) measurement, this device makes for simplified computation of liquid flow. average power consumption is the lowest available with ultra-low 5.5a tof measurement and < 125na duty- cycled temperature measurement. applications ultrasonic heat meters ultrasonic water meters ultrasonic gas meters beneits and features high accuracy flow measurement for billing and leak detection ? time-to-digital accuracy down to 20ps ? measurement range up to 8ms ? two channels: single-stop channel high accuracy temperature measurement for precise heat and flow calculations ? up to four 2-wire sensors ? pt1000 and pt500 rtd support maximizes battery life with low device and overall system power ? ultra-low 5a tof measurement and < 125na duty-cycled temperature measurement ? event timing mode reduces host microcontroller overhead to minimize system power consumption ? 2.3v to 3.6v single-supply operation high-integration solution minimizes parts count and reduces bom cost ? 8kb of nonvolatile flash memory for data logging ? built-in real time clock ? small, 5mm x 5mm, 32-pin tqfp package ? -40c to +85c operation ordering information appears at end of data sheet. 19-7361; rev 1; 1/15 max35103 reduced power time-to-digital converter with afe, rtc, and flash evaluation kit available downloaded from: http:///
max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 2 4-wire interface analog switching and bias control time-to-digital converter programmable alu data and status registers 8kb flash state machine controller configuration registers internal ldo pulse launcher x1 12pf x2 32.768khz 32kx1 12pf 32kx0 12pf 4mhz 12pf 32kout microcontroller t1 t2 t3 t4 tc pt 1000 1k (50ppm) metal film 100 nf cog (np0) (30ppm/c) din ce dout sck rst int wdo csw stop_up launch_up launch_dn stop_dn v cc bypass 100nf low esr piezoelectric transducers cmp_out/up_dn v cc v cc 3.6v high-speed and 32khz oscillators with real-time clock temperature measurement max35103 3.6v gnd gnd gnd gnd gnd pt 1000 typical application circuit downloaded from: http:///
(voltages relative to ground.) voltage range on v cc pins ................................. -0.5v to +4.0v voltage range on all other pins (not to exceed 4.0v) ............................. -0.5v to (v cc + 0.5v) continuous power dissipation (t a = +70c) tqfp (derate 27.80mw/oc above +70c) ........... 2222.20mw operating temperature range ........................... -40c to +85c junction temperature ...................................................... +150c storage temperature range ............................ -55c to +125c lead temperature (soldering, 10s) ................................. +300c soldering temperature (reflow) ....................................... +260c esd protection (all pins, human body model) .................. 2kv tqfp junction-to-ambient thermal resistance ( ja ) .......... 36c/w junction-to-case thermal resistance ( jc ) ..................... 4c/w (note 1) (v cc = 2.3v to 3.6v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = 3.0v and t a = +25c.) (notes 2, 3) (t a = -40 c to +85 c, unless otherwise noted.) (notes 2, 3) parameter symbol conditions min typ max units supply voltage v cc 2.3 3.0 3.6 v input logic 1 ( rst , csw, sck, din, ce ) v ih v cc x 0.7 v cc + 0.3 v input logic 0 ( rst , csw, sck, din, ce ) v il -0.3 v cc x 0.3 v input logic 1 (32kx1) v ih32kx1 v cc x 0.85 v cc + 0.3 v input logic 0 (32kx1) v il32kx1 -0.3 v cc x 0.15 v parameter symbol conditions min typ max units input leakage (csw, rst , sck, din, ce ) i l -0.1 +0.1 a output leakage ( int , wdo , t1,t2,t3,t4) o l -0.1 +0.1 a output voltage low (32kout) v ol32k 2ma 0.2 x v cc v output voltage high (32kout) v oh32k -1ma 0.8 x v cc v output voltage high (dout, cmp_out/up_dn) v oh -4ma 0.8 x v cc v output voltage high (tc) v ohtc v cc = 3.3v, i out = -4ma 2.9 3.1 v max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 3 note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four-layer board. for detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial . absolute maximum ratings stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristicselectrical characteristics recommended operating conditions downloaded from: http:///
(v cc = 2.3v to 3.6v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = 3.0v and t a = +25c.) (notes 2, 3) parameter symbol conditions min typ max units output voltage high (launch_up, launch_dn) v ohlauch v cc = 3.3v, i out = -50ma 2.8 3.0 v output voltage low ( wdo , int , dout, cmp_out/up_dn) v ol 4ma 0.2 x v cc v pulldown resistance (tc) r tc 650 1000 1500 ? input voltage low (tc) v iltc 0.36 x v cc v output voltage low (launch_up, launch_dn) v ollauch v cc = 3.3v, i out = 50ma 0.2 0.4 v resistance (t1, t2, t3, t4) r on 1 ? input capacitance ( ce , sck, din, rst , csw) c in not tested 7 pf rst low time t rst 100 ns current standby current i ddq no oscillators running, t a = +25c 0.1 1 a 32khz osc current i 32khz 32khz oscillator only (note 4) 0.5 0.9 a 4mhz osc current i 4mhz 4mhz oscillator only (note 4) 40 85 a ldo bias current i ccldo i cccpu = 0 (note 4) 15 50 a time measurement unit current i cctmu (note 4) 4.5 8 ma calculator current i cccpu 0.75 1.7 ma device current drain i cc3 tof_diff = 2 per second (3 hits), temperature = 1 per 30s 5.5 a i cc6 tof_diff = 2 per second (6 hits), temperature = 1 per 30s 7.0 flash erase current i flash 0.5 1 ma analog receiver analog input voltage (stop_up, stop_dn) v ana 10 700 2 x v cc x (3/8) mv p-p input offset step size v step 1 mv stop_up/stop_dn bias voltage v bias v cc x (3/8) v receiver sensitivity v ana stop hit detect level (note 5) 10 mv p-p time measurement unit measurement range t meas time of light 8 8000 s time measurement accuracy t acc differential time measurement 20 ps time measurement resolution t res 3.8 ps max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 4 electrical characteristics (continued) downloaded from: http:///
parameter symbol conditions min typ max units flash data retention d r t a = +25c 100 years flash endurance n flash t a = +25c 20k cycles block flash erase time t erase 50 ms ldo stabilization time t stable 135 s word write time t write 72 100 s transfer coniguration to flash command time t config 35 ms execution times power-on-reset time t reset reset to por int 275 s init command time t init command received when init bit set 2.5 ms case switch time t csw csw pin logic-high until cswi bit set 20 ns cal command time t cal command received when cal bit set 1.25 ms serial peripheral interface din to sck setup t dc 20 ns sck to din hold t cdh 2 20 ns sck to dout delay t cdd 5 20 ns sck low time t cl v cc 3.0v 25 4 ns v cc = 2.3v 50 30 sck high time t ch 25 4 ns sck frequency t clk v cc 3.0v 20 mhz v cc = 2.3v 10 ce to sck setup t cc 5 40 ns sck to ce hold t cch 20 ns ce inactive time t cwh 2 40 ns ce to dout high impedance t ccz 5 20 ns max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 5 (v cc = 2.3v to 3.6v, t a = -40 c to +85 c, unless otherwise noted. typical values are at v cc = 3.0v and t a = +25c.) (notes 2, 3) electrical characteristics (continued) downloaded from: http:///
note 2: all voltages are referenced to ground. current entering the device are specified as positive and currents exiting the device are negative. note 3: limits are 100% production tested at t a = +25c. limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. note 4: currents are specified as individual block currents. total current for a point in time can be calculated by taking the standby current and adding any block currents that are active at that time. note 5: receiver sensitivity includes performance degradation contributed by stop_up and stop_dn device pin input offset volt - age and common mode drift. figure 1. spi timing diagram read parameter symbol conditions min typ max units 32khz nominal frequency f 32k 32.768 khz 32khz frequency tolerance f 32k /f 32k t a = +25c -20 +20 ppm 32khz load capacitance c l32k 12.5 pf 32khz series resistance r s32k 70 k? 4mhz crystal nominal frequency f 4m 4.000 mhz 4mhz crystal frequency tolerance f 4m /f 4m t a = +25c -30 +30 ppm 4mhz crystal load capacitance c l4m 12.0 pf 4mhz crystal series resistance r s4m 120 ? 4mhz ceramic nominal frequency 4.000 mhz 4mhz ceramic frequency tolerance t a = +25c -0.5 +0.5 % 4mhz ceramic load capacitance 30 pf 4mhz ceramic series resistance 30 ? dout high impedance msb lsb t cdd t ccz ce sck din t cc t dc t cdh t cwh msb lsb figure 1 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 6 recommended external crystal characteristics timing diagrams downloaded from: http:///
(v cc = 3.3v and t a = +25c, unless otherwise noted.) figure 2. spi timing diagram write ce sck din t cc t dc t cdh t cl t ch t cch t cwh t r t f v ih v il msb dout high impedance t clk lsb figure 2 22 24 26 28 30 32 34 2.20 2.45 2.70 2.95 3.20 3.45 3.70 3.95 error (ns) v cc (v) absolute tof error vs. supply voltage toc01 0 10 20 30 40 50 60 0 5 10 15 20 average i cc (a) tof rate (tofdiff/s) average i cc vs. tof rate toc03 6 hits 3 hits 22 24 26 28 30 32 34 -10 15 40 65 90 error (ns) temperature ( o c) absolute tof error vs. temperature toc02 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 7 timing diagrams (continued) typical operating characteristics downloaded from: http:///
max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 8 average i cc vs. tof rate configuration settings control bit(s) 6-hit settings 3-hit settings value bit settings value bit settings calibration usage disabled cal_use = 0 disabled cal_use = 0 clock setting time 488s clk_2[2:0] = 000 488s clk_2[2:0] = 000 bias charge time 61s ct[1:0] = 00 61s ct[1:0] = 00 pulse launch frequency 1mhz dpl[3:0] = 0001 1mhz dpl[3:0] = 0001 pulse launch size 15 pl[7:0] = 00001111 15 pl[7:0] = 00001111 tof duty cycle 19.97ms tof_cyc[2:0] = 111 19.97ms tof_cyc[2:0] = 111 stop hits 6 stop[2:0] = 101 3 stop[2:0] = 101 t2 wave selector wave 2 t2wv[5:0] = 000110 wave 2 t2wv[5:0] = 000110 hit1 wave select 7 hit1wv[5:0] = 000111 7 hit1wv[5:0] = 000111 hit2 wave select 8 hit2wv[5:0] = 001000 8 hit2wv[5:0] = 001000 hit3 wave select 9 hit3wv[5:0] = 001001 9 hit3wv[5:0] = 001001 hit4 wave select 10 hit4wv[5:0] = 001010 n/a n/a hit5 wave select 11 hit5wv[5:0] = 001011 n/a n/a hit6 wave select 12 hit6wv[5:0] = 001100 n/a n/a temperature port number 4 tp[1:0] = 11 4 tp[1:0] = 11 preamble temperature cycle number 1 precyc[2:0] = 001 1 precyc[2:0] = 001 port cycle time 256s portcyc[1:0] = 01 256s portcyc[1:0] = 01 notes: this data is valid for the ceramic resonator. crystal oscillator startup add ~0.5a per tofdiff. since the tof cycle time is long, the 4mhz oscillator power up twice. downloaded from: http:///
pin name function 1, 22, 25, 28, 30 gnd device ground 2 bypass connect this pin to ground with a capacitor (100nf) to provide stability for the on-board low- dropout regulator that is used to supply the lash circuitry. the effective series resistance of this capacitor needs to be in the 1? to 2? range. 3, 6, 29 v cc main supply. typically sourced from a single lithium cell. 4 32kout cmos output. repeats the 32khz crystal oscillator frequency. 5 launch_dn cmos pulse output transmission in downstream direction of water flow 7 launch _up cmos pulse output transmission in upstream direction of water flow 8 cmp_out/up_dn cmos output. indicates the direction (upstream or downstream) of which the pulse launcher is currently launching pulses or the comparator output. 9 int active-low open-drain interrupt output. the pin is driven low when the device requires service from the host microprocessor. 10 ce active-low cmos digital input. serial peripheral interface chip enable input. tqfp (5mm x 5mm) top view 29 30 28 27 12 11 13 bypass 32kout launch_dn v cc launch_up 14 gnd 32kx0 tc t4 32kx1 t3 t2 1 + 2 gnd 4 5 6 7 23 24 22 20 19 18 v cc gnd rstdout din sck v cc gnd 3 21 31 10 x2 ce ep 32 9 x1 int stop_up 26 15 wdo stop_dn 25 16 csw cmp_out/up_dn t1 8 17 gnd max35103 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 9 pin description pin coniguration downloaded from: http:///
pin name function 11 sck cmos digital input. serial peripheral interface clock input. 12 din cmos digital input. serial peripheral interface data input. 13 dout cmos output. serial peripheral interface data output. 14 rst active-low cmos digital reset input 15 wdo active-low open-drain watchdog output 16 csw cmos digital input. case switch. active-high tamper detect input. 17 t1 open-drain probe 1 temperature measurement 18 t2 open-drain probe 2 temperature measurement 19 t3 open-drain probe 3 temperature measurement 20 t4 open-drain probe 4 temperature measurement 21 tc input/output temperature measurement capacitor connection 23 32kx0 connections for 32.768khz quartz crystal. an external cmos 32.768khz oscillator can also drive the max35103. in this coniguration, the 32kx1 pin is connected to the external oscillator signal and the 32kx0 pin is left unconnected. 24 32kx1 26 stop_dn downstream stop analog input. used for the signal that is received from the downstream transmission of a time-of-light measurement. 27 stop_up upstream stop analog input. used for the signal that is received from the upstream transmission of a time-of-light measurement. 31 x2 connections for 4mhz quartz crystal. a ceramic resonator can also be used. 32 x1 ep exposed pad. connect to gnd. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 10 pin description (continued) downloaded from: http:///
detailed description the max35103 is a time-to-digital converter with built-in amplifier and comparator targeted as a complete analog front-end solution for the ultrasonic heat meter and flow meter markets. with automatic differential time-of-flight (tof) measure - ment, this device makes for simplified computation of liq - uid flow. early edge detection ensures measurements are made with consistent wave patterns to greatly improve accuracy and eliminate erroneous measurements. built-in arithmetic logic unit provides tof difference measure - ments. a programmable receiver hit accumulator can be utilized to minimize the host microprocessor access. multihit capability with stop-enable windowing allows the device to be fine-tuned for the application. internal analog switches, an autozero amplifier/comparator, real- time clock (rtc), and programmable receiver sensitivity provide the analog interface and control for a minimal electrical bill of material solution. the rtc provides an event timing mode that is configurable and runs cyclic algorithms to minimize microprocessor interactivity and increase battery life. for temperature measurement, the max35103 supports up to four (4) 2-wire pt1000/500 platinum resistive tem - perature detectors (rtd). the max35103 offers an event timing mode that is con - figurable and runs cyclic algorithms to minimize micropro - cessor interactivity and increase battery life. the real-time clock (rtc) provides one programmable alarm and watchdog functionality. a simple opcode based 4-wire spi interface allows any microcontroller to effectively configure the device for its intended measurement. on-board user flash allows the max35103 to be nonvola - tile configurable and provides nonvolatile energy use data to be logged. time-to- digital converter programmable alu data and status registers state machine controller pulse launcher stop_up temperature measurement high speed and 32 khz oscillators w/real time clock x1 4-wire interface cmp_out/up_dn analog switching and bias control internal ldo max35103 stop_dn v cc v cc v cc bypass launch_up launch_dn gnd gnd gnd gnd gnd configuration registers 8 kbytes flash wdo csw int rst sck dout din ce x2 32kx1 32kout 32kx0 t1 t2 t3 t4 tc max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 11 block diagram downloaded from: http:///
time-of-flight (tof) measurement operations tof is measured by launching pulses from one piezo - electric transducer and receiving the pulses at a sec - ond transducer. the time between when the pulses are launched and received is defined as the time of flight. the max35103 contains the functionality required to create a string of pulses, sense the receiving pulse string, and measure the time of flight. the max35103 can measure two separate tofs, which are defined as tof up and tof down. a tof up measurement has pulses launched from the launch_up pin, which is connected to the downstream transducer. the ultrasonic pulse is received at the upstream transducer, which is connected to the stop_ up pin. a tof down measurement has pulses launched from the launch_dn pin, which is connected to the upstream transducer. the ultrasonic pulse is received at the downstream transducer, which is connected to the stop_dn pin. tof measurements can be initiated by sending either the tof_up, tof_dn, or tof_diff commands. tof_diff measurements can also be automatically executed using event timing mode commands evtmg1 or evtmg2. the steps involved in a single tof measurement are described here and shown in figure 3 . 1) the 4mhz oscillator and ldo is enabled with a pro - grammable settling delay time set by the clk_s[2:0] bits in calibration and control register. 2) a common-mode bias is enabled on the stop pin. this bias charge time is set by the ct[1:0] bits in the tof1 register. 3) once the bias charge time has expired, the pulse launcher drives the appropriate launch pin with a programmable sequence of pulses. the number of pulses launched is set by the pl[7:0] bits in the tof1 register. the frequency of these 50% duty- cycle pulses is set by the dpl[3:0] bits, also in the tof1 register. the start of these launch pulses gen - erates a start signal for the time-to-digital converter (tdc) and is considered to be time zero for the tof measurement. this is denoted by the start signal in the start/stop tdc timing ( figure 3 ). 4) after a programmable delay time set in tof measurement delay register, the comparator and hit detector at the appropriate stop pin are enabled. this delay allows the receiver to start recording hits when the received wave is expected, eliminating possible false hits from noise in the system. 5) stop hits are detected according to the programmed preferred edge of the acoustic signal sequence received at the stop pin according to the setting figure 3. time-of-flight sequence t 1 hit1 (2) bias applied to stop pin (3) launch pulses tof start (4) tof measurement delay (5) t 1 wave (6) compare return (7) t 2 wave hit2 hit3 hit4 hit5 hit6 (8) stop hits (9) calculatio ns tof command received (1) 4 mhz startup launch pinstop pin comparator offset comparator offset return time of flight measurements wave number 76543 1 2 0 8 9 10 11 tof measurement sequence stop hits selected = 6, stop polarity = positive edge avg = (hit[1:6]) 6 selected waves for hits: t2 = 4 hit1 = 6 hit2 = 7 hit3 = 8 hit4 = 9 hit5 = 10 hit6 = 11 (2) bias charge time (4) enable receiver (10) int asserted t 2 int pin figure 3 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 12 downloaded from: http:///
of the stop_pol bit in the tof1 register. the first stop hit is detected when a wave received at the stop pin exceeds the comparator offset voltage, which is set in the tof6 and tof7 registers. this first detected wave is wave number 0. the width of the waves pulse that exceeds the comparator offset voltage is measured and stored as the t1 time. 6) the offset of the comparator then automatically and immediately switches to the comparator return off - set, which is set in the tof6 and tof7 registers. 7) the t 2 wave is detected and the width of the t 2 pulse is measured and stored as the t 2 time. the wave number for the measurement of the t 2 wave width is set by the t2wv[5:0] bits in the tof2 register. 8) the preferred number of stop hits are then detect - ed. for each hit, the measured tof is stored in the appropriate hitxupint and hitxupfrac or hitxdnint and hitxdnfrac registers. the num - ber of hits to detect is set by the stop[2:0] bits in the tof2 register. the wave number to measure for each stop hit is set by the hitx wave select bits in the tof3, tof4, and tof5 registers. 9) after receiving all of the programmed hits, the max35103 calculates the average of the recorded hits and stores this to avgupint and avgupfrac or avgdnint and avgdnfrac. the ratio of t 1 /t 2 and t 2 /t ideal are calculated and stored in the wvrup or wvrdn register. 10) once all of the hit data, wave ratios, and averages become available in the results registers, the tof bit in the interrupt status register is set and the int pin is asserted (if enabled) and remains asserted until the interrupt status register is accessed by the microprocessor with a read register command. the computation of the total time of flight is performed by counting the number of full and fractional 4mhz clock cycles that elapsed between the launch start and a hit stop as shown in figure 4 . table 1. twos complement tof_diff conversion example figure 4.start/stop for time-to-digital timing register value converter value tof_diffint (hex) tof_difffrac (hex) tof diff value (ns) 7fff ffff 8,191,999.9962 001c 0403 7,003.9177 0001 00a1 250.6142 0000 0089 0.5226 0000 0001 0.0038 0000 0000 0.0000 ffff ffff -0.0038 ffff ffc0 -0.2441 fffe 1432 -480.2780 ff1c 8001 -56,874.9962 8000 0000 -8,192,000.0000 2 3 4 n 4 mhz clock start signal (internally generated when acoustic signal is transmitted) stop signal (generated upon acoustic signal reception) 1 integer tof results portion 1 lsb = t 4mhz fractional tof results portion 1 lsb = t 4mhz /(2^16) total time of flight = integer + fractional figure 4 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 13 downloaded from: http:///
each tof measurement result is comprised of an integer portion and a fractional portion. the integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maxi - mum size of the integer is 7fffh or (2 15 -1) x t 4mhz or ~ 8.19 ms. the maximum size of the fraction is: 16 4mhz 16 21 ffffh or t . or ~ 249.9961 ns. 2 ? early edge detect this early edge detect method of measuring the tof of acoustic waves is used for all of the tof commands including tof_up, tof_dn, and tof_diff. this meth - od allows the max35103 to automatically control the input offset voltage of the receiver comparator so that it can provide advanced measurement accuracy. the input offset of the receiver comparator can be programmed with a range +127 lsbs if triggering on a positive edge and -127 lsbs if triggering on a negative edge, with 1 lsb = v cc /3072. separate input offset settings are available for the upstream received signal and the downstream received signal. the input offset for the upstream received signal is programmed using the c_offsetup[6:0] bits in the tof6 register. the input offset for the down - stream received signal is programmed using the c_ offsetdn[6:0] bits in the tof7 register. once the first hit is detected, the time t1 equal to the width of the earliest detectable edge is measured. the input offset voltage is then automatically and immediately returned to a pre - programmed comparator offset value. this return offset value has a range of +127 lsbs to -128 lsbs in 1 lsb steps and is programmed into the c_offsetupr[7:0] bits in the tof6 register for the upstream received signal and programmed into the c_offsetdnr[7:0] bits in the tof7 register. this preprogrammed comparator offset return value is provided to allow for common-mode shifts that can be present in the received acoustic wave. the max35103 is now ready to measure the successive hits. the next selected wave that is measured is the t 2 wave. in the example in figure 5 , this is the 7th wave after the early edge detect wave. the selection of the t 2 wave is made with the t2wv[5:0] bits in the tof2 register. with reference to figure 5 , the ratio t 1 /t 2 is calculated and registered for the user. this ratio allows determination of abrupt changes in flow rate, received signal strength, par - tially filled tube detection, and empty tube. it also provides noise suppression to prevent erroneous edge detection. also, the ratio t 2 /t ideal is calculated and registered for the user. for this calculation, t ideal is1/2 the period of launched pulse. this ratio adds confirmation that the t 2 wave is a strong signal, which provides insight into the common mode offset of the received acoustic wave. figure 5. early edge detect received wave example wave number 7 6 5 4 3 1 2 0 8 9 10 11 programmable offset detect: 127mv in 1mv steps offset resets automatically to a preprogrammed value (127mv in 1mv steps) to detect subsequent zero crossings t 1 example: measure width of 7 th wave after early edge detect t 2 12 13 14 1 2 hit no.: 3 4 5 6 figure 5 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 14 downloaded from: http:///
tof error handling any of the tof measurements can result in an error. if an error occurs during the measurement, all of the associated registers report ffffh. if a tof_diff is being performed, the tof_diffint and tof_dif_frac registers report 7fffh and ffffh, respectively. the tof_diff_avg results registers do not include the error measurement. if the measurement error is caused by the time measurement exceeding the timeout set by the timout[2:0] bits in the tof2 register, then the to bit in the interrupt status register is set and the int pin asserts (if enabled). temperature measurement operations a temperature measurement is a time measurement of the rc circuit connected to the temperature port device pins t1 through t4 and tc. the tc device pin has a driver to charge the timing capacitor. the ports that are measured and the order in which the measurement is performed is selected with the tp[1:0] bits in the event timing 2 register. figure 6 depicts a 1000 platinum rtd with a 100nf npo cog 30ppm/c capacitor. it shows two dummy cycles with 4 temperature port evaluation measurements and 4 real temperature port measurements. this occurs when setting the tp[1:0] bits in the event timing 2 regis - ter to 11b. the dummy 1 and dummy 2 cycles represent preamble measurements that are intended to eliminate the dielec - tric absorption of the temperature measurement capaci - tor. these dummy cycles are executed using a rtd emulation resistor of 1000? internal to the max35103. this dummy path allows the dielectric absorption effects of the capacitor to be eliminated without causing any of the rtds to be unduly self-heated. the number of dummy measurements to be taken ranges from 0 to 7. this parameter is configured by setting the precyc[2:0] bits in the event timing 2 register. following the dummy cycles, an evaluation, txevaluate, is performed. this measurement allows the max35103 to maximize power efficiency by evaluating the tempera - ture of the rtds with a coarse measurement prior to a real measurement. the coarse measurement provides an approximation to the tdc converter. during the real measurement, the tdc can then optimize its measure - ment parameters to use power efficiently. these evaluate cycles are automatically inserted according to the order of ports selected with the of the temperature port bits. the time from the start of one ports temperature measure - ment to the next ports temperature measurement is set using with the portcyc[1:0] bits in the event timing 2 register. figure 6. temperature command execution cycle example dummy1 dummy2 t1 evaluate t3 evaluate t2 evaluate t4 evaluate t1 t3 t2 t4 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0 128 256 384 512 640 768 896 1,024 1,152 1,280 1,408 portcycle time (portcyc1-portcyc0) set to 00 128s driver to change tc-connected capacitor vtc volts (v) v tc time (s) figure 6 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 15 downloaded from: http:///
once all the temperature measurements are completed, the times measured for each port are reported in the corresponding txint and txfrac results registers. the te bit in the interrupt status register is also set and the int pin asserts (if enabled). actual temperature is determined by a ratiometric calcu - lation. if t1 and t2 are connected to platinum rtds and t3 and t4 are connected to the same reference resistor (as shown in the system diagram), then the ratio of t1/ t3 = r rtd1 /r ref and t2/t4 = r rtd2 /r ref . the ratios r rtd1 /r ref and r rtd2 /r ref can be determined by the host microprocessor and the temperature can be derived from a look-up table of temperature vs. resistance for each of the rtds utilizing interpolation of table entries if required. temperature error handling the temperature measurement unit can detect open and/ or short-circuit temperature probes. if the resultant tem - perature reading in less than 8s, then the max35103 writes a value of 0000h to the corresponding results registers to indicate a short-circuit temperature probe. if the measurement process does not discharge the tc pin below the threshold of the internal temperature compara - tor within 2s of the time set by the portcyc[1:0] bits in the event timing 2 register, then an open circuit tem - perature probe error is declared. the max35103 writes a value of ffffh to the corresponding results registers to indicate an open circuit temperature probe, the to bit in the interrupt status register is set, and the int pin asserts (if enabled). if the temperature measurement error is caused by any other problems, then the max35103 writes a value of ffffh to each of the temperature port results registers indicating that all of the temperature port mea - surements are invalid. event timing operation the event timing mode of operation is an advanced feature that allows the user to configure the max35103 to perform automatic measurement cycles. this allows the host microcontroller to enter low-power mode and only awaken upon assertion of the max35103 int pin (if enabled) when new measurement data is available. by using the tof_diff and temperature commands and configuring the appropriate tofx registers and the event timing registers, the event timing modes directs the max35103 to provide complete data for a sequence of measurements captured on a cyclical basis. there are three versions of the evtmg commands. evtmg2: performs automatic tof_diff measure - ments. the parameters and operation of the tof measurement are described in the time-of-flight (tof) measurement operations section. evtmg3: performs automatic temperature mea - surements. the parameters and operation of the temperature measurements are described in the temperature measurement operations section. evtmg1: performs automatic tof_diff and temperature measurements. continuous event timing operation the max35103 can be configured to continue run - ning event timing sequences at the completion of any sequence. if the et_cont bit in the calibration and control register is set, the currently executing evtmgx command continues to execute until a halt command is received by the max35103. if the et_cont bit is clear, automatic execution of event timing stops after the completion of a full sequence of measurements. continuous interrupt timing operation when operating in event timing mode, the int pin can be asserted (if enabled) either after each tof or tempera - ture measurement, or at the completion of the sequence of measurements. if the cont_int bit in the calibration and control register is set to a 1, then the int pin asserts (if enabled) at the completion of each tof or temperature command. this allows the host microcontroller to interro - gate the current event for accuracy of measurement. if the cont_int bit is set to a 0, then the int pin only asserts (if enabled) at the completion of a sequence of measure - ments. this allows the host microcontroller to remain in a low-power sleep mode and only wake-up upon the asser - tion of the int pin. error handling during event timing operation during execution of event timing modes, any error that occurs during a tof_diff or temperature measurement are handled as described in the corresponding error handling sections. calibration can be executed during event timing operation, if programmed to do so with the calibration configuration bits in the calibration and control register. if a calibration error occurs, this is handled as described in the error handling during calibration sec - tion. if any of these errors occur, the event timing opera - tion does not terminate, but continues operation. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 16 downloaded from: http:///
when making tof measurements in event timing mode, the max35103 provides additional data in the tof_ cycle_count/tof_range register that can be used to check the validity of all of the tof measurements. the tof_cycle_count is the number of valid error-free tof measurements that were recorded during an event timing sequence. if a tof error occurs, the tof_cycle_count register will not be incremented. the tof_range is the range of all valid tof measurements that were captured during a sequence. when making temperature measurements in event tim - ing mode, the max35103 provides additional data in the temp_cycle_count register. this count increments after every valid error-free temperature measurement and can be used to check the validity of all of the temperature measurements. also, the temperature average results registers, txavg, are not updated with the error measure - ment if a temperature error occurs during event timing operation. event timing mode 2 the evtmg2 command execution causes the tof_diff command to be executed automatically with program - mable repetition rates and programmable total counts as shown in figure 7 . during execution of the evtmg2 command, each tof_ diff command execution cycle causes the max35103 to compute a tof_diff measurement (avgup register minus avgdn register) as well as the running average of tof_diff measurements (toff_diff_avg register). the setting of the 8xs and tdf[3:0] bits in the event timing 1 register selects the rate at which tof_diff commands are executed. the setting of the tdm[4:0] bits in the event timing 1 register determines the num - ber of tof_diff measurements to be taken during the sequence. once all of the tof_diff measurements in the sequence are captured, the tof_diff_avg register contains the average of the differences of the resultant avgdn and avgup results register content of each tof_diff measurement. after the tof_diff_avg registers are updated, the tof_evtmg bit is set in the interrupt status register and the int pin asserts (if enabled). event timing mode 3 the evtmg3 command execution causes the tem - perature command to be executed automatically with programmable repetition rates and programmable total counts ( figure 9 ). during execution of the evtmg3 command, each temperature command execution cycle computes the running average of the measurement of each tempera - ture port. the results are provided in the tx_avgint and txavgfrac results registers. the setting of the 8xs and tmf[5:0] bits in the event timing 1 register selects the rate at which temperature commands are executed. the setting of the tmm[4:0] bits in the event timing 2 register determines the number of temperature measurements to be taken during the sequence. once all of the temperature measurements in the sequence are captured tx_avgint and txavgfrac results regis - ters contains the average of all the temperature measure - ments in the sequence. after these registers are updated, the temp_evtmg bit is set in the interrupt status register and the int pin asserts (if enabled). max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 17 downloaded from: http:///
figure 7. evtmg2 command figure 8. evtmg2 pseudo code evtmg2 command time of flight event end get configuration register data start timer is timer > = next 8xs/ tdf3-tdf0 increment? perform tof_diff command is timer > = next 8xs/ tdf3-tdf0 increment? compute running avg for tof_diff measurements and store at tof_diff_avg increment tof_cycle_count increment sequence cycle counter sequence cycle counter = tdm4- tdm0 ? set the tof_evtmg bit in the interrupt status register assert the int device pin is the et_cont bit set? start assert the int device pin assert the int device pin is the cont_int bit set? yes no no setting cont_int allows host microcontroller to interrogate max35103 after each measurement cycle setting et_cont bit causes the sequence to be continuous see error handling description yes no yes assert the int device pin noyes no yes figure 7 host microcontroller use of evtmg2 time of flight event program tof difference measurement frequency ( 8xs/ tdf3-tdf0) (eg. every 2 seconds) program number of tof difference measurements (tdm4-tdm0) to be taken (eg. 15) configure remaining max35103 registers including the cont_int and et_cont bits send the evtmg2 command wait for assertion of int device pin read interrupt status register is tof_evtmg bit set? read tof_diff_avg, tof_diff, avgup, avgdn, hitx registers for tof data is the et_cont bit set? no programmable in 0.5 second steps up to 8 seconds yes up to 32 measurements can be taken average of 15 tof difference measurements are ready for the host microcontroller other process no yes figure 8 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 18 downloaded from: http:///
figure 9. evtmg3 command figure 10. evtmg3 pseudo code evtmg3 command temperature event end get configuration register data start timer is timer > = next 8xs/ tdf5-tdf0 increment? perform temperature command temperature command error ? compute running avg for each measured port and store at t1_avg, t2_avg, t3_avg, t4_avg regisers increment temp_cycle_count results register increment sequence cycle counter sequence cycle counter = tdm4- tdm0 ? set the tof_evtmg bit in the interrupt status register assert the int device pin is the et_cont bit set? start set the te bit in the interrupt status register is the cont_int bit set? yes no no setting cont_int allows host microcontroller to interrogate max35103 after each measurement cycle setting et_cont bit causes the sequence to be continuous see error handling description yes no yes noyes no yes assert the int device pin temperature measurement repetition rate figure 9 host microcontroller use of evtmg3 temperature event program temperature difference measurement frequency ( 8xs/ tdf5-tdf0) (eg. every 15 seconds) program number of temperature difference measurements (tdm4-tdm0) to be taken (eg. 2) configure remaining max35103 registers including the cont_int and et_cont bits send the evtmg3 command wait for assertion of int device pin read interrupt status register is temp_evtmg bit set? read the txint, txfrac, tx_avgint, tx_avgfrac registers for temperature data is the et_cont bit set? no programmable in 1 second steps up to 64 seconds yes up to 32 measurements can be taken accumulation of two temperature measurements are ready for the host microcontroller other process no yes figure 10 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 19 downloaded from: http:///
event timing mode 1 the evtmg1 command execution causes the tof_diff command and the temperature command to be executed automatically with programmable repetition rates and pro - grammable total counts. in essence, both the evtmg2 and evtmg3 commands are simultaneously executed in a synchronous manner. setting up the tof measurements for automatic execu - tion in event timing mode 1 is identical to setting these up for execution with event timing mode 2. likewise, setting up the temperature measurements is identical to setting these up for execution using event timing mode 3. if the tof_dif command repetition rate and the tempera - ture command repetition rate cause both measurements to be required at the same time, the toff_dif command takes precedent. upon completion of the toff_diff command, the pending temperature command is execut - ed ( figure 12 ). once all of the tof_diff measurements in the sequence are complete, the tof_evtmg bit in the interrupt status register is set and the int pin asserts (if enabled). likewise, when all of the temperature measurements in the sequence are completed, the temp_evtmg bit in the interrupt status register is set and the int pin asserts (if enabled). it should be noted that depending upon the selected rates and number of cycles, the tof_diff and temperature measurements can complete their sequenc - es at different times. this causes the int pin to assert (if enabled) before both sequences are complete. calibration operation for more accurate results, calibration of the tdc can be performed. calibration allows the max35103 to per - form a calibration measurement that is based upon the 32.768khz crystal, which is the most accurate clock in the system. this calibration is used when a ceramic oscillator is used in place of an at-cut crystal for the 4mhz refer - ence. the max35103 automatically generates start and stop signals based upon edges of the 32.768khz clock. the number of 32.768khz clock periods that are used and then averaged are selected with the cal_ period[3:0] bits in the calibration and control register. figure 11. evtmg1 pseudo code host microcontroller use of evtmg1 time of flight / temperature event program tof difference measurement frequency ( 8xs/ tdf3-tdf0) (eg. every 2 seconds) program number of tof difference measurements (tdm4-tdm0) to be taken (eg. 2) configure remaining max35103 registers including the cont_int and et_cont bits send the evtmg3 command wait for assertion of int device pin read interrupt status register is temp_evtmg bit set? read the txint, txfrac, tx_avgint, tx_avgfrac registers for temperature data is the et_cont bit set? no programmable in 0.5 second steps up to 8 seconds yes up to 32 measurements can be taken average of two temperature measurements are ready for the host microcontroller other process no yes program temperature measurement frequency ( 8xs/ tmf5-tmf0) (eg. every 15 seconds) programmable in 1 second steps up to 64 seconds program # of temperature measurements (tmm4-tmm0) to be taken (eg. 2) up to 32 measurements can be taken is temp_evtmg bit set? average of 15 tof difference measurements are ready for the host microcontroller read tof_diff_avg, tof_diff, avgup, avgdn, hitx registers for tof data figure 11 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 20 downloaded from: http:///
figure 12. evtmg1 command yes no start timer start get configuration register data is timer > = next 8xs/tdf3-tdf0 increment? is timer > = next 8xs/tmf5Ctmf0 increment? is tof_pending set? is temperature_ pending set? perform temperature command temperature command error? compute running avg for each measured port and store at t1_avg, t2_avg, t3_avg, t4_avg regisers increment temperature cycle counter increment sequence cycle counter sequence cycle counter = tmm4- tmm0? set the temp_evtmg bit in the interrupt status register assert the int device pin end is the et_cont bit set? no assert the int device pin set the bit in the interrupt status register is the cont_int bit set? setting cont_int allows host microcontroll er to interrogate max35101 after each measurement cycle see error handling description perform tof_diff command tof_diff command error? compute running avg for tof_diff measurements and store at tof_diff_avg increment tof_cycle_count increment sequence cycle counter sequence cycle counter = tdm4C tdm0? set the tof_evtmg bit in the interrupt status register is temperature_pend ing set? assert the int device pin end is the et_cont bit set? no set the tof bit in the interrupt status register is temperature_ pending set? assert the int device pin is the cont_int bit set? see error handling description set temperature_ pending set tof_pending temperature measurement repetition rate setting cont_int allows host microcontroller to interrogate max35101 after each measurement cycle setting et_cont bit causes the sequence to be continuous clear temperature_ pending clear tof_pending tof_diff measurement repetition rate nono no yes no yes yes yes yes yes no no yes no yes yes yes yes no no evtmg1 time of flight / temperature command yes yes no no figure 12 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 21 downloaded from: http:///
the tdc measures the number of 4mhz clock pulses that occur during the 32.768khz pulses. the measured time of a 32.768khz clock pulse is reported in the calibrationint and calibrationfrac results registers. these results can then be used as a gain factor for calculating actual time- to-digital converter measurement if the cal_use bit in the event timing 2 register is set. following is a description of an example calibration. each tdc measurement is a 15-bit fixed-point integer value concatenated with a 16-bit fractional value binary repre - sentation of the number of t 4mhz periods that contribute to the time result, the actual period of t 4mhz needs to be known. if the cal_period[3:0] bits in the calibration and control register are set to 6, then 6 measurements of 32.768khz periods are measured by the tdc and then averaged. the expected measured value would be 30.5176s/250ns = 122.0703125 t 4mhz periods. assume that the 4mhz ceramic resonator is actually running at 4.02mhz. the tdc measurement unit would then mea - sure 30.5176s/248.7562ns = 122.6806641 t 4mhz peri - ods and this result would be returned in the calibration results register. for all tdc measurements, a gain value of 122.0703125/122.6806641 = 0.995024876 would then be applied. calibration is performed at the following events: when the calibration command is sent to the max35103. at the completion of this calibration, the cal bit in the interrupt status register and the int pin asserts (if enabled). during event timing operation, automatic calibrations can be performed before executing tof or tempera - ture measurements. this is selectable with the cal_ cfg[2:0] bits in the event timing 2 register. upon completion of an automatic calibration during event timing, the result is updated in the calibration results register, but the cal bit in the interrupt status register is not set and the int pin does not assert. error handling during calibration since calibration can be set to be automatic by configur - ing the cal_cfg[2:0] bits in the event timing 2 register, any errors that occur during the calibrate command stop the calibrationint and the calibrationfrac results regis - ters from being updated with new calibration coefficients. the results for the previous calibration data remain in these two registers and are used for scaling measured results. if the calibration error is caused by the internal calibration time measurement exceeding the time set by the timout[2:0] bits in the tof2 register, then the to bit in the interrupt status register is set and the int pin asserts (if enabled). rtc, alarm, watchdog, and tamper operation rtc operation the max35103 contains a real-time clock that is driven by a 32khz oscillator. the time and calendar information is obtained by reading the appropriate register words. the time and calendar are set or initialized by writing the appropriate register words. the contents of the time and calendar registers are in the binary-coded decimal (bcd) format. the clock/calendar provides hundredths of seconds, tenths of seconds, seconds, minutes, hours, day, date, month, and year information. the date at the end of the month is automatically adjusted for months with fewer than 31 days, including corrections for leap year valid up to 2100. the clock operates in either the 24-hour or 12-hour format with am/pm indicator. the max35103 real-time clock can be programmed for either 12-hour or 24-hour formats. if using the 24-hour format, bit6 (12 hr mode) of the mins_hrs register should be cleared to 0 and then bit5 represents the 20-hour indicator. if using the 12-hour format, bit6 should be set to 1 and bit5 represents am (if 0) or pm (if 1). the day-of-week register increments at midnight. values that correspond to the day of week are user defined but must be sequential (i.e., if 0 equals sunday, then 1 equals monday, and so on). illogical time and date entries result in undefined operation. alarm operation the max35103 real-time clock provides one program - mable alarm. the alarm is activated when either the am1 or am2 bits in the real-time clock register are set. based upon these bits, an alarm can occur when either the minutes and/or hours programmed in the alarm register match the current value in the mins_hrs register. when an alarm occurs, the af bit in the interrupt status register is set and the int device pin asserts (if enabled). for proper alarm function, programming of the alarm register hours bits must match the format (12- or 24-hour modes) used in the mins_hrs register. watchdog operation the max35103 also contains a watchdog alarm. the watchdog alarm counter register is a 16-bit bcd coun - ter that is programmable in 10ms intervals from 0.01s to 99.99s. a seed value may be written to this register repre - senting the start value for the countdown. the watchdog counter begins decrementing when the wd_en bit in the rtc register is set. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 22 downloaded from: http:///
an immediate read of watchdog alarm counter register returns the value just written. a read after a wait dura - tion causes a value seed minus wait to be returned. for example if the seed value was 28.01s, an immediate read returns 28.01. a read after a 4s returns 24.01s. the value read out for any read operation is a snapshot obtained at the instant of a serial read operation. a write operation to the watchdog alarm counter register causes a reload with the newly written seed. when the watchdog is enabled and a nonzero value is written into the watchdog alarm counter register, the watchdog alarm counter register decrements every 1/100s, until it reaches zero. at this point, the wf bit in the real-time clock register is set and the wdo pin asserts low for typically 250ms. at the end of the pulse, the wdo pin becomes high impedance. the wf flag remains set until cleared by writing wf to a logic 0 in the real-time clock register. if the wf bit is cleared while the wdo device pin is being held low, the wdo device pin is immediately released to its high- impedance state. writing a seed value of 0 does not cause the wf bit to assert. tamper detect operation the max35103 provides a single input that can be con - nected to a device case switch and used for tamper detection. upon detection of a case switch event the cswa in the control register and the cswi bit in the interrupt status register is set and the int device pin is asserted (if enabled).device interrupt operations the max35103 is designed to optimize the power effi - ciency of a flow metering application by allowing the host microprocessor to remain in a low-power sleep mode, instead of requiring the microprocessor to keep track of complex real-time events being performed by the max35103. upon completion of any command, the max35103 alerts the host microprocessor using the int pin. the assertion of the int pin can be used to awaken the host microprocessor from its low power mode. upon receiving an interrupt on the int pin, the host micropro - cessor should read the interrupt status register to deter - mine which tasks were completed. interrupt status register the interrupt status register contains flags for all for all commands and events that occur within the max35103. these flags are set when the event occurs or at the completion of the executing command. when the interrupt status register is read, all asserted bits are cleared. if another interrupt source has generated an interrupt dur - ing the read, these new flags assert following the read. int pin the int pin asserts when any of the bits in the interrupt status register are set. the int pin remains asserted until the interrupt status register is read by the user and all bits in this register are clear. in order for the int pin to oper - ate, it must first be enabled by setting the int_en bit in the calibration and control register. serial peripheral interface operation four pins are used for spi-compatible communications: dout (serial-data out), din (serial-data in), ce (chip enable), and sck (serial clock). din and dout are the serial data input and output pins for the devices, respectively. the ce input initiates and terminates a data transfer. sck synchronizes data movement between the master (microcontroller) and the slave (max35103). the sck, which is generated by the microcontroller, is active only when ce is low and during opcode and data transfer to any device on the spi bus. the inactive clock polarity is logic-low. din is latched on the falling edge of sck. there is one clock for each bit transferred. opcode bits are transferred in groups of eight, msb first. data bits are transferred in groups of sixteen, msb first. the serial peripheral interface is used to access the fea - tures and memory of the max35103 using an opcode/command structure. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 23 downloaded from: http:///
opcode commands table 2 shows the opcode/commands that are supported by the device. execution opcode commands the device supports several single byte opcode com - mands that cause the max35103 to execute various routines. all commands have the same spi protocol sequence as shown in figure 13 . once all 8 bits of the opcode are received by the max35103 and the ce device pin is deasserted, the max35103 begins execution of the specified command as described in that commands description. tof_up command (00h) the tof_up command generates a single tof measure - ment in the upstream direction. pulses launch from the launch_up pin and are received by the stop_up pin. the measured hit results are reported in the hitxupint and hitxupfrac registers, with the calculated average of all the measured hits being reported in the avgupint and avgupfrac register. the t 1 /t 2 and t 2 /tideal wave ratios are reported in the wvrup register. once all these results are stored, then the tof bit in the interrupt status register is set and the int pin asserts (if enabled). note: the tof_up command yields a result that is only of use when used in conjunction with the tof_dn com - mand. absolute tof measurements include circuit delays and cannot be considered accurate. table 2. opcode commands figure 13. execution opcode command protocol group command opcode field (hex) address field execution opcode commands tof_up 00h n/a tof_down 01h n/a tof_diff 02h n/a temperature 03h n/a reset 04h n/a initialize 05h n/a transfer coniguration to flash 06h n/a evtmg1 07h n/a evtmg2 08h n/a evtmg3 09h n/a halt 0ah n/a ldo_timed 0bh n/a ldo_on 0ch n/a ldo_off 0dh n/a calibrate 0eh n/a register opcode commands read register b0h thru ffh.each hex value represents the location of a single 16-bit register n/a write register 30h thru 43h.each hex value represents the location of a single 16-bit register n/a flash opcode commands read flash 90h 0000h - 1fffh8 kbytes even only write flash 10h 0000h - 1fffh8 kbytes even only block erase flash 13h 0000h - 1fffh ce sck din dout o o opcode msb lsb 8 bits high impedance execution opcode commands 0 1 2 3 4 5 7 6 figure 13 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 24 downloaded from: http:///
tof_down command (01h) the tof_down command generates a single tof measurement in the downstream direction. pulses launch from the launch_dn pin and are received by the stop_dn pin. the measured hit results are reported in the hitxdnint and hitxdnfrac registers, with the calcu - lated average of all the measured hits being reported in the avgdnint and avgdnfrac register. the t 1 /t 2 and t 2 / t ideal wave ratios are reported in the wvrdn register. once all these results are stored, then the tof bit in the interrupt status register is set and the int pin asserts (if enabled).note: the tof_down command yields a result that is only of use when used in conjunction with the tof_up command. absolute tof measurements include circuit delays and cannot be considered accurate. tof_diff command (02h) the tof_diff command performs back-to-back tof_ up and tof_dn measurements as required for a meter - ing application. the tof_up sequence is followed by the tof_dn sequence. the time between the start of the tof_up measurement and the start of the tof_dn mea - surement is set by the tof_cyc[2:0] bits in the tof2 register. upon completion of the tof_dn measurement, the results of avgup minus avgdn is computed and stored at the tof_diffint and tof_difffrac results register locations. once these results are stored, then the tof bit in the interrupt status register is set and the int pin asserts (if enabled). temperature command (03h) the temperature command initiates a temperature mea - surement sequence as described in the temperature measurement operations section. the characteristics the temperature measurement sequence depends upon the settings in the event timing 1 register, and event timing 2 register. once all the measurements are completed, the times measured for each port are reported in the corre - sponding txint and txfrac results registers. the te bit in the interrupt status register also is set and the int pin asserts (if enabled). reset command (04h) the reset command essentially performs the same func - tion as a power-on reset (por), and causes all of the configuration registers to be set to their prior programmed values stored in flash and all of the results registers and the interrupt status register to be cleared and set to zero. initialize command (05h) the initialize command must be executed after all config - uration of the device is complete and the transfer configu - ration to flash command has been executed. the initialize command starts the time-to-digital converter so that tof and temperature commands can be executed and also recalls all of the configuration register settings from flash. the max35103 sets the init bit in the interrupt status register and asserts the int device pin (if enabled) to tell the host microprocessor that the initialize command has completed and the next desired command can be sent to the max35103. transfer coniguration to flash command (06h) this command causes the configuration register map to be transferred to flash for nonvolatile (nv) storage. the max35103 automatically turns on the ldo for the duration of this transfer. upon device reset, the content of this flash restores the configuration registers. this flash is not part of the 8kb array, and is reserved solely for the transfer configuration to the flash command. the max35103 sets the flash bit in the interrupt status regis - ter and asserts the int device pin (if enabled) to tell the host microprocessor that the transfer configuration to the flash command has completed and the next command can be sent to the device. evtmg1 command (07h) the evtmg1 command initiates the event timing mode 1 advanced automatic measurement feature. this timing mode performs automatic tof_diff and temperature measurements as described in the event timing operation section. the duration of the automatic mea - surements depends upon the settings in the event timing 1 register, event timing 2 register, cont_int and et_ cont bits in the calibration and control register. evtmg2 command (08h) the evtmg2 command initiates the event timing mode 2 advanced automatic measurement feature. this timing mode performs automatic tof_diff measurements as described in the event timing operation section. the duration of the automatic measurements depends upon the settings in the event timing 1 register, cont_int and et_cont bits in the calibration and control register. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 25 downloaded from: http:///
evtmg3 command (09h) the evtmg3 command initiates the event timing mode 3 advanced automatic measurement feature. this timing mode performs automatic temperature measurements as described in the event timing operation section. the duration of the automatic measurements depends upon the settings in the event timing 1 register, event timing 2 register, cont_int and et_cont bits in the calibration and control register. halt command (0ah) the halt command is sent to the max35103 to stop any of the three evtmg1/2/3 commands. all register data content is frozen and the spi is then made available for access by the host microcontroller for commands, mem - ory access, and register access. the halt command takes time to execute. since the evtmgx commands are comprised of multiple tof_diff and temperature com - mands, the halt command causes the max35103 to evaluate its own state and complete the currently execut - ing tof_diff or temperature command. once the halt command has completed, all registers update and the max35103 sets the halt bit in the interrupt status regis - ter and then asserts the int device pin (if enabled). the host microprocessor reads the interrupt status register to determine the interrupt source. ldo_timed command (0bh) to access the flash memory, the internal low-dropout voltage regulator that powers the flash circuitry must be enabled. by sending the ldo_timed command to the max35103 prior to the desired flash access command (read, write, block erase), the internal regulator is enabled and powers the flash circuitry. the ldo bit is set in the interrupt status register and the int device pin asserts (if enabled) when the internal regulator has been turned on and is stable which takes approximately t stable . the host microprocessor, upon detection of the asserted int device pin, should read the interrupt status register ldo bit to determine that the internal regulator is stable and the flash is now ready to be accessed. the internal regu - lator remains enabled for a continuous period until the ce device pin is deasserted after any flash command (read, write, block erase). the ldo_timed command is used in place of the ldo_on command when a data access to the flash is required in a short burst. this minimizes spi access since the ldo_off command is not required to be sent to the max35103 to turn off the internal regulator. ldo_on command (0ch) to access the flash memory, the internal low-dropout voltage regulator that powers the flash circuitry must be enabled. by sending the ldo_on command to the max35103 prior to the desired flash access command (read, write, block erase), the internal regulator is enabled and powers the flash circuitry. the ldo bit is set in the interrupt status register and the int device pin asserts (if enabled) when the internal regulator has been turned on and is stable which takes approximately t stable . the host microprocessor, upon detection of the asserted int device pin, should read the interrupt status register ldo bit to determine that the internal regulator is stable and the flash is now ready to be accessed. the internal regulator remains enabled for a continuous period until the ldo_off command is received by the max35103. the ldo_on command is generally used when the host microprocessor needs to perform multiple-word writes to the max35103 since multiple-word writes require that the ce device pin be toggled after every word of data written. the ldo_on command prevents the ldo from automatically disabling itself after each transition of the ce device pin. ldo_off command (0dh) to access the flash memory, the internal low-dropout voltage regulator that powers the flash circuitry must be enabled. by sending the ldo_off command to the max35103, the internal regulator is disabled and the interrupt status register ldo bit is cleared. the int device pin is not asserted. the ldo_off command is used in conjunction with the ldo_on command. calibrate command (0eh) the calibrate command performs the calibration routine as described in the calibration operation section. when the calibrate command has completed the measurement, the calibration results register contains the measured 32khz period measuremnt value, the max35103 sets the calibration bit in the interrupt status register and then asserts the int device pin (if enabled). the host micro - processor reads the interrupt status register to determine the interrupt source and then read the calibration results register to be able to calculate the 4mhz ceramic oscilla - tor gain factor. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 26 downloaded from: http:///
register opcode commands to manipulate the register memory, there are two com - mands supported by the device: read register and write register. each register accessed with these commands is 16 bits in length. these commands are used to access all sections of the memory map including the rtc and watchdog registers, configuration registers, conversion results registers, and status registers. the conversion results registers and the interrupt status register of the status registers are all read only. read register command the opcode must be clocked into the din device pin before the dout device pin produces the register data. the spi protocol sequence is shown in figure 14 . the read register command can also be used to read consecutive addresses. in this case, the data bits are continuously delivered in sequence starting with the msb of the data register that is addressed in the opcode, and continues with each sck rising edge until the ce device pin is deasserted as shown in figure 15 . the address counter automatically increments. write register command this command applies to all writable registers. see the register memory map for more detail. the spi protocol sequence is shown in figure 16 . the write register command can also be used to write consecutive addresses. in this case, the data bits are con - tinuously received on the din device pin and bound for the initial starting address register that is addressed in the opcode. the address counter automatically increments after each 16 bits of data if the sck device pin is continu - ally clocked and the ce device pin remain asserted as shown in figure 17 . figure 14. read register opcode command protocol figure 14 ce sck din dout o o opcode d d d msb lsb 8 bits d d d d d d lsb msb high impedance high impedance read register command data 16 bits 0 1 2 3 4 5 10 9 8 7 6 20 23 22 21 19 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 27 downloaded from: http:///
figure 15. continuous read register opcode command protocol figure 16. write register opcode command protocol figure 15 ce sck din dout o o opcode d d d msb lsb 8 bits d d d d d d lsb msb high impedance continuous read register command data 16 bits 0 1 2 3 4 5 10 987 6 20 23 22 21 19 d d d d d d d lsb msb high impedance data 16 bits 25 26 24 39 41 43 42 40 27 figure 16 ce sck din dout o o opcode d d d msb lsb 8 bits d d d d d d lsb msb high impedance write register command data 16 bits 0 1 2 3 4 5 10 9 8 7 6 20 23 22 21 19 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 28 downloaded from: http:///
register memory mapthese registers are accessed by the read register com - mand and the write register command: x represents a reserved bit. following a reset, all configuration variables are recalled from flash. the factory-stored flash default value for all configuration registers except tof1 is 0000h. the factory-stored flash configuration for tof1 is 0010h. after a transfer to configuration to flash command, the new user configuration data is recalled from flash after a reset. the rtc register, results registers, interrupt status, and control registers are all 0000h following a reset. figure 17. continuous write register opcode command protocol figure 17 ce sck din dout o o opcode d d d msb lsb 8 bits d d d d d d lsb msb high impedance continuous write register command data 16 bits 0 1 2 3 4 5 10 9 8 7 6 20 23 22 21 19 25 39 27 26 24 d d d d d d d lsb msb data 16 bits max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 29 downloaded from: http:///
table 3. register memory map read opcode write opcode name bits[15:8] bits[7:0] rtc and watchdog registers b0h 30h seconds tenths of seconds hundredth seconds 10 seconds seconds b1h 31h mins_hrs 10-minutes minutes 0 12hr 20hr/am/pm 10hr hours b2h 32h day_date day 10-date date b3h 33h month_ year 10-month month 10-year year b4h 34h watchdog alarm counter tenths of seconds hundredths of seconds 10 seconds seconds b5h 35h alarm 10-minutes minutes 0 12hr 20hr/am/pm 10hr alarm hours configuration registers these registers are restored from lash memory upon device reset. these registers are written to lash memory upon the issuance of the transfer coniguration to lash command. b6h 36h reserved b7h 37h reserved b8h 38h tof1 pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 dpl3 dpl2 dpl1 dpl0 stop _pol x ct1 ct0 b9h 39h tof2 stop 2 stop 1 stop 0 t2wv 5 t2wv 4 t2wv 3 t2wv 2 t2wv 1 t2wv0 tof_ cyc2 tof_ cyc1 tof_ cyc0 en_u p_dn tim out2 tim out1 tim out0 bah 3ah tof3 x x hit1 wv5 hit1 wv4 hit1 wv3 hit1 wv2 hit1 wv1 hit1 wv0 x x hit2 wv5 hit2 wv4 hit2 wv3 hit2 wv2 hit2 wv1 hit2 wv0 bbh 3bh tof4 x x hit3 wv5 hit3 wv4 hit3 wv3 hit3 wv2 hit3 wv1 hit3 wv0 x x hit4 wv5 hit4 wv4 hit4 wv3 hit4 wv2 hit4 wv1 hit4 wv0 bch 3ch tof5 x x hit5 wv5 hit5 wv4 hit5 wv3 hit5 wv2 hit5 wv1 hit5 wv0 x x hit6 wv5 hit6 wv4 hit6 wv3 hit6 wv2 hit6 wv1 hit6 wv0 bdh 3dh tof6 c_of fset rup7 c_of fset rup6 c_of fset rup5 c_of fset rup4 c_of fset rup3 c_of fset rup2 c_of fset rup1 c_of fset rup0 c_of fset up7 c_of fset up6 c_of fset up5 c_of fset up4 c_of fset up3 c_of fset up2 c_of fset up1 c_of fset up0 beh 3eh tof7 c_of fset rdn7 c_of fset rdn6 c_of fset rdn5 c_of fset rdn4 c_of fset rdn3 c_of fset rdn2 c_of fset rdn1 c_of fset rdn0 c_of fset dn7 c_of fset dn6 c_of fset dn5 c_of fset dn4 c_of fset dn3 c_of fset dn2 c_of fset dn1 c_of fset dn0 bfh 3fh event timing 1 tdf3 tdf2 tdf1 tdf0 tdm4 tdm3 tdm2 tdm1 tdm0 tmf5 tmf4 tmf3 tmf2 tmf1 tmf0 8xs max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 30 downloaded from: http:///
table 3. register memory map (continued) read opcode write opcode name bits[15:8] bits[7:0] c0h 40h event timing 2 tmm4 tmm3 tmm2 tmm1 tmm0 cal_ use cal_ auto cal_ cfg1 cal_ cfg0 tp1 tp0 prec yc2 prec yc1 prec yc0 port cyc1 port cyc0 c1h 41h tof measure- ment delay dly15 dly14 ly13 dly12 dly11 dly10 dly9 dly8 dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 c2h 42h calibration and control x x x x cmp_ en cmp_ sel int_ en et_ cont cont _int clk_ s2 clk_ s1 clk_ s0 cal_p eriod3 cal_p eriod2 cal_p eriod1 cal_p eriod0 c3h 43h real-time clock x x x x x x x x x 32k_ bp 32k_ en eosc am2 am1 wf wd_ en conversion results registers c4h read only wvrup c5h read only hit1upint c6h read only hit1upfrac c7h read only hit2upint c8h read only hit2upfrac c9h read only hit3upint cah read only hit3upfrac cbh read only hit4upint cch read only hit4upfrac cdh read only hit5upint ceh read only hit5upfrac cfh read only hit6upint max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 31 downloaded from: http:///
table 3. register memory map (continued) read opcode write opcode name bits[15:8] bits[7:0] d0h read only hit6upfrac d1h read only avgupint d2h read only avgupfrac d3h read only wvrdn d4h read only hit1dnint d5h read only hit1dnfrac d6h read only hit2dnint d7h read only hit2dnfrac d8h read only hit3dnint d9h read only hit3dnfrac dah read only hit4dnint dbh read only hit4dnfrac dch read only hit5dnint ddh read only hit5dnfrac deh read only hit6dnint dfh read only hit6dnfrac e0h read only avgdnint max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 32 downloaded from: http:///
table 3. register memory map (continued) read opcode write opcode name bits[15:8] bits[7:0] e1h read only avgdnfrac e2h read only tof_diffint e3h read only tof_difffrac e4h read only tof_cycle_count e5h read only tof_diff_avgint e6h read only tof_diff_avgfrac e7h read only t1int e8h read only t1frac e9h read only t2int eah read only t2frac ebh read only t3int ech read only t3frac edh read only t4int eeh read only t4frac efh read only temp_cycle_count f0h read only t1_avgint f1h read only t1_avgfrac max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 33 downloaded from: http:///
table 3. register memory map (continued) read opcode write opcode name bits[15:8] bits[7:0] f2h read only t2_avgint f3h read only t2_avgfrac f4h read only t3_avgint f5h read only t3_avgfrac f6h read only t4_avgint f7h read only t4_avgfrac f8h read only calibrationint f9h read only calibrationfrac fah read only reserved fbh read only reserved fch read only reserved fdh read only reserved status registers feh read only interrupt status to af x tof te ldo tof_ evtmg temp_ evtmg flash cal halt cswi init por x x ffh read only control x x x x x x afa cswa x x x x x x x x max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 34 downloaded from: http:///
table 4. rtc seconds register rtc and watchdog register descriptions table 5. rtc mins_hrs register write opcode 30h read opcode b0h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name tenths of seconds hundredths of seconds bit 7 6 5 4 3 2 1 0 name 0 10 seconds seconds bit name description 15:12 tenths of seconds range 0 to 9 11:8 hundredths of seconds range 0 to 9 7 0 this bit always returns 0 6:4 10 second range 0 to 5 3:0 seconds range 0 to 9 write opcode 31h read opcode b1h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name 0 10 minutes minutes bit 7 6 5 4 3 2 1 0 name 0 12/24 20hr/am/pm 10hr hours bit name description 15 0 this bit always returns 0 14:12 10 minutes range 0 to 5 11:8 minutes range 0 to 9 7 0 this bit always returns 0 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 35 downloaded from: http:///
table 5. rtc mins_hrs register (continued) table 6. rtc day_date register bit name description 6 12/24 1 = 12-hour mode0 = 24-hour mode 5 20hr/am/pm in 12-hour mode1 = pm 0 = am in 24-hour mode: 20-hour digit 4 10hr range 0 to 1 3:0 hours range 0 to 9 write opcode 32h read opcode b2h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name 0 0 0 0 0 day bit 7 6 5 4 3 2 1 0 name 0 0 10 date date bit name description 15:11 0 these bits always return 0 10:8 day range 0 to 7 7:6 0 these bits always return 0 5:4 10 date range 0 to 3 3:0 date range 0 to 9 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 36 downloaded from: http:///
table 7. rtc month_year register table 8. watchdog alarm counter register write opcode 33h read opcode b3h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name 0 0 0 10 month month bit 7 6 5 4 3 2 1 0 name 10 year year bit name description 15:13 0 these bits always return 0 12 10 month range 0 to 1 11:8 month range 0 to 9 7:4 10 year range 0 to 9 3:0 year range 0 to 9 write opcode 34h read opcode b4h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name tenths of seconds hundredths of seconds bit 7 6 5 4 3 2 1 0 name 10 seconds seconds bit name description 15:12 tenths of seconds range 0 to 9 11:8 hundredths of seconds range 0 to 9 7:4 10 second range 0 to 9 3:0 seconds range 0 to 9 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 37 downloaded from: http:///
table 9. alarm register table 10. tof1 register coniguration register descriptions write opcode 35h read opcode b5h flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name x 10 minutes minutes bit 7 6 5 4 3 2 1 0 name x 12/24 20hr/am/pm 10hr hours bit name description 15 x reserved 14:12 10 minutes range 0 to 5 11:8 minutes range 0 to 9 7 x reserved 6 12/24 1 = 12-hour mode0 = 24-hour mode 5 20hr/am/pm in 12-hour mode1 = pm 0 = am in 24-hour mode: 20-hour digit 4 10hr range 0 to 1 3:0 hours range 0 to 9 write opcode 38h read opcode b8h flash stored yes factory-stored flash value 0010h bit 15 14 13 12 11 10 9 8 name pl7 pl6 pl5 pl4 pl3 pl2 pl1 pl0 bit 7 6 5 4 3 2 1 0 name dpl3 dpl2 dpl1 dpl0 stop_pol x ct1 ct0 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 38 downloaded from: http:///
table 10. tof1 register (continued) bit name description 15:8 pl[7:0] pulse launcher size : this is a hex value that deines the number of pulses that will be launched from the pulse launcher during transmission. the range of this hex value is 00h to ffh. when pl[7:0] is set to 00h, the pulse launcher is disabled. up to 127 pulses can be launched. when pl7 is set, the pulse count is clamped at 127. 7:4 dpl[3:0] pulse launch divider: this is a hex value that deines the divider ratio of the internal clock signal used to drive the pulse launch signal. the 4mhz external reference oscillator is used as the source for the internal clock reference. the internal reference clock is irst divided by 2 to produce a 2mh z clock. the range of this hex value is 1h to fh, resulting in a range of division from 2 to 16 of the 2mhz clock. a value of 0h is not supported and should not be programmed pulse launch frequency = 2mhz/(1+dpl[3:0]) dpl[3:0] pulse launch frequency 0000b reserved 0001b 1mhz 0002b 666khz . . 1110b 133.33khz 1111b 125khz 3 stop_pol stop polarity: this bit deines the edge sensitivity of the stop_up and stop_dn channel. the signal received on the stop_up and stop_dn device pins will generate a stop condition for the internal tdc time count on the rising slope of this signal if this bit is set to 0. the signal received on the stop_up and stop_dn device pins will generate a stop condition for the internal tdc time count on the falling slope of this signal if this bit is set to 1. 2 x reserved 1:0 ct[1:0] bias charge time: this is the time allotted for charging the external bias network on the stop pins to produce common mode biasing for the analog receiver/comparator. it is based upon the 32.768 khz crystal: ct1 ct2 description 32khz clock cycles (decimal) typical time (s) 0 0 2 61 0 1 4 122 1 0 8 244 1 1 16 488 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 39 downloaded from: http:///
table 11. tof2 register write opcode 39h read opcode b9h flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name stop2 stop1 stop0 t2wv5 t2wv4 t2wv3 t2wv2 t2wv1 bit 7 6 5 4 3 2 1 0 name t2wv0 tof_cyc2 tof_cyc1 tof_cyc0 x timout2 timout1 timout0 bit name description 15:13 stop[2:0] stop hits: these bits set the number of stop hits to be expected and measured. stop2 stop1 stop0 description 0 0 0 1 hit 0 0 1 2 hits 0 1 0 3 hits 0 1 1 4 hits 1 0 0 5 hits 1 0 1 6 hits 1 1 0 6 hits 1 1 1 6 hits 12:7 t2wv[5:0] wave selector for t 2 : these bits determine the wave number for which t 2 is measured. to ensure measurement accuracy, the irst wave measurable after the early edge detect is wave 2. waves are numbered as depicted in figure 5. t2wv[5:0] (decimal) description 0 through 2 wave 2 3 wave 3 4 wave 4 5 through 63 wave 5 through 63 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 40 downloaded from: http:///
table 11. tof2 register (continued) 6:4 tof_cyc[2:0] tof duty cycle: these bits determine the time delay between successive executions of tof measurements. it is the start-to-start time of automatic execution of the tof_up and the tof_dn and is applicable only for the tof_diff command. it is based upon the 32.768khz crystal. if the actual tof of the acoustic path exceeds the programmed start-to-start time in this setting, then the tof duty cycle performs as if the bit setting is 000b. tof_cyc[2:0] description 32khz clock cycles (decimal) typical time 4mhz on between tof_ up and tof_down 000b 0 0s yes 001b 4 122s yes 010b 8 244s yes 011b 16 488s yes 100b 24 732s yes 101b 32 976s yes 110b 546 16.65ms no 111b 655 19.97ms no 3 x reserved 2:0 timout[2:0] timeout: these bits force a timeout in the time-to-digital measurement block. if the hit required to measure t 1 , t 2 , or hit1 through hit6 of the received signal does not occur in this time, the to bit in the interrupt status register is set and the int pin is asserted (if enabled). additionally, any of the conversion results registers read ffffh if the data for that register is invalid. timout2 timout1 timout0 description (s) 0 0 0 128 0 0 1 256 0 1 0 512 0 1 1 1024 1 0 0 2048 1 0 1 4096 1 1 0 8192 1 1 1 16384 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 41 downloaded from: http:///
table 12. tof3 register write opcode 3ah read opcode bah flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name x x hit1wv5 hit1wv4 hit1wv3 hit1wv2 hit1wv1 hit1wv0 bit 7 6 5 4 3 2 1 0 name x x hit2wv5 hit2wv4 hit2wv3 hit2wv2 hit2wv1 hit2wv0 bit name description 15:14 x reserved 13:8 hit1wv[5:0] hit1 wave select: these bits select the wave number for which the hit1 stop time is measured. wave numbers are depicted in figure 5. the hit1 wave select value must be at least 1 greater than the wave selected for t 2 , which is conigured in the tof2 register. for example, if the wave selector for t 2 is set to wave number 7, then the hit1 wave select must be set to delect wave number 8 or greater. the earliest wave for which hit1 can be measured is wave 3. hit1wv[5:0] (decimal) description 0 through 3 wave 3 4 wave 4 5 wave 5 6 through 63 wave 6 through 63 7:6 x reserved 5:0 hit2wv[5:0] hit2 wave select: these bits select the wave number for which the hit2 stop time is measured. wave numbers are depicted in figure 5. the hit2 wave select value must be at least 1 greater than the hit1 wave select value. for example, if hit1 wave select value is set to measure wave number 9, then the hit2 wave select must be set to detect wave number 10 or greater. the earliest wave for which hit2 can be measured is wave 4. hit2wv[5:0] (decimal) description 0 through 4 wave 4 5 wave 5 6 wave 6 7 through 63 wave 7 through 63 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 42 downloaded from: http:///
table 13. tof4 register write opcode 3bh read opcode bbh flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name x x hit3wv5 hit3wv4 hit3wv3 hit3wv2 hit3wv1 hit3wv0 bit 7 6 5 4 3 2 1 0 name x x hit4wv5 hit4wv4 hit4wv3 hit4wv2 hit4wv1 hit4wv0 bit name description 15:14 x reserved 13:8 hit3wv[5:0] hit3 wave select: these bits select the wave number for which the hit3 stop time is measured. wave numbers are depicted in figure 5. the hit3 wave select value must be at least 1 greater than the hit2 wave select value. for example, if the hit2 wave select value is set to measure wave number 10, then the hit3 wave select must be set to detect wave number 11 or greater. the earliest wave for which hit3 can be measured is wave 5. hit3wv[5:0] (decimal) description 0 through 5 wave 5 6 wave 6 7 wave 7 8 through 63 wave 8 through 63 7:6 x reserved 5:0 hit4wv[5:0] hit4 wave select: these bits select the wave number for which the hit4 stop time is measured. wave numbers are depicted in figure 5. the hit4 wave select value must be at least 1 greater than the hit3 wave select value. for example, if the hit3 wave select value is set to measure wave number 11, then the hit4 wave select must be set to detect wave number 12 or greater. the earliest wave for which hit4 can be measured is wave 6. hit4wv[5:0] (decimal) description 0 through 6 wave 6 7 wave 7 8 wave 8 9 through 63 wave 9 through 63 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 43 downloaded from: http:///
table 14. tof5 register write opcode 3ch read opcode bch flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name x x hit5wv5 hit5wv4 hit5wv3 hit5wv2 hit5wv1 hit5wv0 bit 7 6 5 4 3 2 1 0 name x x hit6wv5 hit6wv4 hit6wv3 hit6wv2 hit6wv1 hit6wv0 bit name description 15:14 x reserved 13:8 hit5wv[5:0] hit5 wave select : these bits select the wave number for which the hit5 stop time is measured. wave numbers are depicted in figure 5. the hit5 wave select value must be at least 1 greater than the hit4 wave select value. for example, if the hit4 wave select value is set to measure wave number 12, then the hit5 wave select must be set to detect wave number 13 or greater. the earliest wave for which hit5 can be measured is wave 7. hit5wv[5:0] (decimal) description 0 through 7 wave 7 8 wave 8 9 wave 9 10 through 63 wave 10 through 63 7:6 x reserved 5:0 hit6wv[5:0] hit6 wave select: these bits select the wave number for which the hit6 stop time is measured. wave numbers are depicted in figure 5. hit6 wave select value must at least 1 greater than the hit5 wave select value. for example, if hit5 wave select value is set to measure wave number 13, then the hit6 wave select must be set to detect wave number 14 or greater. the earliest wave for which hit6 can be measured is wave 8. hit6wv[5:0] (decimal) description 0 through 8 wave 8 9 wave 9 10 wave 10 11 through 63 wave 11 through 63 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 44 downloaded from: http:///
table 15. tof6 register write opcode 3dh read opcode bdh flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name c_offset upr7 c_offset upr6 c_offset upr5 c_offset upr4 c_offset upr3 c_offset upr2 c_offset upr1 c_offset upr0 bit 7 6 5 4 3 2 1 0 name x c_offset up6 c_offset up5 c_offset up4 c_offset up3 c_offset up2 c_offset up1 c_offset up0 bit name description 15:8 c_offsetupr [7:0] comparator return offset upstream: when the device is measuring the t 2 wave, the programmed receive comparator offset is returned to a common-mode voltage automatically after the early edge, t 1 , is detected. the actual offset return voltage is dependent upon and scales with the voltage present at the v cc pins. the following formula deines the comparator return offset voltage setting, where c_offsetupr is a twos-complement number: cc cc (1152+c_o comparator re ffsetup turn offset voltage v 3072 v where 1 r lsb 3072 ) = = c_offsetupr[7:0] offset (lsbs) 7fh through 01h 127 through 1 00h 0 80h through ffh -128 through -1 7 x reserved max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 45 downloaded from: http:///
table 16. tof7 register table 15. tof6 register (continued) write opcode 3eh read opcode beh flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name c_offset dnr7 c_offset dnr6 c_offset dnr5 c_offset dnr4 c_offset dnr3 c_offset dnr2 c_offset dnr1 c_offset dnr0 bit 7 6 5 4 3 2 1 0 name x c_offset dn6 c_offset dn5 c_offset dn4 c_offset dn3 c_offset dn2 c_offset dn1 c_offset dn0 bit name description 6:0 c_offsetup [6:0] comparator offset upstream: these bits deine an initial selected receive comparator offset voltage for the analog receiver comparator front-end. this comparator offset is used to detect the early edge wave, t 1 . the actual common-mode voltage is dependent upon and scales with the voltage present at the v cc pins. when the stop_pol bit in the tof1 register is set to zero indicating a rising edge detection of the zero crossing of the received acoustic wave, then the comparator offset is a positive value. when the stop_pol bit in the tof1 register is set to one indicating a falling edge detection of the zero crossing of the received acoustic wave, then the comparator offset is a negative value. the following formulas deine the comparator offset voltage setting offsetup cc offsetup cc cc c stop_pol 0 comparator offset voltag e v 3072 c stop_pol (1152 + ) (11 1 comparato 51- ) r offset voltage v 3072 v where 1 lsb 3072 = = = = = c_offsetup[6:0] offset (lsbs) 00h through 7fh 0 through 127 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 46 downloaded from: http:///
table 16. tof7 register (continued) bit name description 15:8 c_offsetdnr [7:0] comparator return offset downstream: when the max35103 is measuring the t 2 wave, the programmed receive comparator offset is returned to a common-mode voltage automatically after the early edge, t 1 , is detected. the actual offset return voltage is dependent upon and scales with the voltage present at the v cc pins. the following formula deines the comparator return offset voltage setting, where c_offsetdnr is a twos-complement number: cc cc (1152+c_o comparator re ffsetdn turn offset voltage v 3072 v where 1 r lsb 3072 ) = = c_offsetdnr[7:0] offset (lsbs) 7fh through 01h 127 through 1 00h 0 80h through ffh -128 through -1 7 x reserved 6:0 c_offsetdn [6:0] comparator offset downstream: these bits deine an initial selected receive comparator offset voltage for the analog receiver comparator front-end. this comparator offset is used to detect the early edge wave, t 1 . the actual common-mode voltage is dependent upon and scales with the voltage present at the v cc pins. when the stop_pol bit in the tof1 register is set to zero indicating a rising edge detection of the zero crossing of the received acoustic wave, then the comparator offset is a positive value. when the stop_pol bit in the tof1 register is set to one indicating a falling edge detection of the zero crossing of the received acoustic wave, then the comparator offset is a negative value. the following formulas deine the comparator offset voltage setting: offsetdn cc offsetdn cc cc c stop_pol 0 comparator offset voltag e v 3072 c stop_pol (1152 + ) (11 1 comparato 51- ) r offset voltage v 3072 v where 1 lsb 3072 = = = = = c_offsetdn[6:0] offset (lsbs) 00h through 7fh 0 through 127 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 47 downloaded from: http:///
table 17. event timing 1 register write opcode 3fh read opcode bfh flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name tdf3 tdf2 tdf1 tdf0 tdm4 tdm3 tdm2 tdm1 bit 7 6 5 4 3 2 1 0 name tdm0 tmf5 tmf4 tmf3 tmf2 tmf1 tmf0 8xs bit name description 15:12 tdf[3:0] tof difference measurement frequency: along with 8xs, these bits deine the rate at which tof_diff measurements are executed when the evtmg1 or evtmg2 command is executed. rate = 0.5s + (tdf[3:0] x 0.5s) tdf[3:0] (decimal) rate (8xs = 0) rate (8xs = 1) 0 0.5s 0.0625s 1 1.0s 0.1250s . . . 14 7.5s 0.9476s 15 8.0s 1.0000s 11:7 tdm[4:0] tof difference measurements: these bits deine the number of tof_diff measurement cycles to be executed when the evtmg1 or evtmg2 command is executed. cycles = 1+ tdm[4:0] tdm[4:0] (decimal) cycles 0 1 1 2 . . 30 31 31 32 6:1 tmf[5:0] temperature measurement frequency: along with 8xs bits deine the time delay between temperature cycle measurements. it is a start-cycle to start-cycle time duration at which temperature measurement cycles are executed when the evtmg1 or evtmg3 command is executed. rate = 1.0s + (tmf[3:0] x 1.0s) tmf[5:0] (decimal) rate (8xs = 0) rate (8xs = 1) 0 1s 0.125s 1 2s 0.250s . . . 62 63s 7.875s 63 64s 0 8xs 8x sample rate: when set to 1, the sample rate of tof difference and temperature measurements is increased by a factor of 8 in an event timing mode. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 48 downloaded from: http:///
table 18. event timing 2 register write opcode 40h read opcode c0h flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name tmm4 tmm3 tmm2 tmm1 tmm0 cal_use cal_cfg2 cal_cfg1 bit 7 6 5 4 3 2 1 0 name cal_cfg0 tp1 tp0 precyc2 precyc1 precyc0 portcyc1 portcyc0 bit name description 15:11 tmm[4:0] temperature measurements: these bits deine the number of temperature measurement cycles to be executed when the evtmg1 or evtmg3 command is executed. cycles = 1+ tmm[4:0] tmm[4:0] (decimal) cycles 0 1 1 2 . . 30 31 31 32 10 cal_use calibration usage: this bit, when set, causes the max35103 to use the calibration data in the calibrationint and calibrationfrac registers during measurement, averaging and accumulation of data while executing the evtmg commands. all time measurements are scaled using the calibration factors as described by the calibrate command. 9:7 cal_cfg[2:0] calibration coniguration: these bits deine the point in the evtmgx cycle/sequence where the automatic calibration command is executed. cal_cfg[2:0] description during evtmgx sequences, automatic execution of the calibrate command occurs at: 000b through 011b autocalibration disabled 100b the beginning of each tof_diff cycle the beginning of each temperature cycle 101b the beginning of each tof_diff cycle the beginning of each temperature sequence 110b the beginning of each tof_diff sequence the beginning of each temperature cycle 111b the beginning of each tof_diff sequence the beginning of each temperature sequence max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 49 downloaded from: http:///
table 18. event timing 2 register (continued) bit name description 6:5 tp[1:0] temperature port: these bits set the number of temperature ports to stimulate during a temperature measurement sequence and the sequence in which the temperature ports are stimulated. tp1 tp0 description 0 0 measure ports t1 and t3 0 1 measure ports t2 and t4 1 0 measure ports t1, t3, and t2 1 1 measure ports t1, t3, t2, and t4 4:2 precyc[2:0] preamble temperature cycle: these 3 bits are used to set the number of cycles to use as preamble for reducing dielectric absorption of the temperature measurement capacitor. each cycle comprises one temperature measurement sequence as deined by the tp[1:0] bits. precyc2 precyc1 precyc0 description 0 0 0 0 dummy cycle 0 0 1 1 dummy cycles 0 1 0 2 dummy cycles 0 1 1 3 dummy cycles 1 0 0 4 dummy cycles 1 0 1 5 dummy cycles 1 1 0 6 dummy cycles 1 1 1 7 dummy cycles 1:0 portcyc[1:0] port cycle time: these two bits deine the time interval between successive individual temperature port measurements. it is a start-to-start time. these bits also deine the timeout function of the temperature measurement ports. see the temperature operation section for timeout details. portcyc1 portcyc0 description (s) 0 0 128 0 1 256 1 0 384 1 1 512 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 50 downloaded from: http:///
table 19. tof measurement delay register table 20. calibration and control register write opcode 41h read opcode c1h flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name dly15 dly14 dly13 dly12 dly11 dly10 dly9 dly8 bit 7 6 5 4 3 2 1 0 name dly7 dly6 dly5 dly4 dly3 dly2 dly1 dly0 bit name description 15:0 dly[15:0] this is hexadecimal value ranging from 0000h to ffffh (decimal 0 to 65535). it is a multiple of the 4mhz crystal period (250ns). settings less than 0012h are reserved and should not be used. the analog comparator driven by the stop_up and stop_dn device pins does not generate a stop condition until this delay, counted from the internally generated start pulse for the acoustic wave, has expired. this delay applies to early edge detect wave. care must be taken to set the timout bits in the tof2 register so that a timeout interrupt does not occur before this delay expires. write opcode 42h read opcode c2h flash stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name x x x x cmp_en cmp_sel int_en et_cont bit 7 6 5 4 3 2 1 0 name cont_int clk_s2 clk_s1 clk_s0 cal_ period3 cal_ period2 cal_ period1 cal_ period0 bit name description 15:12 x reserved 11 cmp_en comparator/up_dn output enable:1 = cmp_out/up_dn output device pin is enabled. 0 = cmp_out/up_dn output device pin is driven low. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 51 downloaded from: http:///
table 20. calibration and control register (continued) bit name description 10 cmp_sel comparator/up_dn output select: this bit selects the output function of the cmp_out/up_dn pin and is only used when cmp_en = 1. 1 = cmp_en: the output monitors the receiver front end comparator output. 0 = up_dn: the output monitors the launch direction of the pulse launcher. high output: upstream measurement (launch_up to stop_up) low output: downstream measurement (launch_dn to stop_dn) 9 int_en interrupt enable: this bit, when set, enables the int pin. all interrupt sources are wire-ored to the int pin. 8 et_cont event timing continuous operation: this bit, when set, causes the currently executing evtmgx command to continuously execute until the halt command is received by the max35103. this bit, when cleared, causes: ? the currently executing evtmg1 command to run one sequence of tof_diff measurement cycles and/or one sequence of temperature measurement. ? the currently executing evtmg2 command to run one sequence of tof_diff measurements cycles. ? the currently executing evtmg3 command to run one sequence of temperature measurement cycles. 7 cont_int continuous interrupt: this bit, when set, causes the currently executing evtmgx command to assert the int pin (if enabled) after every tof_diff or temperature measurement cycle. this allows the host microprocessor to interrogate the current event for accuracy of measurements and hit data. when this bit is cleared, the currently executing evtmgx command interrupt generation behavior is controlled only by the setting of the et_cont bit. 6:4 clk_s[2:0] clock settling time: these bits deine the time interval that the max35103 waits after enabling the 4mhz clock for it to stabilize before making any measurements of time or temperature. clk_s2 clk_s1 clk_s0 description 32khz clock cycles typical time 0 0 0 16 488s 0 0 1 48 1.46ms 0 1 0 96 2.93ms 0 1 1 128 3.9ms 1 0 0 168 5.13ms 1 0 1 4mhz oscillator on continuously 1 1 0 4mhz oscillator on continuously 1 1 1 4mhz oscillator on continuously max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 52 downloaded from: http:///
table 20. calibration and control register (continued) table 21. real-time clock register bit name description 3:0 cal_period[3:0] 4mhz ceramic oscillator calibration period: these bits deine the number of 32.768khz oscillator periods to measure for determination of the 4mhz ceramic oscillator period.32khz clock cycles = 1+ cal_period[3:0] cal_period[3:0] (decimal) description 32khz clock cycles (decimal) 32khz clock cycles (s) 0 1 30.5 1 2 61 . . . 14 15 457.7 15 16 488.0 write opcode 43h read opcode c3h flash-stored yes factory-stored flash value 0000h bit 15 14 13 12 11 10 9 8 name x x x x x x x x bit 7 6 5 4 3 2 1 0 name x 32k_bp 32k_en eosc am1 am0 wf wd_en bit name description 15:7 x reserved 6 32k_bp 32khz bypass: this bit, when set, allows an external cmos-level 32.768khz signal to be applied to the 32kx1 device pin. the internal 32.768khz oscillator is bypassed and the external signal is driven into the max35103 core. 5 32k_en 32khz clock output enable: this bit enables the 32kout device pin to drive a cmos-level square wave representation of the 32khz crystal. 4 eosc enable oscillator: this active-low bit when set to logic 0 starts the real-time clock oscillator. when this bit is set to logic 1, the oscillator is stopped. max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 53 downloaded from: http:///
table 22. interrupt status register status register descriptions table 21. real-time clock register (continued) bit name description 3:2 am[1:0] alarm control: the max35103 contains a time-of-day alarm. the alarm is activated when either the am1 or am2 bits are set. when the rtcs hours or minutes value increments to a value equal to the alarm settings in alarm registers, the af bit in the interrupt status register is set and the int device pin is asserted (if enabled) and remains asserted until the interrupt status register is accessed by the microprocessor with a read register command. am1 am0 alarm function 0 0 no alarm 0 1 alarm when minutes match 1 0 alarm when hours match 1 1 alarm when hours and minutes match 1 wf watchdog flag : this bit is set when the watchdog counter reaches zero. this bit must be written to a zero to clear the bit. writing this bit to a zero when the wdo pin is asserted low releases the wdo pin to its inactive high-impedance state. 0 wd_en watchdog enable: 1 = watchdog timer is enabled. 0 = watchdog time is disabled, and the wdo pin is high impedance. write opcode read only read opcode feh flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name to af x tof te ldo tof_ evtmg temp_ evtmg bit 7 6 5 4 3 2 1 0 name flash cal halt cswi init por x x note: this register is read only and bits are self-clearing upon a read to this register. see the device interrupt operations section for more information. bit name description 15 to timeout: the to bit is set if any one of the t 1 , t 2 , hit1 through hit6, or temperature measure- ments do not occur within the associated timeout window. 14 af alarm flag: set when the rtcs hours or minutes value increments to a value equal to the alarm settings in alarm registers. 13 x reserved max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 54 downloaded from: http:///
table 22. interrupt status register (continued) bit name description 12 tof time of flight: set when the tof_up, tof_dn, or tof_diff command has completed. during execution of the evtmg1 or evtmg2 command, this bit is set and the int pin asserts (if enabled) upon completion of each of the cycles of the event deined by the tof difference measurements setting if the cont_int bit in the calibration and control register has been set. 11 te temperature: set when the temperature command has completed. during execution of the evtmg1 or evtmg3 command, this bit is set and the int pin asserts (if enabled) upon completion of each of the cycles of the event deined by the temperature measurements setting if the cont_int bit in the calibration and control register has been set. 10 ldo internal ldo stabilized: set when the internal low-dropout regulator is turned on by either the ldo_timed or ldo_on and has stabilized. once asserted, a lash command can be sent to the max35103. 9 tof_evtmg event timing tof completed: set when either the evtmg1 or evtmg2 commands have completed its last tof_diff measurement cycle. this indicates that the data in the tof_diff, tof_diff_avg, avgup, and avgdn results registers is valid. 8 temp_evtmg event timing temperature completed: set when the evtmg1 or evtmg3 commands have completed its last temperature measurements. this indicates that the data in the t1, t2, t3, t4, t1_avg, t2avg, t3avg, and t4_avg results registers is valid. 7 flash flash ready: set when the lash memory is ready to be accessed. during execution of any command that requires write access to the lash memory (write lash, transfer coniguration to lash, block erase, initialize), the spi port is inactive and should not be exercised. the host microprocessor is interrupted by the assertion of the int pin (if enabled) once the command has been completed and the spi of the max35103 is available for access. 6 cal calibrate: set after completion of the calibrate command when the command is manually sent by the host microprocessor. when calibration occurs as a result of the setting of the cal_use, cal_auto and cal_cfgx bits in the event timing 2 register and the max35103 is automatically executing calibration commands as required during execution of any of the evtmgx commands, this bit is not set. 5 halt halt: set when the halt command has completed. 4 cswi case switch: set when a high logic level is detected on the csw device pin. 3 init initialize: set when the initialize command has completed. 2 por power-on-reset: set when the max35103 has been successfully powered by application of v cc . upon application of power, the spi port becomes inactive until this bit has been set. 1:0 x reserved max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 55 downloaded from: http:///
table 23. control register write opcode ffh read opcode 7fh flash stored no default value 0000h bit 15 14 13 12 11 10 9 8 name x x x x x x afa cswa bit 7 6 5 4 3 2 1 0 name x x x x x x x x bit name description 15:10 x reserved 9 afa alarm flag arm: this bit is set when the rtcs hours and/or minutes value matched the alarm settings in the rtc register. this bit is set at the same time as the af bit in the interrupt status register. after resetting the rtc alarm settings, a 0 must be written to this bit to rearm the rtc alarm. this bit can only be written to a 0. 8 cswa case switch arm: this bit is set when the csw pin detects a logic-high, indicating the max35103 has detected a tamper condition. this bit is set at the same time as the cswi bit in the interrupt status register. once set, this bit must be written to a 0 to rearm the case switch detection. the case switch detection must be rearmed before the cswi interrupt can be set again. this bit can only be written to a 0. 7:0 x reserved max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 56 downloaded from: http:///
conversion results register descriptions the devices conversion results registers are all read-only volatile sram. values are not stored in the flash memory and the por value for all registers is 0000h. table 24. conversion results registers description read only address name description c4h wvrup bit 15 through bit 8 holds the 8-bit value of the pulse width ratio (t 1 t 2 ).for the upstream measurement. each bit is weighted as follows: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 bit 7 thru bit 0 holds the 8-bit value of the pulse width ratio (t 2 t ideal ) where t ide al is equal to half the period of the pulse launch frequency for the upstream measurement. each bit is weighted as follows: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 the maximum value of each of these ratios is 1.9921875. c5h hit1upint 15-bit ixed-point integer value of the irst hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . c6h hit1upfrac 16-bit fractional value of the irst hit in the upstream direction. this fractional portion is a bina ry representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . c7h hit2upint 15-bit ixed-point integer value of the second hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . c8h hit2upfrac 16-bit fractional value of the second hit in the upstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . c9h hit3upint 15-bit ixed-point integer value of the third hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . cah hit3upfrac 16-bit fractional value of the third hit in the upstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . cbh hit4upint 15-bit ixed-point integer value of the fourth hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . cch hit4upfrac 16-bit fractional value of the fourth hit in the upstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 57 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description cdh hit5upint 15-bit ixed-point integer value of the ifth hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . ceh hit5upfrac 16-bit fractional value of the ifth hit in the upstream direction. this fractional portion is a bina ry representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . cfh hit6upint 15-bit ixed-point integer value of the sixth hit in the upstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . d0fh hit6upfrac 16-bit fractional value of the sixth hit in the upstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . d1h avgupint 15-bit ixed-point integer value of the average of the hits recorded in the upstream direction this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . d2h avgupfrac 16-bit fractional value of the average of the hits recorded in the upstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . d3h wvrdn bit 15 through bit 8 holds the 8 bit value of the pulse width ratio (t 1 /t 2 ).for the downstream measurement. each bit is weighted as follows: bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 bit 7 thru bit 0 holds the 8 bit value of the pulse width ratio (t 2/ t ideal ) where t ideal is equal to half the period of the pulse launch frequency for the downstream measurement. each bit is weighted as follows: bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 1 0.5 0.25 0.125 0.0625 0.03125 0.015625 0.0078125 the maximum value of each of these ratios is 1.9921875. d4h hit1dnint 15-bit ixed-point integer value of the irst hit in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . d5h hit1dnfrac 16-bit fractional value of the irst hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . d6h hit2dnint 15-bit ixed-point integer value of the second hit in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 58 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description d7h hit2dnfrac 16-bit fractional value of the second hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . d8h hit3dnint 15-bit ixed-point integer value of the third hit in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . d9h hit3dnfrac 16-bit fractional value of the third hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . dah hit4dnint 15-bit ixed-point integer value of the fourth hit in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . dbh hit4dnfrac 16-bit fractional value of the fourth hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . dch hit5dnint 15-bit ixed-point integer value of the ifth hit in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4m h z . ddh hit5dnfrac 16-bit fractional value of the ifth hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . deh hit6dnint 15-bit ixed-point integer value of the sixth hit in the downstream direction this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . dfh hit6dnfrac 16-bit fractional value of the sixth hit in the downstream direction. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . e0h avgdnint 15-bit ixed-point integer value of the average of the hit times recorded in the downstream direction. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 C 1) x t 4mhz . e1h avgdnfrac 16-bit fractional value of the average of the hit times recorded in the downstream direction. this fractional portion is a binary representation of one period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 C 1)/2 16 x t 4mhz . max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 59 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description e2h tof_diffint 16-bit ixed-point twos-complement integer portion of the difference of the averages for the hits recorded in both the upstream and downstream directions. it is computed as: avgup C avgdn this integer represents the number of t 4mhz periods that contribute to computation. the maximum size of the integer is 7fffh or (2 15 C 1) x t 4mhz . the minimum size of this integer is 8000h or -2 15 x t 4mhz . e3h tof_ difffrac 16-bit fractional portion of the twos complement difference of the averages for the hits recorded in both the upstream and downstream directions. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . e4h tof_cycle_ count /tof_range bit 15 through bit 8 holds the 8-bit value of the tof_range. the tof_range is an 8-bit binary integer that indicates the range of valid error-free tof_diff measurements that were made during execution of either of the evtmg1 or evtmg2 commands. the maximum value of tof_range is equal to 2 times the actual pulse launch period as conigured by the pulse launch divider bits in the tof1 register. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 msb tof_range 8-bit binary integer lsb the formulas to calculate the range and resolution of the tof_range integer for a given dpl[3:0] bit setting are shown below: maximum range (s) = dpl[3:0] + 1 resolution = maximum range/256 dpl[3:0] launch frequency maximum range (s) resolution (ns) 0001b 1mhz 2 7.8175 0002b 666.6khz 3 11.7185 . . . . 1110b 133.3khz 15 58.59375 1111b 125khz 16 62.5 bit 7 through bit 0 holds the 8-bit value of the tof cycle count. the tof cycle count is an 8-bit binary integer that indicates the number of valid error-free cycles that either of the evtmg1 or evtmg2 commands has executed. it also represents the number of tof_diff cycles that have been totaled for the purpose of averaging, which affects the results provided in the tof_diff_ avgfrac and tof_diff_avgint registers. it is incremented every time an error-free tof_diff command is executed by either the evtmg1 or evtmg2 sequence. because of this internal error checking, once the complete number of cycles deined by the tof difference masurements bits in the event timing 1 register has been completed and the tof_evtmg bit has been set in the interrupt status register causing the int device pin to be asserted (if enabled), the tof cycle count may not be equal to the setting of the tof difference measurements bits in the event timing 1 register. bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb tof cycle count 8-bit binary integer lsb max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 60 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description e5h tof_diff_ avgint 16-bit ixed-point twos-complement integer portion of the average of the accumulated tof_diff measurements. it is computed as: this integer represents the number of t 4mhz periods that contribute to the computation. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . the minimum size of this integer is 8000h or -2 15 x t 4mhz . e6h tof_diff_ avgfrac 16-bit fractional portion of the twos-complement average of the accumulated tof_diff measurements. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . e7h t1int 15-bit ixed-point integer value of the time taken to discharge the timing capacitor through the rtd connected to the t1 device pin. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . e8h t1frac 16-bit fractional value of the time taken to charge the timing capacitor through the rtd connected to the t1 device pin. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . e9h t2int 15-bit ixed-point integer value of the time taken to charge the timing capacitor through the rtd connected to the t2 device pin. this integer portion is a binary representation of the number of periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . eah t2frac 16-bit fractional value of the time taken to charge the timing capacitor through the rtd connected to the t2 device pin. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . ebh t3int 15-bit ixed-point integer value of the time taken to charge the timing capacitor through the rtd connected to the t3 device pin. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . ech t3frac 16-bit fractional value of the time taken to charge the timing capacitor through the rtd connected to the t3 device pin. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . edh t4int 15-bit ixed-point integer value of the time taken to charge the timing capacitor through the rtd connected to the t4 device pin. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . tof_cycle_count tof_diff n tof_cycle_count n = 1 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 61 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description eeh t4frac 16-bit fractional value of the time taken to charge the timing capacitor through the rtd connected to the t4 device pin. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . efh temp_cycle_ count the temp cycle count is an 8-bit binary integer that indicates the number of valid error-free cycles that either of the evtmg1 or evtmg3 commands has executed. it also represents the number of temperature cycles that have been totaled for the purpose of averaging, which affects the results provided in the tx_avgfrac and tx_avgint registers. it is incremented every time an error-free temperature command is executed by either the evtmg1 or evtmg3 sequence. because of this internal error checking, once the complete number of cycles deined by the temperature measurements bits in the event timing 2 register has been completed and the temp_evtmg bit has been set in the interrupt status register causing the int device pin to be asserted (if enabled), the temperature cycle count may not be equal to the setting of the temperature measurements bits in the event timing 2 register. bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 x x x x x x x x bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 msb temp cycle count lsb f0h t1_avgint 15-bit ixed-point integer value of the average of the t1 port measurements. it is computed as: this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . f1h t1_avgfrac 16-bit fractional portion of the average of the t1 port measurements. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . f2h t2_avgint 15-bit ixed-point integer value of the average of the t2 port measurements. it is computed as: this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . temp_cycle_count temp_cycle_count t1 n n = 1 temp_cycle_count temp_cycle_count t2 n n = 1 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 62 downloaded from: http:///
table 24. conversion results registers description (continued) read only address name description f3h t2_avgfrac 16-bit fractional portion of the average of the t2 port measurements. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . f4h t3_avgint 15-bit ixed-point integer value of the average of the t3 port measurements. it is computed as: this integer portion is a binary representation of the number of periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 -1) x t 4mhz . f5h t3_avgfrac 16-bit fractional portion of the average of the t3 port measurements. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . f6h t4_avgint 15-bit ixed-point integer value of the average of the t4 port measurements. it is computed as: this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . f7h t4_avgfrac 16-bit fractional portion of the average of the t4 port measurements. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . f8h calibration int 15-bit ixed-point integer value of the time taken to measure the period of the 32.768khz crystal oscillator during execution of the calibrate command. this integer portion is a binary representation of the number of t 4mhz periods that contribute to the time results. the maximum size of the integer is 7fffh or (2 15 - 1) x t 4mhz . f9h calibration frac 16-bit fractional value of the time taken to measure the period of the 32.768khz crystal oscillator during execution of the calibrate command. this fractional portion is a binary representation of one t 4mhz period quantized to a 16-bit resolution. the maximum size of the fraction is ffffh or (2 16 - 1)/2 16 x t 4mhz . fah reserved fbh reserved fch reserved fdh reserved temp_cycle_count temp_cycle_count t3 n n = 1 temp_cycle_count temp_cycle_count t4 n n = 1 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 63 downloaded from: http:///
flash opcode commands to access the flash memory, the internal low-dropout voltage regulator that powers the flash circuitry must be enabled. this can be done two ways: sending the ldo_timed command prior to the desired flash access or sending the ldo_on command to the max35103 prior to desired flash access. see the ldo_timed and ldo_on command descriptions for details. to manipulate the flash memory, there are three commands supported by the device: read flash, write flash, and block erase flash. read flash command the read flash command is used to sequentially read a continuous stream of data from the internal 8kb of flash using a built-in autoincrement address counter. for 8kb, 13 address bits are needed to indicate the starting address in memory to begin the read stream. since the memory array is organized in x16 fashion, the starting address must fall on any even number address. the read stream continues until the ce signal is deasserted. once the automatic internal address counter has been incre - mented to the last memory location in the array, it wraps around to the bottom of the memory array and the data for the first memory location of the array is read. figure 18 illustrates the serial peripheral interface signaling associ - ated with the read flash command. write flash command the flash is written in the max35103 in a word-only man - ner. the architecture allows a single 16-bit word to be written to the array supporting the maximum access spi clock speed of t sck . the location to be programmed must have previously been erased with the block erase flash command. to perform a write flash command, the starting flash memory address must fall on an even flash memory address (i.e., the least significant bit of the address (a15C a0) must be 0). the 16-bit address word and at least one 16-bit word of data must be clocked into the device before the ce pin is deasserted. if more than 16 bits of data are clocked into the device during a single ce assertion, only the last bounded 16-bit data word is written. this is not a fifo register. any fraction of a 16-bit word is ignored, and the previous whole 16-bit word is written. once the 16 bits of data are clocked into the device, the host microprocessor deasserts the ce device pin and then waits. the max35103 sets the flash bit in the interrupt status register and assert the int device pin (if enabled) to tell the host microprocessor that the next write flash command can be sent to the max35103. the host microprocessor can then read the interrupt status register after the int device pin is asserted. figure 19 illustrates the serial peripheral interface signal - ing associated with the write flash command. figure 18. read flash opcode command protocol ce sck din dout o o a a opcode address d d d msb lsb msb lsb 16 bits 8 bits d d d d d d d msb lsb msb high impedance high impedance read flash command data max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 64 downloaded from: http:///
block erase flash command a block of 128 words (256 bytes) can be erased in a single operation. for the 8kb array, there are 32 such 128 word (256 byte) blocks. the block to be erased is selected by the 16-bit address word in the block erase flash spi protocol sequence as illustrated in figure 20 . the erased block is the block that contains the specified address. the time from ce deassert to ce assert for the next block erase flash command needs to be approxi - mately t erase . also, the device sets the flash bit in the interrupt status register and asserts the int device pin (if enabled) to tell the host microprocessor that the next block erase flash command can be sent. the host micro - processor can read the interrupt status register after the int device pin is asserted instead of waiting for t erase . flash memory map this memory is accessed by the read flash, write flash, and the block erase flash commands. all flash memory is erased when the max35103 leaves the factory. this means that each flash location has a value of ffffh until written by a user to a different value. figure 19. write flash opcode command protocolfigure 20. block erase flash opcode command protocol write flash command ce sck din dout o o a a opcode address msb lsb msb lsb a15-a0 16 bits d7-d0 high impedance 0 1 2 3 4 5 10 9 8 7 6 20 23 22 21 d d 24 25 26 39 38 37 36 data msb lsb 16 bits block erase flash command ce sck din dout o o a a opcode address msb lsb msb lsb 16 bits 8 bits high impedance 0 1 2 3 4 5 10 9876 20 23 22 21 max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 65 downloaded from: http:///
+ deno tes a lead(pb)-free/rohs-compliant package. t = tape and reel. * ep = exposed pad. table 25. flash memory map part temp range pin-package MAX35103EHJ+ -40c to +85c 32 tqfp-ep* MAX35103EHJ+t -40c to +85c 32 tqfp-ep* package type package code outline no. land pattern no. 32 tqfp-ep h32e+6 21-0079 90-0326 flash address (evens only) block (decimal) description 0000h to 00ffh 0 user lash 0100h to 01ffh 1 user lash 0200h to 02ffh 2 user lash . . user lash 1d00h to 1dffh 29 user lash 1e00h to 1effh 30 user lash 1f00h to 1fffh 31 user lash max35103 reduced power time-to-digital converter with afe, rtc, and flash www.maximintegrated.com maxim integrated 66 package information for the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. chip information process: cmos ordering information downloaded from: http:///
revision number revision date description pages changed 0 10/14 initial release 1 1/15 updated figure 12 21 maxim integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim integrated product. no circuit patent licenses are implied. maxim integrated reserves the right to change the circuitry and speciications without n otice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated and the maxim integrated logo are trademarks of maxim integrated products, inc. ? 2015 maxim integrated products, inc. 67 max35103 reduced power time-to-digital converter with afe, rtc, and flash revision history for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim integrateds website at www.maximintegrated.com. downloaded from: http:///

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