View MAX5069DAUE_9098128.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ge ne ra l de sc ript ion the max5069 is a high-frequency, current-mode, pulse-width modulation (pwm) controller (with dual mosfet drivers) that integrates all the building bl ocks necessary for implementing ac-dc or dc-dc fixed-fre - quency power supplies. isolated or nonisolated push - pull and half/full-bridge power supplies are easily constructed using either primary- or secondary-side regulation. current-mode control with leading-edge blanking simplifies control-loop design and a progr am- mable internal slope-compensation circuit stabilize s the current loop when operating at duty cycles above 50 %. an input undervoltage lockout (uvlo) programs the input-supply startup voltage and ensures proper ope ra- tion during brownout conditions. a single external resistor programs the oscillator frequen- cy from 50khz to 2.5mhz. the max5069a/d provide a sync input for synchronization to an external clock . the maximum fet-driver duty cycle for the max5069 is 50 %. programmable dead time allows additional flexibilit y in optimizing magnetic design and overcoming parasitic effects. programmable hiccup current limit provides additional protection under severe faults. the max5069 is specified over the -40c to +125c a uto- motive temperature range and is available in a 16-pin thermally enhanced tssop-ep package. refer t o the max5068 data sheet for single fet-driver applic ations. warning: the max5069 is designed to work with high voltages. exercise caution. applic a t ions universal-input ac power supplies isolated telecom power supplies networking system power supplies server power supplies industrial power conversion fe a t ure s ? current-mode control with 47a (typ) startupcurrent ? oscillator frequency programmable to 2.5mhz ? resistor-programmable 4.5% accurateswitching frequency ? dual gate-drive output for half/full-bridge orpush-pull applications ? rectified 85vac to 265vac, or 36vdc to 72vdcinput (max5069a/b) ? input directly driven from 10.8v to 24v(max5069c/d) ? programmable dead time and slopecompensation ? programmable startup voltage (uvlo) ? programmable uvlo hysteresis (max5069b/c) ? frequency synchronization input (max5069a/d) ? -40c to +125c automotive temperature range ? 16-pin thermally enhanced tssop-ep package m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs ________________________________________________________________ maxim integrated products 1 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 rt reg5 in v cc ndrva ndrvb pgnd agnd cs top view m ax5069 tssop-ep sync(hyst* ) scomp fb dt uvlo/en comp fltint * max5069b/c. pin configura t ion orde ring i nform a t ion 19-3175; rev 1; 7/04 for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxims website at www.maxim-ic.com. * ep = exposed pad. part temp range pin-package max5069aaue -40c to +125c 16 tssop-ep* max5069baue -40c to +125c 16 tssop-ep* max5069caue -40c to +125c 16 tssop-ep* MAX5069DAUE -40c to +125c 16 tssop-ep* selector guide appears at end of data sheet. downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics (v in = +12v for the max5069c/d, v in = +23.6v for the max5069a/b at startup, then reduce s to +12v, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) stresses beyond those listed under absolute maximu m ratings may cause permanent damage to the device . these are stress ratings only, and functional operation of the device at these or any other condi tions beyond those indicated in the operational sec tions of the specifications is not implied. exposur e to absolute maximum rating conditions for extended per iods may affect device reliability. in to pgnd ........................................ ....................-0.3v to +30v in to agnd......................................... ....................-0.3v to +30v v cc to pgnd............................................ ..............-0.3v to +13v v cc to agnd............................................ ..............-0.3v to +13v fb, comp, cs, hyst, sync, reg5 to agnd ........-0.3v to +6v uvlo/en, rt, dt, scomp, fltint to agnd .........-0.3 v to +6v ndrva, ndrvb to pgnd ..........................-0.3v to (v cc + 0.3v) agnd to pgnd ....................................... ..............-0.3v to +0.3v continuous power dissipation (t a = +70c) 16-pin tssop-ep (derate 21.3mw/c above +70c) ...17 02mw operating temperature range........................ ..-40c to +125c maximum junction temperature ....................... ..............+150c storage temperature range .......................... ...-60c to +150c lead temperature (soldering, 10s) .................. ...............+300c parameter symbol conditions min typ max units undervoltage lockout/startup bootstrap uvlo wake-up level v suvr v in rising, max5069a/b 19.68 21.6 23.60 v bootstrap uvlo shutdown level v suvf v in falling, max5069a/b 9.05 9.74 10.43 v uvlo/en wake-up threshold v ulr2 uvlo/en rising 1.205 1.230 1.255 v uvlo/en shutdown threshold v ulf2 uvlo/en falling 1.18 v hyst fet on-resistance r d s ( on ) _h max5069b/c only, sinking 50ma, v uvlo/en = 0v 10 ? hyst fet leakage current i leak_h v uvlo/en = 2v, v hyst = 5v 3 na in supply current in undervoltage lockout i start v in = +19v, v uvlo/en < v ulf2 47 90 a in range v in 10.8 24.0 v internal supplies (v cc and reg5) v cc regulator set point v ccsp v in = + 10.8v to + 24v , v c c sour ci ng 1a to 25m a 7.0 10.5 v reg5 output voltage v reg5 i reg5 = 0 to 1ma 4.85 5.00 5.15 v reg5 short-circuit current limit i reg5_sc 18 ma f sw = 1.25mhz 7 in supply current after startup i in v in = +24v f sw = 100khz 3 ma shutdown supply current i vin_sd 90 a gate driver (ndrva, ndrvb) z out ( low ) ndrva/ndrvb sinking 100ma 2 4 driver output impedance z out ( high ) ndrva/ndrvb sourcing 25ma 3 6 ? sinking 1000 driver peak output current i ndrv sourcing 650 ma pwm comparator comparator offset voltage v os_pwm v comp > v cs 1.30 1.60 2.00 v comparator propagation delay t pd_pwm v cs = 0.1v 40 ns minimum on-time t on ( min ) includes t cs_blank 110 ns current-limit comparator current-limit trip threshold v cs 298 314 330 mv downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units cs input bias current i b_cl v cs = 0v 0 +2 a cs blanking time t cs_blank 70 ns propagation delay from comparator input to ndrv_ t pd_cl 50mv overdrive 40 ns in clamp voltage in clamp voltage v in_clamp in sinking 2ma (note 2) 24.0 26.0 29.0 v error amplifier (fb, comp) voltage gain a v r comp = 100k ? to agnd 80 db unity-gain bandwidth bw r comp = 100k ? to agnd, c load = 100pf to agnd 5 mhz phase margin pm r comp = 100k ? to agnd, c load = 100pf to agnd 65 d eg r ees fb input offset voltage v os_fb 3m v high 2.6 3.8 comp clamp voltage v comp low 0.4 1.1 v error-amplifier output current i comp sinking or sourcing 0.5 ma +25c t a +125c (note 3) 1.215 1.230 1.245 reference voltage v ref -40c t a +125c (note 3) 1.205 1.230 1.242 v input bias current i b_ea 100 300 na comp short-circuit current i comp_sc 12 ma thermal shutdown thermal-shutdown temperature t sd +170 c thermal hysteresis t hyst 25 c oscillator sync input (max5069a/d only) sync high-level voltage v ih_sync 2.4 v sync low-level voltage v il_sync 0.4 v sync input bias current i b_sync 10 na maximum sync frequency f sync f osc = 2.5mhz (note 4) 3.125 mhz sync high-level pulse width t sync_hi 30 ns sync low-level pulse width t sync_lo 30 ns digital soft-start soft-start duration t ss (note 5) 2047 cycles reference-voltage step v step 9.7 mv reference-voltage steps during soft-start 127 steps oscillator oscillator frequency range f osc f osc = (10 11 / r rt ) 50 2500 khz electrical characteristics (continued) (v in = +12v for the max5069c/d, v in = +23.6v for the max5069a/b at startup, then reduce s to +12v, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 4 _______________________________________________________________________________________ note 1: the max5069 is 100% tested at t a = +25c. all limits over temperature are guaranteed by design. note 2: the max5069a/b are intended for use in universal-in put power supplies. the internal clamp circuit is u sed to prevent the bootstrap capacitor (c1 in figure 1) from charging to a voltage beyond the absolute m aximum rating of the device when uvlo/en is low. the maximum current to v in (hence to clamp) when uvlo is low (device is in shu tdown) must be external- ly limited to 2ma. clamp currents higher than 2ma m ay result in clamp voltages higher than 30v, thus e xceeding the absolute maximum rating for v in . for the max5069c/d, do not exceed the 24v maximum operating voltage of the device. note 3: reference voltage (v ref ) is measured with fb connected to comp (see the functional diagram ). note 4: the sync frequency must be at least 25% higher than the programmed oscillator frequency. note 5: the internal oscillator clock cycle. parameter symbol conditions min typ max units ndrv_ switching frequency f sw f sw = 10 11 / (2 x r rt )2 5 1250 khz rt voltage v rt 40k ? < r rt < 500k ? 2.0 v f osc 500khz -2.5 +2.5 t a = +25 c f osc > 500khz -4 +4 f osc 500khz -4.5 +4.5 oscillator accuracy t a = -40 c to +125 c f osc > 500khz -6 +6 % maximum duty cycle d max dt connected to reg5 100 % dead-time control (dt) dead time t dt r dt = 24.9k ? 60 ns dead-time disable voltage v dt_disable v reg5 - 0.5v v dead-time regulation voltage v dt 1.23 v integrating fault protection (fltint) fltint source current i fltint v fltint = 0v 60 a fltint shutdown threshold v fltint_sd v fltint rising 2.8 v fltint restart threshold v fltint_rs v fltint falling 1.6 v slope compensation slope compensation v slope c slope = 100pf, rt = 110k ? 15 mv/s slope-compensation range v sloper 09 0 mv/s slope-compensation voltage range v scomp 0 2.7 v electrical characteristics (continued) (v in = +12v for the max5069c/d, v in = +23.6v for the max5069a/b at startup, then reduce s to +12v, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, t a = t min to t max , unless otherwise noted. typical values are at t a = +25c.) (note 1) downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs _______________________________________________________________________________________ 5 21.0 21.2 21.1 21.4 21.3 21.5 21.6 -40 35 60 -15 10 85 110 bootstrap uvlo wake-up level vs. tem perature max5069 toc01 temperature ( c) v in (v) max5069a/b 9.5 9.6 9.8 9.7 9.9 10.0 -40 35 60 -15 10 85 110 bootstrap uvlo shutdown level vs. tem perature max5069 toc02 temperature ( c) v in (v) max5069a/b 1.220 1.225 1.235 1.230 1.240 1.245 -40 35 60 -15 10 85 110 uvlo/en wake-up threshold vs. tem perature max5069 toc03 temperature ( c) uvlo/en (v) uvlo/ en rising 1.10 1.19 1.18 1.17 1.16 1.15 1.14 1.13 1.12 1.11 1.20 -40 35 60 -15 10 85 110 uvlo/en shutdown threshold vs. tem perature max5069 toc04 temperature ( c) uvlo/en (v) uvlo/ en falling 40 44 52 48 56 60 -40 35 60 -15 10 85 110 v in supply current in undervoltage lockout vs. tem perature max5069 toc05 temperature ( c) i start ( a) v in = 19v when in bootstrap uvlo (max5069a/b) uvlo/en (max5069c/d) is low v in supply current after startup vs. tem perature max5069 toc06 temperature ( c) i in (ma) 85 60 35 10 -15 3 2 4 6 5 7 8 1 -40 110 v in = 24v f sw = 1.25mhz f sw = 50khz f sw = 500khz f sw = 100khz f sw = 250khz v cc vs. tem perature max5069 toc07 temperature ( c) v cc (v) 85 60 35 10 -15 7.6 7.3 8.2 7.9 8.8 8.5 9.4 9.1 9.7 10.0 7.0 -40 110 v in = 19v, i in = 25ma v in = 19v, i in = 10ma v in = 10.8v, i in = 10ma v in = 10.8v, i in = 25ma reg5 output voltage vs. output current max5069 toc08 output current (ma) reg5 (v) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 4.955 4.960 4.965 4.970 4.975 4.980 4.950 0 2.0 r rt = 100k ? 4.90 4.99 4.98 4.97 4.96 4.95 4.94 4.93 4.92 4.91 5.00 -40 35 60 -15 10 85 110 reg5 vs. tem perature max5069 toc09 temperature ( c) reg5 (v) v in = 10.8v 100 a load 1ma load typic a l ope ra t ing cha ra c t e rist ic s (v in = +23.6v for max5069a/b at startup, then reduces to +12v, v in = +12v for the max5069c/d, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, v fb = 0v, v comp = floating, v cs = 0v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 6 _______________________________________________________________________________________ typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (v in = +23.6v for max5069a/b at startup, then reduces to +12v, v in = +12v for the max5069c/d, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, v fb = 0v, v comp = floating, v cs = 0v, t a = +25c, unless otherwise noted.) reg5 output voltage vs. v in max5069 toc10 v in (v) reg5 (v) 22 20 16 18 14 12 10 24 4.976 4.977 4.978 4.979 4.980 4.981 4.982 4.983 4.984 4.985 4.975 i reg5 = 100 a cs trip threshold vs. tem perature max5069 toc11 temperature ( c) cs trip threshold (mv) 110 85 60 35 10 -15 306 303 309 315 312 321 318 327 324 330 300 -40 switching frequency vs. tem perature max5069 toc12 temperature ( c) switching frequency (khz) 110 85 60 35 -15 10 490 485 495 505 500 515 510 525 520 530 480 -40 f sw = 500khz total number of devices = 200 mean -3 +3 propagation delay from cs com parator input to ndrv vs. tem perature max5069 toc13 temperature ( c) propagation delay (ns) 110 85 35 60 10 -15 32 34 36 38 40 42 44 46 48 50 30 -40 input current vs. input clam p voltage max5069 toc14 input clamp voltage (v) input current (ma) 27.5 25.0 22.5 20.0 17.5 15.0 12.5 2 4 6 8 10 12 14 0 10.0 30.0 input clam p voltage vs. tem perature max5069 toc15 temperature ( c) input clamp voltage (v) 110 85 35 60 10 -15 25.2 25.4 25.6 25.8 26.0 26.2 26.4 26.6 26.8 27.0 25.0 -40 i sink = 2ma 1.0 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 3.0 -40 35 60 -15 10 85 110 ndrva/ndrvb output im pedance vs. tem perature max5069 toc16 temperature ( c) r on ( ? ) v in = 24v sinking 100ma 2.0 3.8 3.6 3.4 3.2 3.0 2.8 2.6 2.4 2.2 4.0 -40 35 60 -15 10 85 110 ndrva/ndrvb output im pedance vs. tem perature max5069 toc17 temperature ( c) r on ( ? ) v in = 24v sourcing 25ma error am plifier open-loop gain and phase vs. frequency max5069 toc18 frequency (hz) gain (db) phase (degrees) 10m 10 100k 1k -20 0 20 40 60 80 100 120 -40 -180 -150 -120 -90 -60 -30 0 30 -210 0.1 gain phase downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs _______________________________________________________________________________________ 7 62.0 62.9 62.8 62.7 62.6 62.5 62.4 62.3 62.2 62.1 63.0 -40 35 60 -15 10 85 110 fltint current vs. tem perature max5069 toc19 temperature ( c) fltint current ( a) 8.0 12.5 12.0 11.5 11.0 10.5 10.0 9.5 9.0 8.5 13.0 -40 35 60 -15 10 85 110 hyst r on vs. tem perature max5069 toc20 temperature ( c) r on ( ? ) v in = 24v sinking 50ma 0.01 0.1 1 2 0.03 0.1 1 2 ndrva switching frequency (f sw) vs. r rt max5069 toc21 r rt (m ? ) f sw (mhz) ndrv switching frequency vs. tem perature max5069 toc22 temperature ( c) ndrv switching frequency (khz) 110 85 35 60 10 -15 48.4 48.8 49.2 49.6 50.0 50.4 50.8 51.2 51.6 52.0 48.0 -40 f sw = 50khz ndrv switching frequency vs. tem perature max5069 toc23 temperature ( c) ndrv switching frequency (khz) 100 125 75 50 25 0 -25 497 496 498 500 499 502 501 504 503 505 495 -50 f sw = 500khz f sw = 500khz dead tim e vs. tem perature max5069 toc25 temperature ( c) time (ns) 110 85 60 35 10 -15 45 50 55 60 65 70 40 -40 v in = 24v r dt = 24.9k ? r rt = 100k ? ndrv switching frequency vs. tem perature max5069 toc24 temperature ( c) ndrv switching frequency (khz) 110 85 60 35 10 -15 1.15 1.20 1.25 1.30 1.35 1.40 1.10 -40 f sw = 1.25mhz dead tim e vs. r dt max5069 toc26 r dt (k ? ) time (ns) 10 20 40 60 80 100 120 140 160 180 200 0 1 100 typic a l ope ra t ing cha ra c t e rist ic s (c ont inue d) (v in = +23.6v for max5069a/b at startup, then reduces to +12v, v in = +12v for the max5069c/d, c in = c reg5 = 0.1f, c vcc = 1f, r rt = 100k ? , ndrv_ = floating, v fb = 0v, v comp = floating, v cs = 0v, t a = +25c, unless otherwise noted.) downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 8 _______________________________________________________________________________________ pin de sc ript ion pin max5069a max5069d max5069bmax5069c name function 11r t oscillator-timing resistor. connect a resistor from rt to agnd to set the internal oscillator frequency. 2 sync external-clock sync input. connect sync to ag nd when not using an external clock. 2 hyst hysteresis input 33 scomp slope-compensation capacitor connection 44d t dead-time resistor connection. connect a resistor f rom dt to agnd to program the output dead time. connect to reg5 for ndrva and ndr vb maximum 50% duty cycle. 55 uvlo/en externally programmable undervoltage lockout. uvlo/ en programs the input start voltage. connect uvlo/en to agnd to disable the out put. 6 6 fb error-amplifier inverting input 7 7 comp error-amplifier output 88 fltint fault-integration input. a capacitor connected to f ltint charges with an internal 60a current source during persistent current-limit faul ts. switching terminates when v fltint is 2.8v. an external resistor connected in parallel di scharges the capacitor. switching resumes when v fltint drops to 1.6v. 9 9 cs current-sense resistor connection 10 10 agnd analog ground. connect to pgnd. 11 11 pgnd power ground. connect to agnd through a gro und plane. 12 12 ndrvb g ate- d r i ver o utp ut b. c onnect n d rv b to the g ate of the exter nal n - channel fe t. 13 13 ndrva gate-driver output a. connect ndrva to the gate of the external n-channel fet. 14 14 v cc 9v linear-regulator output. decouple v cc with a minimum 1f ceramic capacitor to agnd; also internally connected to the fet drivers. 15 15 in power-supply input. in provides power for all inter nal circuitry except the gate driver. decouple in with 0.1f to agnd (see the typical operating circuit ). 16 16 reg5 5v linear-regulator output. decouple reg5 t o agnd with 0.1f ceramic capacitor. ep ep pad exposed paddle. connect to gnd. downloaded from: http:///
de t a ile d de sc ript ion the max5069 is a current-mode, dual mosfet driver, pwm controller designed for isolated and nonisolate d push-pull or half-/full-bridge power-supply applica tions. a bootstrap uvlo with a programmable hysteresis, very low startup, and low operating current result in high-efficiency universal-input power supplies. in addi- tion to the internal bootstrap uvlo, the device als o offers programmable input startup and turn-off volt - ages, programmed through the uvlo/en pin. the max5069 includes a cycle-by-cycle current limit that turns off the gate drive to the external mosfe t during an overcurrent condition. the max5069 integr at- ing fault protection reduces average power dissipat ion during persistent fault conditions (see the integrating fault protection section). the max5069 features a very accurate, wide-range, programmable oscillator that simplifies and optimiz es the design of the magnetics. the max5069a/b are wel l suited for universal-input (rectified 85vac to 265v ac) or telecom (-36vdc to -72vdc) power supplies. the max5069c/d are well suited for low-input voltage (10.8vdc to 24vdc) power supplies. the max5069 high-frequency, universal input, offline/telecom, current-mode pwm controller integr ates all the building blocks necessary for implementing ac- dc and dc-dc fixed-frequency power supplies. push- pull and half-/full-bridge isolated or nonisolated power supplies are easily constructed using either primar y- or secondary-side regulation. current-mode control wit h leading-edge blanking simplifies control-loop desig n and the programmable slope compensation stabilizes the current loop when operating both fet drivers at a combined 100% duty cycle. an input uvlo programs the input-supply startup volt- age and ensures proper operation during brownout co n- ditions. an external voltage-divider programs the s upply startup voltage. the max5069b/c feature a programma - ble uvlo hysteresis. the max5069a/b feature an addi - tional internal bootstrap uvlo with large hysteresi s that requires a minimum startup voltage of 23.6v. the max5069a/d start up from a minimum voltage of 10.8v . internal digital soft-start reduces output-voltage over- shoot at startup. a single external resistor programs the switching f re- quency of each mosfet driver from 25khz to 1.25mhz. the max5069a/d provide a sync input for synchronization to an external clock. the maximum f et driver duty cycle for each driver is limited to 50% . programmable dead time allows additional flexibilit y in optimizing magnetic design and overcoming parasitic effects. integrating fault protection ignores trans ient overcurrent conditions for a set length of time. th e length of time is programmed by an external capacit or. the internal thermal-shutdown circuit protects the device should the junction temperature exceed +170c. power supplies designed with the max5069a/b use a high-value startup resistor, r1, which charges a re ser- voir capacitor, c1 ( figure 1). during this initial period, while the voltage is less than the internal bootstr ap uvlo threshold, the device typically consumes only 47a of quiescent current. this low startup current and the large bootstrap uvlo hysteresis help to minimiz e the power dissipation across r1 even at the high en d of the universal ac input voltage (265vac). the max5069 includes a cycle-by-cycle current limit that turns off the gates to both external mosfets d ur- ing an overcurrent condition. when using the max5069a/b in the bootstrap mode (if the power-sup- ply output is shorted), the tertiary winding voltag e drops below the 9.74v threshold, causing the uvlo t o turn off the gate to the external power mosfets. th is reinitiates a startup sequence with soft-start. curre nt -m ode cont rol the max5069 offers a current-mode control operation feature, such as leading-edge blanking with a dual internal path that only blanks the sensed current s ignal applied to the input of the pwm controller. the cur rent- limit comparator monitors cs at all times and provi des cycle-by-cycle current limit without being blanked. the leading-edge blanking of the cs signal prevents the pwm comparator from prematurely terminating the on cycle. the cs signal contains a leading-edge spike that results from the mosfets gate charge current, and the capacitive and diode reverse-recovery curre nt of the power circuit. since this leading-edge spike is normally lower than the current-limit comparator th resh- old, current limiting is provided under all conditi ons. use the max5069 in push-pull and half-/full-bridge appli- cations where a large duty cycle is desired. the la rge duty cycle results in much lower operating primary rms currents through the mosfet switches, and in most cases it results in a smaller inductor and output f ilter capacitor. the max5069 adjusted slope compensation allows for easy stabilization of the inner current loop. m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs _______________________________________________________________________________________ 9 downloaded from: http:///
m ax 5 0 6 9 u nde rvolt a ge loc k out the max5069 features an input voltage uvlo/en func- tion to enable the pwm controller before any operat ion can begin. the max5069a/d shut down if the voltage at uvlo/en falls below its 1.18v threshold. the max5069b/c also incorporate a uvlo hysteresis input to set the desired turn-off voltage. max5069a/d uvlo adjustment the max5069a/d have an input voltage uvlo/en with a 1.231v threshold. before any operation can com- mence, the uvlo/en voltage must exceed the 1.231v threshold. the uvlo circuit keeps the pwm compara- tor, ilim comparator, oscillator, and output driver s shut- down to reduce current consumption (see the functional diagram) . calculate r6 in figure 2 by using the following formula: where v ulr2 is the uvlo/ens 1.231v rising threshold and v on is the desired startup voltage. choose an r7 value in the 20k ? range. after a successful startup, the max5069a/d shut dow n if the voltage at uvlo/en drops below its 1.18v fal l- ing threshold. max5069b/c uvlo with programmable hysteresis in addition to programmable undervoltage lockout du r- ing startup, the max5069b/c incorporate a uvlo/en r v v r on ulr 61 7 2 = ?? ? ?? ? h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 10 ______________________________________________________________________________________ m ax5069b in ndrva ndrvb hyst uvlo/en cs comp v cc agnd pgnd reg5 rt fb dt fltint r1 c1 q1 q2 v in c2 c3 c4 r3 r4 r9 r2 r8 v out scomp c5 c7 d1 d3 d2 r5 c6 r10 r6 r hyst r7 figure 1. nonisolated power supply with programmable input supply voltage downloaded from: http:///
hysteresis that allows the user to set a voltage (v off ) to disable the controller (see figure 3). at the beginning of the startup sequence, uvlo/en i s below the 1.23v threshold, and q1 turns on connecti ng r hyst to gnd ( figure 4). once the uvlo 1.23v thresh- old is crossed, q1 turns off, resulting in the seri es com- bination of r6, r hyst , and r7, placing the max5069 in normal operating condition. calculate the turn-on voltage (v on ) by using the fol- lowing formula: where v ulr2 is the uvlo/ens 1.23v rising threshold. choose an r hyst value in the 20k ? range. the max5069 turns off when the max5069 uvlo/en falls below the 1.18v falling threshold. the turn-o ff volt- age (v off ) is then defined as: where v ulf2 is the 1.18v uvlo/en falling threshold. boot st ra p u nde rvolt a ge loc k out (m ax 5 0 6 9 a/b) in addition to the externally programmable uvlo fun c- tion offered by the max5069, the max5069a/b feature an additional internal bootstrap uvlo for use in hi gh- voltage power supplies (see the functional diagram ). this allows the device to bootstrap itself during i nitial power-up. the max5069a/b start when v in exceeds the bootstrap uvlo threshold of 23.6v. during startup, the uvlo circuit keeps the pwm com- parator, ilim comparator, oscillator, and output dr ivers shut down to reduce current consumption. once v in reaches 23.6v, the uvlo circuit turns on both the p wm and ilim comparators, as well as the oscillator, an d allows the output driver to switch. if v in drops below 9.7v, the uvlo circuit shuts down the pwm compara- tor, ilim comparator, oscillator, and output driver s, returning the max5069a/b to the startup mode. rr v v r off ulf hyst 76 1 2 / = ?? ? ?? ? r v v r on ulr hyst 61 2 = ?? ? ?? ? m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs ______________________________________________________________________________________ 11 m ax5069a/d 1.23v 1.18v uvlo/en r7 r6 v in figure 2. setting the max5069a/d undervoltage lockout threshold v hyst = v on - v off v off v on figure 3. max5069 hysteresis m ax5069b/c 1.23v 1.18v uvlo/en hyst r hyst r6 r7 v in q1 figure 4. setting the max5069b/c turn-on/turn-off voltages downloaded from: http:///
m ax 5 0 6 9 m ax 5 0 6 9 a/b st a rt up ope ra t ion normally, v in is derived from the tertiary winding of the transformer. however, at startup there is no energy delivered through the transformer; hence, a special bootstrap sequence is required. figure 5 shows the voltages on v in and v cc during startup. initially, both v in and v cc are 0v. after the input voltage is applied, c1 charges through the startup resistor, r1, to an inter- mediate voltage (see figure 1). at this point, the inter- nal regulator begins charging c3 (see figure 5). only 47a of the current supplied by r1 is used by the max5069a/b. the remaining input current charges c1 and c3. the charging of c3 stops when the v cc volt- age reaches approximately 9.5v. the voltage across c1 continues rising until it reaches the wake-up le vel of 23.6v. once v in exceeds the bootstrap uvlo thresh- old, ndrva/ndrvb begin switching the mosfets and energy is transferred to the secondary and tertiary out- puts. if the voltage on the tertiary output builds to high- er than 9.74v (the bootstrap uvlo lower threshold), startup ends and sustained operation commences. if v in drops below 9.74v before startup is complete, the device goes back to low-current uvlo. if this occur s, increase the value of c1 to store enough energy to allow for the voltage at the tertiary winding to bu ild up. startup time considerations for power supplies using the max5069a/b the v in bypass capacitor, c1, supplies current imme- diately after wakeup (see figure 1). the size of c1 and the connection configuration of the tertiary windin g determine the number of cycles available for startu p. large values of c1 increase the startup time and al so supply extra gate charge for more cycles during ini tial startup. if the value of c1 is too small, v in drops below 9.74v because ndrva/ndrvb do not have enough time to switch and build up sufficient voltage acro ss the tertiary output that powers the device. the device goes back into uvlo and does not start. use low-leakage capacitors for c1 and c3. generally, offline power supplies keep typical star tup times to less than 500ms, even in low-line conditio ns (85vac input for universal offline applications or 36vdc for telecom applications). size the startup r esis- tor, r1, to supply both the maximum startup bias of the device (90a) and the charging current for c1 and c 3. the bypass capacitor, c3, must charge to 9.5v, and c1 must charge to 24v, within the desired time peri od of 500ms. because of the internal soft-start time o f the max5069, c1 must store enough charge to deliver cur - rent to the device for at least 2047 oscillator clo ck cycles. to calculate the approximate amount of capa ci- tance required, use the following formula: where i in is the max5069s internal supply current after startup (3.3ma, typ), q gtot is the total gate charge for q1 and q2, f sw is the max5069s programmed output switching frequency, v hyst is the bootstrap uvlo hys- teresis (12v), and t ss is the internal soft-start time (2047 clock cycles x 1 / f osc ). example: i g = (16nc) (250khz) ? 4ma f osc = 500khz t ss = 2047 x (1 / f osc ) = 4.1ms use a 4.7f ceramic capacitor for c1. assuming c1 > c3, calculate the value of r1 as foll ows: where v suvr is the bootstrap uvlo wakeup level (23.6v max), v in(min) is the minimum input supply volt- age for the application (36v for telecom), and i start is the v in supply current at startup (90a, max). i vc ms r vx v ii c suvr in min suvr c start 1 1 1 500 1 05 . () ? ? + c ma ma ms v f 1 33 4 41 12 25 (. ) (. ) . = + = iqx f c iix t v g gtot sw in g ss hyst ( ) = = + 1 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 12 ______________________________________________________________________________________ 100ms/div max5069 v in pin v cc 2v/div 0v 5v/div figure 5. v in and v cc during startup when using the max5069 in bootstrapped mode (see figure 1) downloaded from: http:///
for example: to minimize power loss on this resistor, choose a h igh- er value for r1 than the one calculated above (if a longer startup time can be tolerated). the above startup method applies to a circuit simil ar to the one shown in figure 1. in this circuit, the tertiary winding has the same phase as the secondary wind- ings. thus, the voltage on the tertiary winding at any given time is proportional to the output voltage. t he minimum discharge time of c1 from 22v to 10v must be greater than the soft-start time (t ss ). i vx f ms a r vv aa k c1 24 4 7 500 225 1 36 12 225 90 76 . == ? + = ? m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs ______________________________________________________________________________________ 13 in uvlo/en ndrva ndrvb v cc fb cs pgnd agnd reg5 fltint rt dt scomp comp hyst r1 c1 c2 c3 c4 r2 r3 r4 c5 r6 r7 r5 r8 v out v in q2 q1 c6 r hyst c7 c8 r9 c10 max8515 r13 r14 ps2913 v cc r10 r11 r12 m ax5069b figure 6. secondary-side, regulated, isolated power supply downloaded from: http:///
m ax 5 0 6 9 osc illa t or/sw it c hing fre que nc y use an external resistor at rt to program the max50 69 internal oscillator frequency from 50khz to 2.5mhz. the max5069 ndrva/ndrvb switching frequency is one half of the programmed oscillator frequency with a maximum 50% duty cycle. use the following formula to calculate the internal oscil- lator frequency: where f osc is the oscillator frequency and r rt is a resistor connected from rt to agnd. choose the appropriate resistor at rt to calculate the desired switching frequency (f sw ): for the maximum 50% duty cycle at ndrva/ndrvb, connect dt to reg5. dua l n -cha nne l m osfet sw it c h drive r the max5069 drives two external n-channel mosfets in push-pull isolated power supplies. each mosfet driver operates with a maximum 50% duty cycle. the ndrv_ outputs are supplied by the internal regulato r (v cc ), which is internally set to approximately 9.5v. f or the universal input voltage range, the mosfets used must be able to withstand at least twice the dc lev el of the high-line input voltage. both ndrva and ndrvb can source and sink in excess of 650ma and 1000ma peak current, respectively. dead-time control in typical push-pull designs, it is desirable to ad d some extra delay between the turning off of one mosfet a nd the turning on of the next mosfet (figure 7). the e xtra time ensures that the first mosfet is fully off whe n the other mosfet starts to turn on. this prevents both mosfets from being on simultaneously, thus avoiding shorting out the transformers primary. the max5069 allows the dead-time delay required to turn on the ndrvb fet after the ndrva fet turns off. the dead time can be programmed to a minimum of 30ns to 1 / (0.5 x f sw ). connect a resistor between dt and agnd to set the desired dead time. calculate the dead time usin g the following formula: where r dt is in k ? and the dead time is in ns. ex t e rna l sync hroniza t ion (m ax 5 0 6 9 a/d) the max5069a/d can be synchronized using an exter- nal clock at the sync input. for proper frequency s yn- chronization, the syncs input frequency must be at least 25% higher than the max5069a/d programmed internal oscillator frequency. connect sync to agnd when not using an external clock. i nt e gra t ing fa ult prot e c t ion the integrating fault-protection feature allows tra nsient overcurrent conditions to be ignored for a programm a- ble amount of time, giving the power supply time to behave like a current source to the load. for examp le, this can occur under load-current transients when t he control loop requests maximum current to keep the o ut- put voltage from going out of regulation. program t he fault-integration time by connecting an external su itably sized capacitor to the fltint. under sustained over - current faults, the voltage across this capacitor r amps up towards the fltint shutdown threshold (typically 2.8v). once the threshold is reached, the power sup ply shuts down. a high-value bleed resistor connected i n parallel with the fltint capacitor allows it to dis charge towards the restart threshold (typically 1.6v). onc e this threshold is reached, the supply restarts with a ne w soft-start cycle. dead time r ns dt . () = 60 29 4 rt sw r f = 10 2 11 f r osc rt = 10 11 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 14 ______________________________________________________________________________________ dead time ndrva pwm pwm <50% <50% ndrvb t dt figure 7. max5069 dead-time timing diagram m ax5069a/d agnd rt sync figure 8. external synchronization of the max5069a/d downloaded from: http:///
note that cycle-by-cycle current limiting is provid ed at all times by cs with a threshold of 314mv (typ). th e fault-integration circuit forces a 60a current ont o fltint each time that the current-limit comparator is tripped (see the functional diagram ). use the following formula to calculate the value of the capacitor nec es- sary for the desired shutdown time of the circuit: where i fltint = 60a, t sh is the desired fault-integra- tion time during which current-limit events from th e cur- rent-limit comparator are ignored. for example, a 0 .1f capacitor gives a fault-integration time of 4.7ms. this is an approximate formula. some testing may be required to fine-tune the actual value of the capac itor. to calculate the recovery time, use the following form ula: where t rt is the desired recovery time. choose t rt = 10 x t sh . typical values for t sh range from a few hundred microseconds to a few milliseconds. soft -st a rt the max5069 soft-start feature allows the load volt age to ramp up in a controlled manner, eliminating outp ut- voltage overshoot. soft-start begins after uvlo is deasserted. the voltage applied to the noninverting node of the amplifier ramps from 0 to 1.23v in 2047 oscillator clock cycles (soft-start timeout period) . unlike other devices, the max5069 reference voltage to the internal amplifier is soft-started. this method res ults in superior control of the output voltage under heavy- and light-load conditions. i nt e rna l re gula t ors two internal linear regulators power the max5069 in ter- nal and external control circuits. v cc powers the exter- nal n-channel mosfets and is internally set to approximately 9.5v. the reg5 5v regulator has a 1ma sourcing capability and may be used to provide powe r to external circuitry. bypass v cc and reg5 with 1f and 0.1f high quality capacitors, respectively. us e lower value ceramics in parallel to bypass other unwanted noise signals. bootstrapped operation requires startup through a bleed resistor. do not e xces- sively load the regulators while the max5069 is in the power-up mode. overloading the outputs may cause the max5069 to fail upon startup. error am plifie r the max5069 includes an internal error amplifier th at can regulate the output voltage in the case of a no niso- lated power supply ( figure 1). calculate the output volt- age using the following equation: where v ref = 1.23v. the amplifiers noninverting input internally connects to a digital soft-start referen ce voltage. this forces the output voltage to come up in an ord erly and well-defined manner under all load conditions. slope com pe nsa t ion the max5069 uses an internal-ramp generator for slope compensation. the internal-ramp signal resets at the beginning of each cycle and slews at the rate p ro- grammed by the external capacitor connected at scomp and the resistor at rt. adjust the max5069 slew rate up to 90mv/s using the following equatio n: where r rt is the external resistor at rt that sets the oscil- lator frequency and c scomp is the capacitor at scomp. pwm com pa ra t or the pwm comparator uses the instantaneous current, the error amplifier, and the slope compensation to determine when to switch ndrva and ndrvb off. in normal operation, the n-channel mosfets turns off when: i primary x r cs > v ea C v offset - v scomp where i primary is the current through the n-channel mosfets, v ea is the output voltage of the internal amplifier, v offset is the 1.6v internal dc offset, and v scomp is the ramp function starting at zero and slew- ing at the programmed slew rate (sr). when using th e max5069 in a forward-converter configuration, the f ol- lowing conditions must be met to avoid current-loop subharmonic oscillations: where k = 0.75 and n s and n p are the number of turns on the secondary and primary side of the transforme r, respectively. l is the secondary filter inductor. w hen optimally compensated, the current loop responds to input-voltage transients within one cycle. s p cs out n n k rv l sr = sr rc mv s rt scomp (/) = 165 10 6 v r r xv out ref =+ ?? ? ?? ? 1 9 10 r t c fltint rt fltint . ? 0 595 c ix t v fltint fltint sh . ? 28 m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs ______________________________________________________________________________________ 15 downloaded from: http:///
m ax 5 0 6 9 curre nt lim it the current-sense resistor (r cs ), connected between the source of the mosfet and ground, sets the curre nt limit. the cs input has a voltage trip level (v cs ) of 314mv. use the following equation to calculate the value of r cs : where i pri is the peak current in the primary that flows through the mosfet at full load. when the voltage produced by this current (through the current-sense resistor) exceeds the current-limit c om- parator threshold, the mosfet drivers (ndrva/ ndrvb) quickly terminate the current on-cycle. in m ost cases, a small rc filter is required to filter out the lead- ing-edge spike on the sense waveform. set the corne r frequency to a few mhz above the switching frequenc y. applic a t ions i nform a t ion la yout re c om m e nda t ions keep all pc board traces carrying switching current s as short as possible, and minimize current loops. for universal ac input design, follow all applicabl e safe- ty regulations. offline power supplies may require ul, vde, and other similar agency approvals. contact th ese agencies for the latest layout and component rules. typically, there are two sources of noise emission in a switching power supply: high di/dt loops and high d v/dt surfaces. for example, traces that carry the drain cur- rent often form high di/dt loops. similarly, the he atsink of the mosfet presents a dv/dt source, thus minimize t he surface area of the heatsink as much as possible. to achieve best performance and to avoid ground loops, use a solid ground-plane connection. r v i cs cs pri = h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 16 ______________________________________________________________________________________ se le c t or guide part bootstrap uvlo startup voltage (v) programmable uvlo hysteresis oscillator sync max5069a yes 23.6 no yes max5069b yes 23.6 yes no max5069c no 10.8 yes no max5069d no 10.8 no yes downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs ______________________________________________________________________________________ 17 m ax5069b m ax8515aezk-t r19 r5 r3 r4 r8 c8 c10 c11 r10 pgnd rt uvlo/en scomp dt hyst fb comp fltint reg5 c1 pgnd pgnd pgnd pgnd pgnd r20 c12 c13 c14 r14 r15 r13 r12 r11 c2 c3 c4 q1 si7450dp q2 si7450dp 6t 6t 3t 3t d3 d2 n4148 n4148 d5 d4 n4148 n4148 l2 1mh pgnd d1 25ctq45 c5 c6 c7 l1 10 h ps2911 c15 r17 c16 c17 pgnd gnd out fb in r1 r2 v out 12v up to 15a v cc r21 r16 r17 reg5 in v cc ndrva ndrvb pgnd agnd cs t1 typic a l ope ra t ing circ uit downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs 18 ______________________________________________________________________________________ m ax5069 ndrva ndrvb s q r osc out out dead time thermal shutdown pgnd dt rt error amp pwm comparator current-limit comparator 2.8v/ 1.6v 5k ? 70ns blanking comp fb cs agnd r q s 60 a fltint digital soft-start 314mv 1.23v regulator v cc in reg_ok in v cc 1.23v reference uvlo 1.23v/ 1.18v uvlo/en 21.6v/ 9.74v v in clamp 26v bootstrap uvlo hyst* * reg5 1.6v 5v out sync* slope compensation scomp + + * * max5069a/d * * max5069b/c func t iona l dia gra m chip i nform a t ion transistor count: 4266 process: bicmos downloaded from: http:///
m ax 5 0 6 9 h igh-fre que nc y, curre nt -m ode pwm cont rolle r w it h ac c ura t e osc illa t or a nd dua l fet drive rs maxim cannot assume responsibility for use of any c ircuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the cir cuitry and specifications without notice at any tim e. m a x im i nt e gra t e d produc t s, 1 2 0 sa n ga brie l drive , s unnyva le , ca 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 19 ? 2004 maxim integrated products printed usa is a reg istered trademark of maxim integrated products. pa c k a ge i nform a t ion (the package drawing(s) in this data sheet may not reflect the most current specifications. for the la test package outline info rmation, go to www.maxim-ic.com/packages .) tssop 4.4mm body.eps d 1 1 21-0108 package outline, tssop, 4.40 mm body exposed pad downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX5069DAUE

	To Download MAX5069DAUE Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .