1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. http://www.intersil.com or 407-727-9207 | copyright ? intersil corporation 1999 acts244ms radiation hardened octal non-inverting three-state buffer pinouts 20 pin ceramic dual-in-line mil-std-1835 designator cdip2-t20, lead finish c top view 20 pin ceramic flatpack mil-std-1835 designator cdfp4-f20, lead finish c top view 11 12 13 14 15 16 17 18 20 19 10 9 8 7 6 5 4 3 2 1 ae ai1 bo4 ai2 bo3 ai3 ai4 bo2 bo1 gnd vcc ao1 bi4 ao2 be bi3 ao3 bi2 ao4 bi1 2 3 4 5 6 7 8 120 19 18 17 16 15 14 13 9 10 12 11 ae ai1 bo4 ai2 bo3 ai3 ai4 bo2 bo1 gnd vcc ao1 bi4 ao2 be bi3 ao3 bi2 ao4 bi1 features ? devices qml quali?ed in accordance with mil-prf-38535 ? detailed electrical and screening requirements are contained in smd# 5962-96718 and intersils qm plan ? 1.25 micron radiation hardened sos cmos ? total dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300k rad (si) ? single event upset (seu) immunity: <1 x 10 -10 errors/bit/day (typ) ? seu let threshold . . . . . . . . . . . . . . . . . . . . . . . >100 mev-cm 2 /mg ? dose rate upset . . . . . . . . . . . . . . . . >10 11 rad (si)/s, 20ns pulse ? dose rate survivability . . . . . . . . . . . >10 12 rad (si)/s, 20ns pulse ? latch-up free under any conditions ? military temperature range . . . . . . . . . . . . . . . . . . -55 o c to +125 o c ? signi?cant power reduction compared to alsttl logic ? dc operating voltage range . . . . . . . . . . . . . . . . . . . . 4.5v to 5.5v ? input logic levels - vil = 0.8v max - vih = vcc/2 min ? input current 1 m a at vol, voh ? fast propagation delay . . . . . . . . . . . . . . . 14.5ns (max), 10ns (typ) description the intersil acts244ms is a radiation hardened octal non-inverting three-state buffer having two active low enable inputs. the acts244ms utilizes advanced cmos/sos technology to achieve high-speed operation. this device is a member of radiation hardened, high-speed, cmos/sos logic family. the acts244ms is supplied in a 20 lead ceramic flatpack (k suf?x) or a dual-in-line ceramic package (d suf?x). january 1996 ordering information part number temperature range screening level package 5962f9671801vrc -55 o c to +125 o c mil-prf-38535 class v 20 lead sbdip 5962f9671801vxc -55 o c to +125 o c mil-prf-38535 class v 20 lead ceramic flatpack acts244d/sample 25 o c sample 20 lead sbdip ACTS244K/sample 25 o c sample 20 lead ceramic flatpack acts244hmsr 25 o c die die spec number 518784 file number 3187.1
2 acts244ms functional diagram truth table inputs output ae, be ain, bin aon, bon lll lhh hxz note: h = high voltage level, l = low voltage level, x = immaterial, z = high impedance p n ae ai1 ao1 p n ai2 ao2 p n ai3 ao3 p n ai4 ao4 note: (1 circuit of 2) 1(19) 2(11) 4(13) 6(15) 8(17) 18(9) 16(7) 14(5) 12(3) spec number 518784
3 acts244ms die characteristics die dimensions: 100 x 100 (mils) 2.54 x 2.54 (mm) metallization: type: alsi metal 1 thickness: 7.125k ? 1.125k ? metal 2 thickness: 9k ? 1k ? glassivation: type: sio 2 thickness: 8k ? 1k ? worst case current density: < 2.0 x 10 5 a/cm 2 bond pad size: 110 x 110 ( m m) 4.4 x 4.4 (mils) metallization mask layout acts244ms bo4 (3) ai2 (4) bo3 (5) ai3 (6) bo2 (7) ai4 (8) vcc bo1 (9) ao4 (12) (13) bi2 (14) ao3 (15) bi3 (16) ao2 (17) bi4 (18) ao1 (20) vcc (20) ae (1) ai1 (2) be (19) (11) bi1 (10) gnd (10) gnd spec number 518784 all intersil semiconductor products are manufactured, assembled and tested under iso9000 quality systems certi?cation. intersil products are sold by description only. intersil corporation reserves the right to make changes in circuit design and/o r speci?cations at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnishe d by intersil is believed to be accurate and reliable. however, no responsibility is assumed by intersil or its subsidiaries for its use; nor for any infringements of p atents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of intersil or its subsidiaries. for information regarding intersil corporation and its products, see web site http://www.intersil.com
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