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1 of 17 note: some revisions of this device may incor porate deviations from published specifications known as erra ta. multiple revisions of any device may be simultaneously available through various sales channel s. for information about device errata, click here: www.maxim-ic.com/errata. features ? integrated nv sram, real-time clock (rtc), crystal, power-f ail control circuit, and lithium energy source ? clock registers are accessed identically to the static ram; these registers reside in the 16 top ram locations ? century byte register (i.e., y2k compliant) ? totally nonvolatile wi th over 10 years of operation in the absence of power ? precision power-on reset ? programmable watchdog timer and rtc alarm ? bcd-coded year, month, date, day, hours, minutes, and seconds with automatic leap year compensation valid up to the year 2100 ? battery voltage-level indicator flag ? power-fail write protection allows for ? 10% v cc power-supply tolerance ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? also available in industrial temperature range: -40c to +85c pin configuration pin description a0?a18 - address input dq0?dq7 - data input/outputs irq /ft - interrupt, frequency test output (open drain) rst - power-on reset output (open drain) ce - c h i p e n a b l e oe - output enable we - write enable v cc - power-supply input gnd - ground x1, x2 - crystal connection v bat - battery connection ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram www.maxim-ic.com 1 irq /ft 2 3 a15a16 r st v cc w e o e c e dq7dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 a17a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 a18 x1 gnd v bat x2 powercap module board (uses ds9034pcx powercap ) maxim ds1557 top view 19-5501; rev 9/10 downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 2 of 17 ordering information part temp range voltage (v) pin-package top mark** ds1557p-70+ 0c to +70c 5.0 34 powercap* ds1557p+70 ds1557p-70ind+ -40c to +85c 5.0 34 powercap* ds1557p+70 ind DS1557WP-120+ 0c to +70c 3.3 34 powercap* ds1557wp+120 DS1557WP-120ind+ -40c to +85c 3.3 34 powercap* ds1557wp+120 ind + denotes a lead(pb)-free/ rohs-compliant package. * ds9034pcx+ or ds9034i-pcx+ (powercap) requi red. must be ordered separately. *an ?ind? on the top mark denotes an industrial temperat ure grade device. description the ds1557 is a full-function, year-2000-compliant (y 2kc), real-time clock/ca lendar (rtc) with an rtc alarm, watchdog timer, power-on reset, battery monitor, and 512k x 8 nonvolatile static ram. user access to all registers within the ds1557 is accomplishe d with a byte-wide interface as shown in figure 1. the rtc registers contai n century, year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for day of month and leap year are made automatically. the rtc registers are double-buffered into an internal and external set. the user has direct access to the external set. clock/calendar updates to the external set of registers ca n be disabled and enabled to allow the user to access static data. assuming the internal oscillator is turned on, the internal set of registers is continuously updated; this occurs rega rdless of external regi sters settings to guara ntee that accurate rtc information is always maintained. the ds1557 has interrupt ( irq /ft) and reset ( rst ) outputs which can be used to control cpu activity. the irq /ft interrupt output can be used to generate an external interrupt when the rtc register values match user programmed alarm values. the interrupt is always available while the device is powered from the system supply and can be programmed to occur when in the battery-backed state to serve as a system wakeup. either the irq /ft or rst outputs can also be used as a cpu watchdog timer, cpu activity is monitored and an interrupt or reset output will be activated if the correct activity is not detected within programmed limits. the ds1557 power-on reset can be us ed to detect a system power down or failure and hold the cpu in a safe reset state until normal power returns and stabilizes; the rst output is used for this function. the ds1557 also contains its own power-fail circuitr y, which automatically deselects the device when the v cc supply enters an out-of-tolerance condition. this feature provides a high degree of data security during unpredictable system operation brought on by low v cc levels. downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 3 of 17 figure 1. block diagram table 1. operating modes v cc ce oe we dq0?dq7 mode power v ih x x high-z deselect standby v il x v il d in write active v il v il v ih d out read active v cc > v pf v il v ih v ih high-z read active v so < v cc ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 4 of 17 data write mode the ds1557 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring transition of we or ce . the addresses must be held valid throughout the cycle. ce and we must return inactive for a minimum of t wr prior to the initiation of a subsequent read or write cycle. data in must be valid t ds prior to the end of the write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low, the data bus can become active w ith read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active. data retention mode the 5v device is fully accessible and data can be written and read only when v cc is greater than v pf . however, when v cc is below the power-fail point v pf (point at which writ e protection occurs) the internal clock registers and sram are blocked from any access. when v cc falls below the battery switch point v so (battery supply level), device power is switched from the v cc pin to the internal backup lithium battery. rtc operation and sr am data are maintained from the battery until v cc is returned to nominal levels. the 3.3v device is fully accessible and data can be written and read only when v cc is greater than v pf . when v cc falls below v pf , access to the device is inhibited. if v pf is less than v so , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v pf . if v pf is greater than v so , the device power is switched from v cc to the internal backup lithium battery when v cc drops below v so . rtc operation and sram data are ma intained from the battery until v cc is returned to nominal levels. all control, data, and address signa ls must be powered down when v cc is powered down. battery longevity the ds1557 has a lithium power source that is design ed to provide energy for the clock activity, and clock and ram data retention when the v cc supply is not present. the capab ility of this internal power supply is sufficient to power the ds1557 continuously for the life of the equipment in which it is installed. for specification purposes, the life expectancy is 10 years at 25 ? c with the internal clock oscillator running in the absence of v cc . internal battery monitor the ds1557 constantly monitors the battery voltage of the internal battery. the battery low flag (blf) bit of the flags register (b4 of 7fff0h) is not writabl e and should always be a 0 when read. if a 1 is ever present, an exhausted lithium energy source is indi cated and both the contents of the rtc and ram are questionable. power-on reset a temperature compensated comparator circuit monitors the level of v cc . when v cc falls to the power fail trip point, the rst signal (open drain) is pulled low. when v cc returns to nominal levels, the rst signal continues to be pulled low for a period of 40 ms to 200 ms. the pow er-on reset function is independent of the rtc oscillator and thus is operational whether or not the oscillator is enabled. downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 5 of 17 clock operations table 2 and the following paragraphs describe th e operation of rtc, alar m, and watchdog functions. table 2. register map data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function/range 7ffffh 10 year year year 00-99 7fffeh x x x 10 month month month 01-12 7fffdh x x 10 date date date 01-31 7fffch x ft x x x day day 01-07 7fffbh x x 10 hour hour hour 00-23 7fffah x 10 minutes minutes minutes 00-59 7fff9h osc 10 seconds seconds seconds 00-59 7fff8h w r 10 century century control 00-39 7fff7h wds bmb4 bmb3 bmb2 bmb1 bmb0 rb1 rb0 watchdog 7fff6h ae y abe y y y y y interrupts 7fff5h am4 y 10 date date alarm date 01-31 7fff4h am3 y 10 hours hours alarm hours 00-23 7fff3h am2 10 minutes minutes alarm minutes 00-59 7fff2h am1 10 seconds seconds alarm seconds 00-59 7fff1h y y y y y y y y unused 7fff0h wf af 0 blf 0 0 0 0 flags x = unused, read/writeable under write and read bit control ae = alarm flag enable y = unused, read/writeable without write and read bit control ft = frequency test bit osc = oscillator start/stop bit abe = alarm in battery-backup mode enable w = write bit am1 to am4 = alarm mask bits r = read bit wf = watchdog flag wds = watchdog steering bit af = alarm flag bmb0 to bmb4 = watchdog multiplier bits 0 = 0 (read only) rb0 to rb1 = watchdog resolution bits blf = battery low flag downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 6 of 17 clock oscillator control the clock oscillator may be stopped at any time. to increase the shelf life of the backup lithium battery source, the oscillator can be turned off to minimize current drain from the battery. the osc bit is the msb of the seconds register (b7 of 7fff9h). setting it to a 1 stops the os cillator, setting to a 0 starts the oscillator. the ds1557 is shipped from maxim with the clock oscillator turned off, osc bit set to a 1. reading the clock when reading the rtc data, it is recommended to halt updates to the external set of double-buffered rtc registers. this puts the external registers into a static state allowing data to be read without register values changing during the re ad process. normal updates to the internal registers continue while in this state. external updates are halted wh en a 1 is written into the read bit, b6 of the control register (7fff8h). as long as a 1 remains in the control regist er read bit, updating is halted. after a halt is issued, the registers reflect the rtc count (day, date, and time) that was current at the moment the halt command was issued. normal updates to the external set of registers will resume within 1 second after the read bit is set to a 0 for a minimum of 500 ? s. the read bit must be a zero for a minimum of 500 ? s to ensure the external registers will be updated. setting the clock the msb bit, b7, of the control register is the write bit. setting the write bit to a 1, like the read bit, halts updates to the ds1557 (7fff8h-7ffffh) registers. af ter setting the write bit to a 1, rtc registers can be loaded with the desired rtc count (day, date , and time) in 24-hour bcd format. setting the write bit to a 0 then transfers the values written to the internal rtc regi sters and allows normal operation to resume. clock accuracy the ds1557 and ds9034pcx are each individually te sted for accuracy. once mounted together, the module will typically keep time accuracy to within ? 1.53 minutes per month (35 ppm) at 25c and does not require additional calibration. for this reason, met hods of field clock calibration are not available and not necessary. the electrical enviro nment also affects clock accuracy and caution should be taken to place the rtc in the lowest-level em i section of the pc board layout. for additional information, refer to application note 58. frequency test mode the ds1557 frequency test mode uses the open drain irq /ft output. with the oscillator running, the irq /ft output will toggle at 512 hz when the ft bit is a 1, the alarm flag enable bit (ae) is a 0, and the watchdog steering bit (wds) is a 1 or the watchdog register is reset (register 7fff7h = 00h). the irq /ft output and the frequency test mode can be us ed as a measure of the actual frequency of the 32.768khz rtc oscillator. the irq /ft pin is an open-drain output th at requires a pullup resistor for proper operation. the ft bit is cleared to a 0 on power-up. downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 7 of 17 using the clock alarm the alarm settings and control fo r the ds1557 reside with in registers 7fff2h-7 fff5h. register 7fff6h contains two alarm enable bits: alarm enable (ae) and alarm in backup enable (abe). the ae and abe bits must be set as described below for the irq /ft output to be activated for a matched alarm condition. the alarm can be programmed to activate on a specific day of the month or repeat every day, hour, minute, or second. it can also be programmed to go o ff while the ds1557 is in th e battery-backed state of operation to serve as a system wa keup. alarm mask bits am1 to am4 control the alarm mode. table 3 shows the possible settings. configur ations not listed in the table defa ult to the once per second mode to notify the user of an incorrect alarm setting. table 3. alarm mask bits am4 am3 am2 am1 alarm rate 1 1 1 1 once per second 1 1 1 0 when seconds match 1 1 0 0 when minutes and seconds match 1 0 0 0 when hours, minutes, and seconds match 0 0 0 0 when date, hours, minutes, and seconds match when the rtc register values match alarm register settings, the alarm flag b it (af) is set to a 1. if alarm flag enable (ae) is also set to a 1, the alarm condition activates the irq /ft pin. the irq /ft signal is cleared by a read or write to the flags re gister (address 7fff0h) as shown in figure 2 and 3. when ce is active, the irq /ft signal may be cleared by having the ad dress stable for as short as 15 ns and either oe or we active, but is not guaranteed to be cleared unless t rc is fulfilled. the alarm flag is also cleared by a read or write to the flags register but the flag will not change states until the end of the read/write cycle and the irq /ft signal has been cleared. figure 2. clearing irq waveforms c c e e , , downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 8 of 17 figure 3. clearing irq waveforms the irq /ft pin can also be activated in the battery-backed mode. the irq /ft will go low if an alarm occurs and both abe and ae are set. the abe and ae bits are cleared duri ng the power-up transition, however an alarm generated during power-up will set af. therefore, the af bit can be read after system power-up to determine if an alarm was generated during the power-up sequence. figure 4 illustrates alarm timing during the battery-bac kup mode and power-up states. figure 4. backup mode alarm waveforms 1 1 8 8 ce =0 7fff0h downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 9 of 17 using the watchdog timer the watchdog timer can be used to detect an out-of-control proce ssor. the user programs the watchdog timer by setting the desired amount of timeout into the 8-bit watchdog regist er (address 7fff7h). the five watchdog register bits bmb4 to bmb0 store a binary multiplier and the two lower order bits rb1 to rb0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11= 4 seconds. the watchdog time-out value is then determined by the mu ltiplication of the 5-bit multiplier value with the 2- bit resolution value. (for example: writing 00001110 in the watchdog register = 3 x 1 second or 3 seconds.) if the processor does not reset the timer within the specified peri od, the watchdog flag (wf) is set and a processor interrupt is generated and st ays active until either the watchdog flag (wf) is read or the watchdog register (7fff7h) is read or written. the most significant bit of the wa tchdog register is the watchdog steering bit (wds). when set to a 0, the watchdog will activate the irq /ft output when the watchdog times out. when wds is set to a 1, the watchdog will output a negative pulse on the rst output for a duration of 40 ms to 200 ms. the watchdog register (7fff7h) and the ft bit will reset to a 0 at the end of a watchdog timeout when the wds bit is set to a 1. the watchdog timer resets when the processor perfor ms a read or write of the watchdog register. the timeout period then starts over. writing a value of 00h to the watchdog register disables the watchdog timer. the watchdog function is automatically disa bled upon power-up and the watchdog register is cleared. if the watchdog function is set to output to the irq /ft output and the frequency test function is activated, the watchdog function prevails and the frequency test function is denied. power-on default states upon application of power to the device, th e following register bits are set to a 0: wds = 0, bmb0 to bmb4 = 0, rb0 to rb1 = 0, ae = 0, abe = 0. downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 10 of 17 absolute maxi mum ratings voltage range on any pin relative to ground-0.3v to +6.0v storage temperature range... .......-55c to +125c lead temperature (soldering, 10s) .................... ................... .................. .................. ........... ........ .......+260c soldering temperature (reflow). +260c this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in t he operation sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods of time may affect reliabilit y . operating range range temp range v cc commercial 0c to +70c 3.3v ? 10% or 5v ? 10% industrial -40c to +85c 3.3v ? 10% or 5v ? 10% recommended dc oper ating conditions (t a = over the operating range) parameter symbol conditions min typ max units v ih v cc = 5v ? 10% 2.2 v cc + 0.3v v logic 1 voltage all inputs (note 1) v ih v cc = 3.3v ? 10% 2.0 v cc + 0.3v v v il v cc = 5v ? 10% -0.3 +0.8 logic 0 voltage all inputs (note 1) v il v cc = 3.3v ? 10% -0.3 +0.6 dc electrical characteristics (v cc = 5.0v ? 10%, t a = over the operating range.) parameter symbol conditions min typ max units active supply current i cc (notes 2, 3, 11) 45 90 ma ttl standby current ( ce = v ih ) i cc1 (notes 2, 3) 3 6 ma cmos standby current ( ce ?? v cc - 0.2v) i cc2 (notes 2, 3) 2 6 ma input leakage current (any input) i il -1 +1 ? a output leakage current (any output) i ol -1 +1 ? a output logic 1 voltage (i out = -1.0 ma) v oh (note 1) 2.4 v v ol1 i out = 2.1 ma, dq0?7 outputs (note 1) 0.4 v output logic 0 voltage v ol2 i out = 7.0 ma, irq /ft, and rst outputs (notes 1, 5) 0.4 v write protection voltage v pf (note 1) 4.20 4.50 v battery switchover voltage v so (notes 1, 4) v bat v downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 11 of 17 dc electrical characteristics ( v cc = 3.3v 10% , t a = over the operating range.) parameter symbol conditions min typ max units active supply current i cc (notes 2, 3, 11) 20 30 ma ttl standby current ( ce = v ih ) i cc1 (notes 2, 3) 2 6 ma cmos standby current ( ce ?? v cc - 0.2v) i cc2 (notes 2, 3) 1 4 ma input leakage current (any input) i il -1 +1 ? a output leakage current (any output) i ol -1 +1 ? a output logic 1 voltage (i out = -1.0 ma) v oh (note 1) 2.4 v v ol1 i out = 2.1 ma, dq0?7 outputs (note 1) 0.4 v output logic 0 voltage v ol2 i out = 7.0 ma, irq /ft and rst outputs (notes 1, 5) 0.4 v write protection voltage v pf (note 1) 2.75 2.97 v battery switchover voltage v so (notes 1, 4) v bat or v pf v figure 5. read cycle timing diagram downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 12 of 17 ac characteristicsread cycle (t a = over the operating range) v cc = 5.0v ? 10% v cc = 3.3v ? 10% parameter symbol min max min max units read cycle time t rc 70 120 ns address access time t aa 70 120 ns ce to dq low-z t cel 5 5 ns ce access time t cea 70 120 ns ce data off time t cez 25 40 ns oe to dq low-z t oel 5 5 ns oe access time t oea 35 100 ns oe data off time t oez 25 35 ns output hold from address t oh 5 5 ns ac characteristicswrite cycle (t a = over the operating range) v cc = 5.0v ? 10% v cc = 3.3v ? 10% parameter symbol min max min max units write cycle time t wc 70 120 ns address access time t as 0 0 ns we pulse width t wew 50 100 ns ce pulse width t cew 60 110 ns data setup time t ds 30 80 ns data hold time (note 9) t dh1 5 5 ns data hold time (note 10) t dh2 5 5 ns address hold time (note 9) t ah1 5 0 ns address hold time (note 10) t ah2 5 5 ns we data off time t wez 25 40 ns write recovery time t wr 5 10 ns downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 13 of 17 figure 6. write cycle timing, write-enable controlled figure 7. write cycle timi ng, chip-enable controlled downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 14 of 17 power-up/down characteristics5v (v cc = 5.0v 10%, t a = over the operating range.) parameter symbol conditions min typ max units ce or we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc fall time: v pf(min) to v so t fb 10 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s v pf to rst high t rec 40 200 ms expected data-retention time (oscillator on) t dr (note 6) 10 years figure 8. power-up/down waveform timing5v device downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 15 of 17 power-up/down char acteristics3.3v (v cc = 3.3v 10%, t a = over the operating range.) parameter symbol conditions min typ max units ce or we at v ih , before power-down t pd 0 ? s v cc fall time: v pf(max) to v pf(min) t f 300 ? s v cc rise time: v pf(min) to v pf(max) t r 0 ? s v pf to rst high t rec 40 200 ms expected data-retention time (oscillator on) t dr (note 6) 10 years figure 9. power-up/down w aveform timing3.3v device capacitance (t a = +25c) parameter symbol conditions min typ max units capacitance on all input pins c in (note 1) 14 pf capacitance on irq /ft, rst , and dq pins c io (note 1) 10 pf downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 16 of 17 ac test conditions output load: 50 pf + 1ttl gate input pulse levels: 0 to 3.0v timing measurement reference levels: input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns notes: 1) voltage referenced to ground. 2) typical values are at 25 ? c and nominal supplies. 3) outputs are open. 4) battery switchover occurs at the lower of either the battery voltage or v pf . 5) the irq /ft and rst outputs are open drain. 6) data-retention time is at +25 ? c. 7) maxim recommends that powercap module bases experi ence one pass through so lder reflow oriented with the label side up (?live-bug?). 8) hand soldering and touch-up: do not touch or appl y the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad, and apply solder. to remove the part, apply flux, heat the lead fram e pad until the solder reflow, a nd use a solder wick to remove solder. 9) t ah1 , t dh1 are measured from we going high. 10) t ah2 , t dh2 are measured from ce going high. 11) t wc = 200ns. package information for the latest package outline information and la nd patterns, go to www.maxim-ic.com/packages . note that a ?+?, ?#?, or ?-? in the package code indicates rohs stat us only. package drawings may show a di fferent suffix character, but the drawing pertains to the package re gardless of rohs status. package type package code ou tline no. land pattern no. 34 pwrcp pc2+1 21-0246 ? downloaded from: http:///
ds1557 4meg, nonvolatile, y2k-compliant timekeeping ram 17 of 17 maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the ci rcuitry and specifications wi thout notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2010 maxim integrated products maxim and the dallas logo are registered trademarks of maxim integrated products. revision history revision date description pages changed 9/10 updated the ordering information table to include only lead-free parts; updated the storage temperature range and soldering temperatur e and added the lead temperature to the absolute maximum ratings section; added note 11 to the i cc parameter in the dc electrical characteristics tables (for 5.0v and 3.3v) and the notes section; re placed the package outline drawings with the package information table 2, 10, 11, 16 downloaded from: http:///

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