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integrated silicon solution, inc. ? 1-800-379-4774 1 rev. a 04/17/01 issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2001, integrated silicon solution, inc. is61sp6464 issi ? features ? fast access time: ? 133, 117, 100 mhz; 6 ns (83 mhz); 7 ns (75 mhz); 8 ns (66 mhz) internal self-timed write cycle individual byte write control and global write clock controlled, registered address, data and control pentium? or linear burst sequence control using mode input five chip enables for simple depth expansion and address pipelining common data inputs and data outputs power-down control by zz input jedec 128-pin tqfp 14mm x 20mm package single +3.3v power supply control pins mode upon power-up: ? mode in interleave burst mode ? zz in normal operation mode these control pins can be connected to gnd q or v ccq to alter their power-up state description the issi is61sp6464 is a high-speed, low-power synchro- nous static ram designed to provide a burstable, high- performance, secondary cache for the i486?, pentium?, 680x0?, and powerpc? microprocessors. it is organized as 65,536 words by 64 bits, fabricated with issi 's advanced cmos technology. the device integrates a 2-bit burst counter, high-speed sram core, and high-drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. write cycles are internally self-timed and are initiated by the rising edge of the clock input. write cycles can be from one to eight bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. bw1 controls i/o1-i/o8, bw2 controls i/o9-i/o16, bw3 con- trols i/o17-i/o24, bw4 controls i/o25-i/o32, bw5 controls i/o33-i/o40, bw6 controls i/o41-i/o48, bw7 controls i/o49- i/o56, bw8 controls i/o57-i/o64, conditioned by bwe being low. a low on gw input would cause all bytes to be written. bursts can be initiated with either adsp (address status processor) or adsc (address status cache controller) input pins. subsequent burst addresses can be generated inter- nally by the is61sp6464 and controlled by the adv (burst address advance) input pin. asynchronous signals include output enable ( oe ), sleep mode input (zz), and burst mode input (mode). a high input on the zz pin puts the sram in the power-down state. when zz is pulled low (or no connect), the sram normally operates after the wake-up period. a low input, i.e., gnd q , on mode pin selects linear burst. a v ccq (or no connect) on mode pin selects interleaved burst. 64k x 64 synchronous pipeline static ram april 2001
is61sp6464 issi ? 2 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 block diagram 16 binary counter a15-a0 bw1 gw clr ce clk q0 q1 mode a0' a0 a1 a1' clk adv adsc adsp 14 16 address register ce d clk q dq57-dq64 byte write registers d clk q dq8-dq1 byte write registers d clk q enable register ce d clk q enable delay register d clk q bwe bw8 ce ce2 ce2 ce3 ce3 64k x 64 memory array 64 input registers clk output registers clk 64 oe 8 64 oe data[64:1]
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 3 rev. a 04/17/01 pin configuration 128-pin tqfp vccq i/o 32 i/o 31 i/o 30 i/o 29 i/o 28 i/o 27 i/o 26 i/o 25 i/o 24 i/o 23 i/o 22 gndq vccq i/o 21 i/o 20 i/o 19 i/o 18 i/o 17 i/o 16 i/o 15 i/o 14 i/o 13 i/o 12 gndq vccq i/o 11 i/o 10 i/o 9 i/o 8 i/o 7 i/o 6 i/o 5 i/o 4 i/o 3 i/o 2 i/o 1 gndq vccq ce3 ce2 ce3 ce2 gnd vcc ce bw8 bw7 bw6 bw5 oe clk bwe gw bw4 bw3 gnd vcc bw2 bw1 adsc adsp adv gndq gndq i/o 33 i/o 34 i/o 35 i/o 36 i/o 37 i/o 38 i/o 39 i/o 40 i/o 41 i/o 42 i/o 43 vccq gndq i/o 44 i/o 45 i/o 46 i/o 47 i/o 48 i/o 49 i/o 50 i/o 51 i/o 52 i/o 53 vccq gndq i/o 54 i/o 55 i/o 56 i/o 57 i/o 58 i/o 59 i/o 60 i/o 61 i/o 62 i/o 63 i/o 64 vccq 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 gndq nc mode a15 a14 a13 vcc gnd a12 a11 a10 a9 a8 nc a7 a6 a5 a4 a3 vcc gnd a2 a1 a0 zz vccq 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 pin descriptions a0-a15 address inputs clk clock adsp processor address status adsc controller address status adv burst address advance bw1 - bw8 synchronous byte write enable bwe byte write enable gw global write enable ce , ce2, ce2 , synchronous chip enable ce3, ce3 oe output enable i/o1-i/o64 data input/output zz sleep mode mode burst sequence mode v cc +3.3v power supply gnd ground v ccq isolated output buffer supply: +3.3v nc no connect gnd q isolated output buffer ground
is61sp6464 issi ? 4 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 truth table address operation used ce3 ce2 ce3 ce2 ce adsp adsc adv write oe clk i/o deselected, power-down none x x x x h x l x x x l-h high-z deselected, power-down none l x x x l l xxxxl-hhi gh-z deselected, power-down none x l x x l l xxxxl-hhi gh-z deselected, power-down none x x h x l l xxxxl-hhi gh-z deselected, power-down none x x x h l l xxxxl-hhi gh-z deselected, power-down none l x x x l h l x x x l-h high-z deselected, power-down none x l x x l h l x x x l-h high-z deselected, power-down none x x h x l h l x x x l-h high-z deselected, power-down none x x x h l h l x x x l-h high-z read cycle, begin burst external h h l l l l x x x l l-h dout read cycle, begin burst external h h l l l l x x x h l-h high-z write cycle, begin burst external h h l l l h l x l x l-h din read cycle, begin burst external h h l l l h l x h l l-h dout read cycle, begin burst external h h l l l h l x h h l-h high-z read cycle, continue burst next x x x x x h h l h l l-h dout read cycle, continue burst next x x x x x h h l h h l-h high-z read cycle, continue burst next x x x x h x h l h l l-h dout read cycle, continue burst next x x x x h x h l h h l-h high-z write cycle, continue burst next x x x x x h h l l x l-h din write cycle, continue burst next x x x x h x h l l x l-h din read cycle, suspend burst current x x x x x hhhhll-h dout read cycle, suspend burst current x x x x x hhhhhl-hhi gh-z read cycle, suspend burst current x x x x h x h h h l l-h dout read cycle, suspend burst current x x x x h x hhhhl-hhi gh-z write cycle, suspend burst current x x x x x h h h l x l-h din write cycle, suspend burst current x x x x h x h h l x l-h din notes: 1. all inputs except oe must meet setup and hold times for the low-to-high transition of clock (clk). 2. wait states are inserted by suspending burst. 3. x means don't care. write =l means any one or more byte write enable signals ( bw 1- bw 8) and bwe are low or gw is low. write =h means all byte write enable signals are high. 4. for a write operation following a read operation, oe must be high before the input data required setup time and held high throughout the input data hold time. 5. adsp low always initiates an internal read at the low-to-high edge of clock. a write is performed by setting one or more byte write enable signals and bwe low or gw low for the subsequent l-h edge of clock.
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 5 rev. a 04/17/01 asynchronous truth table operation zz oe i/o status pipelined read l l dout pipelined read l h high-z write l l high-z write l h din deselect l x high-z sleep h x high-z write truth table operation gw bwe bw8 bw7 bw6 bw5 bw4 bw3 bw2 bw1 read hhxx xxxxx x read h lhh hhhhh h write all bytes h l l l l l l l l l write all bytes l x x x x x x x x x write byte 1 h l h h h h h h h l write byte 2 h l h h h h h h l h write byte 3 h l h h h h h l h h write byte 4 h l h h h h l h h h write byte 5 h l h h h l h h h h write byte 6 h l h h l h h h h h write byte 7 h l h l h h h h h h write byte 8 h l l h h h h h h h interleaved burst address table (mode = v cc or no connect) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00
is61sp6464 issi ? 6 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 linear burst address table (mode = gnd q ) 0,0 1,0 0,1 a1 ? , a0 ? = 1,1 absolute maximum ratings (1) symbol parameter value unit t bias temperature under bias ? 10 to +85 c t stg storage temperature ? 55 to +150 c p d power dissipation 1.0 w i out output current (per i/o) 100 ma v in , v out voltage relative to gnd for i/o pins ? 0.5 to v ccq + 0.3 v v in voltage relative to gnd for ? 0.5 to 5.5 v for address and control inputs v cc voltage on vcc supply relatiive to gnd ? 0.5 to 4.6 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high-z at power up. operating range range ambient temperature v cc commercial 0 c to +70 c 3.3v +10%, ? 5% industrial ? 40 c to +85 c 3.3v +10%, ? 5%
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 7 rev. a 04/17/01 dc electrical characteristics (1) (over operating range) symbol parameter test conditions min. max. unit v oh output high voltage i oh = ? 4.0 ma 2.4 ? v v ol output low voltage i ol = 8 ma ? 0.4 v v ih input high voltage 2.0 v ccq + 0.3 v v il input low voltage ? 0.3 0.8 v i li input leakage current gnd - v in - v ccq (2) com. ? 22a ind. ? 10 10 i lo output leakage current gnd - v out - v ccq , oe = v ih com. ? 22a ind. ? 10 10 capacitance (1,2) symbol parameter conditions max. unit c in input capacitance v in = 0v 5 pf c out input/output capacitance v out = 0v 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25 c, f = 1 mhz, vcc = 3.3v. ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing 1.5v and reference level output load see figures 1 and 2 ac test loads output buffer z o = 50 ? 1.5v 50 ? 30 pf figure 1 figure 2 317 ? 5 pf including jig and scope 351 ? output 3.3v
is61sp6464 issi ? 8 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 power supply characteristics (over operating range) -133 -117 -100 -6 -7 -8 symbol parameter test conditions max. max. max. max. max. max. uni t i cc ac operating device selected, com. 280 270 250 200 170 150 ma supply current all inputs = v il or v ih ind. ? 290 270 220 190 170 oe = v ih , cycle time t kc min. i sb 1 standby current device deselected, com. 70 70 70 70 70 70 ma ttl inputs v cc = max., ind. ? 80 80 80 80 80 all inputs = v ih or v il clk cycle time t kc min. i sb 2 standby current device deselected, com. 20 20 20 20 20 20 ma cmos inputs v cc = max., ind. ? 30 30 30 30 30 v in = v cc 0.2v, or v in - 0.2v clk cycle time t kc min. i zz power-down mode zz = v ccq , clk running com. 20 20 20 20 20 20 ma current all inputs - gnd + 0.2v ind. ? 30 30 30 30 30 or v cc ? 0.2v notes: 1. the mode pin has an internal pullup. zz pin has an internal pull-down. this pin may be a no connect, tied to gnd, or tied to v ccq . 2. the mode pin should be tied to vcc or gnd. it exhibits 10 a maximum leakage current when tied to - gnd + 0.2v or vcc ? 0.2v.
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 9 rev. a 04/17/01 read cycle switching characteristics (over operating range) -133 mhz -117 mhz -100 mhz symbol parameter min. max. min. max. min. max. unit t kc cycle time 7.5 ? 8.5 ? 10 ? ns t kh clock high time 3 ? 3.4 ? 4 ? ns t kl clock low time 3 ? 3.4 ? 4 ? ns t kq clock access time ? 5 ? 5 ? 5ns t kqx (1) clock high to output invalid 1.5 ? 1.5 ? 2.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 2 5 2 5 2 5 ns t oeq output enable to output valid ? 5 ? 5 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z ?? ?? 25ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t avs address advance setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? 0.5 ? ns notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp6464 issi ? 10 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 read cycle switching characteristics (over operating range) -6 ns -7 ns -8 ns symbol parameter min. max. min. max. min. max. unit t kc cycle time 12 ? 13 ? 15 ? ns t kh clock high time 4.5 ? 5 ? 6 ? ns t kl clock low time 4.5 ? 5 ? 6 ? ns t kq clock access time ? 6 ? 7 ? 8ns t kqx (1) clock high to output invalid 2.5 ? 3 ? 3 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 2 5 2 5 2 6 ns t oeq output enable to output valid ? 5 ? 5 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z 2 5 2 5 2 6 ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t avs address advance setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? 0.5 ? ns notes: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 11 rev. a 04/17/01 read cycle timing single read high-z high-z data out data in oe ce2, ce3 ce2, ce3 ce bw8-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 rd2 1a 2c 2d 3a unselected burst read t kqx t kc t kl t kh t ss t sh t ss t sh t as t ah t ws t wh t ws t wh rd3 t ces t ceh t ces t ceh t ces t ceh ce3, ce2 and ce2, ce3 only sampled with adsp or adsc ce masks adsp unselected with ce2, ce3 t oeq t oeqx t oelz t kqlz t kq t oehz t kqhz adsc initiate read adsp is blocked by ce inactive t avh t avs suspend burst pipelined read 2a 2b
is61sp6464 issi ? 12 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 write cycle switching characteristics (over operating range) -133 mhz -117 mhz -100 mhz symbol parameter min. max. min. max. min. max. unit t kc cycle time 7.5 ? 8.5 ? 10 ? ns t kh clock high time 3 ? 3.4 ? 4 ? ns t kl clock low time 3 ? 3.4 ? 4 ? ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ds data in setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t avs address advance setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t dh data in hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? 0.5 ? ns write cycle switching characteristics (over operating range) -6 ns -7 ns -8 ns symbol parameter min. max. min. max. min. max. unit t kc cycle time 12 ? 13 ? 15 ? ns t kh clock high time 4.5 ? 5 ? 6 ? ns t kl clock low time 4.5 ? 5 ? 6 ? ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ds data in setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t avs address advance setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t dh data in hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t avh address advance hold time 0.5 ? 0.5 ? 0.5 ? ns
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 13 rev. a 04/17/01 write cycle timing single write data out data in oe ce2, ce3 ce2, ce3 ce bw8-bw1 bwe gw a15-a0 adv adsc adsp clk wr1 wr2 unselected burst write t kc t kl t kh t ss t sh t as t ah t ws t wh t ws t wh wr3 t ces t ceh t ces t ceh t ces t ceh ce3, ce2 and ce2, ce3 only sampled with adsp or adsc ce masks adsp unselected with ce2, ce3 adsc initiate write adsp is blocked by ce inactive t avh t avs adv must be inactive for adsp write wr1 wr2 t ws t wh wr3 t ws t wh high-z high-z 1a 3a t ds t dh bw8-bw1 only are applied to first cycle of wr2 write 2c 2d 2b 2a
is61sp6464 issi ? 14 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 read/write cycle switching characteristics (over operating range) -133 mhz -117 mhz -100 mhz symbol parameter min. max. min. max. min. max. unit t kc cycle time 7.5 ? 8.5 ? 10 ? ns t kh clock high time 3 ? 3.4 ? 4. ? ns t kl clock low time 3 ? 3.4 ? 4 ? ns t kq clock access time ? 5 ? 5 ? 5ns t kqx (1) clock high to output invalid 1.5 ? 1.5 ? 2.5 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 1.5 7.5 1.5 8.5 2 5 ns t oeq output enable to output valid ? 5 ? 5 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z ?? ?? 25ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 15 rev. a 04/17/01 read/write cycle switching characteristics (over operating range) -6 ns -7 ns -8 ns symbol parameter min. max. min. max. min. max. unit t kc cycle time 12 ? 13 ? 15 ? ns t kh clock high time 4.5 ? 5 ? 6 ? ns t kl clock low time 4.5 ? 5 ? 6 ? ns t kq clock access time ? 6 ? 7 ? 8ns t kqx (1) clock high to output invalid 2.5 ? 3 ? 3 ? ns t kqlz (1,2) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (1,2) clock high to output high-z 2 5 2 5 2 6 ns t oeq output enable to output valid ? 5 ? 5 ? 5ns t oeqx (1) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (1,2) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (1,2) output disable to output high-z 2 5 2 5 2 6 ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ws write setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t wh write hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns note: 1. guaranteed but not 100% tested. this parameter is periodically sampled. 2. tested with load in figure 2.
is61sp6464 issi ? 16 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 read/write cycle timing single read single write high-z high-z data out data in oe ce2, ce3 ce2, ce3 ce bw8-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 wr1 wr1 1a 1a 2a 2b 2c 2d unselected burst read t kqx t kc t kl t kh t ss t sh adsp is blocked by ce inactive t ss t sh t as t ah t ws t wh t ws t wh t ws t wh rd2 rd3 t ces t ceh t ces t ceh t ces t ceh ce2, ce3 and ce2, ce3 only sampled with adsp or adsc ce masks adsp unselected with ce2, ce3 t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz t ds t dh t kqhz
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 17 rev. a 04/17/01 snooze and recovery cycle switching characteristics (over operating range) -133 mhz -117 mhz -100 mhz symbol parameter min. max. min. max. min. max. unit t kc cycle time 7.5 ? 8.5 ? 10 ? ns t kh clock high time 3 ? 3.4 ? 4 ? ns t kl clock low time 3 ? 3.4 ? 4 ? ns t kq clock access time ? 5 ? 5 ? 5ns t kqx (3) clock high to output invalid 0 ??? 2.5 ? ns t kqlz (3,4) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (3,4) clock high to output high-z 1.5 7.5 1.5 8.5 2 5 ns t oeq output enable to output valid ? 5 ? 4 ? 5ns t oeqx (3) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (3,4) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (3,4) output disable to output high-z ?? ?? 25ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t zzs zz standby (1) 2 ? 2 ? 2 ? cyc t zzrec zz recovery (2) 2 ? 2 ? 2 ? cyc notes: 1. the assertion of zz allows the sram to enter a lower power state than when deselected within the time specified. data retention is guaranteed when zz is asserted and clock remains active. 2. adsc and adsp must not be asserted for at least 2 cyc after leaving zz state. 3. guaranteed but not 100% tested. this parameter is periodically sampled. 4. tested with load in figure 2.
is61sp6464 issi ? 18 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 snooze and recovery cycle switching characteristics (over operating range) -6 ns -7 ns -8 ns symbol parameter min. max. min. max. min. max. unit t kc cycle time 12 ? 13 ? 15 ? ns t kh clock high time 4.5 ? 5 ? 6 ? ns t kl clock low time 4.5 ? 5 ? 6 ? ns t kq clock access time ? 6 ? 7 ? 8ns t kqx (3) clock high to output invalid 2.5 ? 3 ? 3 ? ns t kqlz (3,4) clock high to output low-z 0 ? 0 ? 0 ? ns t kqhz (3,4) clock high to output high-z 2 5 2 5 2 6 ns t oeq output enable to output valid ? 5 ? 5 ? 5ns t oeqx (3) output disable to output invalid 0 ? 0 ? 0 ? ns t oelz (3,4) output enable to output low-z 0 ? 0 ? 0 ? ns t oehz (3,4) output disable to output high-z 2 5 2 5 2 6 ns t as address setup time 2.5 ? 2.5 ? 2.5 ? ns t ss address status setup time 2.5 ? 2.5 ? 2.5 ? ns t ces chip enable setup time 2.5 ? 2.5 ? 2.5 ? ns t ah address hold time 0.5 ? 0.5 ? 0.5 ? ns t sh address status hold time 0.5 ? 0.5 ? 0.5 ? ns t ceh chip enable hold time 0.5 ? 0.5 ? 0.5 ? ns t zzs zz standby (1) 2 ? 2 ? 2 ? cyc t zzrec zz recovery (2) 2 ? 2 ? 2 ? cyc notes: 1. the assertion of zz allows the sram to enter a lower power state than when deselected within the time specified. data retention is guaranteed when zz is asserted and clock remains active. 2. adsc and adsp must not be asserted for at least 2 cyc after leaving zz state. 3. guaranteed but not 100% tested. this parameter is periodically sampled. 4. tested with load in figure 2.
is61sp6464 issi ? integrated silicon solution, inc. ? 1-800-379-4774 19 rev. a 04/17/01 snooze and recovery cycle timing single read high-z high-z data out data in oe ce2, ce3 ce2, ce3 ce bw8-bw1 bwe gw a15-a0 adv adsc adsp clk rd1 1a read snooze with data retention t kc t kl t kh t ss t sh t as t ah rd2 t ces t ceh t ces t ceh t ces t ceh t oeq t oeqx t oelz t kqlz t kq t oehz t kqx t kqhz zz t zzs t zzrec
is61sp6464 issi ? 20 integrated silicon solution, inc. ? 1-800-379-4774 rev. a 04/17/01 ordering information commercial range: 0 c to +70 c speed order part number package 133 is61sp6464-133tq tqfp is61sp6464-133pq pqfp 117 is61sp6464-117tq tqfp is61sp6464-117pq pqfp 100 is61sp6464-100tq tqfp is61sp6464-100pq pqfp 83 is61sp6464-6tq tqfp is61sp6464-6pq pqfp 75 is61sp6464-7tq tqfp is61sp6464-7pq pqfp 66 is61sp6464-8tq tqfp is61sp6464-8pq pqfp industrial range: ? 40 c to +85 c speed order part number package 133 is61sp6464-133tqi tqfp IS61SP6464-133PQI pqfp 117 is61sp6464-117tqi tqfp is61sp6464-117pqi pqfp 100 is61sp6464-100tqi tqfp is61sp6464-100pqi pqfp 83 is61sp6464-6tqi tqfp is61sp6464-6pqi pqfp 75 is61sp6464-7tqi tqfp is61sp6464-7pqi pqfp 66 is61sp6464-8tqi tqfp is61sp6464-8pqi pqfp issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com

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