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| kinetis kl03 32 kb flash 48 mhz cortex-m0+ based microcontroller supports ultra low power 48 mhz devices with up to 32 kb flash. world's smallest mcu based on arm ? technology. ideal solution for internet of things edge nodes design with ultra small form factor and ultra low power consumption. the products offers: ? tiny footprint packages, including 1.6 x 2.0 mm 2 wlcsp ? run power consumption as low as 50 a/mhz ? static power consumption as low as 2.2 a with 7.5 s wakeup time for full retention and lowest static mode down to 77 na in deep sleep ? highly integrated peripherals, including new boot rom and high accurate internal voltage reference, etc core ? arm ? cortex ? -m0+ core up to 48 mhz memories ? up to 32 kb program flash memory ? 2 kb sram ? 8 kb rom with build-in bootloader ? 16 bytes regfile system peripherals ? nine low-power modes to provide power optimization based on application requirements ? cop software watchdog ? low-leakage wakeup unit ? swd debug interface and micro trace buffer ? bit manipulation engine clocks ? 48 mhz high accuracy internal reference clock ? 8/2 mhz low power internal reference clock ? 32 khz to 40 khz crystal oscillator ? 1 khz lpo clock operating characteristics ? voltage range: 1.71 to 3.6 v ? flash write voltage range: 1.71 to 3.6 v ? temperature range (ambient): -40 to 105c for qfn packages; -40 to 85c for wlcsp packages human-machine interface ? general-purpose input/output up to 22 communication interfaces ? one 8-bit spi module ? one lpuart module ? one i2c module supporting up to 1 mbit/s, with double buffer analog modules ? 12-bit sar adc with internal voltage reference, up to 818 ksps and 7 channels ? high-speed analog comparator containing a 6-bit dac and programmable reference input ? 1.2 v voltage reference (vref) timers ? two 2-channel timer/pwm modules ? one low-power timer ? real time clock security and integrity modules ? 80-bit unique identification number per chip mkl03zxxvfg4 mkl03zxxvfk4 mkl03z32caf4r mkl03z32cbf4r 16-pin qfn (fg) 3 x 3 x 0.65 pitch 0.5 mm 24-pin qfn (fk) 4 x 4 x 0.65 pitch 0.5 mm 20 wlcsp 2 x 1.61 x 0.56 pitch 0.4 mm(af) 2 x 1.61 x 0.32 pitch 0.4 mm (bf) nxp semiconductors document number: KL03P24M48SF0 data sheet: technical data rev. 5.1 08/2017 nxp reserves the right to change the production detail specifications as may be required to permit improvements in the design of its products.
ordering information 1 part number memory maximum number of i\o's flash (kb) sram (kb) mkl03z8vfg4(r) 8 2 14 mkl03z16vfg4(r) 16 2 14 mkl03z32vfg4(r) 32 2 14 mkl03z32caf4r 32 2 18 mkl03z32cbf4r 32 2 18 mkl03z8vfk4(r) 8 2 22 mkl03z16vfk4(r) 16 2 22 mkl03z32vfk4(r) 32 2 22 1. to confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search. related resources type description resource selector guide the solution advisor is a web-based tool that features interactive application wizards and a dynamic product selector. solution advisor product brief the product brief contains concise overview/summary information to enable quick evaluation of a device for design suitability. kl03pb 1 reference manual the reference manual contains a comprehensive description of the structure and function (operation) of a device. KL03P24M48SF0rm 1 data sheet the data sheet includes electrical characteristics and signal connections. KL03P24M48SF0 1 chip errata the chip mask set errata provides additional or corrective information for a particular device mask set. kl03z_ x n86k 2 package drawing package dimensions are provided in package drawings. qfn 16-pin: 98asa00525d 1 qfn 24-pin: 98asa00602d 1 wlcsp 20-pin: 98asa00676d 1 wlcsp 20-pin (ultra thin): 98asa00964d 1 1. to find the associated resource, go to http://www.nxp.com and perform a search using this term. 2. to find the associated resource, go to http://www.nxp.com and perform a search using this term with the x replaced by the revision of the device you are using. figure 1 shows the functional modules in the chip. 2 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors memories and memory interfaces program flash ram analog timers communication interfaces spi x1 clocks lpo core swd interfaces interrupt controller human-machine interface (hmi) system internal watchdog reference internal clocks oscillator low frequency low power uart x1 cortex-m0+ arm with gpios interrupt low power timer mtb bme comparator with x1 analog security and integrity unique id rom register file rtc 6-bit dac vref kinetis kl03 family x1 i c 2 timers 2x2ch 12-bit adc x1 figure 1. functional block diagram kinetis kl03 32 kb flash, rev. 5.1 08/2017 3 nxp semiconductors table of contents 1 ratings.................................................................................... 5 1.1 thermal handling ratings................................................. 5 1.2 moisture handling ratings................................................ 5 1.3 esd handling ratings....................................................... 5 1.4 voltage and current operating ratings............................. 6 2 general................................................................................... 6 2.1 ac electrical characteristics............................................. 6 2.2 nonswitching electrical specifications.............................. 7 2.2.1 voltage and current operating requirements....... 7 2.2.2 lvd and por operating requirements................ 7 2.2.3 voltage and current operating behaviors............. 8 2.2.4 power mode transition operating behaviors........ 9 2.2.5 power consumption operating behaviors............ 10 2.2.6 emc radiated emissions operating behaviors..... 24 2.2.7 emc radiated emissions web search procedure boilerplate.......................................... 25 2.2.8 capacitance attributes......................................... 25 2.3 switching specifications................................................... 25 2.3.1 device clock specifications.................................. 25 2.3.2 general switching specifications......................... 26 2.4 thermal specifications..................................................... 26 2.4.1 thermal operating requirements......................... 26 2.4.2 thermal attributes................................................ 27 3 peripheral operating requirements and behaviors.................. 27 3.1 core modules.................................................................. 27 3.1.1 swd electricals .................................................. 28 3.2 system modules.............................................................. 29 3.3 clock modules................................................................. 29 3.3.1 mcg-lite specifications....................................... 29 3.3.2 oscillator electrical specifications........................ 30 3.4 memories and memory interfaces................................... 31 3.4.1 flash electrical specifications.............................. 31 3.5 security and integrity modules........................................ 33 3.6 analog............................................................................. 33 3.6.1 adc electrical specifications............................... 33 3.6.2 cmp and 6-bit dac electrical specifications....... 37 3.6.3 voltage reference electrical specifications.......... 39 3.7 timers.............................................................................. 40 3.8 communication interfaces............................................... 40 3.8.1 spi switching specifications................................ 41 3.8.2 inter-integrated circuit interface (i2c) timing...... 45 3.8.3 uart................................................................... 47 4 dimensions............................................................................. 47 4.1 obtaining package dimensions....................................... 47 5 pinout...................................................................................... 48 5.1 kl03 signal multiplexing and pin assignments................ 48 5.2 kl03 pinouts.................................................................... 49 6 ordering parts......................................................................... 51 6.1 determining valid orderable parts.................................... 51 7 part identification..................................................................... 51 7.1 description....................................................................... 51 7.2 format............................................................................. 52 7.3 fields............................................................................... 52 7.4 example........................................................................... 52 8 terminology and guidelines.................................................... 53 8.1 definition: operating requirement.................................... 53 8.2 definition: operating behavior......................................... 53 8.3 definition: attribute.......................................................... 54 8.4 definition: rating............................................................. 54 8.5 result of exceeding a rating............................................ 55 8.6 relationship between ratings and operating requirements.................................................................... 55 8.7 guidelines for ratings and operating requirements.......... 55 8.8 definition: typical value................................................... 56 8.9 typical value conditions.................................................. 57 9 revision history....................................................................... 57 4 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 1 ratings 1.1 thermal handling ratings table 1. thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.2 moisture handling ratings table 2. qfn packages moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . table 3. wlcsp packages moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 1 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 1.3 esd handling ratings table 4. esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C2000 +2000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of 105 c C100 +100 ma 3 ratings kinetis kl03 32 kb flash, rev. 5.1 08/2017 5 nxp semiconductors 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78, ic latch-up test . 1.4 voltage and current operating ratings table 5. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 3.8 v i dd digital supply current 120 ma v io io pin input voltage C0.3 v dd + 0.3 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 2 general 2.1 ac electrical characteristics unless otherwise specified, propagation delays are measured from the 50% to the 50% point, and rise and fall times are measured at the 20% and 80% points, as shown in the following figure. 80% 20% 50% v il input signal v ih fall time high low rise time midpoint1 the midpoint is v il + (v ih - v il ) / 2 figure 2. input signal measurement reference all digital i/o switching characteristics, unless otherwise specified, assume the output pins have the following characteristics. ? c l =30 pf loads general 6 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors ? slew rate disabled ? normal drive strength 2.2 nonswitching electrical specifications 2.2.1 voltage and current operating requirements table 6. voltage and current operating requirements symbol description min. max. unit notes v dd supply voltage 1.71 3.6 v v dda analog supply voltage 1.71 3.6 v v dd C v dda v dd -to-v dda differential voltage C0.1 0.1 v v ss C v ssa v ss -to-v ssa differential voltage C0.1 0.1 v v ih input high voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.7 v dd 0.75 v dd v v v il input low voltage ? 2.7 v v dd 3.6 v ? 1.7 v v dd 2.7 v 0.35 v dd 0.3 v dd v v v hys input hysteresis 0.06 v dd v i icio io pin negative dc injection currentsingle pin ? v in < v ss C0.3v C5 ma 1 i iccont contiguous pin dc injection current regional limit, includes sum of negative injection currents of 16 contiguous pins ? negative current injection C25 ma v ram v dd voltage required to retain ram 1.2 v 1. all i/o pins are internally clamped to v ss through a esd protection diode. there is no diode connection to v dd . if v in greater than v io_min (= v ss -0.3 v) is observed, then there is no need to provide current limiting resistors at the pads. if this limit cannot be observed then a current limiting resistor is required. the negative dc injection current limiting resistor is calculated as r = (v io_min - v in )/|i icio |. general kinetis kl03 32 kb flash, rev. 5.1 08/2017 7 nxp semiconductors 2.2.2 lvd and por operating requirements table 7. v dd supply lvd and por operating requirements symbol description min. typ. max. unit notes v por falling v dd por detect voltage 0.8 1.1 1.5 v v lvdh falling low-voltage detect threshold high range (lvdv = 01) 2.48 2.56 2.64 v v lvw1h v lvw2h v lvw3h v lvw4h low-voltage warning thresholds high range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 2.62 2.72 2.82 2.92 2.70 2.80 2.90 3.00 2.78 2.88 2.98 3.08 v v v v 1 v hysh low-voltage inhibit reset/recover hysteresis high range 60 mv v lvdl falling low-voltage detect threshold low range (lvdv=00) 1.54 1.60 1.66 v v lvw1l v lvw2l v lvw3l v lvw4l low-voltage warning thresholds low range ? level 1 falling (lvwv = 00) ? level 2 falling (lvwv = 01) ? level 3 falling (lvwv = 10) ? level 4 falling (lvwv = 11) 1.74 1.84 1.94 2.04 1.80 1.90 2.00 2.10 1.86 1.96 2.06 2.16 v v v v 1 v hysl low-voltage inhibit reset/recover hysteresis low range 40 mv v bg bandgap voltage reference 0.97 1.00 1.03 v t lpo internal low power oscillator period factory trimmed 900 1000 1100 s 1. rising thresholds are falling threshold + hysteresis voltage 2.2.3 voltage and current operating behaviors table 8. voltage and current operating behaviors symbol description min. max. unit notes v oh output high voltage normal drive pad (except reset) ? 2.7 v v dd 3.6 v, i oh = C5 ma ? 1.71 v v dd 2.7 v, i oh = C2.5 ma v dd C 0.5 v dd C 0.5 v v 1 , 2 v oh output high voltage high drive pad (except reset) v dd C 0.5 v dd C 0.5 v v 1 , 2 table continues on the next page... general 8 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 8. voltage and current operating behaviors (continued) symbol description min. max. unit notes ? 2.7 v v dd 3.6 v, i oh = C20 ma ? 1.71 v v dd 2.7 v, i oh = C10 ma i oht output high current total for all ports 100 ma v ol output low voltage normal drive pad ? 2.7 v v dd 3.6 v, i ol = 5 ma ? 1.71 v v dd 2.7 v, i ol = 2.5 ma 0.5 0.5 v v 1 v ol output low voltage high drive pad ? 2.7 v v dd 3.6 v, i ol = 20 ma ? 1.71 v v dd 2.7 v, i ol = 10 ma 0.5 0.5 v v 1 i olt output low current total for all ports 100 ma i in input leakage current (per pin) for full temperature range 1 a 3 i in input leakage current (per pin) at 25 c 0.025 a 3 i in input leakage current (total all pins) for full temperature range 41 a 3 i oz hi-z (off-state) leakage current (per pin) 1 a r pu internal pullup resistors 20 50 k 4 1. i/o have both high drive and normal drive capability selected by the associated ptx_pcrn[dse] control bit. all other gpios are normal drive only. 2. the reset pin only contains an active pull down device when configured as the reset signal or as a gpio. when configured as a gpio output, it acts as a pseudo open drain output. 3. measured at v dd = 3.6 v 4. measured at v dd supply voltage = v dd min and vinput = v ss 2.2.4 power mode transition operating behaviors all specifications except t por and vllsx run recovery times in the following table assume this clock configuration: ? cpu and system clocks = 48 mhz ? bus and flash clock = 24 mhz ? hirc clock mode vllsx run recovery uses lirc clock mode at the default cpu and system frequency of 8 mhz, and a bus and flash clock frequency of 4 mhz. general kinetis kl03 32 kb flash, rev. 5.1 08/2017 9 nxp semiconductors table 9. power mode transition operating behaviors symbol description min. typ. max. unit note t por after a por event, amount of time from the point v dd reaches 1.8 v to execution of the first instruction across the operating temperature range of the chip. 300 s 1 ? vlls0 run 152 166 s ? vlls1 run 152 166 s ? vlls3 run 93 104 s ? vlps run 7.5 8 s ? stop run 7.5 8 s 1. normal boot (ftfa_fopt[lpboot]=11). 2.2.5 power consumption operating behaviors table 10. kl03 qfn packages power consumption operating behaviors symbol description min. typ. max. 1 unit notes i dda analog supply current see note ma 2 i dd_runco running coremark in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.49 5.62 5.71 5.84 ma 3 i dd_runco running while(1) loop in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.16 5.27 5.37 5.48 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 6.03 6.16 6.27 6.41 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v 3 table continues on the next page... general 10 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 10. kl03 qfn packages power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 25 c ? at 105 c 3.71 3.81 3.86 3.96 ma i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 2.47 2.58 2.57 2.68 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock enable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 6.43 6.56 6.69 6.82 ma 3 i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 5.71 5.82 5.94 6.05 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 3.3 3.4 3.43 3.54 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 2.28 2.38 2.37 2.48 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 6.1 6.22 6.34 6.47 ma i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 105 c 3.14 3.27 3.23 3.36 ma i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v 3.54 3.67 3.63 3.76 ma table continues on the next page... general kinetis kl03 32 kb flash, rev. 5.1 08/2017 11 nxp semiconductors table 10. kl03 qfn packages power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 25 c ? at 105 c i dd_vlprco very-low-power run while(1) loop in flash in compute operation mode 2 mhz lirc mode, 2 mhz core/0.5 mhz flash, v dd = 3.0 v ? at 25 c 500 750 a i dd_vlprco very-low-power-run while(1) loop in sram in compute operation mode 8 mhz lirc mode, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 188 217 a i dd_vlprco very-low-power run while(1) loop in sram in compute operation mode:2 mhz lirc mode, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 82 123 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 503 754 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v ? at 25 c 60 90 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock enable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 516 774 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram in all peripheral clock disable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 209 350 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 229 370 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram in all peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 93 140 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v 31 81 a table continues on the next page... general 12 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 10. kl03 qfn packages power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 25 c i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 103 154 a i dd_wait wait mode currentcore disabled, 48 mhz system/24 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.4 1.94 ma i dd_wait wait mode currentcore disabled, 24 mhz system/12 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.02 1.24 ma i dd_vlpw very-low-power wait mode current, core disabled, 4 mhz system/ 1 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 121 181 a i dd_vlpw very-low-power wait mode current, core disabled, 2 mhz system/ 0.5 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 59 97 a i dd_vlpw very-low-power wait mode current, core disabled, 125 khz system/ 31.25 khz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 28 42 a i dd_pstop2 partial stop 2, core and system clock disabled, 12 mhz bus and flash, v dd = 3.0 v 1.53 2.03 ma i dd_pstop2 partial stop 2, core and system clock disabled, flash doze enabled, 12 mhz bus, v dd = 3.0 v 0.881 1.18 ma i dd_stop stop mode current at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 158 164 187 219 175.7 179.48 199.54 236.43 a i dd_vlps very-low-power stop mode current at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 2.2 3.9 13.9 28.4 2.71 6.63 18.25 36.59 a i dd_vlps very-low-power stop mode current at 1.8 v ? at 25 c and below ? at 50 c 2.2 3.8 2.674 6.44 table continues on the next page... general kinetis kl03 32 kb flash, rev. 5.1 08/2017 13 nxp semiconductors table 10. kl03 qfn packages power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 85 c ? at 105 c 13.2 27.8 17.37 35.54 a i dd_vlls3 very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 1.08 1.4 3.45 7.02 1.17 1.52 3.96 8.19 a i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 1.47 1.82 3.93 7.6 1.56 1.94 4.44 8.77 a i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 1.8 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 1.33 1.65 3.56 6.92 1.42 1.77 4.07 8.09 a i dd_vlls1 very-low-leakage stop mode 1 current all peripheral disabled at 3.0 v ? at 25 c and below ? at 50c ? at 85c ? at 105 c 566 788 2270 4980 690 839 2600 5820 na i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 3.0 v ? at 25 c and below ? at 50c ? at 85c ? at 105 c 969 1200 2740 5610 1059 1251 3070 6450 na i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 1.8 v ? at 25 c and below ? at 50c ? at 85c ? at 105 c 826 1040 2400 4910 916 1091 2730 5750 na table continues on the next page... general 14 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 10. kl03 qfn packages power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 0) at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 265 467 1920 4540 373 512.9 2256 5395 na i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 1) at 3 v ? at 25 c and below ? at 50 c ? at 85 c ? at 105 c 77 255 1640 4080 350 465.70 1994 4956 na 4 1. the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). 2. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 3. mcg_lite configured for hirc mode. coremark benchmark compiled using iar 7.10 with optimization level high, optimized for balanced. 4. no brownout table 11. kl03 wlcsp package power consumption operating behaviors symbol description min. typ. max. 1 unit notes i dda analog supply current see note ma 2 i dd_runco running coremark in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 5.49 5.59 5.71 5.81 ma 3 i dd_runco running while(1) loop in flash in compute operation mode48m hirc mode, 48 mhz core / 24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 5.16 5.24 5.37 5.45 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 6.03 6.13 6.27 6.38 ma 3 table continues on the next page... general kinetis kl03 32 kb flash, rev. 5.1 08/2017 15 nxp semiconductors table 11. kl03 wlcsp package power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 3.71 3.78 3.86 3.93 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock disable 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 2.47 2.55 2.57 2.65 ma 3 i dd_run run mode current48m hirc mode, running coremark in flash all peripheral clock enable 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 6.43 6.53 6.69 6.79 ma 3 i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 5.71 5.79 5.94 6.02 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 24 mhz core/12 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 3.3 3.37 3.43 3.50 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock disable, 12 mhz core/6 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 2.28 2.35 2.37 2.44 ma i dd_run run mode current48m hirc mode, running while(1) loop in flash all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 6.1 6.19 6.34 6.44 ma i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock disable, 48 mhz core/24 mhz flash, v dd = 3.0 v 3.14 3.24 3.23 3.33 ma table continues on the next page... general 16 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 11. kl03 wlcsp package power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 25 c ? at 85 c i dd_run run mode current48m hirc mode, running while(1) loop in sram all peripheral clock enable, 48 mhz core/24 mhz flash, v dd = 3.0 v ? at 25 c ? at 85 c 3.54 3.64 3.63 3.73 ma i dd_vlprco very-low-power run while(1) loop in flash in compute operation mode 2 mhz lirc mode, 2 mhz core/0.5 mhz flash, v dd = 3.0 v ? at 25 c 500 750 a i dd_vlprco very-low-power-run while(1) loop in sram in compute operation mode 8 mhz lirc mode, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 188 217 a i dd_vlprco very-low-power run while(1) loop in sram in compute operation mode:2 mhz lirc mode, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 82 123 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 503 754 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v ? at 25 c 60 90 a i dd_vlpr very-low-power run mode current 2 mhz lirc mode, while(1) loop in flash all peripheral clock enable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 516 774 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram in all peripheral clock disable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 209 350 a i dd_vlpr very-low-power run mode current 8 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 4 mhz core / 1 mhz flash, v dd = 3.0 v ? at 25 c 229 370 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram in all table continues on the next page... general kinetis kl03 32 kb flash, rev. 5.1 08/2017 17 nxp semiconductors table 11. kl03 wlcsp package power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes peripheral clock disable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 93 140 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock disable, 125 khz core / 31.25 khz flash, v dd = 3.0 v ? at 25 c 31 81 a i dd_vlpr very-low-power run mode current2 mhz lirc mode, while(1) loop in sram all peripheral clock enable, 2 mhz core / 0.5 mhz flash, v dd = 3.0 v ? at 25 c 103 154 a i dd_wait wait mode currentcore disabled, 48 mhz system/24 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.4 1.94 ma i dd_wait wait mode currentcore disabled, 24 mhz system/12 mhz bus, flash disabled (flash doze enabled), all peripheral clocks disabled, mcg_lite under hirc mode, v dd = 3.0 v 1.02 1.24 ma i dd_vlpw very-low-power wait mode current, core disabled, 4 mhz system/ 1 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 121 181 a i dd_vlpw very-low-power wait mode current, core disabled, 2 mhz system/ 0.5 mhz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 59 97 a i dd_vlpw very-low-power wait mode current, core disabled, 125 khz system/ 31.25 khz bus and flash, all peripheral clocks disabled, v dd = 3.0 v 28 42 a i dd_pstop2 partial stop 2, core and system clock disabled, 12 mhz bus and flash, v dd = 3.0 v 1.53 2.03 ma i dd_pstop2 partial stop 2, core and system clock disabled, flash doze enabled, 12 mhz bus, v dd = 3.0 v 0.881 1.18 ma i dd_stop stop mode current at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c 158 164 187 175.7 179.48 199.54 a i dd_vlps very-low-power stop mode current at 3.0 v ? at 25 c and below 2.2 3.9 2.71 6.63 table continues on the next page... general 18 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 11. kl03 wlcsp package power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 50 c ? at 85 c 13.9 18.25 a i dd_vlps very-low-power stop mode current at 1.8 v ? at 25 c and below ? at 50 c ? at 85 c 2.2 3.8 13.2 2.674 6.44 17.37 a i dd_vlls3 very-low-leakage stop mode 3 current, all peripheral disable, at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c 1.08 1.4 3.45 1.17 1.52 3.96 a i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 3.0 v ? at 25 c and below ? at 50 c ? at 85 c 1.47 1.82 3.93 1.56 1.94 4.44 a i dd_vlls3 very-low-leakage stop mode 3 current with rtc current, at 1.8 v ? at 25 c and below ? at 50 c ? at 85 c 1.33 1.65 3.56 1.42 1.77 4.07 a i dd_vlls1 very-low-leakage stop mode 1 current all peripheral disabled at 3.0 v ? at 25 c and below ? at 50c ? at 85c 566 788 2270 690 839 2600 na i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 3.0 v ? at 25 c and below ? at 50c ? at 85c 969 1200 2740 1059 1251 3070 na i dd_vlls1 very-low-leakage stop mode 1 current rtc enabled at 1.8 v ? at 25 c and below ? at 50c ? at 85c 826 1040 2400 916 1091 2730 na i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 0) at 3.0 v 265 373 table continues on the next page... general kinetis kl03 32 kb flash, rev. 5.1 08/2017 19 nxp semiconductors table 11. kl03 wlcsp package power consumption operating behaviors (continued) symbol description min. typ. max. 1 unit notes ? at 25 c and below ? at 50 c ? at 85 c 467 1920 512.9 2256 na i dd_vlls0 very-low-leakage stop mode 0 current all peripheral disabled (smc_stopctrl[porpo] = 1) at 3 v ? at 25 c and below ? at 50 c ? at 85 c 77 255 1640 350 465.70 1994 na 4 1. the maximum values represent characterized results equivalent to the mean plus three times the standard deviation (mean + 3 sigma). 2. the analog supply current is the sum of the active or disabled current for each of the analog modules on the device. see each module's specification for its supply current. 3. mcg_lite configured for hirc mode. coremark benchmark compiled using iar 7.10 with optimization level high, optimized for balanced. 4. no brownout table 12. low power mode peripheral adders typical value symbol description temperature (c) unit -40 25 50 70 85 105 1 i lirc8mhz 8 mhz internal reference clock (lirc) adder. measured by entering stop or vlps mode with 8 mhz lirc enabled, mcg_sc[fcrdiv]=000b, mcg_mc[lirc_div2]=000b. 68 68 68 68 68 68 a i lirc2mhz 2 mhz internal reference clock (lirc) adder. measured by entering stop mode with the 2 mhz lirc enabled, mcg_sc[fcrdiv]=000b, mcg_mc[lirc_div2]=000b. 27 27 27 27 27 27 a i erefsten32khz external 32 khz crystal clock adder by means of the osc0_cr[erefsten and erefsten] bits. measured by entering all modes with the crystal enabled. ? vlls1 ? vlls3 ? vlps ? stop 340 340 340 340 410 410 420 420 460 460 480 480 470 490 570 570 480 530 610 610 600 600 850 850 na i lptmr lptmr peripheral adder measured by placing the device in vlls1 mode with lptmr enabled using lpo. 30 30 30 85 100 200 na table continues on the next page... general 20 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 12. low power mode peripheral adders typical value (continued) symbol description temperature (c) unit -40 25 50 70 85 105 1 i cmp cmp peripheral adder measured by placing the device in vlls1 mode with cmp enabled using the 6-bit dac and a single external input for compare. includes 6-bit dac power consumption. 15 15 15 15 15 15 a i rtc rtc peripheral adder measured by placing the device in vlls1 mode with external 32 khz crystal enabled by means of the rtc_cr[osce] bit and the rtc alarm set for 1 minute. includes erclk32k (32 khz external crystal) power consumption. 340 440 440 480 520 620 na i uart uart peripheral adder measured by placing the device in stop or vlps mode with selected clock source waiting for rx data at 115200 baud rate. includes selected clock source power consumption. ? lirc8m (8 mhz internal reference clock) ? lirc2m (2 mhz internal reference clock) 85 28 85 28 85 28 85 28 85 28 85 28 a i tpm tpm peripheral adder measured by placing the device in stop or vlps mode with selected clock source configured for output compare generating 100 hz clock signal. no load is placed on the i/o generating the clock signal. includes selected clock source and i/o switching currents. ? lirc8m (8 mhz internal reference clock) ? lirc2m (2 mhz internal reference clock) 93 35 93 35 93 35 93 35 93 35 93 35 a i bg bandgap adder when bgen bit is set and device is placed in vlpx or vllsx mode. 45 45 45 45 45 45 a i adc adc peripheral adder combining the measured values at v dd and v dda by placing the device in stop or vlps mode. adc is configured for low power mode using the internal clock and continuous conversions. 340 340 340 340 340 340 a 1. for qfn packages only. general kinetis kl03 32 kb flash, rev. 5.1 08/2017 21 nxp semiconductors 2.2.5.1 diagram: typical idd_run operating behavior the following data was measured under these conditions: ? mcg-lite in hirc for run mode, and lirc for vlpr mode ? no gpios toggled ? code execution from flash ? for the alloff curve, all peripheral clocks are disabled except ftfa 4.00e-03 5.00e-03 6.00e-03 7.00e-03 current consumption on vdd (a) run mode current vs core frequency alloff temperature=25, vdd=3, mcg mode=hirc, while loop located in flash all peripheral clk gates 000.00e+00 1.00e-03 2.00e-03 3.00e-03 '1-1 '1-1 '1-1 '1-1 1-1 '1-2 3 6 8 12 24 48 current consumption on vdd (a) allon clk ratio flash - core core freq (mhz) figure 3. run mode supply current vs. core frequency (loop located in flash) general 22 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 2.00e-03 2.50e-03 3.00e-03 3.50e-03 4.00e-03 current consumption on vdd (a) run mode current vs core frequency alloff temperature=25, vdd=3, mcg mode=hirc, while loop located in sram all peripheral clk gates 000.00e+00 500.00e-06 1.00e-03 1.50e-03 '1-1 '1-1 '1-1 '1-1 1-1 '1-2 3 6 8 12 24 48 current consumption on vdd (a) allon clk ratio flash - core core freq (mhz) figure 4. run mode supply current vs. core frequency (loop located in sram) general kinetis kl03 32 kb flash, rev. 5.1 08/2017 23 nxp semiconductors 150.00e-06 200.00e-06 250.00e-06 current consumption on vdd (a) vlpr mode current vs core frequency alloff all peripheral clk gates temperature=25, vdd=3, mcg=lirc8m, while loop in sram 000.00e+00 50.00e-06 100.00e-06 '1-1 '1-2 '1-4 1 2 4 current consumption on vdd (a) allon clk ratio flash - core core freq (mhz) figure 5. vlpr mode current vs. core frequency (loop in sram) 2.2.6 emc radiated emissions operating behaviors table 13. emc radiated emissions operating behaviors for 24-pin qfn package symbol description frequency band (mhz) typ. unit notes v re1 radiated emissions voltage, band 1 0.15C50 5 dbv 1 , 2 v re2 radiated emissions voltage, band 2 50C150 7 dbv v re3 radiated emissions voltage, band 3 150C500 5 dbv v re4 radiated emissions voltage, band 4 500C1000 5 dbv v re_iec iec/sae level 0.15C1000 n 2 , 3 1. determined according to iec 61967-2 (and sae j1752/3) radiated radio frequency (rf) emissions measurement standard. typical configuration: appendix b: dut software configuration2. typical configuration. 2. v dd = 3.3 v, t a = 25 c, f irc48m = 48 mhz, f sys = 48 mhz, f bus = 24 mhz 3. iec/sae level maximums: n12 dbv, m18 dbv, l24 dbv, k30 dbv, i 36 dbv, h 42 dbv, g48 dbv. general 24 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 2.2.7 emc radiated emissions web search procedure boilerplate to find application notes that provide guidance on designing your system to minimize interference from radiated emissions: 1. go to www.nxp.com . 2. perform a keyword search for "emc design" 2.2.8 capacitance attributes table 14. capacitance attributes symbol description min. max. unit c in input capacitance 7 pf 2.3 switching specifications 2.3.1 device clock specifications table 15. device clock specifications symbol description min. max. unit normal run mode f sys system and core clock 48 mhz f bus bus clock 24 mhz f flash flash clock 24 mhz f lptmr lptmr clock 24 mhz vlpr and vlps modes 1 f sys system and core clock 4 mhz f bus bus clock 1 mhz f flash flash clock 1 mhz f lptmr lptmr clock 2 24 mhz f erclk external reference clock 16 mhz f erclk external reference clock 32.768 khz f lptmr_erclk lptmr external reference clock 16 mhz f tpm tpm asynchronous clock 8 mhz f uart0 uart0 asynchronous clock 8 mhz general kinetis kl03 32 kb flash, rev. 5.1 08/2017 25 nxp semiconductors 1. the frequency limitations in vlpr and vlps modes here override any frequency specification listed in the timing specification for any other module. these same frequency limits apply to vlps, whether vlps was entered from run or from vlpr. 2. the lptmr can be clocked at this speed in vlpr or vlps only when the source is an external pin. 2.3.2 general switching specifications these general-purpose specifications apply to all signals configured for gpio and uart signals. table 16. general switching specifications description min. max. unit notes gpio pin interrupt pulse width (digital glitch filter disabled) synchronous path 1.5 bus clock cycles 1 external reset and nmi pin interrupt pulse width asynchronous path 100 ns 2 gpio pin interrupt pulse width asynchronous path 16 ns 2 port rise and fall time 36 ns 3 1. the greater synchronous and asynchronous timing must be met. 2. this is the shortest pulse that is guaranteed to be recognized. 3. 75 pf load 2.4 thermal specifications 2.4.1 thermal operating requirements table 17. thermal operating requirements of wlcsp package symbol description min. max. unit note t j die junction temperature C40 95 c t a ambient temperature C40 85 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a + r ja chip power dissipation. table 18. thermal operating requirements of other packages symbol description min. max. unit note t j die junction temperature C40 125 c t a ambient temperature C40 105 c 1 1. maximum t a can be exceeded only if the user ensures that t j does not exceed the maximum. the simplest method to determine t j is: t j = t a + r ja chip power dissipation. general 26 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 2.4.2 thermal attributes table 19. thermal attributes board type symbol description 16 qfn 20 wlcsp 24 qfn unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 64.2 69.8 60.7 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 53.3 57.5 48.5 c/w 1 , 2 , 3 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 55.4 62.03 51.0 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 48.9 54.3 43.6 c/w 1 , 3 r jb thermal resistance, junction to board 33.5 51.64 30.4 c/w 4 r jc thermal resistance, junction to case 20.9 0.73 9.8 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 0.2 0.2 0.2 c/w 6 jb thermal characterization parameter, junction to package bottom outside center (natural convection) 22.4 D 21.8 c/w 7 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per semi g38-87 and jedec jesd51-2 with the single layer board horizontal. 3. per jedec jesd51-6 with the board horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the case top surface as measured by the cold plate method (mil spec-883 method 1012.1). 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization parameter is written as psi-jt. 7. thermal characterization parameter indicating the temperature difference between package bottom center and the junction temperature per jedec jesd51-12. when greek letters are not available, the thermal characterization parameter is written as psi-jb. 3 peripheral operating requirements and behaviors 3.1 core modules peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 27 nxp semiconductors 3.1.1 swd electricals table 20. swd full voltage range electricals symbol description min. max. unit operating voltage 1.71 3.6 v j1 swd_clk frequency of operation ? serial wire debug 0 25 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 0 ns j11 swd_clk high to swd_dio data valid 32 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 6. serial wire clock input timing peripheral operating requirements and behaviors 28 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 7. serial wire data timing 3.2 system modules there are no specifications necessary for the device's system modules. 3.3 clock modules 3.3.1 mcg-lite specifications table 21. hirc48m specification symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i dd48m supply current 400 500 a f irc48m internal reference frequency 48 mhz f irc48m_ol_lv total deviation of irc48m frequency at low voltage (vdd=1.71v-1.89v) over temperature 0.5 1.5 %f irc48m table continues on the next page... peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 29 nxp semiconductors table 21. hirc48m specification (continued) symbol description min. typ. max. unit notes f irc48m_ol_hv total deviation of irc48m frequency at high voltage (vdd=1.89v-3.6v) over temperature 0.5 1.0 %f irc48m j cyc_irc48m period jitter (rms) 35 150 ps t irc48mst startup time 2 3 s 1 1. irc48m startup time is defined as the time between clock enablement and clock availability for system use. enable the clock by setting mcg_mc[hircen] = 1. see reference manual for details. table 22. lirc8m/2m specification symbol description min. typ. max. unit notes v dd supply voltage 1.08 1.47 v t temperature range -40 125 c i dd_2m supply current in 2 mhz mode 14 17 a i dd_8m supply current in 8 mhz mode 30 35 a f irc_2m output frequency 2 mhz f irc_8m output frequency 8 mhz f irc_t_2m output frequency range (trimmed) 3 %f irc v dd 1.89 v f irc_t_8m output frequency range (trimmed) 3 %f irc v dd 1.89 v t su_2m startup time 12.5 s t su_8m startup time 12.5 s 3.3.2 oscillator electrical specifications 3.3.2.1 oscillator dc electrical specifications table 23. oscillator dc electrical specifications symbol description min. typ. max. unit notes v dd supply voltage 1.71 3.6 v i ddosc supply current low-power mode ? 32 khz 500 na 1 c x extal load capacitance 2 , 3 c y xtal load capacitance 2 , 3 r f feedback resistor low-frequency, low-power mode m 2 , 4 r s series resistor low-frequency, low-power mode k table continues on the next page... peripheral operating requirements and behaviors 30 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 23. oscillator dc electrical specifications (continued) symbol description min. typ. max. unit notes v pp 5 peak-to-peak amplitude of oscillation (oscillator mode) low-frequency, low-power mode 0.6 v 1. v dd =3.3 v, temperature =25 c 2. see crystal or resonator manufacturer's recommendation 3. c x ,c y can be provided by using either the integrated capacitors or by using external components. 4. when low power mode is selected, r f is integrated and must not be attached externally. 5. the extal and xtal pins should only be connected to required oscillator components and must not be connected to any other devices. 3.3.2.2 oscillator frequency specifications table 24. oscillator frequency specifications symbol description min. typ. max. unit notes f osc_lo oscillator crystal or resonator frequency low frequency mode 32 40 khz t dc_extal input clock duty cycle (external clock mode) 40 50 60 % t cst crystal startup time 32 khz low-frequency, low-power mode 750 ms 1 , 2 1. proper pc board layout procedures must be followed to achieve specifications. 2. crystal startup time is defined as the time between the oscillator being enabled and the oscinit bit in the mcg_s register being set. 3.4 memories and memory interfaces 3.4.1 flash electrical specifications this section describes the electrical characteristics of the flash memory module. 3.4.1.1 flash timing specifications program and erase the following specifications represent the amount of time the internal charge pumps are active and do not include command overhead. table 25. nvm program/erase timing specifications symbol description min. typ. max. unit notes t hvpgm4 longword program high-voltage time 7.5 18 s t hversscr sector erase high-voltage time 13 113 ms 1 t hversall erase all high-voltage time 52 452 ms 1 peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 31 nxp semiconductors 1. maximum time based on expectations at cycling end-of-life. 3.4.1.2 flash timing specifications commands table 26. flash command timing specifications symbol description min. typ. max. unit notes t rd1sec1k read 1s section execution time (flash sector) 60 s 1 t pgmchk program check execution time 45 s 1 t rdrsrc read resource execution time 30 s 1 t pgm4 program longword execution time 65 145 s t ersscr erase flash sector execution time 14 114 ms 2 t rd1all read 1s all blocks execution time 0.5 ms t rdonce read once execution time 25 s 1 t pgmonce program once execution time 65 s t ersall erase all blocks execution time 61 500 ms 2 t vfykey verify backdoor access key execution time 30 s 1 1. assumes 25 mhz flash clock frequency. 2. maximum times for erase parameters based on expectations at cycling end-of-life. 3.4.1.3 flash high voltage current behaviors table 27. flash high voltage current behaviors symbol description min. typ. max. unit i dd_pgm average current adder during high voltage flash programming operation 2.5 6.0 ma i dd_ers average current adder during high voltage flash erase operation 1.5 4.0 ma 3.4.1.4 reliability specifications table 28. nvm reliability specifications symbol description min. typ. 1 max. unit notes program flash t nvmretp10k data retention after up to 10 k cycles 5 50 years t nvmretp1k data retention after up to 1 k cycles 20 100 years n nvmcycp cycling endurance 10 k 50 k cycles 2 1. typical data retention values are based on measured response accelerated at high temperature and derated to a constant 25 c use profile. engineering bulletin eb618 does not apply to this technology. typical endurance defined in engineering bulletin eb619. 2. cycling endurance represents number of program/erase cycles at -40 c t j 125 c. peripheral operating requirements and behaviors 32 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 3.5 security and integrity modules there are no specifications necessary for the device's security and integrity modules. 3.6 analog 3.6.1 adc electrical specifications all adc channels meet the 12-bit single-ended accuracy specifications. 3.6.1.1 12-bit adc operating conditions table 29. 12-bit adc operating conditions symbol description conditions min. typ. 1 max. unit notes v dda supply voltage absolute 1.71 3.6 v v dda supply voltage delta to v dd (v dd C v dda ) -100 0 +100 mv 2 v ssa ground voltage delta to v ss (v ss C v ssa ) -100 0 +100 mv 2 v refh adc reference voltage high 1.13 v dda v dda v 3 v refl adc reference voltage low v ssa v ssa v ssa v 3 v adin input voltage v refl v refh v c adin input capacitance ? 8-bit / 10-bit / 12-bit modes 4 5 pf r adin input series resistance 2 5 k r as analog source resistance (external) 12-bit modes f adck < 4 mhz 5 k 4 f adck adc conversion clock frequency 12-bit mode 1.0 18.0 mhz 5 c rate adc conversion rate 12-bit modes no adc hardware averaging continuous conversions enabled, subsequent conversion time 20.000 818.330 ksps 6 1. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 1.0 mhz, unless otherwise stated. typical values are for reference only, and are not tested in production. 2. dc potential difference. peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 33 nxp semiconductors 3. for packages without dedicated vrefh and vrefl pins, v refh is internally tied to v dda , and v refl is internally tied to v ssa . 4. this resistance is external to mcu. to achieve the best results, the analog source resistance must be kept as low as possible. the results in this data sheet were derived from a system that had < 8 analog source resistance. the r as /c as time constant should be kept to < 1 ns. 5. to use the maximum adc conversion clock frequency, cfg2[adhsc] must be set and cfg1[adlpc] must be clear. 6. for guidelines and examples of conversion rate calculation, download the adc calculator tool . r as v as c as z as v adin z adin r adin r adin r adin r adin c adin pad leakage due to input protection input pin input pin input pin simplified input pin equivalent circuit simplified channel select circuit adc sar engine figure 8. adc input impedance equivalency diagram 3.6.1.2 12-bit adc electrical characteristics table 30. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) symbol description conditions 1 . min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 6 3 6 lsb 4 5 table continues on the next page... peripheral operating requirements and behaviors 34 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors table 30. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.9 0.4 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.5 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes 5 2 3 lsb 4 v adin = v dda 5 e q quantization error ? 12-bit modes 0.5 lsb 4 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 6 v temp25 temp sensor voltage 25 c 706 716 726 mv 6 1. all accuracy numbers assume the adc is calibrated with v refh = v dda 2. typical values assume v dda = 3.0 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. adc conversion clock < 3 mhz table 31. 12-bit adc characteristics (v refh = v refo , v refl = v ssa ) symbol description conditions 1 . min. typ. 2 max. unit notes i dda_adc supply current 0.215 1.7 ma 3 f adack adc asynchronous clock source ? adlpc = 1, adhsc = 0 ? adlpc = 1, adhsc = 1 ? adlpc = 0, adhsc = 0 ? adlpc = 0, adhsc = 1 1.2 2.4 3.0 4.4 2.4 4.0 5.2 6.2 3.9 6.1 7.3 9.5 mhz mhz mhz mhz t adack = 1/f adack table continues on the next page... peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 35 nxp semiconductors table 31. 12-bit adc characteristics (v refh = v refo , v refl = v ssa ) (continued) symbol description conditions 1 . min. typ. 2 max. unit notes sample time see reference manual chapter for sample times tue total unadjusted error ? 12-bit modes ? <12-bit modes 4 1.4 6.8 2.1 lsb 4 5 dnl differential non- linearity ? 12-bit modes ? <12-bit modes 0.7 0.2 C1.1 to +1.9 C0.3 to 0.5 lsb 4 5 inl integral non- linearity ? 12-bit modes ? <12-bit modes 1.0 0.5 C2.7 to +1.9 C0.7 to +0.5 lsb 4 5 e fs full-scale error ? 12-bit modes ? <12-bit modes C4 C1.4 C5.4 C1.8 lsb 4 v adin = v dda 5 e q quantization error ? 12-bit modes 0.5 lsb 4 e il input leakage error i in r as mv i in = leakage current (refer to the mcu's voltage and current operating ratings) temp sensor slope across the full temperature range of the device 1.55 1.62 1.69 mv/c 6 v temp25 temp sensor voltage 25 c 706 716 726 mv 6 1. all accuracy numbers assume the adc is calibrated with v refh = v refo 2. typical values assume v refo = 1.2 v, temp = 25 c, f adck = 2.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 3. the adc supply current depends on the adc conversion clock speed, conversion rate and adc_cfg1[adlpc] (low power). for lowest power operation, adc_cfg1[adlpc] must be set, the adc_cfg2[adhsc] bit must be clear with 1 mhz adc conversion clock speed. 4. 1 lsb = (v refh - v refl )/2 n 5. adc conversion clock < 16 mhz, max hardware averaging (avge = %1, avgs = %11) 6. adc conversion clock < 3 mhz peripheral operating requirements and behaviors 36 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors adc clock frequency (mhz) 0 2 4 6 8 10 12 14 16 18 2220 hardware averaging disabled averaging of 8 samples averaging of 32 samples 10 10.1 10.3 10.2 10.4 10.5 10.6 10.7 10.8 10.9 11 11.1 11.3 11.2 11.4 11.5 11.6 11.7 11.8 11.9 enob typical adc 12-bit single ended enob vs adc clock 100hz, 90% fs sine input figure 9. typical enob vs. adc_clk for 12-bit single-ended mode 3.6.2 cmp and 6-bit dac electrical specifications table 32. comparator and 6-bit dac electrical specifications symbol description min. typ. max. unit v dd supply voltage 1.71 3.6 v i ddhs supply current, high-speed mode (en=1, pmode=1) 200 a i ddls supply current, low-speed mode (en=1, pmode=0) 20 a v ain analog input voltage v ss C 0.3 v dd v v aio analog input offset voltage 20 mv v h analog comparator hysteresis 1 ? cr0[hystctr] = 00 ? cr0[hystctr] = 01 ? cr0[hystctr] = 10 ? cr0[hystctr] = 11 5 10 20 30 mv mv mv mv v cmpoh output high v dd C 0.5 v v cmpol output low 0.5 v t dhs propagation delay, high-speed mode (en=1, pmode=1) 20 50 200 ns t dls propagation delay, low-speed mode (en=1, pmode=0) 80 250 600 ns analog comparator initialization delay 2 40 s table continues on the next page... peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 37 nxp semiconductors table 32. comparator and 6-bit dac electrical specifications (continued) symbol description min. typ. max. unit i dac6b 6-bit dac current adder (enabled) 7 a inl 6-bit dac integral non-linearity C0.5 0.5 lsb 3 dnl 6-bit dac differential non-linearity C0.3 0.3 lsb 1. typical hysteresis is measured with input voltage range limited to 0.6 to v dd C0.6 v. 2. comparator initialization delay is defined as the time between software writes to change control inputs (writes to cmp_daccr[dacen], cmp_daccr[vrsel], cmp_daccr[vosel], cmp_muxcr[psel], and cmp_muxcr[msel]) and the comparator output settling to a stable level. 3. 1 lsb = v reference /64 00 01 10 hystctr setting 0.1 10 11 vin level (v) cmp hystereris (v) 3.1 2.82.5 2.2 1.91.61.3 1 0.70.4 0.05 0 0.01 0.02 0.03 0.08 0.07 0.06 0.04 figure 10. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 0) peripheral operating requirements and behaviors 38 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 00 01 10 hystctr setting 10 11 0.1 3.12.82.5 2.2 1.91.61.3 1 0.70.4 0.1 0 0.02 0.04 0.06 0.18 0.14 0.12 0.08 0.16 vin level (v) cmp hysteresis (v) figure 11. typical hysteresis vs. vin level (vdd = 3.3 v, pmode = 1) 3.6.3 voltage reference electrical specifications table 33. vref full-range operating requirements symbol description min. max. unit notes v dda supply voltage 1.71 3.6 v t a temperature operating temperature range of the device c c l output load capacitance 100 nf 1 , 2 1. c l must be connected to vref_out if the vref_out functionality is being used for either an internal or external reference. 2. the load capacitance should not exceed +/-25% of the nominal specified c l value over the operating temperature range of the device. table 34 is tested under the condition of setting vref_trm[chopen], vref_sc[regen] and vref_sc[icompen] bits to 1. peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 39 nxp semiconductors table 34. vref full-range operating behaviors symbol description min. typ. max. unit notes v out voltage reference output with factory trim at nominal v dda and temperature=25c 1.1915 1.195 1.1977 v 1 v out voltage reference output factory trim 1.1584 1.2376 v 1 v out voltage reference output user trim 1.193 1.197 v 1 v step voltage reference trim step 0.5 mv 1 v tdrift temperature drift (vmax -vmin across the full temperature range: 0 to 70c) 50 mv 1 ac aging coefficient 400 uv/yr i bg bandgap only current 80 a 1 i lp low-power buffer current 360 ua 1 i hp high-power buffer current 1 ma 1 v load load regulation ? current = 1.0 ma 200 v 1 , 2 t stup buffer startup time 100 s v vdrift voltage drift (vmax -vmin across the full voltage range) 2 mv 1 1. see the chip's reference manual for the appropriate settings of the vref status and control register. 2. load regulation voltage is the difference between the vref_out voltage with no load vs. voltage with defined load table 35. vref limited-range operating requirements symbol description min. max. unit notes t a temperature 0 50 c table 36. vref limited-range operating behaviors symbol description min. max. unit notes v out voltage reference output with factory trim 1.173 1.225 v 3.7 timers see general switching specifications . 3.8 communication interfaces peripheral operating requirements and behaviors 40 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 3.8.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd thresholds, unless noted, as well as input signal transitions of 3 ns and a 30 pf maximum load on all spi pins. table 37. spi master mode timing on slew rate disabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t periph C 30 1024 x t periph ns 6 t su data setup time (inputs) 22 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 10 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph C 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output 1. for spi0, f periph is the bus clock (f bus ). 2. t periph = 1/f periph table 38. spi master mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation f periph /2048 f periph /2 hz 1 2 t spsck spsck period 2 x t periph 2048 x t periph ns 2 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck table continues on the next page... peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 41 nxp semiconductors table 38. spi master mode timing on slew rate enabled pads (continued) num. symbol description min. max. unit note 5 t wspsck clock (spsck) high or low time t periph C 30 1024 x t periph ns 6 t su data setup time (inputs) 96 ns 7 t hi data hold time (inputs) 0 ns 8 t v data valid (after spsck edge) 52 ns 9 t ho data hold time (outputs) 0 ns 10 t ri rise time input t periph C 25 ns t fi fall time input 11 t ro rise time output 36 ns t fo fall time output 1. for spi0, f periph is the bus clock (f bus ). 2. t periph = 1/f periph (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 12. spi master mode timing (cpha = 0) peripheral operating requirements and behaviors 42 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors < table 40. spi slave mode timing on slew rate enabled pads num. symbol description min. max. unit note 1 f op frequency of operation 0 f periph /4 hz 1 2 t spsck spsck period 4 x t periph ns 2 3 t lead enable lead time 1 t periph 4 t lag enable lag time 1 t periph 5 t wspsck clock (spsck) high or low time t periph C 30 ns 6 t su data setup time (inputs) 2 ns 7 t hi data hold time (inputs) 7 ns 8 t a slave access time t periph ns 3 9 t dis slave miso disable time t periph ns 4 10 t v data valid (after spsck edge) 122 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t periph C 25 ns t fi fall time input 13 t ro rise time output 36 ns t fo fall time output 1. for spi0, f periph is the bus clock (f bus ). 2. t periph = 1/f periph 3. time to data active from high-impedance state 4. hold time to high-impedance state 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 14. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors 44 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 15. spi slave mode timing (cpha = 1) 3.8.2 inter-integrated circuit interface (i2c) timing table 41. i2c timing characteristic symbol standard mode fast mode unit minimum maximum minimum maximum scl clock frequency f scl 0 100 1 0 400 2 khz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 4 0.6 s low period of the scl clock t low 4.7 1.25 s high period of the scl clock t high 4 0.6 s set-up time for a repeated start condition t su ; sta 4.7 0.6 s data hold time for i 2 c bus devices t hd ; dat 0 3 3.45 4 0 5 0.9 3 s data set-up time t su ; dat 250 6 100 4 , 7 ns rise time of sda and scl signals t r 1000 20 +0.1c b 8 300 ns fall time of sda and scl signals t f 300 20 +0.1c b 7 300 ns set-up time for stop condition t su ; sto 4 0.6 s bus free time between stop and start condition t buf 4.7 1.3 s pulse width of spikes that must be suppressed by the input filter t sp n/a n/a 0 50 ns 1. the ptb3 and ptb4 pins can support only the standard mode. 2. the maximum scl clock frequency in fast mode with maximum bus loading can be achieved only when using the normal drive pins and vdd 2.7 v. peripheral operating requirements and behaviors kinetis kl03 32 kb flash, rev. 5.1 08/2017 45 nxp semiconductors 3. the master mode i 2 c deasserts ack of an address byte simultaneously with the falling edge of scl. if no slaves acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the sda and scl lines. 4. the maximum thd; dat must be met only if the device does not stretch the low period (tlow) of the scl signal. 5. input signal slew = 10 ns and output load = 50 pf 6. set-up time in slave-transmitter mode is 1 ipbus clock period, if the tx fifo is empty. 7. a fast mode i 2 c bus device can be used in a standard mode i2c bus system, but the requirement t su; dat 250 ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, then it must output the next data bit to the sda line t rmax + t su; dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification) before the scl line is released. 8. c b = total capacitance of the one bus line in pf. to achieve 1mhz i2c clock rates, consider the following recommendations: ? to counter the effects of clock stretching, the i2c baud rate select bits can be configured for faster than desired baud rate. ? use high drive pad and dse bit should be set in portx_pcrn register. ? minimize loading on the i2c sda and scl pins to ensure fastest rise times for the scl line to avoid clock stretching. ? use smaller pull up resistors on sda and scl to reduce the rc time constant. table 42. i 2 c 1mbit/s timing characteristic symbol minimum maximum unit scl clock frequency f scl 0 1 1 mhz hold time (repeated) start condition. after this period, the first clock pulse is generated. t hd ; sta 0.26 s low period of the scl clock t low 0.5 s high period of the scl clock t high 0.26 s set-up time for a repeated start condition t su ; sta 0.26 s data hold time for i 2 c bus devices t hd ; dat 0 s data set-up time t su ; dat 50 ns rise time of sda and scl signals t r 20 +0.1c b 120 ns fall time of sda and scl signals t f 20 +0.1c b 2 120 ns set-up time for stop condition t su ; sto 0.26 s bus free time between stop and start condition t buf 0.5 s pulse width of spikes that must be suppressed by the input filter t sp 0 50 ns 1. the maximum scl clock frequency of 1 mbit/s can support 200 pf bus loading when using the normal drive pins and vdd 2.7 v. 2. c b = total capacitance of the one bus line in pf. peripheral operating requirements and behaviors 46 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors ? ? sda hd; sta t hd; dat t low t su; dat t high t su; sta sr p s s t hd; sta t sp t su; sto t buf t f t r t f t r scl figure 16. timing definition for devices on the i 2 c bus 3.8.3 uart see general switching specifications . 4 dimensions 4.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to nxp.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 16-pin qfn 98asa00525d 24-pin qfn 98asa00602d 20-pin wlcsp 98asa00676d 20-pin wlcsp (ultra thin) 98asa00964d dimensions kinetis kl03 32 kb flash, rev. 5.1 08/2017 47 nxp semiconductors pinout 5.1 kl03 signal multiplexing and pin assignments the following table shows the signals available on each pin and the locations of these pins on the devices supported by this document. the port control module is responsible for selecting which alt functionality is available on each pin. note ptb3 and ptb4 are true open drain pins. the external pullup resistor must be added to make them output correct values in using i2c, gpio, and lpuart0. 24 qfn 20 wlc sp 16 qfn pin name default alt0 alt1 alt2 alt3 alt4 alt5 1 ptb6/ irq_2/ lptmr0_alt3 disabled ptb6/ irq_2/ lptmr0_alt3 tpm1_ch1 tpm_clkin1 2 ptb7/ irq_3 disabled ptb7/ irq_3 tpm1_ch0 3 b5 1 vdd vdd vdd 4 c5 2 vss vss vss 5 c4 3 pta3 extal0 extal0 pta3 i2c0_scl i2c0_sda lpuart0_tx 6 c3 4 pta4 xtal0 xtal0 pta4 i2c0_sda i2c0_scl lpuart0_rx clkout 7 d3 5 pta5/ rtc_clk_in disabled pta5/ rtc_clk_in tpm0_ch1 spi0_ss_b 8 d5 6 pta6 disabled pta6 tpm0_ch0 spi0_miso 9 ptb10 disabled ptb10 tpm0_ch1 spi0_ss_b 10 ptb11 disabled ptb11 tpm0_ch0 spi0_miso 11 d4 7 pta7/ irq_4 disabled pta7/ irq_4 spi0_miso spi0_mosi 12 c1 8 ptb0/ irq_5/ llwu_p4 adc0_se9 adc0_se9 ptb0/ irq_5/ llwu_p4 extrg_in spi0_sck i2c0_scl 13 d1 9 ptb1/ irq_6 adc0_se8/ cmp0_in3 adc0_se8/ cmp0_in3 ptb1/ irq_6 lpuart0_tx lpuart0_rx i2c0_sda 14 b1 10 ptb2/ irq_7 vref_out/ cmp0_in5 vref_out/ cmp0_in5 ptb2/ irq_7 lpuart0_rx lpuart0_tx 15 d2 pta8 adc0_se3 adc0_se3 pta8 i2c0_scl spi0_mosi 16 c2 pta9 adc0_se2 adc0_se2 pta9 i2c0_sda spi0_sck 5 pinout 48 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 24 qfn 20 wlc sp 16 qfn pin name default alt0 alt1 alt2 alt3 alt4 alt5 17 a1 11 ptb3/ irq_10 disabled ptb3/ irq_10 i2c0_scl lpuart0_tx 18 b2 12 ptb4/ irq_11 disabled ptb4/ irq_11 i2c0_sda lpuart0_rx 19 a2 13 ptb5/ irq_12 nmi_b adc0_se1/ cmp0_in1 ptb5/ irq_12 tpm1_ch1 nmi_b 20 b3 pta12/ irq_13/ lptmr0_alt2 adc0_se0/ cmp0_in0 adc0_se0/ cmp0_in0 pta12/ irq_13/ lptmr0_alt2 tpm1_ch0 tpm_clkin0 clkout 21 a3 ptb13/ clkout32k disabled ptb13/ clkout32k tpm1_ch1 rtc_clkout 22 a4 14 pta0/ irq_0/ llwu_p7 swd_clk adc0_se15/ cmp0_in2 pta0/ irq_0/ llwu_p7 tpm1_ch0 swd_clk 23 b4 15 pta1/ irq_1/ lptmr0_alt1 reset_b pta1/ irq_1/ lptmr0_alt1 tpm_clkin0 reset_b 24 a5 16 pta2 swd_dio pta2 cmp0_out swd_dio 5.2 kl03 pinouts the following figures show the pinout diagrams for the devices supported by this document. many signals may be multiplexed onto a single pin. to determine what signals can be used on which pin, see kl03 signal multiplexing and pin assignments . pinout kinetis kl03 32 kb flash, rev. 5.1 08/2017 49 nxp semiconductors 24 23 22 pta2 pta1/irq_1/lptmr0_alt1 pta0/irq_0/llwu_p7 pta12/irq_13/lptmr0_alt2 ptb5/irq_12 21 20 19 ptb13/clkout32k pta9 pta8 16 15 ptb4/irq_11 ptb3/irq_10 18 17 ptb2/irq_7 ptb1/irq_6 14 13 ptb0/irq_5/llwu_p4 pta7/irq_4 ptb11 ptb10 12 11 10 9 pta6 8 pta5/rtc_clk_in 7 pta4 pta3 vss vdd ptb7/irq_3 ptb6/irq_2/lptmr0_alt3 6 5 4 3 2 1 figure 17. kl03 24-pin qfn pinout diagram 1 2 3 4 a 5 ptb5 b ptb13 pta12 pta4 c pta0 pta1 pta3 pta7 d pta8 pta9 pta5 ptb1 ptb0 ptb2 pta2 vdd vss pta6 ptb3 ptb4 figure 18. kl03 20-pin wlcsp pinout diagram pinout 50 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 1 vdd 2 vss 3 pta3 4 pta4 5 pta5/rtc_clk_in 6 pta6 7 pta7/irq_4 8 ptb0/irq_5/llwu_p4 9 ptb1/irq_6 10 ptb2/irq_7 11 ptb3/irq_10 12 ptb4/irq_11 13 ptb5/irq_12 14 pta0/irq_0/llwu_p7 15 pta1/irq_1/lptmr0_alt1 16 pta2 figure 19. kl03 16-pin qfn pinout diagram 6 ordering parts 6.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to nxp.com and perform a part number search. 7 part identification 7.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. ordering parts kinetis kl03 32 kb flash, rev. 5.1 08/2017 51 nxp semiconductors 7.2 format part numbers for this device have the following format: q kl## a fff r t pp cc n 7.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): table 43. part number fields description field description values q qualification status ? m = fully qualified, general market flow(full reels for wlcsp) ? p = prequalification ? k = fully qualified, general market flow, 100 pieces reels (wlcsp only) kl## kinetis family ? kl03 a key attribute ? z = cortex-m0+ fff program flash memory size ? 8 = 8 kb ? 16 = 16 kb ? 32 = 32 kb r silicon revision ? (blank) = main ? a = revision after main t temperature range (c) ? v = C40 to 105 ? c = C40 to 85 pp package identifier ? fg = 16 qfn (3 mm x 3 mm) ? af = 20 wlcsp (2 mm x 1.61 mm x 0.56 mm) ? bf = 20 wlcsp (2 mm x 1.61 mm x 0.32 mm) ? fk = 24 qfn (4 mm x 4 mm) cc maximum cpu frequency (mhz) ? 4 = 48 mhz n packaging type ? r = tape and reel ? (blank) = trays 7.4 example this is an example part number: part identification 52 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors mkl03z32vfk4 terminology and guidelines 8.1 definition: operating requirement an operating requirement is a specified value or range of values for a technical characteristic that you must guarantee during operation to avoid incorrect operation and possibly decreasing the useful life of the chip. 8.1.1 example this is an example of an operating requirement: symbol description min. max. unit v dd 1.0 v core supply voltage 0.9 1.1 v 8.2 definition: operating behavior unless otherwise specified, an operating behavior is a specified value or range of values for a technical characteristic that are guaranteed during operation if you meet the operating requirements and any other specified conditions. 8.2.1 example this is an example of an operating behavior: symbol description min. max. unit i wp digital i/o weak pullup/ pulldown current 10 130 a 8 terminology and guidelines kinetis kl03 32 kb flash, rev. 5.1 08/2017 53 nxp semiconductors 8.3 definition: attribute an attribute is a specified value or range of values for a technical characteristic that are guaranteed, regardless of whether you meet the operating requirements. 8.3.1 example this is an example of an attribute: symbol description min. max. unit cin_d input capacitance: digital pins 7 pf 8.4 definition: rating a rating is a minimum or maximum value of a technical characteristic that, if exceeded, may cause permanent chip failure: ? operating ratings apply during operation of the chip. ? handling ratings apply when the chip is not powered. 8.4.1 example this is an example of an operating rating: symbol description min. max. unit v dd 1.0 v core supply voltage C0.3 1.2 v terminology and guidelines 54 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 8.5 result of exceeding a rating 40 30 20 10 0 measured characteristic operating rating failures in time (ppm) the likelihood of permanent chip failure increases rapidly as soon as a characteristic begins to exceed one of its operating ratings. 8.6 relationship between ratings and operating requirements C - no permanent failure - correct operation normal operating range fatal range expected permanent failure fatal range expected permanent failure operating rating (max.) operating requirement (max.) operating requirement (min.) operating rating (min.) operating (power on) degraded operating range degraded operating range C no permanent failure handling range fatal range expected permanent failure fatal range expected permanent failure handling rating (max.) handling rating (min.) handling (power off) - no permanent failure - possible decreased life - possible incorrect operation - no permanent failure - possible decreased life - possible incorrect operation 8.7 guidelines for ratings and operating requirements follow these guidelines for ratings and operating requirements: ? never exceed any of the chips ratings. terminology and guidelines kinetis kl03 32 kb flash, rev. 5.1 08/2017 55 nxp semiconductors ? during normal operation, dont exceed any of the chips operating requirements. ? if you must exceed an operating requirement at times other than during normal operation (for example, during power sequencing), limit the duration as much as possible. 8.8 definition: typical value a typical value is a specified value for a technical characteristic that: ? lies within the range of values specified by the operating behavior ? given the typical manufacturing process, is representative of that characteristic during operation when you meet the typical-value conditions or other specified conditions typical values are provided as design guidelines and are neither tested nor guaranteed. 8.8.1 example 1 this is an example of an operating behavior that includes a typical value: symbol description min. typ. max. unit i wp digital i/o weak pullup/pulldown current 10 70 130 a 8.8.2 example 2 this is an example of a chart that shows typical values for various voltage and temperature conditions: terminology and guidelines 56 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors 0.90 0.95 1.00 1.05 1.10 0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 150 c 105 c 25 c C40 c v dd (v) i (a) dd_stop t j 8.9 typical value conditions typical values assume you meet the following conditions (or other conditions as specified): table 44. typical value conditions symbol description value unit t a ambient temperature 25 c v dd 3.3 v supply voltage 3.3 v 9 revision history the following table provides a revision history for this document. table 45. revision history rev. no. date substantial changes 3.1 07/2014 initial public release. 4 08/2014 changed pinout signal names adc0_se5, adc0_se6, and adc0_se12 to adc0_se8, adc0_se9 and adc0_se15 respectively. table continues on the next page... revision history kinetis kl03 32 kb flash, rev. 5.1 08/2017 57 nxp semiconductors table 45. revision history (continued) rev. no. date substantial changes 5 07/2017 ? added new part of mkl03z32cbf4r and its package information. ? updated the resource and its footnote to the chip errata in the front page ? updated the descriptions to the vlpw to be very low power wait mode in the power consumption operating behaviors ? added a note to the t a in the thermal operating requirements ? updated the foot note to the typ. of the table 31 to be vrefo = 1.2 v ? added i2c 1 mbit/s timing specifications in inter-integrated circuit interface (i2c) timing ? updated determining valid orderable parts ? updated the 20-pin wlcsp package (af) size in fields 5.1 08/2017 updated the max. of msl for wlcsp packages to 1 in the moisture handling ratings revision history 58 kinetis kl03 32 kb flash, rev. 5.1 08/2017 nxp semiconductors how to reach us: home page: nxp.com web support: nxp.com/support information in this document is provided solely to enable system and software implementers to use nxp products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. nxp reserves the right to make changes without further notice to any products herein. nxp makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does nxp assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in nxp data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer ? s technical experts. nxp does not convey any license under its patent rights nor the rights of others. nxp sells products pursuant to standard terms and conditions of sale, which can be found at the following address: nxp.com/salestermsandconditions . nxp, the nxp logo, nxp secure connections for a smarter world, freescale, the freescale logo, and kinetis are trademarks of nxp b.v. all other product or service names are the property of their respective owners. arm, the arm powered logo, and cortex are registered trademarks of arm limited (or its subsidiaries) in the eu and/or elsewhere. all rights reserved. ?2014-2017 nxp b.v. document number KL03P24M48SF0 revision 5.1 08/2017 |
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