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yss902 ac3d dolby digital (ac-3) / pro logic decoder + sub dsp yamaha corporation yss902catalog catalog no.:lsi-4ss902a3 1998. 7 introduction the yss902 is one chip lsi consisting of two built-in dsps ; dolby digital (ac-3) / pro logic (main dsp) and a sound processing dsp (sub dsp). sub dsp is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient. featurers dolby digital 5.1 channel full decode. 24 bit dsp. (group-a dolby digital decoder) no external memory is required. (memory for center and surround channel delay is included) possible to decode multi-language encoded data. (possible to decode based on data-stream-number) ac-3 karaoke mode. original compression mode as well as four compression modes recommended by dolby. dolby digital decoding latency is fixed to two audio blocks (512 samples). included de-emphasis filter. pro logic decoding for dolby digital 2 channels decoded signal as well as ordinary pcm. high performance 25 mips programmable dsp suitable for a variety of sound field processing such as original surround, filtering, virtual surround etc. up to 1.36 second delay time is capable when used with an external 1mbit sram. (at fs= 48 khz) reads dolby digital decode information through the microprocessor interface. provide total sixteen i/o ports. possible to connect most of spdif receivers, a/d and d/a converters, by setting i/o data interface format. has a built-in pll oscillation circuit to generates its own operating clock. internal operating clock is 25mhz. supply voltage: 3.3v for core logic. 5v for i/os. power saving mode. si-gate cmos process. 100 qfp.(YSS902-F) note: "ac-3" and "pro logic" are registered trademarks of dolby laboratories licensing corporation. use of this lsi must be licensed by dolby laboratories licensing corporation.
yss902 2 pin configuration
yss902 3 pin function no. name i/o function 1 vdd1 - +5v power supply (for i/os) 2 ramcen o external sram interface /ce 3 rama16 o external sram interface address 16 4 rama15 o external sram interface address 15 5sdib0i+pcm in p ut 0 to sub dsp 6sdib1i+pcm in p ut 1 to sub dsp 7sdib2i+pcm in p ut 2 to sub dsp 8xi icr y stal oscillator connection ( 6.125mhz - 50.0mhz ) 9xo ocr y stal oscillator connection 10 vss - ground 11 avdd - +3.3 v p ower su pp l y ( for pll circuit ) 12 test test terminal ( to be o p en in normal use ) 13 test test terminal ( to be o p en in normal use ) 14 test test terminal ( to be o p en in normal use ) 15 ovfb o detection of overflow at sub dsp 16 test test terminal ( to be o p en in normal use ) 17 test test terminal ( to be o p en in normal use ) 18 test test terminal ( to be o p en in normal use ) 19 cpo a out p ut terminal for pll, to be connected to g round throu g h the external analo g filter circuit 20 avss - ground ( for pll circuit ) 21 vdd2 - +3.3 v p ower su pp l y ( for core lo g ic ) 22 sdoa2 o pcm out p ut from main dsp ( c, lfe ) 23 sdoa1 o pcm out p ut from main dsp ( ls, rs ) 24 sdoa0 o pcm out p ut from main dsp ( l, r ) 25 rama14 o external sram interface address 14 26 rama13 o external sram interface address 13 27 rama12 o external sram interface address 12 28 rama11 o external sram interface address 11 29 rama10 o external sram interface address 10 30 vss - ground 31 vdd1 - +5v p ower su pp l y ( for i/os ) 32 oport0 o out p ut p ort for g eneral p ur p ose 33 oport1 o out p ut p ort for g eneral p ur p ose 34 oport2 o out p ut p ort for g eneral p ur p ose 35 oport3 o out p ut p ort for g eneral p ur p ose 36 oport4 o out p ut p ort for g eneral p ur p ose 37 oport5 o out p ut p ort for g eneral p ur p ose 38 oport6 o out p ut p ort for g eneral p ur p ose 39 oport7 o out p ut p ort for g eneral p ur p ose 40 vss - ground 41 vdd2 - +3.3 v p ower su pp l y ( for core lo g ic ) 42 rama9 o external sram interface address 9 43 rama8 o external sram interface address 8 44 rama7 o external sram interface address 7 45 sdob2 o pcm out p ut from sub dsp 46 sdob1 o pcm out p ut from sub dsp 47 sdob0 o pcm out p ut from sub dsp 48 sdbck1 i+ bit clock in p ut for sdoa, sdib, sdob 49 sdwck1 i+ word clock in p ut for sdoa, sdib, sdob 50 vss - ground 51 vdd2 - +3.3 v p ower su pp l y ( for core lo g ic ) 52 nonpcm o detection of non-pcm data 53 crc o detection of crc error 54 mute o detection of auto mute 55 karaoke o detection of ac-3 karaoke data
yss902 4 no. name i/o function 56 surenc o detection of ac-3 2/0 mode dolb y surround encoded in p ut 57 /sdbck0 o inverted sdbck0 clock output (refer to block diagram) 58 rama6 o external sram interface address 6 59 rama5 o external sram interface address 5 60 vss - ground 61 rama4 o external sram interface address 4 62 /ic is initial clear 63 test test terminal (to be open in normal use) 64 rama3 o external sram interface address 3 65 /csb is+ sub dsp chip select 66 /cs is microprocessor interface chip select input 67 so ot microprocessor interface serial data output 68 si is microprocessor interface / sub dsp serial data input 69 sck is microprocessor interface / sub dsp clock input 70 rama2 o external sram interface address 2 71 vdd1 - +5v power supply (for i/os) 72 ramd0 i+/ o external sram interface data (stream0 output when external sram is not in use) 73 ramd1 i+/ o external sram interface data (stream1 output when external sram is not in use) 74 ramd2 i+/ o external sram interface data (stream2 output when external sram is not in use) 75 ramd3 i+/ o external sram interface data (stream3 output when external sram is not in use) 76 ramd4 i+/ o external sram interface data (stream4 output when external sram is not in use) 77 ramd5 i+/ o external sram interface data (stream5 output when external sram is not in use) 78 ramd6 i+/ o external sram interface data (stream6 output when external sram is not in use) 79 ramd7 i+/ o external sram interface data (stream7 output when external sram is not in use) 80 vss - ground 81 vdd2 - +3.3 v power supply (for core logic) 82 sdwck0 i word clock input for sdia, sdoa, sdib, sdob 83 sdbck0 i bit clock input for sdia, sdoa, sdib, sdob 84 sdia0 i ac-3 bitstream (or pcm) data input for main dsp 85 sdia1 i ac-3 bitstream (or pcm) data input for main dsp 86 rama1 o external sram interface address 1 87 rama0 o external sram interface address 0 88 ramwen o external sram interface /we 89 ramoen o external sram interface /oe 90 vss - ground 91 vdd2 - +3.3 v power supply (for core logic) 92 iport7 i+ input port for general purpose 93 iport6 i+ input port for general purpose 94 iport5 i+ input port for general purpose 95 iport4 i+ input port for general purpose 96 iport3 i+ input port for general purpose 97 iport2 i+ input port for general purpose 98 iport1 i+ input port for general purpose 99 iport0 i+ input port for general purpose 100 vss - ground note) is: schmidt trigger input terminal i+: input terminal with a pull-up resistor o: digital output terminal ot: tri-state digital output terminal a: analog terminal
yss902 5 block diagram cpo xo xi sdwck1 sdbck1 oport0 - 7 iport0 - 7 so si sck /cs ovfb rama0 - 16 ramoen ramwen ramcen ramd0 - 7 delay ram sdiasel sdia1 sdia0 sdwck0 sdbck0 /sdbck0 /csb sck si sdoacksel sdibcksel sdobcksel operating clock (25mhz) eramuse external ram sdob interface 24 * 16 sub dsp sdib interface sdoa interface sdia interface input buffer decoder 24 * 24 main dsp ac-3/pro logic data ram microprocessor control registers control signals coefficient/ program ram stream0 - 7 pll interface control signals interface sdob0 sdob1 sdob2 sdib2 sdib1 sdib0 sdoa2 sdoa1 sdoa0 surenc karaoke mute crc nonpcm crc sdibsel l, r ls, rs c, lfe
yss902 6 function description the yss902 consist of main dsp section where ac-3/pro logic decoding is executed and sub dsp section where various sound field effects are added. please refer to block diagram section. sub dsp is a 6 ch input / 6 ch output programmable dsp exclusively for the sound field processing. it can apply such effects as virtual surround, echo and equalizing. in addition, with an sram up to 1mbit connected, it can produce reverberation for one second or longer. by using this function, it is possible to simulate various sound fields such as a hall or a church. * if adopting some technology owned by another company is desired for use in sub dsp section, note that a separate contract may be required between the owner of that technology and the user with respect to adoption of the technology. 1. clocks xi, xo, cpo the crystal oscillation circuit is formed by using xi and xo terminals. oscillation frequency 50mhz is divided by 2 internally to provide the operating clock signals of 25mhz. clock signals should be obtained through self oscillation by using xi and xo terminals, or external clock signals should be fed through the xi terminal. this lsi operates in a pll oscillation mode as well. when the pll oscillation mode is selected and an external clock signal whose frequency is lower than 49mhz is fed through the xi terminal and multiplied, connect an external analog filter between cpo terminal and ground. 2. data interface sdia0, sdia1, sdoa0-2, sdib0-2, sdob0-2, sdwck0, sdbck0, sdwck1, sdbck1, /sdbck0 main dsp section ac-3 bitstream or pcm data should be fed from sdia0 or sdia1 terminal. these signals are processed by ac-3 / pro logic decoding procedure in main dsp section and then transmitted to sub dsp section as well as outputted through sdoa0-2 terminals. sub dsp section in sub dsp section, various types of processing can be applied to the pcm data decoded in main dsp section or inputted through sdib0-2 terminals. then, processed signals are outputted from each of sdob0-2 terminals. following parameters can be selected by changing the control register setting. . selection of main dsp input signal (sdia0, sdia1) . selection of sub dsp input signal (main dsp output, sdib0-2 input) . polarity of bit clock and word clock . format and bit count of input/output data for more information on the format of the input/output data, please refer to serial data interface section. 3. microprocessor interface /cs, /csb, sck, si, so the control registers can be read/written via the serial microprocessor interface by using /cs, sck, si, and so terminals. please refer to the following format diagram for the details of read/write timing.
yss902 7 format diagram for read/write timing when /cs=1, the so output becomes high-impedance. * be sure to set /csb to 1 when making an access to the control register. the sound field processing program used for sub dsp is down-loaded by using the /csb, sck, and si terminals. please refer to application manual for the details of sub dsp. 4. external interface rama0-16, ramd0-7, ramcen, ramoen, ramwen an external sram can be connected to sub dsp. 5. general purpose i/o ports oport0-7, iport0-7 oport0-7 terminals are output ports for general purpose. data written on the register (address 0x04) are outputted from these terminals. iport0-7 terminals are input ports for general purpose. data inputted to these terminals can be read from the register (address 0x05). 6. initial clear /ic this lsi requires initial clear when turning on the power. 7. lsi test terminals test leave the test terminals open in normal use.
yss902 8 control register the decoding system is controlled by reading and writing the control registers through microprocessor interface. (/cs, sck, si and so) note : all bits are set to 0 by initial clear (/ic=0) except for pll0(bit 4) of pll/dsn register (0x00). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 pll/dsn register plluse pll2-0 dsnign dsn2 - 0 0x01 mute register lmuten cmuten rmuten rsmuten lsmuten lfemuten dspmuten amoff 0x02 sdia register sdiasel pdown sdiafmt1 - 0 sdiabit1 - 0 sdiawp sdiabp 0x03 sdoa register sdoacksel sdoafmt1 - 0 sdoabit1 - 0 sdoawp sdoabp 0x04 oport register oport7 - 0 0x05 iport register iport7 - 0 (read only) 0x09 noise level register noiselev7 - 0 0x0a center delay register cdelay2 - 0 0x0b surround delay registe r srdelay3 - 0 0x0c noise register noise pn/wn 0x0d fs register fs1 - 0 0x0e l volume register lvol7 - 0 0x0f c volume register cvol7 - 0 0x10 r volume register rvol7 - 0 0x11 ls volume register lsvol7 - 0 0x12 rs volume register rsvol7 - 0 0x13 lfe volume register lfevol7 - 0 0x14 compression register empon aibon volon dithoff p11off dialoff compmod1 - 0 0x15 hdynrng register hdynrng7 - 0 0x16 ldynrng register ldynrng7 - 0 0x17 mode register ac3/pcm pldecon plsrmod dualmod1 - 0 outmod2 - 0 0x30 coef0-h register coef0-15 - 8 0x31 coef0-l register coef0-7 - 0 0x32 coef1-h register coef1-15 - 8 0x33 coef1-l register coef1-7 - 0 0x34 sdib register sdibcksel sdibsel sdibfmt1 - 0 sdibbit1 - 0 sdibwp sdibbp 0x35 sdob register sdobcksel sdbuse sdobfmt1 - 0 sdobbit1 - 0 sdobwp sdobbp 0x36 eram register eramuse note : do not write "1" into the cross-hatched bits because the y are used for testin g the lsi. the following registers of address 0x18 to 0x2f are read-only (write disabled). address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x18 bitstream register 0 fscod frmsi zecod 0x19 bitstream register 1 bsid bsmod 0x1a bitstream register 2 acmod cmixlev surmixlev lfeon 0x1b bitstream register 3 dsurmod copyrightb origbs 0 0 0 0 0x1c bitstream register 4 0 0 0 dialnorm 0x1d bitstream register 5 0 0 0 dialnorm2 0x1e bitstream register 6 audprodie mixlevel roomtyp 0x1f bitstream register 7 audprodi2e mixlevel2 roomtyp2 0x20 bitstream register 8 timecod1e 0 timecod1 0x21 bitstream register 9 timecod1 0x22 bitstream register 10 timecod2e 0 timecod2 0x23 bitstream register 11 timecod2 0x24 bitstream register 12 langcode langcod2e compre compr2e 0 0 0 0 0x25 bitstream register 13 langcod
yss902 9 (registermap continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x26 bitstream register 14 langcod2 0x27 bitstream register 15 compr 0x28 bitstream register 16 compr2 0x29 bitstream register 17 dynrng 0x2a bitstream register 18 dynrng2 0x2b 0x2c 0x2d (not used) (write disable, all 0 out when read) 0x2e data stream register stream7 stream6 stream5 stream4 stream3 stream2 stream1 stream0 0x2f status register 0 0 2/0mode surenc karaoke mute crc nonpcm address 0x06 to 0x08 and 0x37 to 0x7f are assigned for test. never access to these registers. please refer to application manual for details of control register. serial data interface data timing of the serial data interface is as follows. please refer to application manual for details of sdia, sdoa, sdib, and sdob registers.
yss902 10 electrical characteristics 1. absolute maximum ratings parameter symbol min. max. unit power supply voltage v dd1 vss-0.5 vss+7.0 v v dd2 , av dd vss-0.5 v ss +4.6 v input voltage v i vss-0.5 v dd1 +0.5 v storage temperature t stg -50 125 c 2. recommended operating conditions parameter symbol min. typ. max. unit power supply voltage v dd1 4.75 5.0 5.25 v v dd2 , av dd 3. 0 3.3 3.6 v operating temperature t op 02570 c 3. dc characteristics (condition: under recommended operating conditions) parameter symbol condition min. typ. max. unit input voltage h level (1) v ih1 *1 0.7v dd1 v input voltage h level (2) v ih2 *2 2.2 v input voltage l level (1) v il1 *1 0.2v dd1 v input voltage l level (2) v il2 *2 0.8 v output voltage h level v oh i oh = -80 m a v dd1 -1.0 v output voltage l level v ol i ol = 1.6 ma 0.4 v input leakage current i li terminal without a pull-up resistor -10 10 m a pull-up resistor r u 25 100 k w power consumption p d xi=50mhz, pll not used 250 500 mw *1 applicable to xi and /ic input terminals. *2 applicable to input terminals except xi and /ic terminals. 4. xi parameter symbol conditions min typ max unit xi clock frequency x in 6.125 50 mhz xi clock duty x duty 40 50 60 %
yss902 11 external dimensions c-pk100fp-1 the figure in the parenthesis ( ) should be used as a reference. plastic body dimensions do not include burr of resin. unit: mm 1 30 0.15 0.05 2.95 max. 0 min. (stand off) 0-15 1.20 0.20 (2.40) 80 51 24.80 0.40 14.00 0.30 p-0.65typ 0.30 0.10 20.00 0.30 18.80 0.40 50 31 100 81 (lead thickness)
yss902 copying prohibited ? 1987 yamaha corporation printed in japan important notice 1. yamaha reserves the right to make changes to its products and to this document without notice. the information contained in this document has been carefully checked and is believed to be reliable. however, yamaha assumes no responsibilities fo r inaccuracies and makes no commitment to update or to keep current the information contained in this document. 2. these yamaha products are designed only for commercial and normal industrial applications, and are not suitable for other uses, such as medical life support equipment, nuclear facilities, critical care equipment or any other application the failure of which could lead to death, personal injury or environmental or property damage. use of the products in any such application is at the customer's sole risk and expense. 3. yamaha assumes no liability for incidental, consequential or special damages or injury that may result from misapplication or improper use or operation of the products. 4. yamaha makes no warranty or representation that the products are subject to intellectual property license from yamaha or anythird party, and yamaha makes no warranty or representation of non-infringement with respect to the products. yamaha specifically excludes any liability to the customer or any third party arising from or related to the products' infringement of any third party's intellectual property rights, including the patent, copyright, trademark or trade secret rights of any third party. 5. examples of use described herein are merely to indicate the characteristics and performance of yamaha products. yamaha assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. yamaha makes no warranty with respect to the products, express or implied, including, but not limited to the warranties of merchantability, fitness for a particular use and title. note) the specifications of this product are subject to improvement change without prior notice. head office tokyo office osaka office 203, matsunokijima, toyooka-mura, tel. +81-539-62-4918 2-17-11, takanawa, minato-ku, tokyo, 108-8568 yamaha corporation semi-conductor sales & marketing department agency address inquiries to: iwata-gun, shizuoka-ken,438-0192 fax. +81-539-62-5054 tel. +81-3-5488-5431 fax. +81-3-5488-5088 u.s.a office 1-13-17, nanba-naka, naniwa-ku osaka city, osaka, 556-0011 tel. +81-6-633-3690 fax. +81-6-633-3691 yamaha systems technology. 100 century center court, san jose, ca 95112 tel. +1-408-467-2300 fax. +1-408-437-8791 nanba tsujimoto nissei bldg. 4f

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