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ICM7555
General purpose CMOS timer
Rev. 02 -- 3 August 2009 Product data sheet
1. General description
The ICM7555 is a CMOS timer providing significantly improved performance over the standard NE/SE555 timer, while at the same time being a direct replacement for those devices in most applications. Improved parameters include low supply current, wide operating supply voltage range, low THRESHOLD, TRIGGER, and RESET currents, no crowbarring of the supply current during output transitions, higher frequency performance and no requirement to decouple CONTROL_VOLTAGE for stable operation. The ICM7555 is a stable controller capable of producing accurate time delays or frequencies. In the one-shot mode, the pulse width of each circuit is precisely controlled by one external resistor and capacitor. For astable operation as an oscillator, the free-running frequency and the duty cycle are both accurately controlled by two external resistors and one capacitor. Unlike the NE/SE555 device, the CONTROL_VOLTAGE terminal need not be decoupled with a capacitor. The TRIGGER and RESET inputs are active LOW. The output inverter can source or sink currents large enough to drive TTL loads or provide minimal offsets to drive CMOS loads.
2. Features
I I I I I I I I I I I I I Exact equivalent in most applications for NE/SE555 Low supply current: 80 A (typical) Extremely low trigger, threshold, and reset currents: 20 pA (typical) High-speed operation: 500 kHz guaranteed Wide operating supply voltage range guaranteed 3 V to 16 V over full automotive temperatures Normal reset function; no crowbarring of supply during output transition Can be used with higher-impedance timing elements than the NE/SE555 for longer time constants Timing from microseconds through hours Operates in both astable and monostable modes Adjustable duty cycle High output source/sink driver can drive TTL/CMOS Typical temperature stability of 0.005 % / C at 25 C Rail-to-rail outputs
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ICM7555
General purpose CMOS timer
3. Applications
I I I I I I I Precision timing Pulse generation Sequential timing Time delay generation Pulse width modulation Pulse position modulation Missing pulse detector
4. Ordering information
Table 1. Ordering information Temperature range Tamb = 0 C to +70 C Tamb = -40 C to +85 C Tamb = 0 C to +70 C Tamb = -40 C to +85 C DIP8 plastic dual in-line package; 8 leads (300 mil) SOT97-1 Package Name ICM7555CD ICM7555ID ICM7555CN ICM7555IN SO8 Description plastic small outline package; 8 leads; body width 3.9 mm Version SOT96-1 Type number
5. Functional diagram
flip-flop VDD 8 R comparator A 6 THRESHOLD 5 CONTROL_VOLTAGE R comparator B TRIGGER 2 R 1 GND DISCHARGE 7 N 1 GND RESET 4
output drivers 3 OUTPUT
002aae403
Remark: Unused inputs should be connected to appropriate voltage from Table 3.
Fig 1.
Functional diagram
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6. Pinning information
6.1 Pinning
GND TRIGGER OUTPUT RESET
1 2 3 4
002aae400
8
VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE
GND TRIGGER OUTPUT RESET
1
8
VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE
ICM7555CD 7 ICM7555ID
6 5
2 ICM7555CN 7 3 4
002aae401
ICM7555IN
6 5
Fig 2.
Pin configuration for SO8
Fig 3.
Pin configuration for DIP8
6.2 Pin description
Table 2. Symbol GND TRIGGER OUTPUT RESET CONTROL_VOLTAGE THRESHOLD DISCHARGE VDD Pin description Pin 1 2 3 4 5 6 7 8 Description supply ground start timer input; (active LOW) timer logic level output timer inhibit input; (active LOW) timing capacitor upper voltage sense input timing capacitor lower voltage sense input timing capacitor discharge output supply voltage
7. Functional description
Refer to Figure 1 "Functional diagram".
7.1 Function selection
Table 3. don't care > 23 V+ Vth < 23 V+ don't care
[1]
Function selection TRIGGER voltage don't care > 13 V+ Vtrig > 13 V+ <
1 3
THRESHOLD voltage
RESET[1] L H H H
OUTPUT L L stable H
Discharge switch on on stable off
V+
RESET will dominate all other inputs; TRIGGER will dominate over THRESHOLD.
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General purpose CMOS timer
8. Limiting values
Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI Parameter supply voltage input voltage TRIGGER CONTROL_VOLTAGE THRESHOLD RESET IO P output current power dissipation Tamb = 25 C (still air) DIP8 package SO8 package Tstg Tsp
[1]
[2][3] [1]
Conditions
Min -0.3 -0.3 -0.3 -0.3 -65 -
Max 18 VDD + 0.3 VDD + 0.3 VDD + 0.3 VDD + 0.3 100 1160 780 +150 300
Unit V V V V V mA mW mW C C
storage temperature solder point temperature soldering 60 s
Due to the SCR structure inherent in the CMOS process used to fabricate these devices, connecting any terminal to a voltage greater than VDD + 0.3 V or less than GND - 0.3 V may cause destructive latch-up. For this reason it is recommended that no inputs from external sources not operating from the same power supply be applied to the device before its power supply is established. In multiple systems, the supply of the ICM7555 must be turned on first. Above 25 C, derate at the following rates: DIP8 package at 9.3 mW / C SO8 package at 6.2 mW / C Refer to Section 11.2 "Power supply considerations" section.
[2]
[3]
9. Characteristics
Table 5. Characteristics Tamb = 25 C unless otherwise specified. Sym bol VDD IDD Parameter supply voltage supply current[1] Conditions Tmin Tamb Tmax VDD = Vmin VDD = Vmax Astable mode timing[2][3] f/f frequency stability VDD = 5 V VDD = 10 V VDD = 15 V VI input voltage TRIGGER: VDD = 5 V CONTROL_VOLTAGE: VDD = 5 V THRESHOLD: VDD = 5 V RESET: VDD = Vmin and Vmax 0.29VDD 0.62VDD 0.63VDD 0.4VDD 1.0 0.1 50 75 100 0.31VDD 0.65VDD 0.65VDD 0.7VDD 5.0 3.0 0.34VDD 0.67VDD 0.67VDD 1.0VDD % %/V ppm/C ppm/C ppm/C V V V V f/V frequency variation with voltage f/T frequency variation with temperature[4] Min 3 Typ 50 180 Max 16 200 300 Unit V A A
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ICM7555
General purpose CMOS timer
Table 5. Characteristics ...continued Tamb = 25 C unless otherwise specified. Sym bol II Parameter input current Conditions TRIGGER VDD = Vtrig = Vmax VDD = Vtrig = 5 V VDD = Vtrig = Vmin THRESHOLD VDD = Vth = Vmax VDD = Vth = 5 V VDD = Vth = Vmin RESET VDD = Vrst = Vmax VDD = Vrst = 5 V VDD = Vrst = Vmin VOL VOH LOW-level output voltage HIGH-level output voltage VDD = Vmax; Isink = 3.2 mA VDD = 5 V; Isink = 3.2 mA Isource = -1.0 mA VDD = Vmax VDD = 5 Vmax Vo tr(o) tf(o) fosc
[1] [2]
Min
Typ
Max
Unit
15.25 4.0 -
50 10 1 50 10 1 100 20 2 0.1 0.2 15.7 4.5 0.2 45 20 -
0.4 0.4 0.4 75 75 500
pA pA pA pA pA pA pA pA pA V V V V V ns ns kHz
output voltage output rise time[4] output fall time[4] oscillator frequency
DISCHARGE: VDD = 5 V; IDIS = 10 mA RL = 10 M; CL = 10 pF; VDD = 5 V astable mode
-
The supply current value is essentially independent of the TRIGGER, THRESHOLD and RESET voltages. Astable timing is calculated using the following equation:
1.38 f = -------------------------------( R A + 2R B )C
The components are defined in Figure 15. [3] [4] RA, RB = 1 k to 100 k; C = 0.1 F; 5 V < VDD < 15 V Parameter is not 100 % tested.
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General purpose CMOS timer
10. Typical performance curves
002aae404
250 IDD (A) 200
150
Tamb = -55 C +25 C +125 C
100
50
0 0 5 10 15 VDD (V) 20
Fig 4.
Supply current versus supply voltage
102
002aae405
Io(source) (mA) 10
VDD = 18 V 5V 2V
1
10-1 10-1
1
10
VDD - VO (V)
102
Tamb = +25 C.
Fig 5.
High output voltage drop versus output source current
102 IDIS (mA) 10
002aae406
1
VDD = 18 V 5V 2V
10-1 10-1
1 VDIS (V)
10
Tamb = +25 C.
Fig 6.
Discharge low output voltage versus discharge sink current
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General purpose CMOS timer
102 Io(sink) (mA) 10 VDD = 18 V 5V 2V
002aae407
1
10-1 10-1
1 VOL (V)
10
a. Tamb = +125 C.
102 Io(sink) (mA) 10 VDD = 18 V 5V 2V
002aae408
1
10-1 10-1
1 VOL (V)
10
b. Tamb = +25 C.
102 Io(sink) (mA) 10 VDD = 18 V 5V 2V
002aae409
1
10-1 10-1
1 VOL (V)
10
c. Tamb = -55 C. Fig 7. Low output voltage versus output sink current
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ICM7555
General purpose CMOS timer
500 TRIGGER pulse width (ns) 400 VDD = 18 V 5V 2V
002aae410
300
200
100
0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 8.
Minimum pulse width for triggering
1000
002aae411
tPD (ns) 750
Tamb = -55 C +25 C +125 C
500
250
0 0 10 20 30 40 lowest voltage level of TRIGGER pulse (% VDD)
Fig 9.
Propagation delay versus voltage level of TRIGGER pulse (VDD = 5 V)
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General purpose CMOS timer
6 normalized frequency (%) 4
002aae413
2
0 -2 -4 0 5 10 15 VDD (V) 20
Tamb = +25 C RA = RB = 10 k C = 0.1 F
Fig 10. Normalized frequency stability as a function of supply voltage (astable mode)
4 normalized frequency (%) 2 VDD = 18 V 5V 2V
002aae414
0
-2
-4 -75
-25
25
75 Tamb (C)
125
RA = RB = 1 k C = 0.1 F
Fig 11. Normalized frequency stability as a function of temperature (astable mode)
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General purpose CMOS timer
102 C (F) 10 1 10-1 10-2 10-3 10-4 10-5 10-1 1 k 10 k 100 k 1 M 10 M
002aae415
1
10
102
103
104
105
106 f (Hz)
107
VDD = 5 V; Tamb = +25 C
Fig 12. Free-running frequency as a function of RA, RB resistance and external capacitance
102 C (F) 10 1 10-1 10-2 10-3 10-4 10-5 10-7 1 k 10 k 100 k 1 M 10 M
002aae416
10-6
10-5
10-4
10-3
10-2
10-1
1 td (s)
10
VDD = 5 V; Tamb = +25 C
Fig 13. Monostable time delay versus RA resistance and external capacitance
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11. Application information
11.1 General
The ICM7555 device is, in most instances, a direct replacement for the NE/SE555 device. However, it is possible to effect economies in the external component count using the ICM7555. Because the NE/SE555 device produces large crowbar currents in the output driver, it is necessary to decouple the power supply lines with a good capacitor close to the device. The ICM7555 device produces no such transients. See Figure 14. The ICM7555 produces supply current spikes of only 2 mA to 3 mA instead of 300 mA to 400 mA and supply decoupling is normally not necessary. Secondly, in most instances, the CONTROL_VOLTAGE decoupling capacitors are not required since the input impedance of the CMOS comparators on chip are very high. Thus, for many applications, 2 capacitors can be saved using an ICM7555.
500 IDD (mA) 300
002aae417
(1)
100
(2)
-100 0 200 400 600 time (ns) 800
Tamb = +25 C (1) NE/SE555 (2) ICM7555
Fig 14. Supply current transient compared with a standard NE/SE555 device during an output transition
11.2 Power supply considerations
Although the supply current consumed by the ICM7555 device is very low, the total system supply can be high unless the timing components are high-impedance. Therefore, high values for R and low values for C in Figure 15 and Figure 16 are recommended.
11.3 Output drive capability
The output driver consists of a CMOS inverter capable of driving most logic families including CMOS and TTL. As such, if driving CMOS, the output swing at all supply voltages will equal the supply voltage. At a supply voltage of 4.5 V or more, the ICM7555 will drive at least 2 standard TTL loads.
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General purpose CMOS timer
11.4 Astable operation
If the circuit is connected as shown in Figure 15, it will trigger itself and free run as a multivibrator. The external capacitor charges through RA and RB and discharges through RB only. Thus, the duty cycle () may be precisely set by the ratio of these two resistors. In this mode of operation, the capacitor charges and discharges between 13 VDD and 2 V . Since the charge rate and the threshold levels are directly proportional to the 3 DD supply voltage, the frequency of oscillation is independent of the supply voltage. 1.38 f = ------------------------------------( R A + 2R B ) x C R A + RB = ---------------------R A + 2R B (1)
(2)
VDD
1 2 3
GND TRIGGER OUTPUT RESET
VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE
8 7 6 5
VDD
RA
OUTPUT
RB
VDD
4
C
002aae418
Fig 15. Astable operation
11.5 Monostable operation
In this mode of operation, the timer functions as a one-shot. Initially, the external capacitor (C) is held discharged by a transistor inside the timer. Upon application of a negative pulse to pin 2, TRIGGER, the internal flip-flop is set, which releases the low-impedance on DISCHARGE; the external capacitor charges and drives the OUTPUT HIGH. The voltage across the capacitor increases exponentially with a time constant t = RAC. When the voltage across the capacitor equals 23 V+, the comparator resets the flip-flop, which in turn discharges the capacitor rapidly and also drives the OUTPUT to its LOW state. TRIGGER must return to a HIGH state before the OUTPUT can return to a LOW state.
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General purpose CMOS timer
VDD 1 2 3 4 8 7 6 5
optional capacitor C RA
GND TRIGGER OUTPUT RESET
VDD DISCHARGE THRESHOLD CONTROL_VOLTAGE
002aae419
VDD 18 V; t = 1.05 RAC
Fig 16. Monostable operation
11.6 Control voltage
The CONTROL_VOLTAGE terminal permits the two trip voltages for the THRESHOLD and TRIGGER internal comparators to be controlled. This provides the possibility of oscillation frequency modulation in the astable mode, or even inhibition of oscillation, depending on the applied voltage. In the monostable mode, delay times can be changed by varying the applied voltage to the CONTROL_VOLTAGE pin.
11.7 RESET
The RESET terminal is designed to have essentially the same trip voltage as the standard NE/SE555 device, i.e., 0.6 V to 0.7 V. At all supply voltages it represents an extremely high input impedance. The mode of operation of the RESET function is, however, much improved over the standard NE/SE555 device in that it controls only the internal flip-flop, which in turn controls simultaneously the state of the OUTPUT and DISCHARGE pins. This avoids the multiple threshold problems sometimes encountered with slow falling edges in the NE/SE555 devices.
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12. Package outline
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Notes 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03 JEDEC MS-012 JEITA EUROPEAN PROJECTION A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.05 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8o o 0
ISSUE DATE 99-12-27 03-02-18
Fig 17. Package outline SOT96-1 (SO8)
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General purpose CMOS timer
DIP8: plastic dual in-line package; 8 leads (300 mil)
SOT97-1
D seating plane
ME
A2
A
L
A1
c Z e b1 wM (e 1) b2 5 MH
b 8
pin 1 index E
1
4
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.02 A2 max. 3.2 0.13 b 1.73 1.14 0.068 0.045 b1 0.53 0.38 0.021 0.015 b2 1.07 0.89 0.042 0.035 c 0.36 0.23 0.014 0.009 D (1) 9.8 9.2 0.39 0.36 E (1) 6.48 6.20 0.26 0.24 e 2.54 0.1 e1 7.62 0.3 L 3.60 3.05 0.14 0.12 ME 8.25 7.80 0.32 0.31 MH 10.0 8.3 0.39 0.33 w 0.254 0.01 Z (1) max. 1.15 0.045
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT97-1 REFERENCES IEC 050G01 JEDEC MO-001 JEITA SC-504-8 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 18. Package outline SOT97-1 (DIP8)
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13. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
13.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
13.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
13.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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13.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 19) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 6 and 7
Table 6. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 7. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 19.
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temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 19. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
14. Soldering of through-hole mount packages
14.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
14.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
14.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
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14.4 Package related soldering information
Table 8. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2]
[1] [2]
Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.
15. Abbreviations
Table 9. Acronym CMOS TTL SCR Abbreviations Description Complementary Metal-Oxide Semiconductors Transistor-Transistor Logic Silicon-Controlled Rectifier
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16. Revision history
Table 10. Revision history Release date 20090803 Data sheet status Product data sheet Change notice Supersedes ICM7555_1 Document ID ICM7555_2 Modifications:
* * * * *
The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Provided separate pinning diagrams for SO8 and DIP8 packages (Figure 2 and Figure 3, respectively). Added Table 2 "Pin description". Table 4 "Limiting values": - Symbols VTRIG, VCV, VTH, VRST are replaced with VI (specific pin names are now noted under Conditions column). - Symbol/parameter "PDMAX, maximum power dissipation" replaced with "P, power dissipation" (only maximum values given). - Symbol/parameter "TSTG, storage temperature range" replaced with "Tstg, storage temperature". - Symbol changed from "TSOLD" to "Tsp, solder point temperature"
*
Table 5 "Characteristics": - Symbols f/f, f/V, f/T, have been added for Astable mode timing. - Symbols VTRIG, VCV, VTH, VRST are replaced with VI (specific pin names are now noted under Conditions column). - Symbols ITRIG, ITH, IRST are replaced with II (specific pin names are now noted under Conditions column). - Symbol/parameter "VDIS, discharge output voltage" changed to "Vo, output voltage" (specific pin name is now noted under Conditions column). - Symbol/parameter "tR, rise time of output" changed to "tr(o), output rise time". - Symbol/parameter "tF, fall time of output" changed to "tf(o), output fall time". - Symbol "FMAX" changed to "fosc, oscillator frequency".
* * * *
ICM7555_1
Section 11.4 "Astable operation": changed symbol for duty cycle from "D" to "". Added Section 12 "Package outline". Added soldering information. Added Section 15 "Abbreviations". Product specification ECN 853-1192 13721 dated 1994 Aug 31 -
19940831
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NXP Semiconductors
ICM7555
General purpose CMOS timer
17. Legal information
17.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
17.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
17.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners.
18. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
ICM7555_2
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 02 -- 3 August 2009
21 of 22
NXP Semiconductors
ICM7555
General purpose CMOS timer
19. Contents
1 2 3 4 5 6 6.1 6.2 7 7.1 8 9 10 11 11.1 11.2 11.3 11.4 11.5 11.6 11.7 12 13 13.1 13.2 13.3 13.4 14 14.1 14.2 14.3 14.4 15 16 17 17.1 17.2 17.3 17.4 18 19 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 Functional description . . . . . . . . . . . . . . . . . . . 3 Function selection. . . . . . . . . . . . . . . . . . . . . . . 3 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Typical performance curves . . . . . . . . . . . . . . . 6 Application information. . . . . . . . . . . . . . . . . . 11 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Power supply considerations . . . . . . . . . . . . . 11 Output drive capability . . . . . . . . . . . . . . . . . . 11 Astable operation . . . . . . . . . . . . . . . . . . . . . . 12 Monostable operation . . . . . . . . . . . . . . . . . . . 12 Control voltage . . . . . . . . . . . . . . . . . . . . . . . . 13 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 14 Soldering of SMD packages . . . . . . . . . . . . . . 16 Introduction to soldering . . . . . . . . . . . . . . . . . 16 Wave and reflow soldering . . . . . . . . . . . . . . . 16 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 16 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 17 Soldering of through-hole mount packages . 18 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Soldering by dipping or by solder wave . . . . . 18 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 18 Package related soldering information . . . . . . 19 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . 20 Legal information. . . . . . . . . . . . . . . . . . . . . . . 21 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 21 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Contact information. . . . . . . . . . . . . . . . . . . . . 21 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 3 August 2009 Document identifier: ICM7555_2

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