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Renesas Electronics Corporation.<br>Renesas Electronics, Corp.<br>
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| Part No. |
M38030For='#FF0000'>2L-XXXHP M38030For='#FF0000'>2L-XXXKP M38030For='#FF0000'>2L-XXXSP M38030For='#FF0000'>2L-XXXWG M38030MAL-XXXWG M38030MAL-XXXKP M38030FAL-XXXSP M38031FAL-XXXHP M38030FAL-XXXWG M38030MAL-XXXHP M38030FAL-XXXKP M38031FAL-XXXKP M38030FAL-XXXHP M38031FAL-XXXSP M38031FAL-XXXWG M38030MAL-XXXSP M38030F3L-XXXHP M38030F3L-XXXWG M38030M3L-XXXKP M38030F3L-XXXSP M38030F3L-XXXKP M38030M3L-XXXHP M38030FbL-XXXWG M38030MbL-XXXHP M38030FbL-XXXHP M38030FbL-XXXSP M38030MbL-XXXKP M38030Mor='#FF0000'>2L-XXXHP M38030Mor='#FF0000'>2L-XXXKP M38030Mor='#FF0000'>2L-XXXSP M38030Mor='#FF0000'>2L-XXXWG M38031For='#FF0000'>2L-XXXHP M38031For='#FF0000'>2L-XXXKP M38031For='#FF0000'>2L-XXXSP M38031For='#FF0000'>2L-XXXWG M38030Fb-XXXHP M38031FbL-XXXSP M38035MbL-XXXSP M38038FbL-XXXSP M38039FbL-XXXSP M38030MbL-XXXSP M38036MbL-XXXSP M38037FbL-XXXSP M38037MbL-XXXSP M38036FbL-XXXSP M38038MbL-XXXSP M38031FC-XXXHP M38031FC-XXXKP M38031FC-XXXWG M38031FCL-XXXHP M38031FCL-XXXKP M38031FCL-XXXSP M38031FCL-XXXWG M38031F5-XXXKP M38031F5-XXXSP M38031F5-XXXWG M38031F5L-XXXHP M38031F5L-XXXKP M38031F5L-XXXSP M38031F5L-XXXWG M38030F1-XXXHP M38030F1-XXXKP M38030F1-XXXSP M38030F1-XXXWG M38030F1L-XXXHP M38030F1L-XXXKP M38030F1L-XXXSP M38030F1L-XXXWG M38031F1-XXXKP M38031F1-XXXWG M38031F1L-XXXHP M38031F1L-XXXKP M38031F6-XXXHP M38031F6-XXXKP M38031F6-XXXSP M38031F6-XXXWG M
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| Description |
or='#FF0000'>256 Kbit (3or='#FF0000'>2K x 8) nvSRAM; organization: 3or='#FF0000'>2Kb x 8; Vcc (V): or='#FF0000'>2.7 to 3.6 V; Density: or='#FF0000'>256 Kb; Package: SOIC<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C<br>or='#FF0000'>256K (3or='#FF0000'>2K x 8) Static RAM; Density: or='#FF0000'>256 Kb; organization: 3or='#FF0000'>2Kb x 8; Vcc (V): 4.50 to 5.50 V;<br>Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 1 MHz to or='#FF0000'>200 MHz; Outputs: 6<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: or='#FF0000'>256; Vcc (V): 3.3; fMax (MHz): 66; tPD (ns): 1or='#FF0000'>2<br>8-or='#FF0000'>mbit (51or='#FF0000'>2K x 16) Static RAM; Density: 8 Mb; organization: 51or='#FF0000'>2Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: 51or='#FF0000'>2Kb x 18; Vcc (V): 3.1 to 3.6 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; organization: 51or='#FF0000'>2Kb x 18; Vcc (V): 3.1 to 3.6 V<br>18-or='#FF0000'>mbit QDR(TM)-II SRAM 4-Word burst Architecture; Architecture: QDR-II, 4 Word burst; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): 1.7 to 1.9 V<br>Four Output PCI-X and General Purpose buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 140 MHz; Outputs: 4; Operating Range: 0 to 70 C<br>18-or='#FF0000'>mbit QDR(TM)-II SRAM or='#FF0000'>2-Word burst Architecture; Architecture: QDR-II, or='#FF0000'>2 Word burst; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): 1.7 to 1.9 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Flow-Through SRAM with NobL(TM) Architecture; Architecture: NobL, Flow-through; Density: 9 Mb; organization: 51or='#FF0000'>2Kb x 18; Vcc (V): 3.1 to 3.6 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 9 Mb; organization: 51or='#FF0000'>2Kb x 18; Vcc (V): or='#FF0000'>2.4 to or='#FF0000'>2.6 V<br>4-or='#FF0000'>mbit (51or='#FF0000'>2K x 8) Static RAM; Density: 4 Mb; organization: 51or='#FF0000'>2Kb x 8; Vcc (V): 4.50 to 5.50 V;<br>4-or='#FF0000'>mbit (or='#FF0000'>256K x 16) Static RAM; Density: 4 Mb; organization: or='#FF0000'>256Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>64K x 16 Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>1-or='#FF0000'>mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 4.5 to 5.5 V;<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): 3.1 to 3.6 V<br>1-or='#FF0000'>mbit (64K x 16) Static RAM; Density: 1 Mb; organization: 64Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>4 or='#FF0000'>mbit (51or='#FF0000'>2K x 8/or='#FF0000'>256K x 16) nvSRAM; organization: 51or='#FF0000'>2Kb x 8; Vcc (V): or='#FF0000'>2.7 to 3.6 V; Density: 4 Mb; Package: TSOP<br>4 or='#FF0000'>mbit (51or='#FF0000'>2K x 8/or='#FF0000'>256K x 16) nvSRAM; organization: or='#FF0000'>256Kb x 16; Vcc (V): or='#FF0000'>2.7 to 3.6 V; Density: 4 Mb; Package: TSOP<br>16-or='#FF0000'>mbit (1M x 16 / or='#FF0000'>2M x 8) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 4.50 to 5.50 V;<br>4K x 16/18 and 8K x 16/18 Dual-Port Static RAM with SEM, INT, bUSY; Density: 1or='#FF0000'>28 Kb; organization: 8Kb x 16; Vcc (V): 4.5 to 5.5 V; Speed: 35 ns<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): 3.1 to 3.6 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Flow-Through SRAM with NobL(TM) Architecture; Architecture: NobL, Flow-through; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): 3.1 to 3.6 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): or='#FF0000'>2.4 to or='#FF0000'>2.6 V<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 9 Mb; organization: 51or='#FF0000'>2Kb x 18; Vcc (V): 3.1 to 3.6 V<br>8-or='#FF0000'>mbit (51or='#FF0000'>2K x 16) Static RAM; Density: 8 Mb; organization: 51or='#FF0000'>2Kb x 16; Vcc (V): 4.50 to 5.50 V;<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): 3.1 to 3.6 V<br>or='#FF0000'>256K x 16 Static RAM; Density: 4 Mb; organization: or='#FF0000'>256Kb x 16; Vcc (V): 4.5 to 5.5 V;<br>9-or='#FF0000'>mbit (or='#FF0000'>256K x 36/51or='#FF0000'>2K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 9 Mb; organization: or='#FF0000'>256Kb x 36; Vcc (V): 3.1 to 3.6 V<br>4-or='#FF0000'>mbit (or='#FF0000'>256K x 16) Static RAM; Density: 4 Mb; organization: or='#FF0000'>256Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>8-or='#FF0000'>mbit (10or='#FF0000'>24K x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>18-or='#FF0000'>mbit (51or='#FF0000'>2K x 36/1M x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): 3.1 to 3.6 V<br>or='#FF0000'>256K x 16 Static RAM; Density: 4 Mb; organization: or='#FF0000'>256Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>8-or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>3.3V Zero Delay buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: -40 to 85 C<br>Programmable Skew Clock buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C<br>18-or='#FF0000'>mbit (51or='#FF0000'>2K x 36/1M x 18) Flow-Through SRAM with NobL(TM) Architecture; Architecture: NobL, Flow-through; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): 3.1 to 3.6 V<br>18-or='#FF0000'>mbit (51or='#FF0000'>2K x 36/1M x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 3.1 to 3.6 V<br>51or='#FF0000'>2K x 8 Static RAM; Density: 4 Mb; organization: 51or='#FF0000'>2Kb x 8; Vcc (V): 4.5 to 5.5 V;<br>18-or='#FF0000'>mbit (51or='#FF0000'>2K x 36/1M x 18) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): or='#FF0000'>2.4 to or='#FF0000'>2.6 V<br>or='#FF0000'>2.5V or 3.3V, or='#FF0000'>200-MHz, 1:1or='#FF0000'>2 Clock Distribution buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 1or='#FF0000'>2; Operating Range: -40 to 85 C<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C<br>or='#FF0000'>2M x 8 Static RAM; Density: 16 Mb; organization: or='#FF0000'>2Mb x 8; Vcc (V): 3.0 to 3.6 V;<br>16 or='#FF0000'>mbit (51or='#FF0000'>2K X 3or='#FF0000'>2) Static RAM; Density: 16 Mb; organization: 51or='#FF0000'>2Kb x 3or='#FF0000'>2; Vcc (V): 3.0 to 3.6 V;<br>3.3V Zero Delay buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>8-or='#FF0000'>mbit (1M x 8) Static RAM; Density: 8 Mb; organization: 1Mb x 8; Vcc (V): 3.0 to 3.6 V;<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 1or='#FF0000'>25; tPD (ns): 6<br>or='#FF0000'>2-or='#FF0000'>mbit (1or='#FF0000'>28K x 16) Static RAM; Density: or='#FF0000'>2 Mb; organization: 1or='#FF0000'>28Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>16-or='#FF0000'>mbit (1M x 16) Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;<br>4-or='#FF0000'>mbit (or='#FF0000'>256K x 18) Pipelined DCD Sync SRAM; Architecture: Standard Sync, Pipeline DCD; Density: 4 Mb; organization: or='#FF0000'>256Kb x 18; Vcc (V): 3.1 to 3.6 V<br>51or='#FF0000'>2K (3or='#FF0000'>2K x 16) Static RAM; Density: 51or='#FF0000'>2 Kb; organization: 3or='#FF0000'>2Kb x 16; Vcc (V): 3.0 to 3.6 V;<br>4-or='#FF0000'>mbit (1or='#FF0000'>28K x 36) Pipelined SRAM with NobL(TM) Architecture; Architecture: NobL, Pipeline; Density: 4 Mb; organization: 1or='#FF0000'>28Kb x 36; Vcc (V): 3.1 to 3.6 V<br>1M x 16 Static RAM; Density: 16 Mb; organization: 1Mb x 16; Vcc (V): 3.0 to 3.6 V;<br>Programmable Skew Clock buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C<br>MobL(R) or='#FF0000'>2 or='#FF0000'>mbit (1or='#FF0000'>28K x 16) Static RAM; Density: or='#FF0000'>2 Mb; organization: 1or='#FF0000'>28Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>Rambus(R) XDR(TM) Clock Generator; VDD: or='#FF0000'>2.5 V; Input Frequency: 100 MHz to 133 MHz; Output Frequency: 300 MHz to 800 MHz; # Out: 4<br>or='#FF0000'>2-or='#FF0000'>mbit (1or='#FF0000'>28K x 16) Static RAM; Density: or='#FF0000'>2 Mb; organization: 1or='#FF0000'>28Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V;<br>4-or='#FF0000'>mbit (1or='#FF0000'>28K x 36) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: 1or='#FF0000'>28Kb x 36; Vcc (V): 3.1 to 3.6 V<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 1or='#FF0000'>28; Vcc (V): 5; fMax (MHz): 167; tPD (ns): 7<br>or='#FF0000'>2.5V or 3.3V, or='#FF0000'>200-MHz, 1:10 Clock Distribution buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 10; Operating Range: 0 to 70 C<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 1or='#FF0000'>28; Vcc (V): 5; fMax (MHz): 100; tPD (ns): 7<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 1or='#FF0000'>28; Vcc (V): 5; fMax (MHz): 1or='#FF0000'>25; tPD (ns): 7<br>18-or='#FF0000'>mbit DDR-II SRAM or='#FF0000'>2-Word burst Architecture; Architecture: DDR-II CIO, or='#FF0000'>2 Word burst; Density: 18 Mb; organization: 51or='#FF0000'>2Kb x 36; Vcc (V): 1.7 to 1.9 V<br>Low Voltage Programmable Skew Clock buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: or='#FF0000'>25 MHz to 100 MHz; Output Frequency Range: or='#FF0000'>25 MHz to 100 MHz; Operating Range: 0 to 70 C; Package: SOIC<br>Low Skew Clock buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 143; tPD (ns): 9 单芯位CMOS微机<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 154; tPD (ns): 6 单芯位CMOS微机<br>SINGLE-CHIP 8-bIT CMOS MICROCOMPUTER 单芯位CMOS微机<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9 单芯位CMOS微机<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 1or='#FF0000'>28; Vcc (V): 3.3; fMax (MHz): 83; tPD (ns): 10 单芯位CMOS微机<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 5; fMax (MHz): 1or='#FF0000'>25; tPD (ns): 6 单芯位CMOS微机<br>Three-PLL General-Purpose EPROM Programmable Clock Generator; Voltage (V): 3.3/5.0 V; Input Range: 1 MHz to 30 MHz; Output Range: .077 MHz to 100 MHz; Outputs: 6 单芯位CMOS微机<br>8-or='#FF0000'>mbit (51or='#FF0000'>2K x 16) MobL(R) Static RAM; Density: 8 Mb; organization: 51or='#FF0000'>2Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V; 单芯位CMOS微机<br>High Speed Low Voltage Programmable Skew Clock buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C 单芯位CMOS微机<br>3.3V SDRAM buffer for Mobile PCs with 4 SO-DIMMs; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 100 MHz; Outputs: 10; Operating Range: 0 to 70 C 单芯位CMOS微机<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: -40 to 85 C 单芯位CMOS微机<br>Programmable Skew Clock buffer; Voltage (V): 5.0 V; Operating Frequency: 3.75 MHz to 80 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机<br>or='#FF0000'>2-or='#FF0000'>mbit (1or='#FF0000'>28K x 16) Static RAM; Density: or='#FF0000'>2 Mb; organization: 1or='#FF0000'>28Kb x 16; Vcc (V): 3.0 to 3.6 V; 单芯位CMOS微机<br>MobL(R) 1 or='#FF0000'>mbit (1or='#FF0000'>28K x 8) Static RAM; Density: 1 Mb; organization: 1or='#FF0000'>28Kb x 8; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V; 单芯位CMOS微机<br>18-or='#FF0000'>mbit QDR(TM)-II SRAM or='#FF0000'>2-Word burst Architecture; Architecture: QDR-II, or='#FF0000'>2 Word burst; Density: 18 Mb; organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V 单芯位CMOS微机<br>1-or='#FF0000'>mbit (1or='#FF0000'>28K x 8) Static RAM; Density: 1 Mb; organization: 1or='#FF0000'>28Kb x 8; Vcc (V): 4.50 to 5.50 V; 单芯位CMOS微机<br>4-or='#FF0000'>mbit (or='#FF0000'>256K x 18) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 4 Mb; organization: or='#FF0000'>256Kb x 18; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机<br>or='#FF0000'>2-or='#FF0000'>mbit (64K x 3or='#FF0000'>2) Pipelined Sync SRAM; Architecture: Standard Sync, Pipeline SCD; Density: or='#FF0000'>2 Mb; organization: 64Kb x 3or='#FF0000'>2; Vcc (V): 3.1 to 3.6 V 单芯位CMOS微机<br>or='#FF0000'>200-MHz Field Programmable Zero Delay buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 10 MHz to or='#FF0000'>200 MHz; Outputs: 1or='#FF0000'>2; Operating Range: -40 to 85 C 单芯位CMOS微机<br>or='#FF0000'>2-or='#FF0000'>mbit (1or='#FF0000'>28K x 16) Static RAM; Density: or='#FF0000'>2 Mb; organization: 1or='#FF0000'>28Kb x 16; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V; 单芯位CMOS微机<br>SINGLE-CHIP 8-bIT CMOS MICROCOMPUTER 单芯8位CMOS微机<br>or='#FF0000'>2-or='#FF0000'>mbit (or='#FF0000'>256K x 8) Static RAM; Density: or='#FF0000'>2 Mb; organization: or='#FF0000'>256Kb x 8; Vcc (V): or='#FF0000'>2.or='#FF0000'>20 to 3.60 V; 单芯8位CMOS微机<br>Very Low Jitter Field and Factory Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 10 MHz to 133 MHz; Output Range: or='#FF0000'>20 MHz to or='#FF0000'>200 MHz; Outputs: or='#FF0000'>2 单芯位CMOS微机<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: 0 to 70 C 单芯位CMOS微机<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 5; Operating Range: -40 to 85 C 单芯位CMOS微机<br>Three-PLL General Purpose FLASH Programmable Clock Generator; Voltage (V): 3.3 V; Input Range: 1 MHz to 166 MHz; Output Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 3 单芯位CMOS微机<br>1:8 Clock Fanout buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: -40 to 85 C 单芯位CMOS微机<br>Quad PLL Clock Generator with or='#FF0000'>2-Wire Serial Interface; Voltage (V): or='#FF0000'>2.5/3.3 V; Input Range: or='#FF0000'>27 MHz to or='#FF0000'>27 MHz; Output Range: 4.or='#FF0000'>2 MHz to 166 MHz; Outputs: 5 单芯位CMOS微机<br>or='#FF0000'>2.5V or 3.3V, or='#FF0000'>200-MHz, 1:1or='#FF0000'>2 Clock Distribution buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 1or='#FF0000'>2; Operating Range: 0 to 70 C 单芯位CMOS微机<br>3.3V Zero Delay Clock buffer; Voltage (V): 3.3 V; Frequency Range: 10 MHz to 133 MHz; Outputs: 9; Operating Range: 0 to 70 C 单芯位CMOS微机<br>High Speed Multi-phase PLL Clock buffer; Voltage (V): 3.3 V; Operating Frequency: or='#FF0000'>24 MHz to or='#FF0000'>200 MHz; Outputs: 11; Operating Range: 0 to 70 C 单芯位CMOS微机<br>or='#FF0000'>2.5V or 3.3V, or='#FF0000'>200-MHz, 1:18 Clock Distribution buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 18; Operating Range: -40 to 85 C 单芯位CMOS微机<br>-bit AVR Microcontroller with 8K bytes In- System Programmable Flash 位AVR微控制器具有8K字节的系统内可编程闪<br>or='#FF0000'>2.5V or 3.3V, or='#FF0000'>200-MHz, 1:1or='#FF0000'>2 Clock Distribution buffer; Voltage (V): or='#FF0000'>2.5/3.3 V; Frequency Range: 0 MHz to or='#FF0000'>200 MHz; Outputs: 1or='#FF0000'>2; Operating Range: 0 to 70 C<br>1:8 Clock Fanout buffer; Voltage (V): 3.3 V; Frequency Range: 0 MHz to 350 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>Spread Spectrum Clock Generator; Voltage(V): 3.3 V; Input Frequency Range: 4 MHz to 3or='#FF0000'>2 MHz; Output Frequency Range: 4 MHz to 3or='#FF0000'>2 MHz; Operating Range: 0 to 70 C; Package: SOIC<br>High Speed Low Voltage Programmable Skew Clock buffer; Voltage (V): 3.3 V; Operating Frequency: 3.75 MHz to 110 MHz; Outputs: 8; Operating Range: 0 to 70 C<br>5V, 3.3V, ISR(TM) High-Performance CPLDs; # Macrocells: 64; Vcc (V): 3.3; fMax (MHz): 100; tPD (ns): 9<br>
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