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Part No. |
K4D553235F-GC220
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OCR Text |
...outputs ? 4 banks operation ? mrs cycle with address key programs -. read latency 4, 5 and 6 (clock) -. burst length (2, 4 and 8) -. burst type (sequential & interleave) ? all inputs except data & dm are sampled at the p... |
Description |
8M X 32 DDR DRAM, 0.45 ns, PBGA144
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File Size |
316.09K /
18 Page |
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it Online |
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INTEGRATED DEVICE TECHNOLOGY INC
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Part No. |
72V275L10PF8
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OCR Text |
...et logic wen wclk d 0 -d 17 ld mrs ren rclk oe q 0 -q 17 offset register prs fwft/si sen rt 4512 drw 01
2 commercial and industrial temperature ranges idt72v275/72v285 3.3v cmos supersync fifo tm 32,768 x 18 and 65,536 x 18 pin configur... |
Description |
32K X 18 OTHER FIFO, 6.5 ns, PQFP64
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File Size |
266.29K /
25 Page |
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it Online |
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INTEGRATED SILICON SOLUTION INC
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Part No. |
IS46DR16128-3DBLA2 IS43DR16128-3DBI
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OCR Text |
...fresh commands. 11. issue a mrs command with low to a 8 to initialize device operation. (i.e. to program operating parameters without resetting the dll.) 12. wait at least 200 clock cycles after step 8 and then execute ocd calibrat... |
Description |
128M X 16 DDR DRAM, 0.45 ns, PBGA84
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File Size |
501.03K /
26 Page |
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it Online |
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PROMOS TECHNOLOGIES INC
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Part No. |
V59C1256804QALP19E V59C1256808QALP19E V59C1G01164QALF37E
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OCR Text |
...iting act rda read srf ref ckel mrs ckeh ckeh ckel write automatic sequence command sequence rda wra read pr, pra pr refreshing refreshing down power down active with rda reading with wra active precharge reading writing pr(a) = precharge... |
Description |
32M X 8 DDR DRAM, BGA68 64M X 16 DDR DRAM, BGA92
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File Size |
1,035.33K /
79 Page |
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it Online |
Download Datasheet |
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Price and Availability
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