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ER107 72454 4ALVCH16 NE3510M HAT2099H 1SS15407 2001723 MAX9235
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  multiple-input Datasheet PDF File

For multiple-input Found Datasheets File :: 32961    Search Time::1.297ms    
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    Cypress Semiconductor, Corp.
Part No. CY7C63513C-PVXC CY7C63613C-SXC
OCR Text ...rive is available by connecting multiple gpio pins together to drive a common output ? each gpio port can be configured as inputs with inte...input with an internal pull-up by writing a ?1? to the pin. the sink current for each dac i/o pin c...
Description Low-Speed High I/O, 1.5-Mbps USB Controller; # Endpoints: 3; #of I/O: 40; Core: M8B (8-bit RISC); Development Kit: CY3654, CY3654-P02 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO48
Low-Speed High I/O, 1.5-Mbps USB Controller 8-BIT, OTPROM, 12 MHz, RISC MICROCONTROLLER, PDSO24

File Size 794.61K  /  34 Page

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    Diodes, Inc.
Part No. PA7536PI-15L PA7536J-15L PA7536S-15
OCR Text ... applications - integration of multiple plds and random logic - buried counters, complex state-machines - comparators, decoders, multip...input pins and 36 registers/latches (12 buried logic cells, 12 input registers/latches and 12 bur...
Description EE PLD, 15 ns, PDIP28 0.600 INCH, LEAD FREE, PLASTIC, DIP-28
EE PLD, 15 ns, PQCC28 LEAD FREE, PLASTIC, LCC-28
EE PLD, 15 ns, PDSO28 SOIC-28

File Size 281.93K  /  10 Page

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    Cypress Semiconductor, Corp.
Part No. CYPSI2G50P456-1MGC CYPSI2G100SP456-1MGC CYPSI2G100P456-1MGC CYPSI5G100SP456-1MGC CYPSI5G100P456-1MGC CYPSI2G50SP456-1MGC
OCR Text ...el conversion in receive path  multiple selectable loopback/loop-through modes  50k to 200k usable gates of cpld logic  120k to 480 kb of...input with internal termination and dc-restoration  differential cml serial output with source mat...
Description SPECIALTY MICROPROCESSOR CIRCUIT, PBGA456 35 X 35 MM, 2.33 MM HEIGHT, BGA-456

File Size 752.26K  /  59 Page

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    Integrated Device Technology, Inc.
INTEGRATED DEVICE TECHNOLOGY INC
Part No. 821024PP 821024J
OCR Text ...lk frequency must be an integer multiple of the fsx frequency. pclk i 29 34 pcm clock. the pcm clock shifts out the pcm data to ...input signal is received by the adc and converted into digital data. the digital output of the overs...
Description A/MU-LAW, PCM CODEC, PQFP44 TQFP-44
A/MU-LAW, PCM CODEC, PQCC32

File Size 260.92K  /  13 Page

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    NTE2732A

NTE[NTE Electronics]
Part No. NTE2732A
OCR Text ...ol eliminates bus contention in multiple bus microprocessor systems. The NTE2732A also features an standby mode which reduces the power diss...input. Features: D Fast Access Time: 200ns Max D 0 to +70C Standard Temperature Range D Single +5V P...
Description Integrated Circuit 32K (4K x 8) NMOS UV Erasable PROM

File Size 44.83K  /  6 Page

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    NTE2764

NTE[NTE Electronics]
Part No. NTE2764
OCR Text ...ol eliminates bus contention in multiple-bus microprocessor systems. The NTE2764 features fast, simple one-pulse programming controlled by T...Input/Output TTL Compatible for Reading and Programming D Single +5V Power Supply D Three-State Outp...
Description Integrated Circuit NMOS 64K Erasable EPROM 200ns
Integrated Circuit NMOS, 64K Erasable EPROM, 200ns

File Size 32.34K  /  5 Page

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    Zarlink Semiconductor, Inc.
Part No. PDSP16488A/B0/AC
OCR Text ...s is passed down the chain in a multiple device system, using the pc0 input on the next device. this pin is used in conjunction with pc1 in multiple device systems. it terminates the write strobe from a master device which is eprom support...
Description 8-BIT, DSP-CONVOLVER, CPGA84 POWER, PGA-84

File Size 469.80K  /  33 Page

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    Integrated Device Technology, Inc.
Part No. MPC962308EF-1R2
OCR Text ...capacitive load on fbk input ? multiple configurations, see table 11. available mpc962308 configurations ? multiple low-skew outputs ? 200 ps max output-output skew ? 700 ps max device-device skew ? two banks of four outputs, output tr i...
Description 962308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 SOIC-16

File Size 192.58K  /  7 Page

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    QL8050 QL8150 QL8250 QL8025 QL8325

ETC[ETC]
Part No. QL8050 QL8150 QL8250 QL8025 QL8325
OCR Text ...ing $GYDQFHG &ORFN 1HWZRUN Multiple dedicated Low Skew Clock Networks High drive input-only networks Quadrant-based segmentable clock networks User Programmable Phase Locked Loops (PEHGGHG &RPSXWDWLRQDO 8QLWV (&8V Hardwired ...
Description LOW POWER FPGA COMBINING PERFORMANCE DENSITY AND EMBEDED RAM

File Size 442.48K  /  49 Page

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    Motorola Mobility Holdings, Inc.
Part No. MPC962308D-1R2 MPC962308D-2R2 MPC962308D-3R2
OCR Text ...capacitive load on fbk input  multiple configurations, see ?available mpc962308 configurations? table  multiple low-skew outputs ? 200 ps max output-output skew ? 700 ps max device-device skew ? two banks of four outputs, output tristate...
Description 3.3 V Zero Delay Buffer PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16

File Size 445.68K  /  12 Page

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For multiple-input Found Datasheets File :: 32961    Search Time::1.297ms    
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