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For term.block Found Datasheets File :: 7174 Search Time::1.282ms
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				LATTICE[Lattice Semiconductor]
Part No.	LC4256B-10F256AI LC4256B-10F256BI LC4256B-10T100I LC4256B-10T176I LC4256B-3T100C LC4256B-3T176C LC4256B-5F256AI LC4256B-5F256BC LC4256B-5T100C LC4256B-5T100I LC4256B-5T176I LC4256B-75F256AC LC4256B-75T100C LC4256B-75T176C LC4256B-75T176I LC4032V-25T44C LC4032V-25T48C LC4032V-5T44I LC4032V-5T48C LC4032V-75T44C LC4032V-75T44E LC4032V-75T48C LC4032V-75T48I LC4064V-75T44C LC4256V-75F256BC LC4256V-75F256BI LC4512V-75T176I LC4032V-75T44I LC4032C-75T44C LC4032C-75T44I LC4256B-3F256AC LC4256B-3F256BC LC4256B-5F256AC LC4256B-5T176C LC4256B-75F256AI LC4256B-75F256BC LC4256B-75F256BI LC4256B-75T100I LC4032V-10T44I LC4032V-10T48I LC4032V-5T44C LC4032V-5T48I LC4032V-75T48E LC4064V-10T100I LC4064V-10T44I LC4064V-10T48I LC4064V-25T100C LC4064V-25T44C LC4064V-25T48C LC4064V-5T100C LC4064V-5T100I LC4064V-5T44C LC4064V-5T44I LC4064V-5T48C LC4064V-5T48I LC4064V-75T100C LC4064V-75T100E LC4064V-75T100I LC4064V-75T44E LC4064V-75T44I LC4064V-75T48C LC4064V-75T48E LC4064V-75T48I LC4032C LC4128V-10T100I LC4128V-10T128I LC4128V-10T144I LC4128V-27T100C LC4128V-27T128C LC4128V-27T144C LC4128V-5T100C LC4128V-5T100I LC4128V-5T128C LC4128V-5T128I LC4128V-5T144C LC4128V-5T144I LC4128V-75T100C LC4128V-75T100E LC41
OCR Text	...+OE 1+OE 1+OE To ORP To Product Term Output Enable Sharing Logic Allocator 36 Inputs from GRP AND Array The programmable AND Array...Block CLK0 Block CLK1 Block CLK2 Block CLK3 PT Clock (optional) Shared PT Clock Enhanced Clock Mu...
Description	3.3V/2.5V/1.8V IN-SYSTEM PROGRAMMABLE SUPERFAST HIGH DENSITY PLDS
File Size	230.73K / 74 Page	View it Online	Download Datasheet

				Xilinx, Inc.
Part No.	XCR5128-7TQ128C XCR5128-7TQ128I XCR5128-7VQ100I XCR5128-7VQ100C XCR5128-7PQ160C XCR5128-12PC84I XCR5128-10TQ128I XCR5128-12TQ128C XCR5128-15PC84I XCR5128-10PQ100C
OCR Text	...rogrammers innovative control term structure provides either sum terms or product terms in each logic block for: - programmable 3-state buffer - asynchronous macrocell register preset/reset programmable global 3-state pin facilitates "...
Description	128 Macrocell CPLD EE PLD, 9.5 ns, PQFP160 128 Macrocell CPLD EE PLD, 9.5 ns, PQFP100 128 Macrocell CPLD 128个宏单元CPLD 128 Macrocell CPLD EE PLD, 12 ns, PQFP128 128 Macrocell CPLD EE PLD, 14.5 ns, PQFP128 128 Macrocell CPLD EE PLD, 17.5 ns, PQCC84 128 Macrocell CPLD EE PLD, 12 ns, PQFP100
File Size	123.21K / 20 Page	View it Online	Download Datasheet

				XILINX[Xilinx, Inc]
Part No.	XCR3032 XCR3032-10VQ44I XCR3032-8VQ44C XCR3032-8VQ44I XCR3032-12VQ44C XCR3032-12VQ44I XCR3032-10VQ44C XCR3032-8PC44I XCR3032-10PC44C XCR3032-10PC44I XCR3032-12PC44C XCR3032-12PC44I XCR3032-8PC44C
OCR Text	... placed on a single PLA product term and shared across multiple outputs via the OR array, effectively increasing design density. The XCR3032...block for: - Programmable 3-state buffer - Asynchronous macrocell register preset/reset Programmable...
Description	32 Macrocell CPLD
File Size	201.35K / 14 Page	View it Online	Download Datasheet

				NXP SEMICONDUCTORS
Part No.	PZ3064DS12BP
OCR Text	...rogrammers ? innovative control term structure provides either sum terms or product terms in each logic block for: programmable 3-state buffer asynchronous macrocell register preset/reset up to 2 asynchronous clocks ? programmable global...
Description	EE PLD, 13.5 ns, PQFP100
File Size	171.79K / 20 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C374
OCR Text	...6 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. The logic blocks in the FLASH370 architecture are con...Block Diagram CLOCK INPUTS INPUTS 2 INPUT MACROCELLS 4 8 I/Os I/O0-I/O7 LOGIC BLOCK 36 16 36 1...
Description	128-Macrocell Flash CPLD
File Size	396.57K / 16 Page	View it Online	Download Datasheet

				Cypress Semiconductor Corp.
Part No.	CY7C374I
OCR Text	...6 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 I/O0-I/O7 8 I/Os LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM 4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGI...
Description	UltraLogic 128-Macrocell Flash CPLD(超逻辑28 宏单元闪速CPLD) From old datasheet system
File Size	282.56K / 13 Page	View it Online	Download Datasheet

				Cypress Semiconductor
Part No.	CY7C374I
OCR Text	...6 macrocells, a 72 x 86 product term array, and an intelligent product term allocator. CLOCK INPUTS INPUTS 1 INPUT MACROCELL 4 I/O0-I/O7 8 I/Os LOGIC BLOCK 36 16 36 16 36 16 36 16 PIM 4 INPUT/CLOCK MACROCELLS 4 36 16 36 16 36 16 36 16 LOGI...
Description	128-Macrocell Flash CPLD
File Size	416.61K / 15 Page	View it Online	Download Datasheet

				ANACHIP[Anachip Corp]
Part No.	PA7536SI-15 PA7536 PA7536J-15 PA7536JI-15 PA7536P-15 PA7536PI-15 PA7536S-15
OCR Text	...PLA structure with true product-term sharing - Logic functions and registers can be I/O-buried Ideal for Combinatorial, Synchronous and Asyn...Block Diagram 2 Input/ Global Clock Pins Global Cells 76 (38X2) Array Inputs true and com plement 1...
Description	PEEL Array-TM Programmable Electrically Erasable Logic Array
File Size	238.42K / 10 Page	View it Online	Download Datasheet

				Diodes, Inc. Integrated Circuit Technology Corp ETC[ETC] List of Unclassifed Manufacturers
Part No.	PEEL22LV10AZTI-35 22LV10AZ-25 PEEL22LV10AZJ-25 PEEL22LV10AZJ-35 PEEL22LV10AZJI-25 PEEL22LV10AZJI-35 PEEL22LV10AZP-25 PEEL22LV10AZP-35 PEEL22LV10AZPI-25 PEEL22LV10AZPI-35 PEEL22LV10AZS-25 PEEL22LV10AZS-35 PEEL22LV10AZSI-25 PEEL22LV10AZSI-35 PEEL22LV10AZT-25 PEEL22LV10AZT-35 PEEL22LV10AZTI-25
OCR Text	... Programmable clock; pin 1 or p-term - Programmable clock polarity - 24-Pin DIP/SOIC/TSSOP and 28 Pin PLCC - Schmitt triggers on clock and d...Block Diagram CLK MUX (O ptiona l) I I I NC I I I 4 3 2 1 28 27 26 5 25 6 24 7 23 8 22 9 21 1...
Description	Video Difference Amplifier; Package: SO; No of Pins: 8; Temperature Range: -40°C to 85°C 专用集成电路 Low Power, High Speed Operational Amplifier; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to 70°C 电可擦除可编程逻辑器件 ASIC 专用集成电路 EE PLD, 35 ns, PDIP24 0.300 INCH, PLASTIC, DIP-24 EE PLD, 35 ns, PDSO24 0.170 INCH, TSSOP-24 Video Difference Amplifier; Package: SO; No of Pins: 8; Temperature Range: 0°C to 70°C Video Difference Amplifier; Package: PDIP; No of Pins: 8; Temperature Range: 0°C to 70°C Electrically-Erasable PLD Video Difference Amplifier; Package: SO; No of Pins: 8; Temperature Range: -40°C to 85°C CMOS Programmable Electrically Erasable Logic Device
File Size	135.54K / 10 Page	View it Online	Download Datasheet

For term.block Found Datasheets File :: 7174 Search Time::1.282ms
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