1 features ultra high performance ? system speeds to 100 mhz ? array multipliers > 50 mhz ? 10nsflexiblesram ? internal tri-state capability in each cell freeram ? ? flexible, single/dual port, synchronous/asynchronous 10 ns sram ? 2,048 - 18,432 bits of distributed sram independent of logic cells 128 - 384 pci compliant i/os ? programmable output drive ? fast, flexible array access facilitates pin locking ? pin-compatible with xc4000, xc5200 fpgas 8 global clocks ? fast, low skew clock distribution ? programmable rising/falling edge transitions ? distributed clock shutdown capability for low power management ? global reset/asynchronous reset options ? 4 additional dedicated pci clocks cache logic ? dynamic full/partial re-configurability in-system ? unlimited re-programmability via serial or parallel modes ? enables adaptive designs ? enables fast vector multiplier updates ? quickchange ? tools for fast, easy design changes pin-compatible package options ? plastic leaded chip carriers (plcc) ? thin, plastic quad flat packs (lqfp, tqfp, pqfp) ?ballgridarrays(sbga) industry-standard design tools ? seamless integration (libraries, interface, full back-annotation) with concept ? , everest, exemplar ? ,mentor ? , orcad ? ,synario ? , synopsys ? , verilog ? , veribest ? , viewlogic ? , synplicity ? ? timing driven placement & routing ? automatic/interactive multi-chip partitioning ? fast, efficient synthesis ? over 75 automatic component generators create 1000s of reusable, fully deterministic logic and ram functions intellectual property cores ? fir filters, uarts, pci, fft and other system level functions easy migration to atmel gate arrays for high volume production supply voltage 3.3v 5v i/o tolerant 5k - 50k gates coprocessor fpga with freeram ? at40k05al at40k10al at40k20al at40k40al summary rev. 2818cs?fpga?06/02 note: this is a summary document. a complete document is availableonourwebsiteat www.atmel.com .
2 at40kal series fpga 2818cs?fpga?06/02 note: 1. pac k a g es with fc k will have 8 less re g isters. description the at 4 0 k a l is a f amily o ff ully pc i- compliant , sra m- based fpgas with distributed 10 ns pro g rammable synchronous/asynchronous , dual - port/sin g le - port sra m, 8 g lobal cloc k s , cache l o g ic ability ( partially or f ully recon f i g urable without loss o f data ), auto - matic component g enerators , and ran g einsi z e f rom 5, 000 to 5 0 , 000 usable g ates. i / o counts ran g e f rom 128 to 3 8 4 in industry standard pac k a g es ran g in gf rom 8 4- pin p l cc to 35 2 - ball s q uare b ga , and support 3 . 3v desi g ns. the at 4 0 k a l is desi g ned to q uic k ly implement hi g h - per f ormance , lar g e g ate count desi g ns throu g htheuseo f synthesis and schematic - based tools used on a pc or sun plat f orm. atmel?s desi g n tools provide seamless inte g ration with industry standard tools such as synplicity ,m odelsim ,ex emplar and v iewlo g ic. see the ? id s d atasheet? avail - able on the atmel web site ( http://www.atmel.com/atmel/acrobat/doc1 4 21.pd f) f or a list o f other supported tools. the at 4 0 k a l can be used as a coprocessor f or hi g h - speed (d sp/processor - based ) desi g ns by implementin g avarietyo f computation intensive , arithmetic f unctions. these include adaptive f inite impulse response ( f i r )f ilters ,f ast fourier trans f orms ( fft ), con - volvers , interpolators and discrete - cosine trans f orms (d ct ) that are re q uired f or video compression and decompression , encryption , convolution and other multimedia applications . fast, flexible and efficient sram the at 4 0 k a l fpga o ff ers a patented distributed 10 ns sra m capability where the ra m can be used without losin g lo g ic resources. m ultiple independent , synchronous or asynchronous , dual - port or sin g le - port ra mf unctions ( f i f o, scratch pad , etc. ) can be created usin g atmel?s macro g enerator tool. fast, efficient array and vector multipliers the at 4 0 k a l ?s patented 8 - sided core cell with direct hori z ontal , vertical and dia g onal cell - to - cell connections implements ultra f ast array multipliers without usin g any busin g resources. the at 4 0 k a l ?s cache l o g ic capability enables a lar g e number o f desi g n coe ff icients and variables to be implemented in a very small amount o f silicon , enablin g vast improvement in system speed at much lower cost than conventional fpgas. ta ble 1. at 4 0 k a l family ( 1 ) device at40k05al at40k10al at40k20al at40k40al u sable gates 5k - 10 k 10 k- 20 k 20 k-3 0 k4 0 k-5 0 k rows x columns 16 x 16 2 4x 2 43 2 x3 2 4 8 x4 8 cells 2 5 6 57 61 , 02 4 2 ,3 0 4 re g isters 49 6 ( 1 ) 954 ( 1 ) 1 ,5 20 ( 1 ) 3, 0 4 8 ( 1 ) ra mb its 2 , 0 4 8 4, 608 8 , 1 9 218 ,43 2 i / o(m a x imum ) 128 1 9 22 5 6 3 8 4
3 at40kal series fpga 2818cs?fpga?06/02 cache logic design the at 4 0 k a l, at6000 and fps li c f amilies are capable o f implementin g cache l o g ic ( dynamic f ull/partial lo g ic recon f i g uration , without loss o f data , on - the -f ly )f or buildin g adaptive lo g ic and systems. as new lo g ic f unctions are re q uired , they can be loaded into the lo g ic cache without losin g the data already there or disruptin g the operation o f the rest o f the chip ; replacin g or complementin g the active lo g ic. the at 4 0 k a l can act as a recon f i g urable coprocessor. automatic component generators the at 4 0 k a l fpga f amily is capable o f implementin g user - de f ined , automatically g en - erated , macros in multiple desi g ns ; speed and f unctionality are una ff ected by the macro orientation or density o f the tar g et device. this enables the f astest , most predictable and e ff icient fpga desi g n approach and minimi z es desi g nris k by reusin g already proven f unctions. the automatic component generators wor k seamlessly with industry stan - dard schematic and synthesis tools to create the f astest , most e ff icient desi g ns available. the patented at 4 0 k a l series architecture employs a symmetrical g rid o f small yet power f ul cells connected to a f le x ible busin g networ k . i ndependently controlled cloc k s and resets g overn every column o f cells. the array is surrounded by pro g rammable i / o . d evices ran g einsi z e f rom 5, 000 to 5 0 , 000 usable g ates in the f amily , and have 2 5 6to 3, 0 4 8re g isters. pin locations are consistent throu g hout the at 4 0 k a l series f or easy desi g nmi g ration in the same pac k a g e f ootprint. the at 4 0 k a l series fpgas utili z ea reliable 0. 35 triple - metal , c mo s process and are 100 %f actory - tested. atmel?s pc - and wor k station - based inte g rated development system (id s ) is used to create at 4 0 k a l series desi g ns. m ultiple desi g n entry methods are supported. the atmel architecture was developed to provide the hi g hest levels o f per f ormance , f unctional density and desi g n f le x ibility in an fpga. the cells in the atmel array are small , e ff icient and can implement any pair o fb oolean f unctions o f( the same ) three inputs or any sin g le b oolean f unction o ff our inputs. the cell?s small si z e leads to arrays with lar g e numbers o f cells ,g reatly multiplyin g the f unctionality in each cell. a simple , hi g h - speed busin g networ k provides f ast , e ff icient communication over medium and lon g distances. for a complete version o f this datasheet , re f er to the fpga section o f the atmel web site , www.atmel.com.
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