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august 2011 doc id 18267 rev 2 1/29 AN3320 application note getting started with stm32f20xxx/21xxx mcu hardware development introduction this application note is intended for system designers who require a hardware implementation overview of the development board features such as the power supply, the clock management, the reset control, the boot mode settings and the debug management. it shows how to use the high-density perform ance line stm32f20xxx/21xxx product families and describes the minimum hardware resources required to develop an stm32f20xxx/21xxx application. detailed reference design schematics are also contained in this document with descriptions of the main components, interfaces and modes. www.st.com
contents AN3320 2/29 doc id 18267 rev 2 contents 1 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.1.1 independent a/d converter supply and reference voltage . . . . . . . . . . . . 7 1.1.2 battery backup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.1.3 voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.2 power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 1.3 reset & power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.3.1 power on reset (por) / power down reset (pdr) . . . . . . . . . . . . . . . . . . 9 1.3.2 programmable voltage detector (pvd) . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3.3 system reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1 hse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.1.1 external source (hse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.1.2 external crystal/ceramic resonator (hse crystal) . . . . . . . . . . . . . . . . . 13 2.2 lse osc clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.1 external source (lse bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.2.2 external crystal/ceramic resonator (lse crystal) . . . . . . . . . . . . . . . . . . 14 2.3 clock security system (css) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3 boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 boot mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 boot pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 embedded boot loader mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 debug management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 swj debug port (serial wire and jtag) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.1 swj debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3.2 flexible swj-dp pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.3.3 internal pull-up and pull-down resistors on jtag pins . . . . . . . . . . . . . . 19 4.3.4 swj debug port connection with standard jtag connector . . . . . . . . . 20
AN3320 contents doc id 18267 rev 2 3/29 5 recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.1 printed circuit board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.2 component position . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.3 ground and power supply (v ss , v dd ) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.4 decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 5.5 other signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.6 unused i/os and features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6 reference design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.1 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.3 boot mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.4 swj interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.1.5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.2 component references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
list of tables AN3320 4/29 doc id 18267 rev 2 list of tables table 1. boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 2. debug port pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3. swj i/o pin availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 4. mandatory components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 5. optional components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6. reference connection for all packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
AN3320 list of figures doc id 18267 rev 2 5/29 list of figures figure 1. power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 figure 2. power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 4. pvd thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5. reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6. hse external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 7. hse crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 figure 8. lse external clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 9. lse crystal/ceramic resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 10. boot mode selection implementation example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 11. host-to-board connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 figure 12. jtag connector implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13. typical layout for v dd /v ss pair . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 14. stm32f207ig(h6) microcontroller reference schematic . . . . . . . . . . . . . . . . . . . . . . . . . . 25
power supplies AN3320 6/29 doc id 18267 rev 2 1 power supplies 1.1 introduction the device requires a 1.8 v to 3.6 v operating voltage supply (v dd ), excepted the wlcsp package witch requires 1.65 v to 3.6 v. an embedded regulator is used to supply the internal 1.2 v digital power. the real-time clock (rtc) and backup registers can be powered from the v bat voltage when the main v dd supply is powered off. figure 1. power supply overview 1. v dda and v ssa must be connected to v dd and v ss , respectively. 2. the voltage on v ref ranges from 1.65 v to v dda for wlcsp64+2 packages. ai #ore -emories $igital peripherals 6 $$! domain 6 $$ 6 $$! from6upto6 $$! 6 2%& 6 33 6 33! 6 33 6 $$ 6 "!4 6 #!0 !$converter $!# 4empsensor 2esetblock 0,,s 6 $$ domain 6domain &lashmemory )/ring 3tandbycircuitry wakeuplogic)7$' 6oltageregulator ,3%crystal+(zosc 2##"$#2register 24#and"+0registers "+032!- "ackupdomain ,owvoltageregulator
AN3320 power supplies doc id 18267 rev 2 7/29 1.1.1 independent a/d converter supply and reference voltage to improve conversion accuracy, the adc has an independent power supply that can be filtered separately, and shielded from noise on the pcb. the adc voltage supply input is available on a separate v dda pin an isolated supply ground connection is provided on the v ssa pin when available (depending on package), v ref? must be tied to v ssa . on 100-pin package and above and on wlcsp64+2 to ensure a better accuracy on low-voltage inputs, the user can connect a separate external reference voltage adc input on v ref+ . the voltage on v ref+ may range from 1.8 v to v dda . on wlcsp64+2, the v ref- pin is not available, it is internally connected to the adc ground (v ssa ). on 64-pin packages the v ref+ and v ref- pins are not available, they are internally connected to the adc voltage supply (v dda ) and ground (v ssa ). 1.1.2 battery backup to retain the content of the backup registers when v dd is turned off, the v bat pin can be connected to an optional standby voltage supplied by a battery or another source. the v bat pin also powers the rtc unit, allowing the rtc to operate even when the main digital supply (v dd ) is turned off. the switch to the v bat supply is controlled by the power down reset (pdr) circuitry embedded in the reset block. if no external battery is used in the application, it is highly recommended to connect v bat externally to v dd . 1.1.3 voltage regulator the voltage regulator is always enabled after reset. it works in three different modes depending on the application modes. in run mode, the regulator supplies full powe r to the 1.2 v domain (core, memories and digital peripherals) in stop mode, the regulator supplies low power to the 1.2 v domain, preserving the contents of the registers and sram in standby mode, the regulator is powered down. the contents of the registers and sram are lost except for those concerned with the standby circuitry and the backup domain. note: depending on the selected package, there are specific pins that should be connected either to v ss or v dd to activate or deactivate the voltage regulator. refer to section "voltage regulator" in stm32f20xxx/21xxx datasheet for details .
power supplies AN3320 8/29 doc id 18267 rev 2 1.2 power supply schemes the circuit is powered by a stabilized power supply, v dd . caution: ? the v dd voltage range is 1.8 v to 3.6 v (and 1.65 v to 3.6 v for wlcsp64+2 package) the v dd pins must be connected to v dd with external decoupling capacitors: one single tantalum or ceramic capacitor (min. 4.7 f typ.10 f) for the package + one 100 nf ceramic capacitor for each v dd pin. the v bat pin can be connected to the external battery (1.65 v < v bat < 3.6 v). if no external battery is used, it is recommended to connect this pin to v dd with a 100 nf external ceramic de coupling capacitor. the v dda pin must be connected to two external decoupling capacitors (100 nf ceramic + 1 f tantalum or ceramic). the v ref+ pin can be connected to the v dda external power supply. if a separate, external reference voltage is applied on v ref+ , a 100 nf and a 1 f capacitors must be connected on this pin. in all cases, v ref+ must be kept between 1.65 v and v dda . additional precautions can be taken to filter analog noise: ?v dda can be connected to v dd through a ferrite bead. ?the v ref+ pin can be connected to v dda through a resistor (typ. 47 ). for the voltage regulator configuration, there are specific pins (regoff and irroff depending on the package) that should be connected either to vss or vdd to activate or deactivate the voltage regulator specific . refer to section "voltage regulator" in stm32f20xxx/21xxx datasheet for details . when the voltage regulator is enabled, v cap1 and v cap2 pins must be connected to 2*2.2 f ceramic capacitor.
AN3320 power supplies doc id 18267 rev 2 9/29 figure 2. power supply scheme 1. optional. if a separate, external reference voltage is connected on v ref+ , the two capacitors (100 nf and 1 f) must be connected. 2. v ref + is either connected to v ref or to v dda . 3. n is the number of v dd and v ss inputs. 4. refer to section "voltage regulator" in stm32f20xxx/21xxx datasheet to connect regoff and irroff pins. 1.3 reset & power supply supervisor 1.3.1 power on reset (por) / power down reset (pdr) the device has an integrated por/pdr circuitry that allows proper operation starting from 1.8 v. the device remains in the reset mode as long as v dd is below a specified threshold, v por/pdr , without the need for an external reset circuit. for more details concerning the power on/power down reset threshold, refer to the electrical characteristics in stm32f20xxx/21xxx datasheets. on wlcsp66 package if irroff pin is set to v dd (in that case regoff pin must not be activated, refer to section "voltage regulator" in stm32f20xxx/21xxx datasheet for details ), the pdr is not functional. then the v dd can lower below 1.8 v, but the external circuitry must ensure that reset pin is activated when v dd /v dda becomes below 1.65 v. 6 "!4 34-&xxxxxx .n& 6 $$ ?& n&?& n&?& note "attery 6 "!4 6 2%& 6 $$! 6 33! 6 2%&n 6 $$. 6 33. 6 2%& 6 $$ !)b 6 #!0 ?& 6 #!0 2%'/&& )22/&&
power supplies AN3320 10/29 doc id 18267 rev 2 figure 3. power-on reset/power-down reset waveform 1. t rsttempo is approximately 2.6 ms. v por/pdr rising edge is 1.74 v (typ.) and v por/pdr falling edge is 1.70 v (typ.). refer to stm32f20xxx/ 21xxx datasheets for actual value. 1.3.2 programmable vo ltage detector (pvd) you can use the pvd to monitor the v dd power supply by comparing it to a threshold selected by the pls[2:0] bits in the power control register (pwr_cr). the pvd is enabled by setting the pvde bit. a pvdo flag is available, in the power control/status register (pwr_csr), to indicate whether v dd is higher or lower than the pvd threshold. this event is internally connected to exti line16 and can generate an interrupt if enabled through the exti registers. the pvd output interrupt can be generated when v dd drops below the pvd threshold and/or when v dd rises above the pvd threshold dependi ng on the exti line16 rising/falling edge configuration. as an example the service routine can perform emergency shutdown tasks. figure 4. pvd thresholds 6 $$ 0/2 0$2 m6 hysteresis 4emporization t 2344%-0/ 2%3%4 aib 6 0/20$2 fallingedge 6 0/20$2 risingedge 6 $$ m6 hysteresis 06$threshold 06$output aib 6 06$ fallingedge 6 06$ risingedge
AN3320 power supplies doc id 18267 rev 2 11/29 1.3.3 system reset a system reset sets all register s to their reset values except for the reset flags in the clock controller csr register and the registers in the backup domain (see figure 1 ). a system reset is generated when one of the following events occurs: 1. a low level on the nrst pin (external reset) 2. window watchdog end-of-count condition (wwdg reset) 3. independent watchdog end-of-count condition (iwdg reset) 4. a software reset (sw reset) 5. low-power management reset the reset source can be identified by checking the reset flags in the control/status register, rcc_csr. the stm32f20xxx/21xxx does not require an external reset circuit to power-up correctly. only a pull-down capacitor is recommended to improve ems performance by protecting the device against parasitic resets. see figure 5 . charging and discharging a pull-down capacitor through an internal resistor increases the device power consumption. the capacitor recommended value (100 nf) can be reduced to 10 nf to limit this power consumption; figure 5. reset circuit 2 05 6 $$ 77$'reset )7$'reset 0ulse generator 0owerreset min?s 3ystemreset &ilter 3oftwarereset ,ow powermanagementreset ?& %xternal resetcircuit .234 !)
clocks AN3320 12/29 doc id 18267 rev 2 2 clocks three different clock sources can be us ed to drive the system clock (sysclk): hsi oscillator clock (high-speed internal clock signal) hse oscillator cloc k (high-speed external clock signal) pll clock the devices have two secondary clock sources: 32 khz low-speed internal rc (lsi rc) that drives the independent watchdog and, optionally, the rtc used for auto-wakeup from the stop/standby modes. 32.768 khz low-speed external crystal (lse crystal) that optionally drives the real-time clock (rtcclk) each clock source can be switched on or off independently when it is not used, to optimize the power consumption. refer to the stm32f20xxx/21xxx reference manual rm0033 for the description of the clock tree. 2.1 hse osc clock the high-speed external clock signal (hse) can be generated from two possible clock sources: hse external crystal/ceramic resonator (see figure 7 ) hse user external clock (see figure 6 ) 1. the value of r ext depends on the crystal characteristics. typi cal value is in the range of 5 to 6 r s (resonator series resistance). 2. load capacitance c l has the following formula: c l = c l1 x c l2 / (c l1 + c l2 ) + c stray where: c stray is the pin capacitance and board or trace pcb-related capacitanc e. typically, it is between 2 pf and 7 pf. please refer to section 5: recommendations on page 21 to minimize its value. figure 6. hse external clock figure 7. hse crystal/ceramic resonators osc_out osc_in external source (hi-z) ai14369 hardware configuration /3#?/54 /3#?). aia 34-& 2 %84 # , # , (ardwareconfiguration
AN3320 clocks doc id 18267 rev 2 13/29 2.1.1 external source (hse bypass) in this mode, an external clock source must be provided. it can have a frequency from 1 to 16 mhz (refer to stm32f20xxx/21xxx da tasheets for actual max value). the external clock signal (square, sine or tr iangle) with a duty cycle of about 50%, has to drive the osc_in pin while the osc_out pin must be left in the high impedance state (see figure 7 and figure 6 ). 2.1.2 external crystal/ceram ic resonator (hse crystal) the external oscillator frequen cy ranges from 4 to 26 mhz. the external oscillator has the advantage of producing a very accurate rate on the main clock. the associated hardware configuration is shown in figure 7 . using a 25 mhz oscillator frequency is a good choice to get accurate ethernet , usb otg high-speed peripheral, and i 2 s. the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output dist ortion and startup stabilization time. the load capacitance values must be adjusted according to the selected oscillator. for c l1 and c l2 it is recommended to use high-quality ceramic capacitors in the 5 pf-to- 25 pf range (typ.), designed for high-frequency applications and selected to meet the requirements of the crystal or resonator. c l1 and c l2, are usually the same value. the crystal manufacturer typically specifies a load capacitance that is the series combination of c l1 and c l2 . the pcb and mcu pin capacitances must be included when sizing c l1 and c l2 (10 pf can be used as a rough estimate of the combined pin and board capacitance). refer to the electrical characteristics sections in the datasheet of your product for more details.
clocks AN3320 14/29 doc id 18267 rev 2 2.2 lse osc clock the low-speed external clock signal (lse) can be generated from two possible clock sources: lse external crystal/ce ramic resonator (see figure 9 ) lse user external clock (see figure 8 ) 1. ?lse crystal/ceramic resonators? figure: to avoid exceeding the maximum value of c l1 and c l2 (15 pf) it is strongly recommended to use a resonator with a load capacitance c l 7 pf. never use a resonator with a load capacitance of 12.5 pf. 2. ?lse external clock? and ?lse crystal/ceramic resonators? figures: osc32_in and osc32_out pins can be used also as gpio, but it is recommended not to use them as both rtc and gpio pins in the same application. 3. ?lse crystal/ceramic resonators? figure: the value of r ext depends on the crystal characteristics. a 0 resistor would work but would not be optimal. to fine tube r s value, refer to an2867 - oscillator design guide for st microcontrollers. 2.2.1 external source (lse bypass) in this mode, an external clock source must be provided. it can have a frequency of up to 1 mhz. the external clock signal (square, sine or triangle) with a duty cycle of about 50% has to drive the osc32_in pin while the osc32_out pin must be left high impedance (see figure 8 ). 2.2.2 external crystal/ceram ic resonator (lse crystal) the lse crystal is a 32.768 khz low-speed external crystal or ceramic resonator. it has the advantage of providing a low-power, but highly accurate clock source to the real-time clock peripheral (rtc) for clock/calendar or other timing functions. the resonator and the load capacitors have to be connected as close as possible to the oscillator pins in order to minimize output dist ortion and startup stabilization time. the load capacitance values must be adjusted according to the selected oscillator. figure 8. lse external clock figure 9. lse crystal/ceramic resonators osc32_out osc32_in external source (hi-z) ai14371 hardware configuration /3#?/54 /3#?). aid 34-& # , # , (ardwareconfiguration 2 %84
AN3320 clocks doc id 18267 rev 2 15/29 2.3 clock security system (css) the clock security system can be activated by software. in this case, the clock detector is enabled after the hse oscillator startup delay, and disabled when this oscillator is stopped. if a failure is detected on the hse oscilla tor clock, the oscillator is automatically disabled. a clock failure event is sent to the break input of the tim1 advanced control timer and an interrupt is generated to inform the software about the failure (clock security system interrupt cssi), allowing the mcu to perform rescue operations. the cssi is linked to the cortex?-m3 nmi (n on-maskable interrupt) exception vector. if the hse oscillator is used directly or indi rectly as the system clock (indirectly means that it is used as the pll input clock, and the pll clock is used as the system clock), a detected failure causes a switch of the system clock to the hsi oscillator and the disabling of the external hse oscillator. if th e hse oscillator clock (div ided or not) is the clock entry of the pll used as system cl ock when the failure occurs, the pll is disabled too. for details, see the stm32f20xxx/21xxx (rm00 33) reference manuals available from the stmicroelectronics website www.st.com .
boot configuration AN3320 16/29 doc id 18267 rev 2 3 boot configuration 3.1 boot mode selection in the stm32f20xxx/21xxx, three different boot modes can be selected by means of the boot[1:0] pins as shown in ta b l e 1 . the values on the boot pins are latched on the 4 th rising edge of sysclk after a reset. it is up to the user to set the boot1 and boot0 pins after reset to select the required boot mode. the boot pins are also resampled when exiting the standby mode. consequently, they must be kept in the required boot mode configuration in the standby mode. after this startup delay has elapsed, the cpu fetches the top-of-stack value from address 0x0000 0000, and starts code execution from the boot memory starting from 0x0000 0004. 3.2 boot pin connection figure 10 shows the external connection required to select the boot memory of the stm32f20xxx/21xxx. figure 10. boot mode selection implementation example 1. resistor values are giv en only as a typical example. table 1. boot modes boot mode selection pins boot mode aliasing boot1 boot0 x 0 main flash memory main flash memory is selected as boot space 0 1 system memory system memory is selected as boot space 1 1 embedded sram embedded sram is selected as boot space aib 6 $$ 34-& "//4 "//4 6 $$ k k
AN3320 boot configuration doc id 18267 rev 2 17/29 3.3 embedded boot loader mode the embedded boot loader mode is used to reprogram the flash memory using one of the available serial usart1(pa9/pa10), usart3(p b10/11 & pc10/11), can2(pb5/13) or usb otg fs(pa11/12) in device mode (dfu: device firmware upgrade). the usart peripheral operates with t he internal 16 mhz oscilla tor (hsi). the can and usb otg fs, however, can only function if an external clock (hse) multiple of 1 mhz (between 4 and 26 mhz)is present. this embedded boot loader is located in the system memory and is programmed by st during production. for additional information, refer to an2606.
debug management AN3320 18/29 doc id 18267 rev 2 4 debug management 4.1 introduction the host/target interface is the hardware equipment that connects the host to the application board. this interface is made of three components: a hardware debug tool, a jtag or sw connector and a cable connecting the host to the debug tool. figure 11 shows the connection of the host to the evaluation board stm3220g-eval. figure 11. host-to-board connection 4.2 swj debug port (serial wire and jtag) the stm32f20xxx/21xxx core integrates the serial wire / jtag debug port (swj-dp). it is an arm? standard coresight? debug port that combines a jtag-dp (5-pin) interface and a sw-dp (2-pin) interface. the jtag debug port (jtag-dp) provides a 5-pin standard jtag interface to the ahp- ap port the serial wire debug port (sw-dp) provides a 2-pin (clock + data) interface to the ahp-ap port in the swj-dp, the two jtag pins of the sw-dp are multiplexed with some of the five jtag pins of the jtag-dp. 4.3 pinout and debug port pins the stm32f20xxx/21xxx mcu is offered in various packages with different numbers of available pins. as a result, some functionality re lated to the pin availability may differ from one package to another. 4.3.1 swj debug port pins five pins are used as outputs for the swj-dp as alternate functions of general-purpose i/os (gpios). these pins, shown in ta b l e 2 , are available on all packages. %valuationboard (ost0# 0owersupply *4!'37connector $ebugtool aib
AN3320 debug management doc id 18267 rev 2 19/29 4.3.2 flexible swj-dp pin assignment after reset (sysresetn or poreset n), all five pins used for the swj-dp are assigned as dedicated pins immediately usable by the debugger host (note that the trace outputs are not assigned except if explicitly programmed by the debugger host). however, some of the jtag pins shown in ta bl e 3 can be configured to an alternate function through the gpiox_afrx registers. ta bl e 3 shows the different possibilit ies to release some pins. for more details, see the stm32f20xxx/21xxx (rm0033) reference manual, available from the stmicroelectronics website www.st.com . 4.3.3 internal pull-up and pu ll-down resistors on jtag pins the jtag input pins must not be floating since they are directly connected to flip-flops to control the debug mode features. special care must be taken with the swclk/tck pin that is directly connected to the clock of some of these flip-flops. table 2. debug port pin assignment swj-dp pin name jtag debug port sw debug port pin assignment type description type debug assignment jtms/swdio i jtag test mode selection i/o serial wire data input/output pa 1 3 jtck/swclk i jtag test clock i serial wire clock pa14 jtdi i jtag test data input - - pa15 jtdo/traceswo o jtag test data output - traceswo if async trace is enabled pb3 jntrst i jtag test nreset - - pb4 table 3. swj i/o pin availability available debug ports swj i/o pin assigned pa13 / jtms/ swdio pa1 4 / jtck/ swclk pa15 / jtdi pb3 / jtdo pb4/ jntrst full swj (jtag-dp + sw-dp) - reset state x x x x x full swj (jtag-dp + sw-dp) but without jntrst xxxx jtag-dp disabled and sw-dp enabled x x jtag-dp disabled and sw-dp disabled released
debug management AN3320 20/29 doc id 18267 rev 2 to avoid any uncontrolled i/o levels, the stm32f20xxx/21xxx embeds internal pull-up and pull-down resistors on jtag input pins: jntrst: internal pull-up jtdi: internal pull-up jtms/swdio: internal pull-up tck/swclk: internal pull-down once a jtag i/o is released by the user software, the gpio controller takes control again. the reset states of the gpio control registers put the i/os in the equivalent state: jntrst: input pull-up jtdi: input pull-up jtms/swdio: input pull-up jtck/swclk: input pull-down jtdo: input floating the software can then use these i/os as standard gpios. note: the jtag ieee standard recommends to ad d pull-up resistors on tdi, tms and ntrst but there is no special recommendation for tck. however, for the stm32f20xxx/21xxx , an integrated pull-down resistor is used for jtck. having embedded pull-up and pull-down resistors removes the need to add external resistors. 4.3.4 swj debug port connecti on with standard jtag connector figure 12 shows the connection between the stm32f20xxx/21xxx and a standard jtag connector. figure 12. jtag connector implementation aib 6 $$ 6 $$ 34-& n*4234 *4$) *34-37$)/ *4#+37#,+ *4$/ n234). 642%& n4234 4$) 4-3 4#+ 24#+ 4$/ n3234 $"'21 $"'!#+ k k k 6 33 #onnector *4!'connector#.
AN3320 recommendations doc id 18267 rev 2 21/29 5 recommendations 5.1 printed circuit board for technical reasons, it is best to use a multilayer printed circuit board (pcb) with a separate layer dedicated to ground (v ss ) and another dedicated to the v dd supply. this provides good decoupling and a good shielding effect. for many applications, economical reasons prohibit the use of this type of board. in this case, the major requirement is to ensure a good structure for ground and for the power supply. 5.2 component position a preliminary layout of the pcb must separate the different circuits according to their emi contribution in order to reduce cross-coupling on the pcb, that is noisy, high-current circuits, low-voltage circuits, and digital components. 5.3 ground and power supply (v ss , v dd ) every block (noisy, low-level sensitive, digital, etc.) should be grounded individually and all ground returns should be to a single point. loops must be avoided or have a minimum area. the power supply should be implemented close to the ground line to minimize the area of the supply loop. this is due to the fact that the supply loop acts as an antenna, and is therefore the main transmitter and receiver of emi. all component-free pcb areas must be filled with additional grounding to create a ki nd of shielding (especia lly when using single- layer pcbs). 5.4 decoupling all power supply and ground pins must be properly connected to the power supplies. these connections, including pads, tracks and vias should have as low impedance as possible. this is typically achieved with thick track widths and, preferably, the use of dedicated power supply planes in multilayer pcbs. in addition, each power supply pair should be decoupled with filtering ceramic capacitors c (100 nf) and one single tantalum or ceramic capacitor (min. 4.7 f typ.10 f) connected in parallel on the stm32f20xxx/21xxx device. these capacitors need to be placed as close as possible to, or below, the appropriate pins on the underside of the pcb. typical values are 10 nf to 100 nf, but exact values depend on the application needs. figure 13 shows the typical layout of such a v dd /v ss pair.
recommendations AN3320 22/29 doc id 18267 rev 2 figure 13. typical layout for v dd /v ss pair 5.5 other signals when designing an application, the emc performance can be improved by closely studying: signals for which a temporary disturbance affects the running process permanently (the case of interrupts and handshaking strobe signals, and not the case for led commands). for these signals, a surrounding ground trace, shorter lengths and the absence of noisy and sensitive traces nearby (crosstalk effect) improve emc performance. for digital signals, the best possible electrical margin must be reached for the two logical states and slow schmitt triggers ar e recommended to eliminate parasitic states. noisy signals (clock, etc.) sensitive signals (high impedance, etc.) 5.6 unused i/os and features all microcontrollers are designed for a vari ety of applications and often a particular application does not use 100% of the mcu resources. to increase emc performance, unused clocks, counters or i/os, should not be left free, e.g. i/os should be set to ?0? or ?1?(pull-up or pull-down to the unused i/o pins.) and unused features should be ?frozen? or disabled. via to v ss via to v dd cap. v dd v ss stm32f20xxx/21xxx
AN3320 reference design doc id 18267 rev 2 23/29 6 reference design 6.1 description the reference design shown in figure 14 , is based on the stm32f207if(h6), a highly integrated microcontroller running at 120 mhz, that combines the cortex ? -m3 32-bit risc cpu core with 1 mbyte of embedded flash memory and up to 128 + 4 kbytes of high-speed sram . this reference design can be tailored to any other stm32f20xxx/21xxx device with different package, using the pins correspondence given in table 6: reference connection for all packages . 6.1.1 clock two clock sources are used for the microcontroller: lse: x1? 32.768 khz crystal for the embedded rtc hse: x2? 25 mhz crystal for the stm32f20xxx/21xxx microcontroller refer to section 2: clocks on page 12 . 6.1.2 reset the reset signal in figure 14 is active low. the reset sources include: reset button (b1) debugging tools via the connector cn1 refer to section 1.3: reset & power supply supervisor on page 9 . 6.1.3 boot mode the boot option is configured by setting switches sw2 (boot 0) and sw1 (boot 1). refer to section 3: boot configuration on page 16 . note: in low-power mode (more specially in standby mode) the boot mode is mandatory to be able to connect to tools (the device should boot from the sram). 6.1.4 swj interface the reference design shows the connection between the stm32f20xxx/21xxx and a standard jtag connector. refer to section 4: debug management on page 18 . note: it is recommended to connect the reset pins so as to be able to reset the application from the tools. 6.1.5 power supply refer to section 1: power supplies on page 6 .
reference design AN3320 24/29 doc id 18267 rev 2 6.2 component references table 4. mandatory components id components name reference quantity comments 1 microcontroller stm32f207ig(h6) 1 176-pin package 2 capacitors 100 nf 16 ceramic capacitors (decoupling capacitors) 3 capacitor 10 f 1 ceramic capac itor (decoupling capacitor) table 5. optional components id components name reference quantity comments 1resistor 10 k 5 pull-up and pull-down for jtag and boot mode. 2resistor 390 1 used for hse: the value depends on the crystal characteristics. this resistor value is given only as a typical example. 3resistor 0 1 used for lse: the value depends on the crystal characteristics. this resistor value is given only as a typical example. 4 capacitor 100 nf 2 ceramic capacitor. 5 capacitor 2 pf 2 used for lse: the value depends on the crystal characteristics. 6 capacitor 1 f 2 used for v dda and v ref . 7 capacitor 2.2 f 2 used for internal regulator when it is on. 8 capacitor 20 pf 2 used for hse: the value depends on the crystal characteristics. 9 quartz 25 mhz 1 used for hse. 10 quartz 32 khz 1 used for lse. 11 jtag connector he10 1 12 transil diode 5 v-400 w 11 for jtag protection. 13 resistor 22 ohm 11 for jtag protection. 14 battery 3v3 1 if no external battery is used in the application, it is recommended to connect v bat externally to v dd. 15 switch 3v3 2 used to select the right boot mode. 16 push-button b1 1 17 jumper 3 pins 2 used to select v bat source, and regoff pin. 18 debug trace connector ftsh-110- 01-l-dv 1 used for jtag/swd and debug trace.
AN3320 reference design doc id 18267 rev 2 25/29 figure 14. stm32f207ig(h6) microcontroller reference schematic 1. if no external battery is used in the application, it is recommended to connect v bat externally to v dd . 2. to be able to reset the device from t he tools this resistor has to be kept. 1 4 3 2 b1 reset c27 100nf c24 20pf c23 20pf x1 25mhz r17 390 r20 10k +3v3 2 3 1 sw2 09.03290.01 4 1 3 2 x2 ref tbd c26 2pf c25 2pf r19 0 r18 0 bootloader_boot0 bootloader_reset pc14 pc15 ph0 ph1 bt1 cr1220 holder l1 bead c4 100nf r2 0 vdda vdd_mcu vref+ c2 100nf tp1 vref 1 2 3 jp2 +3v3 vdd_mcu c20 100nf vdd_mcu c5 2.2uf c6 2.2uf c21 100nf c22 100nf c7 100nf c19 100nf c18 100nf c17 100nf c11 100nf vdd_mcu c12 100nf c13 100nf c14 100nf c15 100nf c10 100nf c9 100nf c8 100nf +3v3 boot0 d12 bat60jfilm jp3 d13 bat60jfilm +1v2 +1v2 jp4 sb1 sb2 pe2 a2 pe3 a1 pe4 b1 pe5 b2 pe6 b3 pi8 d2 pc13 d1 pc14 e1 pc15 f1 pi9 d3 pi10 e3 pi11 e4 pf0 e2 pf1 h3 pf2 h2 pf3 j2 pf4 j3 pf5 k3 pf6 k2 pf7 k1 pf8 l3 pf9 l2 pf10 l1 ph0 g1 ph1 h1 nrst j1 pc0 m2 pc1 m3 pc2 m4 pc3 m5 pa 0 n3 pa 1 n2 pa 2 p2 ph2 f4 ph3 g4 ph4 h4 ph5 j4 pa 3 r2 pa 4 n4 pa 5 p4 pa 6 p3 pa 7 r3 pc4 n5 pc5 p5 pb0 r5 pb1 r4 pb2 m6 pf11 r6 pf12 p6 pf13 n6 pf14 r7 pf15 p7 pg0 n7 pg1 m7 pe7 r8 pe8 p8 pe9 p9 pe10 r9 pe11 p10 pe12 r10 pe13 n11 pe14 p11 pe15 r11 pb10 r12 pb11 r13 ph6 m11 ph7 n12 ph8 m12 ph9 m13 ph10 l13 ph11 l12 ph12 k12 pb12 p12 pb13 p13 pb14 r14 pb15 r15 pd8 p15 pd9 p14 pd10 n15 pd11 n14 pd12 n13 pd13 m15 pd14 m14 pd15 l14 pg2 l15 pg3 k15 pg4 k14 pg5 k13 pg6 j15 pg7 j14 pg8 h14 pc6 h15 pc7 g15 pc8 g14 pc9 f14 pa 8 f15 pa 9 e15 pa 10 d15 pa 11 c15 pa 12 b15 pa 13 a15 ph13 e12 ph14 e13 ph15 d13 pi0 e14 pi1 d14 pi2 c14 pi3 c13 pa 14 a14 pa 15 a13 pc10 b14 pc11 b13 pc12 a12 pd0 b12 pd1 c12 pd2 d12 pd3 d11 pd4 d10 pd5 c11 pd6 b11 pd7 a11 pg9 c10 pg10 b10 pg11 b9 pg12 b8 pg13 a8 pg14 a7 pg15 b7 pb3 a10 pb4 a9 pb5 a6 pb6 b6 pb7 b5 boot0 d6 pb8 a5 pb9 b4 pe0 a4 pe1 a3 pi4 d4 pi5 c4 pi6 c3 pi7 c2 u1a stm32f207igh6 stm32f217igh6 r11 10k +3v3 2 3 1 sw1 09.03290.01 pa 14 pa 15 pb2 pb3 pb4 pa 13 boot1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cn1 jtag +3v3 r9 10k r10 10k r5 10k jtag connector d1 z5v1 d6 z5v1 d5 z5v1 d4 z5v1 d3 z5v1 d2 z5v1 tms/swdio tck/swclk tdi tdo/swo trst c16 10f c3 1f c1 1f vbat c1 vss f2 vdd f3 vss g2 vdd g3 vref- n1 vssa m1 vref+ p1 vdda r1 regoff l4 vdd k4 vss m8 vdd n8 vss m9 vdd n9 vcap m10 vdd n10 vss h12 vdd j12 vss_sa d5 vdd j13 vss g12 vdd h13 vcap f13 vss f12 vdd g13 vss d9 vdd c9 vss d8 vdd c8 vss d7 vdd c7 rfu c6 vdd_sa c5 u1b stm32f207igh6 1 2 3 jp1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 cn2 ftsh-110-01-l-dv +3v3 key trace_d3 trace_d2 trace_d1 trace_d0 trace_ck trace_d3 trace_d2 trace_d1 trace_d0 trace_ck d11 z5v1 d7 z5v1 d8 z5v1 d9 z5v1 d10 z5v1 r16 22 r15 22 r14 22 r13 22 r12 22 r8 22 r7 22 r6 22 r4 22 r3 22 r1 22 !)
reference design AN3320 26/29 doc id 18267 rev 2 table 6. reference connection for all packages pin name pin numbers for lqfp packages pin numbers for bga package pin numbers for wlcsp package 176 pins 144 pins 100 pins 64 pins 176 pins 64+2 pins osc_in 29 23 12 5 g1 e9 osc_out 30 24 13 6 h1 f9 pc15- osc32_out 10 9 9 4 f1 c9 pc14- osc32_in 9 8 8 3 e1 b9 boot0 166 138 94 60 d6 b6 pb2-boot1 58 48 37 28 m6 j4 nrst 31 25 14 7 j1 e8 pa13 124 105 72 46 a15 b2 pa14 137 109 76 49 a14 a1 pa15 138 110 77 50 a13 a2 pb4 162 134 90 56 a9 b4 pb3 161 133 89 55 a10 a4 v cap_1 81 71 49 31 m10 j3 v cap_2 125 106 73 47 f13 c2 v ss_2 126 107 74 - f12 b1 v ss_3 ---63- d8 v ss_4 48 38 27 18 - f1 v ss_5 22 16 10 - g2 h9 v ss_6 61 51 - - m8 - v ss_7 71 61 - - m9 - v ss_8 102 83 - - - - v ss_9 113 94 - - g12 - v ss_10 148 120 - - d8 - v ss_11 158 130 - - d7 - v ss_13 14 - - - f2 - v ss_14 90 - - - h12 - v ss_15 135 - - - d9 - v dd_1 82 72 50 32 n10 - v dd_2 127 108 75 48 g13 a8 v dd_3 172 144 100 64 c5 d9
AN3320 reference design doc id 18267 rev 2 27/29 v dd_4 49 39 28 19 k4 e1 v dd_5 23 17 11 - g3 - v dd_6 62 52 - - n8 - v dd_7 72 62 - - n9 - v dd_8 103 84 - - j13 - v dd_9 114 95 - - h13 - v dd_10 149 121 - - c8 - v dd_11 159 131 - - c7 - v dd_12 36 30 19 - - - v dd_13 15 - - - f3 - v dd_14 91 - - - j12 - v dd_15 136 - - - c9 - v ref+ 38 32 21 - p1 f7 v ref- --- -n1 - v ss ----d5 - v ssa 37 31 20 12 m1 - v dda 39 33 22 13 r1 - v bat 6661c1 a9 regoff----l4 h7 irroff----- c8 table 6. reference connection for all packages (continued) pin name pin numbers for lqfp packages pin numbers for bga package pin numbers for wlcsp package 176 pins 144 pins 100 pins 64 pins 176 pins 64+2 pins
revision history AN3320 28/29 doc id 18267 rev 2 7 revision history table 7. document revision history date revision changes 25-feb-2011 1 initial release. 22-aug-2011 2 updated regoff and irroff pin configuration. updated standby mode in chapter 1.1.3: voltage regulator . updated voltage regulator configuration in chapter 1.2: power supply schemes . updated frequence of external clock (hse) in chapter 3.3: embedded boot loader mode section.
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