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SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 1 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 50 a, vrpower ? integrated power stage description the sic783a is an integrated power stage solution optimized for synchronous buck applications to offer high current, high efficien cy and high power density performance. packaged in vishays proprietary mlp 6 mm x 6 mm package, sic783a enables voltage regulator designs to deliver current s up to 50 a per phase. the internal power mosfets utilize vishays state-of-the-art trench mosfet technology that delivers industry benchmark performa nce to significantly reduce switching and conduction losses. the sic783a incorporates an advanced mosfet gate driver ic that features high current driving capability, adaptive dead-time control, an integrated bootstrap schottky diode, and a thermal warning (thwn) that alerts the system of excessive junction temperature. this driver is compatible with wide rang e of pwm controllers and supports tri-state pwm logic (3.3 v) as well as zero current detect to improve light load efficiency. features ? thermally enhanced powerpak ? mlp66-40l package ? industry benchmark mosfet with integrated schottky diode ? delivers up to 50 a continuous current ? high frequency operation up to 1 mhz ? optimized for 12 v input rail applications ? 3.3 v pwm logic with tri-state threshold ? zero current detect control for light load efficiency improvement. ? short pwm propagation delay (< 20 ns) ? thermal monitor flag ? faster disable ?v cin under voltage lock out (uvlo) applications ? synchronous buck converters ? multi-phase vrds for cpu, gpu and memory ? dc/dc pol modules typical application diagram fig. 1 - sic783a typi cal application diagram pwm controller g ate driver 5 v input output v cin d s bl# pwm thwn v drv g h v in boot v s wh p g nd g l c g nd pha s e zcd_en#
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 2 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pinout configuration fig. 2 - sic783a pin configuration pin description pin number name function 1 zcd_en# zcd control. active low 2v cin supply voltage for internal logic circuitry 3v drv supply voltage for internal gate driver 4 boot high-side driver bootstrap voltage 5, 37, p1 c gnd analog ground for the driver ic 6 gh high-side gate signal 7 phase return path of high-side gate driver 8 to 14, p2 v in power stage input voltage. drain of high-side mosfet 15, 29 to 35, p3 v swh switch node of the power stage 16 to 28 p gnd power ground 36 gl low-side gate signal 38 thwn thermal warning open drain output 39 dsbl# disable pin. active low 40 pwm pwm control input ordering information part number package marking code SIC783ACD-t1-ge3 powerpak mlp66-40l sic783a sic783adb reference board zcd_en# 1 vcin 2 vdrv 3 boot 4 c g nd 5 g h 6 pha s e 7 vin 8 vin 9 vin 10 vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 p g nd 30 v s wh 29 v s wh 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm p1 c g nd p2 vin p3 v s wh top view 1 zcd_en# 2 vcin 3 vdrv 4 boot 5 c g nd 6 g h 7 pha s e 8 vin 9 vin 10 vin vin 11 vin 12 vin 13 vin 14 v s wh 15 p g nd 16 p g nd 17 p g nd 18 p g nd 19 p g nd 20 p g nd 28 p g nd 27 p g nd 26 p g nd 25 p g nd 24 p g nd 23 p g nd 22 p g nd 21 v s wh 30 v s wh 29 31 v s wh 32 v s wh 33 v s wh 34 v s wh 35 v s wh 36 g l 37 c g nd 38 thwn 39 d s bl# 40 pwm bottom view p1 c g nd p2 vin p3 v s wh
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 3 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes ? stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratin gs only, and functional operation of the device at these or any ot her conditions beyond those indicated in the operational section s of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliabilit y. (1) the specification values indicate ac voltage is v swh to p gnd , -7 v (< 50 ns, 10 j), minimum and 27 v (< 50 ns), maximum. (2) the specification value indicates ac voltage is v boot to p gnd , 34 v (< 50 ns) maximum. (3) the specification value indicates ac voltage is v boot to v phase , 8 v (< 20 ns) maximum. absolute maximum ratings electrical paramete r symbol limits unit input voltage v in -0.3 to +20 v control logic supply voltage v cin -0.3 to +7 drive supply voltage v drv -0.3 to +7 switch node (dc voltage) v swh -0.3 to +20 switch node (ac voltage) (1) -7 to +27 boot voltage (dc voltage) v boot 27 boot voltage (ac voltage) (2) 34 boot to phase (dc voltage) v boot_phase -0.3 to +7 boot to phase (ac voltage) (3) -0.3 to +8 all logic inputs and outputs (pwm, dsbl#, zcd_en# and thwn) -0.3 to v cin +0.3 max. operating junction temperature t j 150 c ambient temperature t a -40 to +125 storage temperature -65 to +150 electrostatic disc harge protection human body model, jesd22-a114 4000 v charged device mo del, jesd22-c101 1000 recommended operating range electrical min. typ. max. unit input voltage (v in )4.5-16 v drive supply voltage (v drv ) 4.5 5 5.5 control logic supply voltage (v cin ) 4.5 5 5.5 switch node (v swh , dc voltage) - - 20 boot to phase (v boot_phase , dc voltage) 4 4.5 5.5 thermal resistance thermal resistance from junction to case - 2.5 - c/w thermal resistance from junction to pad - 1 -
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 4 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical specifications parameter symbol test conditions unless otherwise specified (dsbl# = zcd_en# = 5 v, v in = 12 v, v drv = v cin = 5 v, t a = 25 c) min. typ. (1) max. unit power supplies control logic supply current i vcin v dsbl# = 0 v, no switching -13- a v dsbl# = 5 v, no switching, v pwm = float - 300 - v dsbl# = 5 v, f s = 300 khz, d = 0.1 - 325 - drive supply current i vdrv f s = 300 khz, d = 0.1 -1625 ma f s = 1 mhz, d = 0.1 -55- v dsbl# = 0 v, no switching -20- a v dsbl# = 5 v, no switching -55- bootstrap supply bootstrap switch forward voltage v f i f = 2 ma --0.4v pwm control input rising threshold v th_pwm_r 2.1 2.4 2.8 v falling threshold v th_pwm_f 0.7 0.9 1.2 tri-state rising threshold v th_tri_r 0.9 1.2 1.5 tri-state falling threshold v th_tri_f 1.9 2.2 2.6 tri-state voltage v tri v pwm = float -1.8- tri-state rising threshold hysteresis v hys_tri_r - 250 - mv tri-state falling threshold hysteresis v hys_tri_f - 350 - pwm current i pwm v pwm = 0 v - - -225 a v pwm = 3.3 v - - 225 driver timing tri-state to gh/gl rising propagation delay t pd_tri_r -30- ns tri-state hold-off time t tsho - 130 - gh - turn off propagation delay t pd_off_gh -20- gh - turn on propagation delay (dead time rising) t pd_on_gh -8- gl - turn off propagation delay t pd_off_gl -12- gl - turn on propagation delay (dead time falling) t pd_on_gl -8- dsbl# low to gh/gl falling propagation delay t pd_dsbl_f fig. 5 - 15 - dsbl#, zcd_en# input dsbl# logic input voltage v ih_dsbl# input logic high 2 - - v v il_dsbl# input logic low - - 0.8 zcd_en# logic input voltage v ih_zcd_en# input logic high 2 - - v il_zcd_en# input logic low - - 0.8
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 5 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 notes (1) typical limits are established by characterization and are not production tested. (2) guaranteed by design. protection under voltage lockout v uvlo v cin rising, on threshold -3.74.3 v v cin falling, off threshold 2.7 3.2 - under voltage lockout hysteresis v uvlo_hyst - 500 - mv thwn flag set (2) t thwn_set - 160 - c thwn flag clear (2) t thwn_clear - 135 - thwn flag hysteresis (2) t thwn_hyst -25- thwn output low v ol_thwn i thwn = 2 ma -0.02- v device truth table dsbl# zcd_en# pwm gh gl open x x l l lxxll hlll h, i l > 0 a l, i l < 0 a hlhhl hltri-statell hhl lh hhhhl hhtri-statel l electrical specifications parameter symbol test conditions unless otherwise specified (dsbl# = zcd_en# = 5 v, v in = 12 v, v drv = v cin = 5 v, t a = 25 c) min. typ. (1) max. unit
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 6 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 detailed operational description pwm input with tri-state function the pwm input receives the pwm control signal from the vr controller ic. the pwm input is designed to be compatible with standard controllers using two state logic (h and l) and advanced controllers that incorporate tri-state logic (h, l and tri-state) on the pwm output. pwm input operates as follows for two state logic. when pwm is driven above v th_pwm_r the low-side is turned off and the high-side is turned on. when pwm in put is driven below v th_pwm_f the high-side turns off and the low- side turns on. for tri-state logic, the pwm input operates as above for driving the mosfets. however, if the pwm input stays tri-state for the tri-state hold-off period, t tsho , both high-side and low-side mosfets are turned off. this function allows the vr phase to be disabled without negative output voltage swing caused by inductor ringing and saves a schottky diode clamp. the pwm and tri-stat e regions are separated by hysteresis to prevent false triggering. the sic783a incorporates pwm voltage thresholds that are compatible with 3.3 v logic. disable (dsbl#) in the low-state, the dsbl# pi n shuts down the driver ic and disables both high-side and low-side mosfets. in this state, the standby current is minimized. if dsbl# is left unconnected an internal pull-down resistor will pull the pin down to c gnd and shut down the ic. diode emulation mode (zcd_en#) when zcd_en# pin is low and pwm signal switches low, gl is forced on (after normal bbm time). during this time, it is under control of the zcd (zero crossing detect) comparator. if, after the internal blanking delay, the inductor current becomes zero, gl is tu rned off. this improves light load efficiency by avoiding di scharge of output capacitors. if pwm enters tri-state, then device will go into normal tri-state mode after tri-state delay. the gl output will be turned off regardless of indu ctor current, this is an alternative method of improving light load efficiency by reducing switching losses. thermal warning (thwn) the thwn pin is an open drain signal that flags the presence of excessive junction tempe rature. connect a maximum of 20 k to pull this pin up to v cin . an internal temperature sensor detects the junction temperature. the temperature threshold is 160 c. when th is junction temperature is exceeded the thwn flag is set. when the junction temperature drops below 135 c the device will clear the thwn signal. the sic783a does not stop operation when the flag is set. the decision to shutdown must be made by an external thermal control function. voltage input (v in ) this is the power input to th e drain of the high-side power mosfet. this pin is connected to the high power intermediate bus rail. switch node (v swh and phase) the switch node, v swh , is the circuit power stage output. this is the output applied to the power inductor and output filter to deliver the output for the buck converter. the phase pin is internally connected to the switch node v swh . this pin is to be used exclusively as the return pin for the boot capacitor. a 20 k resistor is connected between gh and phase to provide a discharge path for the hs mosfet in the event that v cin goes to zero while v in is still applied. ground connections (c gnd and p gnd ) p gnd (power ground) should be externally connected to c gnd (control signal ground). the layout of the printed circuit board should be such that the inductance separating c gnd and p gnd is minimized. transient differences due to inductance effects between these two pins should not exceed 0.5 v. control and drive supp ly voltage input (v drv , v cin ) v cin is the bias supply for th e gate drive control ic. v drv is the bias supply for the gate drivers. it is recommended to separate these pins through a resistor. this creates a low pass filtering effect to avoid coupling of high frequency gate driver noise into the ic. bootstrap circuit (boot) an integrated bootstrap diode is incorporated so that only an external capacitor is necessary to complete the bootstrap circuit. connect a bootstrap capacitor with one leg tied to boot pin and the other tied to phase pin.
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 7 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 shoot-through protection and adaptive dead time (ast) the sic783a has an internal adaptive logic to avoid shoot through and optimize dead time. the shoot through protection ensures that bo th high-side and low-side mosfets are not turned on at the same time. the adaptive dead time control operates as follows. the hs and ls gate voltages are monitored to prevent the one turning on from tuning on until the other's gate voltage is sufficiently low (< 1 v). built in delays also ensure that one power mos is completely off, before the ot her can be turned on. this feature helps to adjust dead time as gate transitions change with respect to output current and temperature. under voltage lockout (uvlo) during the start up cycle, the uvlo disables the gate drive holding high-side and low-side mosfet gate low until the input voltage rail has reached a point at which the logic circuitry can be safely activated. the sic783a also incorporates logic to clamp the gate drive signals to zero when the uvlo falling edge triggers the shutdown of the device. as an added precaution, a 20 k resistor is connected between gh and ph ase to provide a discharge path for the hs mosfet. functional block diagram fig. 3 - sic783a functi onal block diagram pwm c g nd 20k boot g h v s wh g l p g nd + - v ref = 1 v v ref = 1 v g l + - anti-cro ss conduction control logic v drv pwm logic control & s tate machine uvlo thermal monitor & warning thwn zcd_en# v in pha s e + - v s wh v s wh v cin d s bl # v drv
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 8 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 pwm timing diagram fig. 4 - definition of pwm logic and tri-state operation timing diagram: dsbl# fig. 5 - dsbl# propagation delay v th_pwm_r v th_pwm_f v th_tri_r v th_tri_f pwm g h g l t pd_off_ g l t t s ho t pd_on_ g h t pd_off_ g h t pd_on_ g l t t s ho t pd_tri_r t pd_tri_r pwm d s bl # g h g l d s bl # low to g h falling propagation delay t d s bl # low to g l falling propagation delay pwm d s bl # g h g l t di s able
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 9 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 electrical characteristics (v in = 12 v, f sw = 500 khz, v drv = v cin = 5 v, l o/p = 0.33 h / dcr 0.83 m (ihlp-5050fd0r33-01), unl ess noted otherwise) fig. 6 - efficiency vs. i out fig. 7 - power stage power loss vs. i out 78 80 82 84 86 88 90 92 94 0 2 4 6 8 10 12 14 16 18 20 efficency (%) i out (a) v out = 1.2 v; fccm v out = 1.2 v; zcd 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 2 4 6 8 101214161820 power lo ss (w) i out (a)
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 10 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 fig. 8 - zero cross detect mode operation (zcd) ch1 (green) = pwm (2v/div), ch2 (red) = gh (5v/di v), ch3 (yellow) = gl (5 v/div), ch4 (blue) = v swh (5v/div) recommended land pattern powerpak mlp66-40l ch1 ch2 ch3 ch4 1 1 0.025 0.100 0.100 0.100 0.100 0.025 40 0.100 0.100 0.100 0.100 0.100 0.100 0.600 2.600 1.700 0.320 0.310 40 2.200 2.200 0.276 0.276 0.200 4.600 all dimen s ion s are in milimeter s
SIC783ACD www.vishay.com vishay siliconix s14-1639-rev. b, 25-aug-14 11 document number: 64902 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 package outline drawing vishay siliconix maintains worldw ide manufacturing ca pability. products may be manufactured at one of several qualified locatio ns. reliability da ta for silicon technology and package reliability represent a composite of all qualified locations. for related documents su ch as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?64902 . 40 1 2 x 2 x pin 1 dot by marking mlp66-40l (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.08 c a1 a2 0.41 k2 k1 d2-1 pin #1 dent e2-1 e d2-3 d2-2 e2-3 e2-2 (nd-1)x e ref. (nd-1)x e ref. 0.10 m c a b dim. millimeters inches min. nom. max. min. nom. max. a 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n40 40 nd 10 10 ne 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc
package information www.vishay.com vishay siliconix revision: 12-jan-15 1 document number: 64846 for technical questions, contact: powerictechsupport@vishay.com this document is subject to change without notice. the products described herein and this document are subject to specific disclaimers, set forth at www.vishay.com/doc?91000 powerpak ? mlp66-40 case outline notes 1. use millimeters as the primary measurement 2. dimensioning and tolerances conform to asme y14.5m. - 1994 3. n is the number of terminals. nd is the number of terminals in x-direction and ne is the number of terminals in y-direction 4. dimension b applies to plated terminal and is m easured between 0.20 mm and 0.25 mm from terminal tip 5. the pin #1 identifier must be existed on the top surface of the package by using indentation mark or other feature of packag e body 6. exact shape and size of this feature is optional 7. package warpage max. 0.08 mm 8. applied only for terminals dim. millimeters inches min. nom. max. min. nom. max. a (8) 0.70 0.75 0.80 0.027 0.029 0.031 a1 0.00 - 0.05 0.000 - 0.002 a2 0.20 ref. 0.008 ref. b (4) 0.20 0.25 0.30 0.078 0.098 0.011 d 6.00 bsc 0.236 bsc e 0.50 bsc 0.019 bsc e 6.00 bsc 0.236 bsc l 0.35 0.40 0.45 0.013 0.015 0.017 n (3) 40 40 nd (3) 10 10 ne (3) 10 10 d2-1 1.45 1.50 1.55 0.057 0.059 0.061 d2-2 1.45 1.50 1.55 0.057 0.059 0.061 d2-3 2.35 2.40 2.45 0.095 0.094 0.096 e2-1 4.35 4.40 4.45 0.171 0.173 0.175 e2-2 1.95 2.00 2.05 0.076 0.078 0.080 e2-3 1.95 2.00 2.05 0.076 0.078 0.080 k1 0.73 bsc 0.028 bsc k2 0.21 bsc 0.008 bsc ecn: t14-0826-rev. b, 12-jan-15 dwg: 5986 40 1 2 x 2 x pin 1 dot by marking mlp66-40 (6 mm x 6 mm) 10 11 20 21 30 31 56 4 top view bottom view side view a b c d 0.10 c b e 0.10 c a a 0.0 8 c a1 a2 0.41 k2 k1 d2-1 e2-1 e d2-3 d2-2 e2-3 e2-2 ( n d-1)x e ref. ( n d-1)x e ref. 0.10 m c a b
legal disclaimer notice www.vishay.com vishay revision: 08-feb-17 1 document number: 91000 disclaimer ? all product, product specifications and data ar e subject to change with out notice to improve reliability, function or design or otherwise. vishay intertechnology, inc., its affiliates, agents, and employee s, and all persons acting on it s or their behalf (collectivel y, vishay), disclaim any and all liability fo r any errors, inaccuracies or incompleteness contained in any datasheet or in any o ther disclosure relating to any product. vishay makes no warranty, representation or guarantee regarding the suitability of th e products for any particular purpose or the continuing production of any product. to the maximum extent permitted by applicable law, vi shay disclaims (i) any and all liability arising out of the application or use of any product , (ii) any and all liability, including without limitation specia l, consequential or incidental damages, and (iii) any and all implied warranties, includ ing warranties of fitness for particular purpose, non-infringement and merchantability. statements regarding the suitability of products for certain types of applicatio ns are based on vishays knowledge of typical requirements that are often placed on vishay products in generic applications. such statements are not binding statements about the suitability of products for a particular applic ation. it is the customers responsibility to validate tha t a particular product with the prope rties described in the product sp ecification is suitable for use in a particular application. parameters provided in datasheets and / or specifications may vary in different ap plications and perfor mance may vary over time. all operating parameters, including ty pical parameters, must be va lidated for each customer application by the customer s technical experts. product specifications do not expand or otherwise modify vishays term s and conditions of purchase, including but not limited to the warranty expressed therein. except as expressly indicated in writing, vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the vishay product could result in personal injury or death. customers using or selling vishay product s not expressly indicated for use in such applications do so at their own risk. please contact authorized vishay personnel to obtain writ ten terms and conditions rega rding products designed for such applications. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is gran ted by this document or by any conduct of vishay. product names and markings noted herein may be trademarks of their respective owners. ? 2017 vishay intertechnology, inc. all rights reserved

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