| |
|
 |
|
| Part No. |
KM736V747T-10
|
| OCR Text |
...dvance pin (adv). adv should be driven to low once the device has been deselected in order to load a new address for next operation. clock enable( cke ) pin allows the operation of the chip to be suspended as long as necessary. when cke i... |
| Description |
128K X 36 ZBT SRAM, 10 ns, PQFP100
|
| File Size |
386.96K /
17 Page |
 View
it Online |
Download Datasheet
|
| |
|
|
CYPRESS SEMICONDUCTOR CORP
|
| Part No. |
CY22E016L-SZ25XC
|
| OCR Text |
...r e cycle. when the hsb pin is driven low, the cy22e016l conditionally initiates a store operation after t delay . an actual store cycle begins if a write to the sram took place since the la st store or recall cycle. the hsb pin also act... |
| Description |
2K X 8 NON-VOLATILE SRAM, 25 ns, PDSO28
|
| File Size |
2,055.46K /
14 Page |
View
it Online |
Download Datasheet |
| |
|
|
MOTOROLA INC
FREESCALE SEMICONDUCTOR INC
|
| Part No. |
XPC823CZT66B2T
|
| OCR Text |
...out to ta , bi assertion (when driven by the memory controller or pcmcia interface) 2.5 11 2.5 9.25 2.5 9.25 ns b12 clkout to ts , bb negation 10 19 5 13 5 12 ns b12a clkout to ta , bi negation (when driven by the memory controller or ... |
| Description |
32-BIT, 66 MHz, RISC PROCESSOR, PBGA256
|
| File Size |
593.47K /
81 Page |
View
it Online |
Download Datasheet |
| |
|
|
ALLIANCE SEMICONDUCTOR CORP
|
| Part No. |
AS7C33128NTD36A-100BC AS7C33128NTD36A-166TQC
|
| OCR Text |
...ted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 , ce1, ce2 isync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv... |
| Description |
128K X 36 ZBT SRAM, 12 ns, PQFP100
128K X 36 ZBT SRAM, 9 ns, PQFP100
|
| File Size |
161.04K /
10 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
PI3USB40
|
| OCR Text |
... maximum loading. 3. per ttl driven input (control inputs only); a and b pins do not contribute to i cc . parameter description test conditions min. typ. (2) max. units x talk crosstalk rl = 100?, f = 250mhz - -27 - db o irr off isolatio... |
| Description |
ASSP | 3.3V. Wide Bandwidth. 8-Channel. 2:1 Mux/Demux USB 2.0 Switch
|
| File Size |
271.31K /
6 Page |
View
it Online |
Download Datasheet |
| |
|
|
|
| Part No. |
|
| OCR Text |
...ured in the output register and driven to the cpu during the second clock edge. ss is driven low during this cycle, signaling that the sram should drive out the data. during consecutive read cycles where the address is the same, the data... |
| Description |
|
| File Size |
446.61K /
14 Page |
View
it Online |
Download Datasheet |
|
Price and Availability
|
