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ALLIANCE SEMICONDUCTOR CORP
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Part No. |
AS7C33128NTD36A-100BC AS7C33128NTD36A-166TQC
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OCR Text |
...ted. dq[a,b,c,d] i/o sync data. driven as output when the chip is enabled and oe is active. ce0 , ce1, ce2 isync synchronous chip enables. sampled at the rising edge of clk, when adv/ld is asserted. are ignored when adv/ld is high. adv... |
Description |
128K X 36 ZBT SRAM, 12 ns, PQFP100 128K X 36 ZBT SRAM, 9 ns, PQFP100
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File Size |
161.04K /
10 Page |
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it Online |
Download Datasheet |
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Part No. |
PI3USB40
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OCR Text |
... maximum loading. 3. per ttl driven input (control inputs only); a and b pins do not contribute to i cc . parameter description test conditions min. typ. (2) max. units x talk crosstalk rl = 100?, f = 250mhz - -27 - db o irr off isolatio... |
Description |
ASSP | 3.3V. Wide Bandwidth. 8-Channel. 2:1 Mux/Demux USB 2.0 Switch
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File Size |
271.31K /
6 Page |
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it Online |
Download Datasheet |
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CYPRESS[Cypress Semiconductor]
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Part No. |
CY7C1353 CY7C1353-66AC CY7C1353-40AC CY7C1353-50AC
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OCR Text |
...ng deselected, ADV/LD should be driven LOW in order to load a new address. Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN. CLK is only recognized if CEN is active LOW. Chip Enable 1 Input, activ... |
Description |
256Kx18 Flow-Through SRAM with NoBL Architecture
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File Size |
158.83K /
13 Page |
View
it Online |
Download Datasheet |
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Price and Availability
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